diff --git a/code/Core/Src/main.c b/code/Core/Src/main.c index 2918c68..1420f87 100644 --- a/code/Core/Src/main.c +++ b/code/Core/Src/main.c @@ -38,16 +38,19 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN PD */ -#define FEED_DISTANCE 127863 // pi * 40.7mm dia in um, per revolution -#define REVOLUTION_COUNT 370800 // 360 * 1030 (gear ratio) +#define UM_PER_REV 127863 // pi * 40.7mm dia in um, per revolution +#define GEAR_RATIO 1030 // 1030 (gear ratio) #define CNT_MAX 65535 #define CNT_LIMIT_ZONE 1000 +#define ENCODER_PPR 7 +#define ENCODER_CPR ENCODER_PPR *4 #define UUID_LENGTH 12 // 12 8bit values #define PHOTON_NETWORK_CONTROLLER_ADDRESS 0x00 #define PHOTON_NETWORK_BROADCAST_ADDRESS 0xFF #define PWM_MAX 2400 #define MAX_PWM_DIFFERENCE 10 +#define PROTOCOL_VERSION 1 /* USER CODE END PD */ @@ -92,6 +95,9 @@ int32_t i_max = 500; int32_t pid_max_step = 10; pid_i32_t motor_pid; pid_motor_cmd_t motor_cmd; +uint8_t vendor_options[VENDOR_SPECIFIC_OPTIONS_LENGTH]; +uint8_t feed_distance = 4; +int32_t pid_add = 0; /* USER CODE END PV */ /* Private function prototypes -----------------------------------------------*/ @@ -110,6 +116,7 @@ static void MX_TIM14_Init(void); void set_LED (uint8_t R, uint8_t G, uint8_t B); void handleRS485Message(uint8_t *buffer, uint8_t size); void set_Feeder_PWM(uint16_t PWM, uint8_t direction); +void update_Feeder_Target(int32_t difference); /* USER CODE END PFP */ @@ -702,14 +709,29 @@ void HAL_TIM_PeriodElapsedCallback (TIM_HandleTypeDef * htim) target_count+= INT32_MAX/4; } + + if (pid_add!=0) + { + int64_t temp = target_count + pid_add; + pid_add = 0; + if (temp < (INT32_MIN+10000)) + { + //todo throw error + } + else if(temp > (INT32_MAX-10000)) + { + //todo throw error + } + target_count = temp; + } motor_cmd = pid_update_motor(&motor_pid,target_count,total_count); set_Feeder_PWM(motor_cmd.pwm,motor_cmd.dir); } - if (htim == &htim3) return; // PWM timer + if (htim == &htim1) return; // PWM timer else if (htim == &htim3) // encoder overflow { - // will this fire on rising / falling overflow the same ? + // will fire upon wraparound if update IT is enabled } if (htim == &htim16) //SW1 timer { @@ -775,6 +797,14 @@ void set_LED (uint8_t R, uint8_t G, uint8_t B) HAL_GPIO_WritePin(LED_B_GPIO_Port,LED_B_Pin,B); } +void comp_crc_header(CRC8_107 *lcrc, PhotonResponse *lresponse) +{ + CRC8_107_add(lcrc,lresponse->header.toAddress); + CRC8_107_add(lcrc,lresponse->header.fromAddress); + CRC8_107_add(lcrc,lresponse->header.packetId); + CRC8_107_add(lcrc,lresponse->header.payloadLength); +} + void handleRS485Message(uint8_t *buffer, uint8_t size) { PhotonPacketHeader *header = (PhotonPacketHeader *) buffer; @@ -790,43 +820,201 @@ void handleRS485Message(uint8_t *buffer, uint8_t size) { PhotonCommand *command = (PhotonCommand *) buffer; PhotonResponse response; + CRC8_107 crc; + CRC8_107_init(&crc); response.header.fromAddress = my_address; response.header.packetId = command->header.packetId; response.header.toAddress = command->header.fromAddress; + uint8_t *payload_ptr; + size_t packet_len; switch (command->commandId) { case GET_FEEDER_ID: + memcpy(response.payload.getFeederId.uuid,UUID,UUID_LENGTH); + response.status = STATUS_OK; + comp_crc_header(&crc,&response); + payload_ptr =(uint8_t*) &response.payload; + for (uint32_t i = 0; ipayload.initializeFeeder.uuid,UUID_LENGTH) == 0) + { + is_initialized = 1; + response.status = STATUS_OK; + } + else + { + response.status = STATUS_WRONG_FEEDER_ID; + } + + comp_crc_header(&crc,&response); + payload_ptr =(uint8_t*) &response.payload; + for (uint32_t i = 0; ipayload.getFeederAddress.uuid,UUID_LENGTH) == 0) + { + response.status = STATUS_OK; + } + else + { + return; // this makes no sense, but original code behaves like this + } + + response.header.payloadLength = 1; // only status byte + comp_crc_header(&crc,&response); + CRC8_107_add(&crc,response.status); + response.header.crc = CRC8_107_getChecksum(&crc); + packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength; + HAL_UART_Transmit(&huart2,(uint8_t *)&response,packet_len,100); break; case IDENTIFY_FEEDER: + if(memcmp(UUID,command->payload.getFeederAddress.uuid,UUID_LENGTH) == 0) + { + response.status = STATUS_OK; + } + else + { + return; // this makes no sense, but original code behaves like this + } + + response.header.payloadLength = 1; // only status byte + comp_crc_header(&crc,&response); + CRC8_107_add(&crc,response.status); + response.header.crc = CRC8_107_getChecksum(&crc); + packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength; + // todo: call identify function + HAL_UART_Transmit(&huart2,(uint8_t *)&response,packet_len,100); break; case PROGRAM_FEEDER_FLOOR: + // todo write address into EEPROM (1wire) + + response.status = STATUS_FAIL; + + response.header.payloadLength = 1; // only status byte + comp_crc_header(&crc,&response); + CRC8_107_add(&crc,response.status); + response.header.crc = CRC8_107_getChecksum(&crc); + packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength; + HAL_UART_Transmit(&huart2,(uint8_t *)&response,packet_len,100); break; case UNINITIALIZED_FEEDERS_RESPOND: + if (is_initialized) return; + memcpy(response.payload.getFeederId.uuid,UUID,UUID_LENGTH); + response.header.payloadLength=sizeof(response.payload)+1; + response.status=STATUS_OK; + + payload_ptr =(uint8_t*) &response.payload; + for (uint32_t i = 0; i INT32_MAX/2) + { + //todo error + return; + } + else if (temp < INT32_MIN/2) + { + //todo error + return; + } + else + { + pid_add += temp; + return; + } +} + + + void set_Feeder_PWM(uint16_t PWM, uint8_t direction) { if (direction) diff --git a/code/Debug/Core/Src/crc.cyclo b/code/Debug/Core/Src/crc.cyclo new file mode 100644 index 0000000..6005241 --- /dev/null +++ b/code/Debug/Core/Src/crc.cyclo @@ -0,0 +1,2 @@ +../Core/Src/crc.c:10:6:CRC8_107_add 3 +../Core/Src/crc.c:21:9:CRC8_107_getChecksum 1 diff --git a/code/Debug/Core/Src/crc.d b/code/Debug/Core/Src/crc.d new file mode 100644 index 0000000..2914ff5 --- /dev/null +++ b/code/Debug/Core/Src/crc.d @@ -0,0 +1,2 @@ +Core/Src/crc.o: ../Core/Src/crc.c ../Core/Inc/crc.h +../Core/Inc/crc.h: diff --git a/code/Debug/Core/Src/crc.o b/code/Debug/Core/Src/crc.o new file mode 100644 index 0000000..c7cbf88 Binary files /dev/null and b/code/Debug/Core/Src/crc.o differ diff --git a/code/Debug/Core/Src/crc.su b/code/Debug/Core/Src/crc.su new file mode 100644 index 0000000..9c8295d --- /dev/null +++ b/code/Debug/Core/Src/crc.su @@ -0,0 +1,2 @@ +../Core/Src/crc.c:10:6:CRC8_107_add 24 static +../Core/Src/crc.c:21:9:CRC8_107_getChecksum 16 static diff --git a/code/Debug/Core/Src/main.cyclo b/code/Debug/Core/Src/main.cyclo index f4e59af..6a313bb 100644 --- a/code/Debug/Core/Src/main.cyclo +++ b/code/Debug/Core/Src/main.cyclo @@ -1,21 +1,24 @@ ../Core/Inc/pid.h:39:23:clamp_i32 3 ../Core/Inc/pid.h:46:20:pid_init 1 ../Core/Inc/pid.h:77:31:pid_update_motor 8 -../Core/Src/main.c:124:5:main 18 -../Core/Src/main.c:234:6:SystemClock_Config 3 -../Core/Src/main.c:273:13:MX_TIM1_Init 10 -../Core/Src/main.c:367:13:MX_TIM3_Init 3 -../Core/Src/main.c:416:13:MX_TIM14_Init 2 -../Core/Src/main.c:447:13:MX_TIM16_Init 2 -../Core/Src/main.c:479:13:MX_TIM17_Init 2 -../Core/Src/main.c:511:13:MX_USART1_UART_Init 5 -../Core/Src/main.c:559:13:MX_USART2_UART_Init 5 -../Core/Src/main.c:605:13:MX_DMA_Init 1 -../Core/Src/main.c:626:13:MX_GPIO_Init 1 -../Core/Src/main.c:676:6:HAL_TIM_PeriodElapsedCallback 11 -../Core/Src/main.c:724:6:HAL_GPIO_EXTI_Callback 5 -../Core/Src/main.c:746:6:HAL_UARTEx_RxEventCallback 4 -../Core/Src/main.c:766:6:set_LED 4 -../Core/Src/main.c:776:6:handleRS485Message 1 -../Core/Src/main.c:794:6:set_Feeder_PWM 2 -../Core/Src/main.c:815:6:Error_Handler 1 +../Core/Inc/crc.h:18:20:CRC8_107_init 1 +../Core/Src/main.c:130:5:main 18 +../Core/Src/main.c:240:6:SystemClock_Config 3 +../Core/Src/main.c:279:13:MX_TIM1_Init 10 +../Core/Src/main.c:373:13:MX_TIM3_Init 3 +../Core/Src/main.c:422:13:MX_TIM14_Init 2 +../Core/Src/main.c:453:13:MX_TIM16_Init 2 +../Core/Src/main.c:485:13:MX_TIM17_Init 2 +../Core/Src/main.c:517:13:MX_USART1_UART_Init 5 +../Core/Src/main.c:565:13:MX_USART2_UART_Init 5 +../Core/Src/main.c:611:13:MX_DMA_Init 1 +../Core/Src/main.c:632:13:MX_GPIO_Init 1 +../Core/Src/main.c:682:6:HAL_TIM_PeriodElapsedCallback 12 +../Core/Src/main.c:746:6:HAL_GPIO_EXTI_Callback 5 +../Core/Src/main.c:768:6:HAL_UARTEx_RxEventCallback 4 +../Core/Src/main.c:788:6:set_LED 4 +../Core/Src/main.c:798:6:comp_crc_header 1 +../Core/Src/main.c:806:6:handleRS485Message 26 +../Core/Src/main.c:989:6:update_Feeder_Target 1 +../Core/Src/main.c:996:6:set_Feeder_PWM 2 +../Core/Src/main.c:1017:6:Error_Handler 1 diff --git a/code/Debug/Core/Src/main.d b/code/Debug/Core/Src/main.d index f1773c5..3a54d32 100644 --- a/code/Debug/Core/Src/main.d +++ b/code/Debug/Core/Src/main.d @@ -29,7 +29,7 @@ Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h \ - ../Core/Inc/photon_protocol.h ../Core/Inc/pid.h + ../Core/Inc/photon_protocol.h ../Core/Inc/pid.h ../Core/Inc/crc.h ../Core/Inc/main.h: ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: @@ -63,3 +63,4 @@ Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: ../Core/Inc/photon_protocol.h: ../Core/Inc/pid.h: +../Core/Inc/crc.h: diff --git a/code/Debug/Core/Src/main.o b/code/Debug/Core/Src/main.o index 15d8e5a..1306d98 100644 Binary files a/code/Debug/Core/Src/main.o and b/code/Debug/Core/Src/main.o differ diff --git a/code/Debug/Core/Src/main.su b/code/Debug/Core/Src/main.su index c6ad22a..7c7d45b 100644 --- a/code/Debug/Core/Src/main.su +++ b/code/Debug/Core/Src/main.su @@ -1,21 +1,24 @@ ../Core/Inc/pid.h:39:23:clamp_i32 24 static ../Core/Inc/pid.h:46:20:pid_init 24 static ../Core/Inc/pid.h:77:31:pid_update_motor 72 static -../Core/Src/main.c:124:5:main 56 static -../Core/Src/main.c:234:6:SystemClock_Config 64 static -../Core/Src/main.c:273:13:MX_TIM1_Init 120 static -../Core/Src/main.c:367:13:MX_TIM3_Init 64 static -../Core/Src/main.c:416:13:MX_TIM14_Init 8 static -../Core/Src/main.c:447:13:MX_TIM16_Init 8 static -../Core/Src/main.c:479:13:MX_TIM17_Init 8 static -../Core/Src/main.c:511:13:MX_USART1_UART_Init 8 static -../Core/Src/main.c:559:13:MX_USART2_UART_Init 8 static -../Core/Src/main.c:605:13:MX_DMA_Init 16 static -../Core/Src/main.c:626:13:MX_GPIO_Init 56 static -../Core/Src/main.c:676:6:HAL_TIM_PeriodElapsedCallback 24 static -../Core/Src/main.c:724:6:HAL_GPIO_EXTI_Callback 16 static -../Core/Src/main.c:746:6:HAL_UARTEx_RxEventCallback 16 static -../Core/Src/main.c:766:6:set_LED 24 static -../Core/Src/main.c:776:6:handleRS485Message 24 static -../Core/Src/main.c:794:6:set_Feeder_PWM 16 static -../Core/Src/main.c:815:6:Error_Handler 8 static,ignoring_inline_asm +../Core/Inc/crc.h:18:20:CRC8_107_init 16 static +../Core/Src/main.c:130:5:main 56 static +../Core/Src/main.c:240:6:SystemClock_Config 64 static +../Core/Src/main.c:279:13:MX_TIM1_Init 120 static +../Core/Src/main.c:373:13:MX_TIM3_Init 64 static +../Core/Src/main.c:422:13:MX_TIM14_Init 8 static +../Core/Src/main.c:453:13:MX_TIM16_Init 8 static +../Core/Src/main.c:485:13:MX_TIM17_Init 8 static +../Core/Src/main.c:517:13:MX_USART1_UART_Init 8 static +../Core/Src/main.c:565:13:MX_USART2_UART_Init 8 static +../Core/Src/main.c:611:13:MX_DMA_Init 16 static +../Core/Src/main.c:632:13:MX_GPIO_Init 56 static +../Core/Src/main.c:682:6:HAL_TIM_PeriodElapsedCallback 32 static +../Core/Src/main.c:746:6:HAL_GPIO_EXTI_Callback 16 static +../Core/Src/main.c:768:6:HAL_UARTEx_RxEventCallback 16 static +../Core/Src/main.c:788:6:set_LED 24 static +../Core/Src/main.c:798:6:comp_crc_header 16 static +../Core/Src/main.c:806:6:handleRS485Message 88 static +../Core/Src/main.c:989:6:update_Feeder_Target 16 static +../Core/Src/main.c:996:6:set_Feeder_PWM 16 static +../Core/Src/main.c:1017:6:Error_Handler 8 static,ignoring_inline_asm diff --git a/code/Debug/Core/Src/subdir.mk b/code/Debug/Core/Src/subdir.mk index 0891ba3..1be359e 100644 --- a/code/Debug/Core/Src/subdir.mk +++ b/code/Debug/Core/Src/subdir.mk @@ -5,6 +5,7 @@ # Add inputs and outputs from these tool invocations to the build variables C_SRCS += \ +../Core/Src/crc.c \ ../Core/Src/main.c \ ../Core/Src/stm32c0xx_hal_msp.c \ ../Core/Src/stm32c0xx_it.c \ @@ -13,6 +14,7 @@ C_SRCS += \ ../Core/Src/system_stm32c0xx.c OBJS += \ +./Core/Src/crc.o \ ./Core/Src/main.o \ ./Core/Src/stm32c0xx_hal_msp.o \ ./Core/Src/stm32c0xx_it.o \ @@ -21,6 +23,7 @@ OBJS += \ ./Core/Src/system_stm32c0xx.o C_DEPS += \ +./Core/Src/crc.d \ ./Core/Src/main.d \ ./Core/Src/stm32c0xx_hal_msp.d \ ./Core/Src/stm32c0xx_it.d \ @@ -36,7 +39,7 @@ Core/Src/%.o Core/Src/%.su Core/Src/%.cyclo: ../Core/Src/%.c Core/Src/subdir.mk clean: clean-Core-2f-Src clean-Core-2f-Src: - -$(RM) ./Core/Src/main.cyclo ./Core/Src/main.d ./Core/Src/main.o ./Core/Src/main.su ./Core/Src/stm32c0xx_hal_msp.cyclo ./Core/Src/stm32c0xx_hal_msp.d ./Core/Src/stm32c0xx_hal_msp.o ./Core/Src/stm32c0xx_hal_msp.su ./Core/Src/stm32c0xx_it.cyclo ./Core/Src/stm32c0xx_it.d ./Core/Src/stm32c0xx_it.o ./Core/Src/stm32c0xx_it.su ./Core/Src/syscalls.cyclo ./Core/Src/syscalls.d ./Core/Src/syscalls.o ./Core/Src/syscalls.su ./Core/Src/sysmem.cyclo ./Core/Src/sysmem.d ./Core/Src/sysmem.o ./Core/Src/sysmem.su ./Core/Src/system_stm32c0xx.cyclo ./Core/Src/system_stm32c0xx.d ./Core/Src/system_stm32c0xx.o ./Core/Src/system_stm32c0xx.su + -$(RM) ./Core/Src/crc.cyclo ./Core/Src/crc.d ./Core/Src/crc.o ./Core/Src/crc.su ./Core/Src/main.cyclo ./Core/Src/main.d ./Core/Src/main.o ./Core/Src/main.su ./Core/Src/stm32c0xx_hal_msp.cyclo ./Core/Src/stm32c0xx_hal_msp.d ./Core/Src/stm32c0xx_hal_msp.o ./Core/Src/stm32c0xx_hal_msp.su ./Core/Src/stm32c0xx_it.cyclo ./Core/Src/stm32c0xx_it.d ./Core/Src/stm32c0xx_it.o ./Core/Src/stm32c0xx_it.su ./Core/Src/syscalls.cyclo ./Core/Src/syscalls.d ./Core/Src/syscalls.o ./Core/Src/syscalls.su ./Core/Src/sysmem.cyclo ./Core/Src/sysmem.d ./Core/Src/sysmem.o ./Core/Src/sysmem.su ./Core/Src/system_stm32c0xx.cyclo ./Core/Src/system_stm32c0xx.d ./Core/Src/system_stm32c0xx.o ./Core/Src/system_stm32c0xx.su .PHONY: clean-Core-2f-Src diff --git a/code/Debug/feeder_mk2.elf b/code/Debug/feeder_mk2.elf index 8a29e07..c7a26b6 100644 Binary files a/code/Debug/feeder_mk2.elf and b/code/Debug/feeder_mk2.elf differ diff --git a/code/Debug/feeder_mk2.list b/code/Debug/feeder_mk2.list index bd31efc..f142034 100644 --- a/code/Debug/feeder_mk2.list +++ b/code/Debug/feeder_mk2.list @@ -5,47 +5,47 @@ Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000000c0 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA - 1 .text 00004cfc 080000c0 080000c0 000010c0 2**2 + 1 .text 00004d80 080000c0 080000c0 000010c0 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE - 2 .rodata 000000dc 08004dbc 08004dbc 00005dbc 2**2 + 2 .rodata 000000dc 08004e40 08004e40 00005e40 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA - 3 .ARM.extab 00000000 08004e98 08004e98 00006024 2**0 + 3 .ARM.extab 00000000 08004f1c 08004f1c 00006024 2**0 CONTENTS, READONLY - 4 .ARM 00000000 08004e98 08004e98 00006024 2**0 + 4 .ARM 00000000 08004f1c 08004f1c 00006024 2**0 CONTENTS, READONLY - 5 .preinit_array 00000000 08004e98 08004e98 00006024 2**0 + 5 .preinit_array 00000000 08004f1c 08004f1c 00006024 2**0 CONTENTS, ALLOC, LOAD, DATA - 6 .init_array 00000004 08004e98 08004e98 00005e98 2**2 + 6 .init_array 00000004 08004f1c 08004f1c 00005f1c 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA - 7 .fini_array 00000004 08004e9c 08004e9c 00005e9c 2**2 + 7 .fini_array 00000004 08004f20 08004f20 00005f20 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA - 8 .data 00000024 20000000 08004ea0 00006000 2**2 + 8 .data 00000024 20000000 08004f24 00006000 2**2 CONTENTS, ALLOC, LOAD, DATA - 9 .bss 0000048c 20000024 08004ec4 00006024 2**2 + 9 .bss 00000490 20000024 08004f48 00006024 2**2 ALLOC - 10 ._user_heap_stack 00000600 200004b0 08004ec4 000064b0 2**0 + 10 ._user_heap_stack 00000604 200004b4 08004f48 000064b4 2**0 ALLOC 11 .ARM.attributes 00000028 00000000 00000000 00006024 2**0 CONTENTS, READONLY - 12 .debug_info 000104fc 00000000 00000000 0000604c 2**0 + 12 .debug_info 00010a96 00000000 00000000 0000604c 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 13 .debug_abbrev 000021de 00000000 00000000 00016548 2**0 + 13 .debug_abbrev 00002210 00000000 00000000 00016ae2 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 14 .debug_aranges 00000e00 00000000 00000000 00018728 2**3 + 14 .debug_aranges 00000e18 00000000 00000000 00018cf8 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS - 15 .debug_rnglists 00000b16 00000000 00000000 00019528 2**0 + 15 .debug_rnglists 00000b29 00000000 00000000 00019b10 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 16 .debug_macro 00014883 00000000 00000000 0001a03e 2**0 + 16 .debug_macro 0001380c 00000000 00000000 0001a639 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 17 .debug_line 00010e4c 00000000 00000000 0002e8c1 2**0 + 17 .debug_line 000110ba 00000000 00000000 0002de45 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 18 .debug_str 000840c3 00000000 00000000 0003f70d 2**0 + 18 .debug_str 000844c2 00000000 00000000 0003eeff 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 19 .comment 00000043 00000000 00000000 000c37d0 2**0 + 19 .comment 00000043 00000000 00000000 000c33c1 2**0 CONTENTS, READONLY - 20 .debug_frame 00003320 00000000 00000000 000c3814 2**2 + 20 .debug_frame 00003384 00000000 00000000 000c3404 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS - 21 .debug_line_str 0000004d 00000000 00000000 000c6b34 2**0 + 21 .debug_line_str 0000004d 00000000 00000000 000c6788 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: @@ -67,7 +67,7 @@ Disassembly of section .text: 80000da: bd10 pop {r4, pc} 80000dc: 20000024 .word 0x20000024 80000e0: 00000000 .word 0x00000000 - 80000e4: 08004da4 .word 0x08004da4 + 80000e4: 08004e28 .word 0x08004e28 080000e8 : 80000e8: 4b04 ldr r3, [pc, #16] @ (80000fc ) @@ -82,7 +82,7 @@ Disassembly of section .text: 80000fa: 46c0 nop @ (mov r8, r8) 80000fc: 00000000 .word 0x00000000 8000100: 20000028 .word 0x20000028 - 8000104: 08004da4 .word 0x08004da4 + 8000104: 08004e28 .word 0x08004e28 08000108 <__udivsi3>: 8000108: 2200 movs r2, #0 @@ -813,7 +813,7 @@ int main(void) /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); - 80005ce: f001 f83e bl 800164e + 80005ce: f001 f880 bl 80016d2 /* USER CODE BEGIN Init */ @@ -876,21 +876,21 @@ int main(void) 800062a: 4b68 ldr r3, [pc, #416] @ (80007cc ) 800062c: 60bb str r3, [r7, #8] *puuid = HAL_GetUIDw0(); - 800062e: f001 f88b bl 8001748 + 800062e: f001 f8cd bl 80017cc 8000632: 0002 movs r2, r0 8000634: 68bb ldr r3, [r7, #8] 8000636: 601a str r2, [r3, #0] *(puuid+1) = HAL_GetUIDw1(); 8000638: 68bb ldr r3, [r7, #8] 800063a: 1d1c adds r4, r3, #4 - 800063c: f001 f88e bl 800175c + 800063c: f001 f8d0 bl 80017e0 8000640: 0003 movs r3, r0 8000642: 6023 str r3, [r4, #0] *(puuid+2) = HAL_GetUIDw2(); 8000644: 68bb ldr r3, [r7, #8] 8000646: 3308 adds r3, #8 8000648: 001c movs r4, r3 - 800064a: f001 f891 bl 8001770 + 800064a: f001 f8d3 bl 80017f4 800064e: 0003 movs r3, r0 8000650: 6023 str r3, [r4, #0] @@ -899,7 +899,7 @@ int main(void) 8000654: 4b5f ldr r3, [pc, #380] @ (80007d4 ) 8000656: 2240 movs r2, #64 @ 0x40 8000658: 0018 movs r0, r3 - 800065a: f004 faa7 bl 8004bac + 800065a: f004 fae9 bl 8004c30 /* Infinite loop */ /* USER CODE BEGIN WHILE */ @@ -923,7 +923,7 @@ int main(void) 8000674: 4a5a ldr r2, [pc, #360] @ (80007e0 ) 8000676: 0019 movs r1, r3 8000678: 0010 movs r0, r2 - 800067a: f001 fd27 bl 80020cc + 800067a: f001 fd69 bl 8002150 800067e: 1e03 subs r3, r0, #0 8000680: d004 beq.n 800068c 8000682: 1dbb adds r3, r7, #6 @@ -940,7 +940,7 @@ int main(void) 8000690: 4a53 ldr r2, [pc, #332] @ (80007e0 ) 8000692: 0019 movs r1, r3 8000694: 0010 movs r0, r2 - 8000696: f001 fd19 bl 80020cc + 8000696: f001 fd5b bl 8002150 800069a: 1e03 subs r3, r0, #0 800069c: d10c bne.n 80006b8 800069e: 1dbb adds r3, r7, #6 @@ -966,7 +966,7 @@ int main(void) 80006bc: 4a48 ldr r2, [pc, #288] @ (80007e0 ) 80006be: 0019 movs r1, r3 80006c0: 0010 movs r0, r2 - 80006c2: f001 fd03 bl 80020cc + 80006c2: f001 fd45 bl 8002150 80006c6: 1e03 subs r3, r0, #0 80006c8: d102 bne.n 80006d0 80006ca: 4b43 ldr r3, [pc, #268] @ (80007d8 ) @@ -992,7 +992,7 @@ int main(void) 80006e6: 4a3e ldr r2, [pc, #248] @ (80007e0 ) 80006e8: 0019 movs r1, r3 80006ea: 0010 movs r0, r2 - 80006ec: f001 fcee bl 80020cc + 80006ec: f001 fd30 bl 8002150 80006f0: 1e03 subs r3, r0, #0 80006f2: d004 beq.n 80006fe 80006f4: 1d3b adds r3, r7, #4 @@ -1009,7 +1009,7 @@ int main(void) 8000702: 4a37 ldr r2, [pc, #220] @ (80007e0 ) 8000704: 0019 movs r1, r3 8000706: 0010 movs r0, r2 - 8000708: f001 fce0 bl 80020cc + 8000708: f001 fd22 bl 8002150 800070c: 1e03 subs r3, r0, #0 800070e: d108 bne.n 8000722 8000710: 1d3b adds r3, r7, #4 @@ -1031,7 +1031,7 @@ int main(void) 8000726: 4a2e ldr r2, [pc, #184] @ (80007e0 ) 8000728: 0019 movs r1, r3 800072a: 0010 movs r0, r2 - 800072c: f001 fcce bl 80020cc + 800072c: f001 fd10 bl 8002150 8000730: 1e03 subs r3, r0, #0 8000732: d102 bne.n 800073a 8000734: 4b2c ldr r3, [pc, #176] @ (80007e8 ) @@ -1155,14 +1155,14 @@ void SystemClock_Config(void) 800080c: 231c movs r3, #28 800080e: 001a movs r2, r3 8000810: 2100 movs r1, #0 - 8000812: f004 fa91 bl 8004d38 + 8000812: f004 fad3 bl 8004dbc RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000816: 003b movs r3, r7 8000818: 0018 movs r0, r3 800081a: 2314 movs r3, #20 800081c: 001a movs r2, r3 800081e: 2100 movs r1, #0 - 8000820: f004 fa8a bl 8004d38 + 8000820: f004 facc bl 8004dbc __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_1); 8000824: 4b1c ldr r3, [pc, #112] @ (8000898 ) @@ -1198,12 +1198,12 @@ void SystemClock_Config(void) if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8000850: 193b adds r3, r7, r4 8000852: 0018 movs r0, r3 - 8000854: f001 fcb2 bl 80021bc + 8000854: f001 fcf4 bl 8002240 8000858: 1e03 subs r3, r0, #0 800085a: d001 beq.n 8000860 { Error_Handler(); - 800085c: f000 fc24 bl 80010a8 + 800085c: f000 fc66 bl 800112c } /** Initializes the CPU, AHB and APB buses clocks @@ -1234,12 +1234,12 @@ void SystemClock_Config(void) 800087e: 003b movs r3, r7 8000880: 2101 movs r1, #1 8000882: 0018 movs r0, r3 - 8000884: f001 fe7e bl 8002584 + 8000884: f001 fec0 bl 8002608 8000888: 1e03 subs r3, r0, #0 800088a: d001 beq.n 8000890 { Error_Handler(); - 800088c: f000 fc0c bl 80010a8 + 800088c: f000 fc4e bl 800112c } } 8000890: 46c0 nop @ (mov r8, r8) @@ -1270,7 +1270,7 @@ static void MX_TIM1_Init(void) 80008a8: 2310 movs r3, #16 80008aa: 001a movs r2, r3 80008ac: 2100 movs r1, #0 - 80008ae: f004 fa43 bl 8004d38 + 80008ae: f004 fa85 bl 8004dbc TIM_MasterConfigTypeDef sMasterConfig = {0}; 80008b2: 2354 movs r3, #84 @ 0x54 80008b4: 18fb adds r3, r7, r3 @@ -1278,7 +1278,7 @@ static void MX_TIM1_Init(void) 80008b8: 230c movs r3, #12 80008ba: 001a movs r2, r3 80008bc: 2100 movs r1, #0 - 80008be: f004 fa3b bl 8004d38 + 80008be: f004 fa7d bl 8004dbc TIM_OC_InitTypeDef sConfigOC = {0}; 80008c2: 2338 movs r3, #56 @ 0x38 80008c4: 18fb adds r3, r7, r3 @@ -1286,14 +1286,14 @@ static void MX_TIM1_Init(void) 80008c8: 231c movs r3, #28 80008ca: 001a movs r2, r3 80008cc: 2100 movs r1, #0 - 80008ce: f004 fa33 bl 8004d38 + 80008ce: f004 fa75 bl 8004dbc TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0}; 80008d2: 1d3b adds r3, r7, #4 80008d4: 0018 movs r0, r3 80008d6: 2334 movs r3, #52 @ 0x34 80008d8: 001a movs r2, r3 80008da: 2100 movs r1, #0 - 80008dc: f004 fa2c bl 8004d38 + 80008dc: f004 fa6e bl 8004dbc /* USER CODE BEGIN TIM1_Init 1 */ @@ -1330,12 +1330,12 @@ static void MX_TIM1_Init(void) if (HAL_TIM_Base_Init(&htim1) != HAL_OK) 800090c: 4b57 ldr r3, [pc, #348] @ (8000a6c ) 800090e: 0018 movs r0, r3 - 8000910: f002 f8b4 bl 8002a7c + 8000910: f002 f8f6 bl 8002b00 8000914: 1e03 subs r3, r0, #0 8000916: d001 beq.n 800091c { Error_Handler(); - 8000918: f000 fbc6 bl 80010a8 + 8000918: f000 fc08 bl 800112c } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 800091c: 2160 movs r1, #96 @ 0x60 @@ -1348,22 +1348,22 @@ static void MX_TIM1_Init(void) 8000928: 4b50 ldr r3, [pc, #320] @ (8000a6c ) 800092a: 0011 movs r1, r2 800092c: 0018 movs r0, r3 - 800092e: f002 fc0d bl 800314c + 800092e: f002 fc4f bl 80031d0 8000932: 1e03 subs r3, r0, #0 8000934: d001 beq.n 800093a { Error_Handler(); - 8000936: f000 fbb7 bl 80010a8 + 8000936: f000 fbf9 bl 800112c } if (HAL_TIM_PWM_Init(&htim1) != HAL_OK) 800093a: 4b4c ldr r3, [pc, #304] @ (8000a6c ) 800093c: 0018 movs r0, r3 - 800093e: f002 f8f5 bl 8002b2c + 800093e: f002 f937 bl 8002bb0 8000942: 1e03 subs r3, r0, #0 8000944: d001 beq.n 800094a { Error_Handler(); - 8000946: f000 fbaf bl 80010a8 + 8000946: f000 fbf1 bl 800112c } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 800094a: 2154 movs r1, #84 @ 0x54 @@ -1383,12 +1383,12 @@ static void MX_TIM1_Init(void) 8000960: 4b42 ldr r3, [pc, #264] @ (8000a6c ) 8000962: 0011 movs r1, r2 8000964: 0018 movs r0, r3 - 8000966: f003 f89b bl 8003aa0 + 8000966: f003 f8dd bl 8003b24 800096a: 1e03 subs r3, r0, #0 800096c: d001 beq.n 8000972 { Error_Handler(); - 800096e: f000 fb9b bl 80010a8 + 800096e: f000 fbdd bl 800112c } sConfigOC.OCMode = TIM_OCMODE_PWM1; 8000972: 2138 movs r1, #56 @ 0x38 @@ -1424,12 +1424,12 @@ static void MX_TIM1_Init(void) 80009a0: 4b32 ldr r3, [pc, #200] @ (8000a6c ) 80009a2: 2200 movs r2, #0 80009a4: 0018 movs r0, r3 - 80009a6: f002 fad1 bl 8002f4c + 80009a6: f002 fb13 bl 8002fd0 80009aa: 1e03 subs r3, r0, #0 80009ac: d001 beq.n 80009b2 { Error_Handler(); - 80009ae: f000 fb7b bl 80010a8 + 80009ae: f000 fbbd bl 800112c } if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 80009b2: 2338 movs r3, #56 @ 0x38 @@ -1437,12 +1437,12 @@ static void MX_TIM1_Init(void) 80009b6: 4b2d ldr r3, [pc, #180] @ (8000a6c ) 80009b8: 2204 movs r2, #4 80009ba: 0018 movs r0, r3 - 80009bc: f002 fac6 bl 8002f4c + 80009bc: f002 fb08 bl 8002fd0 80009c0: 1e03 subs r3, r0, #0 80009c2: d001 beq.n 80009c8 { Error_Handler(); - 80009c4: f000 fb70 bl 80010a8 + 80009c4: f000 fbb2 bl 800112c } if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 80009c8: 2338 movs r3, #56 @ 0x38 @@ -1450,12 +1450,12 @@ static void MX_TIM1_Init(void) 80009cc: 4b27 ldr r3, [pc, #156] @ (8000a6c ) 80009ce: 2208 movs r2, #8 80009d0: 0018 movs r0, r3 - 80009d2: f002 fabb bl 8002f4c + 80009d2: f002 fafd bl 8002fd0 80009d6: 1e03 subs r3, r0, #0 80009d8: d001 beq.n 80009de { Error_Handler(); - 80009da: f000 fb65 bl 80010a8 + 80009da: f000 fba7 bl 800112c } if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) 80009de: 2338 movs r3, #56 @ 0x38 @@ -1463,12 +1463,12 @@ static void MX_TIM1_Init(void) 80009e2: 4b22 ldr r3, [pc, #136] @ (8000a6c ) 80009e4: 220c movs r2, #12 80009e6: 0018 movs r0, r3 - 80009e8: f002 fab0 bl 8002f4c + 80009e8: f002 faf2 bl 8002fd0 80009ec: 1e03 subs r3, r0, #0 80009ee: d001 beq.n 80009f4 { Error_Handler(); - 80009f0: f000 fb5a bl 80010a8 + 80009f0: f000 fb9c bl 800112c } sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE; 80009f4: 1d3b adds r3, r7, #4 @@ -1529,12 +1529,12 @@ static void MX_TIM1_Init(void) 8000a48: 4b08 ldr r3, [pc, #32] @ (8000a6c ) 8000a4a: 0011 movs r1, r2 8000a4c: 0018 movs r0, r3 - 8000a4e: f003 f88f bl 8003b70 + 8000a4e: f003 f8d1 bl 8003bf4 8000a52: 1e03 subs r3, r0, #0 8000a54: d001 beq.n 8000a5a { Error_Handler(); - 8000a56: f000 fb27 bl 80010a8 + 8000a56: f000 fb69 bl 800112c } /* USER CODE BEGIN TIM1_Init 2 */ @@ -1542,7 +1542,7 @@ static void MX_TIM1_Init(void) HAL_TIM_MspPostInit(&htim1); 8000a5a: 4b04 ldr r3, [pc, #16] @ (8000a6c ) 8000a5c: 0018 movs r0, r3 - 8000a5e: f000 fc11 bl 8001284 + 8000a5e: f000 fc53 bl 8001308 } 8000a62: 46c0 nop @ (mov r8, r8) @@ -1575,14 +1575,14 @@ static void MX_TIM3_Init(void) 8000a80: 2324 movs r3, #36 @ 0x24 8000a82: 001a movs r2, r3 8000a84: 2100 movs r1, #0 - 8000a86: f004 f957 bl 8004d38 + 8000a86: f004 f999 bl 8004dbc TIM_MasterConfigTypeDef sMasterConfig = {0}; 8000a8a: 003b movs r3, r7 8000a8c: 0018 movs r0, r3 8000a8e: 230c movs r3, #12 8000a90: 001a movs r2, r3 8000a92: 2100 movs r1, #0 - 8000a94: f004 f950 bl 8004d38 + 8000a94: f004 f992 bl 8004dbc /* USER CODE BEGIN TIM3_Init 1 */ @@ -1653,12 +1653,12 @@ static void MX_TIM3_Init(void) 8000af6: 4b0e ldr r3, [pc, #56] @ (8000b30 ) 8000af8: 0011 movs r1, r2 8000afa: 0018 movs r0, r3 - 8000afc: f002 f876 bl 8002bec + 8000afc: f002 f8b8 bl 8002c70 8000b00: 1e03 subs r3, r0, #0 8000b02: d001 beq.n 8000b08 { Error_Handler(); - 8000b04: f000 fad0 bl 80010a8 + 8000b04: f000 fb12 bl 800112c } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8000b08: 003b movs r3, r7 @@ -1673,12 +1673,12 @@ static void MX_TIM3_Init(void) 8000b16: 4b06 ldr r3, [pc, #24] @ (8000b30 ) 8000b18: 0011 movs r1, r2 8000b1a: 0018 movs r0, r3 - 8000b1c: f002 ffc0 bl 8003aa0 + 8000b1c: f003 f802 bl 8003b24 8000b20: 1e03 subs r3, r0, #0 8000b22: d001 beq.n 8000b28 { Error_Handler(); - 8000b24: f000 fac0 bl 80010a8 + 8000b24: f000 fb02 bl 800112c } /* USER CODE BEGIN TIM3_Init 2 */ @@ -1735,12 +1735,12 @@ static void MX_TIM14_Init(void) if (HAL_TIM_Base_Init(&htim14) != HAL_OK) 8000b66: 4b05 ldr r3, [pc, #20] @ (8000b7c ) 8000b68: 0018 movs r0, r3 - 8000b6a: f001 ff87 bl 8002a7c + 8000b6a: f001 ffc9 bl 8002b00 8000b6e: 1e03 subs r3, r0, #0 8000b70: d001 beq.n 8000b76 { Error_Handler(); - 8000b72: f000 fa99 bl 80010a8 + 8000b72: f000 fadb bl 800112c } /* USER CODE BEGIN TIM14_Init 2 */ @@ -1798,12 +1798,12 @@ static void MX_TIM16_Init(void) if (HAL_TIM_Base_Init(&htim16) != HAL_OK) 8000bb2: 4b05 ldr r3, [pc, #20] @ (8000bc8 ) 8000bb4: 0018 movs r0, r3 - 8000bb6: f001 ff61 bl 8002a7c + 8000bb6: f001 ffa3 bl 8002b00 8000bba: 1e03 subs r3, r0, #0 8000bbc: d001 beq.n 8000bc2 { Error_Handler(); - 8000bbe: f000 fa73 bl 80010a8 + 8000bbe: f000 fab5 bl 800112c } /* USER CODE BEGIN TIM16_Init 2 */ @@ -1863,12 +1863,12 @@ static void MX_TIM17_Init(void) if (HAL_TIM_Base_Init(&htim17) != HAL_OK) 8000c06: 4b05 ldr r3, [pc, #20] @ (8000c1c ) 8000c08: 0018 movs r0, r3 - 8000c0a: f001 ff37 bl 8002a7c + 8000c0a: f001 ff79 bl 8002b00 8000c0e: 1e03 subs r3, r0, #0 8000c10: d001 beq.n 8000c16 { Error_Handler(); - 8000c12: f000 fa49 bl 80010a8 + 8000c12: f000 fa8b bl 800112c } /* USER CODE BEGIN TIM17_Init 2 */ @@ -1945,44 +1945,44 @@ static void MX_USART1_UART_Init(void) if (HAL_UART_Init(&huart1) != HAL_OK) 8000c74: 4b12 ldr r3, [pc, #72] @ (8000cc0 ) 8000c76: 0018 movs r0, r3 - 8000c78: f003 f82e bl 8003cd8 + 8000c78: f003 f870 bl 8003d5c 8000c7c: 1e03 subs r3, r0, #0 8000c7e: d001 beq.n 8000c84 { Error_Handler(); - 8000c80: f000 fa12 bl 80010a8 + 8000c80: f000 fa54 bl 800112c } if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 8000c84: 4b0e ldr r3, [pc, #56] @ (8000cc0 ) 8000c86: 2100 movs r1, #0 8000c88: 0018 movs r0, r3 - 8000c8a: f003 ff0d bl 8004aa8 + 8000c8a: f003 ff4f bl 8004b2c 8000c8e: 1e03 subs r3, r0, #0 8000c90: d001 beq.n 8000c96 { Error_Handler(); - 8000c92: f000 fa09 bl 80010a8 + 8000c92: f000 fa4b bl 800112c } if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 8000c96: 4b0a ldr r3, [pc, #40] @ (8000cc0 ) 8000c98: 2100 movs r1, #0 8000c9a: 0018 movs r0, r3 - 8000c9c: f003 ff44 bl 8004b28 + 8000c9c: f003 ff86 bl 8004bac 8000ca0: 1e03 subs r3, r0, #0 8000ca2: d001 beq.n 8000ca8 { Error_Handler(); - 8000ca4: f000 fa00 bl 80010a8 + 8000ca4: f000 fa42 bl 800112c } if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK) 8000ca8: 4b05 ldr r3, [pc, #20] @ (8000cc0 ) 8000caa: 0018 movs r0, r3 - 8000cac: f003 fec2 bl 8004a34 + 8000cac: f003 ff04 bl 8004ab8 8000cb0: 1e03 subs r3, r0, #0 8000cb2: d001 beq.n 8000cb8 { Error_Handler(); - 8000cb4: f000 f9f8 bl 80010a8 + 8000cb4: f000 fa3a bl 800112c } /* USER CODE BEGIN USART1_Init 2 */ @@ -2060,12 +2060,12 @@ static void MX_USART2_UART_Init(void) 8000d12: 2300 movs r3, #0 8000d14: 2200 movs r2, #0 8000d16: 2100 movs r1, #0 - 8000d18: f003 fe1a bl 8004950 + 8000d18: f003 fe5c bl 80049d4 8000d1c: 1e03 subs r3, r0, #0 8000d1e: d001 beq.n 8000d24 { Error_Handler(); - 8000d20: f000 f9c2 bl 80010a8 + 8000d20: f000 fa04 bl 800112c } if (HAL_UARTEx_SetTxFifoThreshold(&huart2, UART_TXFIFO_THRESHOLD_1_2) != HAL_OK) 8000d24: 2380 movs r3, #128 @ 0x80 @@ -2073,12 +2073,12 @@ static void MX_USART2_UART_Init(void) 8000d28: 4b0f ldr r3, [pc, #60] @ (8000d68 ) 8000d2a: 0011 movs r1, r2 8000d2c: 0018 movs r0, r3 - 8000d2e: f003 febb bl 8004aa8 + 8000d2e: f003 fefd bl 8004b2c 8000d32: 1e03 subs r3, r0, #0 8000d34: d001 beq.n 8000d3a { Error_Handler(); - 8000d36: f000 f9b7 bl 80010a8 + 8000d36: f000 f9f9 bl 800112c } if (HAL_UARTEx_SetRxFifoThreshold(&huart2, UART_RXFIFO_THRESHOLD_1_2) != HAL_OK) 8000d3a: 2380 movs r3, #128 @ 0x80 @@ -2086,22 +2086,22 @@ static void MX_USART2_UART_Init(void) 8000d3e: 4b0a ldr r3, [pc, #40] @ (8000d68 ) 8000d40: 0011 movs r1, r2 8000d42: 0018 movs r0, r3 - 8000d44: f003 fef0 bl 8004b28 + 8000d44: f003 ff32 bl 8004bac 8000d48: 1e03 subs r3, r0, #0 8000d4a: d001 beq.n 8000d50 { Error_Handler(); - 8000d4c: f000 f9ac bl 80010a8 + 8000d4c: f000 f9ee bl 800112c } if (HAL_UARTEx_DisableFifoMode(&huart2) != HAL_OK) 8000d50: 4b05 ldr r3, [pc, #20] @ (8000d68 ) 8000d52: 0018 movs r0, r3 - 8000d54: f003 fe6e bl 8004a34 + 8000d54: f003 feb0 bl 8004ab8 8000d58: 1e03 subs r3, r0, #0 8000d5a: d001 beq.n 8000d60 { Error_Handler(); - 8000d5c: f000 f9a4 bl 80010a8 + 8000d5c: f000 f9e6 bl 800112c } /* USER CODE BEGIN USART2_Init 2 */ @@ -2147,19 +2147,19 @@ static void MX_DMA_Init(void) 8000d8e: 2200 movs r2, #0 8000d90: 2100 movs r1, #0 8000d92: 2009 movs r0, #9 - 8000d94: f000 fda2 bl 80018dc + 8000d94: f000 fde4 bl 8001960 HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); 8000d98: 2009 movs r0, #9 - 8000d9a: f000 fdb4 bl 8001906 + 8000d9a: f000 fdf6 bl 800198a /* DMA1_Channel2_3_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel2_3_IRQn, 0, 0); 8000d9e: 2200 movs r2, #0 8000da0: 2100 movs r1, #0 8000da2: 200a movs r0, #10 - 8000da4: f000 fd9a bl 80018dc + 8000da4: f000 fddc bl 8001960 HAL_NVIC_EnableIRQ(DMA1_Channel2_3_IRQn); 8000da8: 200a movs r0, #10 - 8000daa: f000 fdac bl 8001906 + 8000daa: f000 fdee bl 800198a } 8000dae: 46c0 nop @ (mov r8, r8) @@ -2186,7 +2186,7 @@ static void MX_GPIO_Init(void) 8000dc8: 2314 movs r3, #20 8000dca: 001a movs r2, r3 8000dcc: 2100 movs r1, #0 - 8000dce: f003 ffb3 bl 8004d38 + 8000dce: f003 fff5 bl 8004dbc /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ @@ -2252,7 +2252,7 @@ static void MX_GPIO_Init(void) 8000e36: 05db lsls r3, r3, #23 8000e38: 2200 movs r2, #0 8000e3a: 0018 movs r0, r3 - 8000e3c: f001 f963 bl 8002106 + 8000e3c: f001 f9a5 bl 800218a /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, LED_R_Pin|LED_B_Pin|LED_G_Pin, GPIO_PIN_RESET); @@ -2260,7 +2260,7 @@ static void MX_GPIO_Init(void) 8000e42: 2200 movs r2, #0 8000e44: 2138 movs r1, #56 @ 0x38 8000e46: 0018 movs r0, r3 - 8000e48: f001 f95d bl 8002106 + 8000e48: f001 f99f bl 800218a /*Configure GPIO pins : USART2_NRE_Pin ONEWIRE_Pin */ GPIO_InitStruct.Pin = USART2_NRE_Pin|ONEWIRE_Pin; @@ -2285,7 +2285,7 @@ static void MX_GPIO_Init(void) 8000e68: 05db lsls r3, r3, #23 8000e6a: 0011 movs r1, r2 8000e6c: 0018 movs r0, r3 - 8000e6e: f000 ffbb bl 8001de8 + 8000e6e: f000 fffd bl 8001e6c /*Configure GPIO pins : LED_R_Pin LED_B_Pin LED_G_Pin */ GPIO_InitStruct.Pin = LED_R_Pin|LED_B_Pin|LED_G_Pin; @@ -2309,7 +2309,7 @@ static void MX_GPIO_Init(void) 8000e8c: 4a12 ldr r2, [pc, #72] @ (8000ed8 ) 8000e8e: 0019 movs r1, r3 8000e90: 0010 movs r0, r2 - 8000e92: f000 ffa9 bl 8001de8 + 8000e92: f000 ffeb bl 8001e6c /*Configure GPIO pins : SW2_Pin SW1_Pin */ GPIO_InitStruct.Pin = SW2_Pin|SW1_Pin; @@ -2331,17 +2331,17 @@ static void MX_GPIO_Init(void) 8000eae: 4a0a ldr r2, [pc, #40] @ (8000ed8 ) 8000eb0: 0019 movs r1, r3 8000eb2: 0010 movs r0, r2 - 8000eb4: f000 ff98 bl 8001de8 + 8000eb4: f000 ffda bl 8001e6c /* EXTI interrupt init*/ HAL_NVIC_SetPriority(EXTI4_15_IRQn, 0, 0); 8000eb8: 2200 movs r2, #0 8000eba: 2100 movs r1, #0 8000ebc: 2007 movs r0, #7 - 8000ebe: f000 fd0d bl 80018dc + 8000ebe: f000 fd4f bl 8001960 HAL_NVIC_EnableIRQ(EXTI4_15_IRQn); 8000ec2: 2007 movs r0, #7 - 8000ec4: f000 fd1f bl 8001906 + 8000ec4: f000 fd61 bl 800198a /* USER CODE BEGIN MX_GPIO_Init_2 */ @@ -2363,3330 +2363,3336 @@ static void MX_GPIO_Init(void) void HAL_TIM_PeriodElapsedCallback (TIM_HandleTypeDef * htim) { 8000ee0: b580 push {r7, lr} - 8000ee2: b084 sub sp, #16 + 8000ee2: b086 sub sp, #24 8000ee4: af00 add r7, sp, #0 8000ee6: 6078 str r0, [r7, #4] if (htim == &htim14) // encoder check timer (runs at 20khz) 8000ee8: 687a ldr r2, [r7, #4] - 8000eea: 4b3f ldr r3, [pc, #252] @ (8000fe8 ) + 8000eea: 4b4c ldr r3, [pc, #304] @ (800101c ) 8000eec: 429a cmp r2, r3 - 8000eee: d162 bne.n 8000fb6 + 8000eee: d000 beq.n 8000ef2 + 8000ef0: e07c b.n 8000fec { uint16_t count = htim3.Instance->CNT; - 8000ef0: 4b3e ldr r3, [pc, #248] @ (8000fec ) - 8000ef2: 681b ldr r3, [r3, #0] - 8000ef4: 6a5a ldr r2, [r3, #36] @ 0x24 - 8000ef6: 210e movs r1, #14 - 8000ef8: 187b adds r3, r7, r1 - 8000efa: 801a strh r2, [r3, #0] + 8000ef2: 4b4b ldr r3, [pc, #300] @ (8001020 ) + 8000ef4: 681b ldr r3, [r3, #0] + 8000ef6: 6a5a ldr r2, [r3, #36] @ 0x24 + 8000ef8: 2116 movs r1, #22 + 8000efa: 187b adds r3, r7, r1 + 8000efc: 801a strh r2, [r3, #0] if ((encoder_previous > (CNT_MAX-CNT_LIMIT_ZONE)) && (count < CNT_LIMIT_ZONE)) // positive turnaround - 8000efc: 4b3c ldr r3, [pc, #240] @ (8000ff0 ) - 8000efe: 881b ldrh r3, [r3, #0] - 8000f00: 4a3c ldr r2, [pc, #240] @ (8000ff4 ) - 8000f02: 4293 cmp r3, r2 - 8000f04: d90b bls.n 8000f1e - 8000f06: 187b adds r3, r7, r1 - 8000f08: 881a ldrh r2, [r3, #0] - 8000f0a: 23fa movs r3, #250 @ 0xfa - 8000f0c: 009b lsls r3, r3, #2 - 8000f0e: 429a cmp r2, r3 - 8000f10: d205 bcs.n 8000f1e + 8000efe: 4b49 ldr r3, [pc, #292] @ (8001024 ) + 8000f00: 881b ldrh r3, [r3, #0] + 8000f02: 4a49 ldr r2, [pc, #292] @ (8001028 ) + 8000f04: 4293 cmp r3, r2 + 8000f06: d90b bls.n 8000f20 + 8000f08: 187b adds r3, r7, r1 + 8000f0a: 881a ldrh r2, [r3, #0] + 8000f0c: 23fa movs r3, #250 @ 0xfa + 8000f0e: 009b lsls r3, r3, #2 + 8000f10: 429a cmp r2, r3 + 8000f12: d205 bcs.n 8000f20 { encoder_count_extra ++; - 8000f12: 4b39 ldr r3, [pc, #228] @ (8000ff8 ) - 8000f14: 681b ldr r3, [r3, #0] - 8000f16: 1c5a adds r2, r3, #1 - 8000f18: 4b37 ldr r3, [pc, #220] @ (8000ff8 ) - 8000f1a: 601a str r2, [r3, #0] + 8000f14: 4b45 ldr r3, [pc, #276] @ (800102c ) + 8000f16: 681b ldr r3, [r3, #0] + 8000f18: 1c5a adds r2, r3, #1 + 8000f1a: 4b44 ldr r3, [pc, #272] @ (800102c ) + 8000f1c: 601a str r2, [r3, #0] return; - 8000f1c: e060 b.n 8000fe0 + 8000f1e: e07a b.n 8001016 } else if ((encoder_previous < CNT_LIMIT_ZONE) && (count > CNT_MAX-CNT_LIMIT_ZONE)) // negative turnaround - 8000f1e: 4b34 ldr r3, [pc, #208] @ (8000ff0 ) - 8000f20: 881a ldrh r2, [r3, #0] - 8000f22: 23fa movs r3, #250 @ 0xfa - 8000f24: 009b lsls r3, r3, #2 - 8000f26: 429a cmp r2, r3 - 8000f28: d20b bcs.n 8000f42 - 8000f2a: 230e movs r3, #14 - 8000f2c: 18fb adds r3, r7, r3 - 8000f2e: 881b ldrh r3, [r3, #0] - 8000f30: 4a30 ldr r2, [pc, #192] @ (8000ff4 ) - 8000f32: 4293 cmp r3, r2 - 8000f34: d905 bls.n 8000f42 + 8000f20: 4b40 ldr r3, [pc, #256] @ (8001024 ) + 8000f22: 881a ldrh r2, [r3, #0] + 8000f24: 23fa movs r3, #250 @ 0xfa + 8000f26: 009b lsls r3, r3, #2 + 8000f28: 429a cmp r2, r3 + 8000f2a: d20b bcs.n 8000f44 + 8000f2c: 2316 movs r3, #22 + 8000f2e: 18fb adds r3, r7, r3 + 8000f30: 881b ldrh r3, [r3, #0] + 8000f32: 4a3d ldr r2, [pc, #244] @ (8001028 ) + 8000f34: 4293 cmp r3, r2 + 8000f36: d905 bls.n 8000f44 { encoder_count_extra --; - 8000f36: 4b30 ldr r3, [pc, #192] @ (8000ff8 ) - 8000f38: 681b ldr r3, [r3, #0] - 8000f3a: 1e5a subs r2, r3, #1 - 8000f3c: 4b2e ldr r3, [pc, #184] @ (8000ff8 ) - 8000f3e: 601a str r2, [r3, #0] + 8000f38: 4b3c ldr r3, [pc, #240] @ (800102c ) + 8000f3a: 681b ldr r3, [r3, #0] + 8000f3c: 1e5a subs r2, r3, #1 + 8000f3e: 4b3b ldr r3, [pc, #236] @ (800102c ) + 8000f40: 601a str r2, [r3, #0] return; - 8000f40: e04e b.n 8000fe0 + 8000f42: e068 b.n 8001016 } total_count = (encoder_count_extra * CNT_MAX) + count; - 8000f42: 4b2d ldr r3, [pc, #180] @ (8000ff8 ) - 8000f44: 681a ldr r2, [r3, #0] - 8000f46: 0013 movs r3, r2 - 8000f48: 041b lsls r3, r3, #16 - 8000f4a: 1a9a subs r2, r3, r2 - 8000f4c: 230e movs r3, #14 - 8000f4e: 18fb adds r3, r7, r3 - 8000f50: 881b ldrh r3, [r3, #0] - 8000f52: 18d2 adds r2, r2, r3 - 8000f54: 4b29 ldr r3, [pc, #164] @ (8000ffc ) - 8000f56: 601a str r2, [r3, #0] + 8000f44: 4b39 ldr r3, [pc, #228] @ (800102c ) + 8000f46: 681a ldr r2, [r3, #0] + 8000f48: 0013 movs r3, r2 + 8000f4a: 041b lsls r3, r3, #16 + 8000f4c: 1a9a subs r2, r3, r2 + 8000f4e: 2316 movs r3, #22 + 8000f50: 18fb adds r3, r7, r3 + 8000f52: 881b ldrh r3, [r3, #0] + 8000f54: 18d2 adds r2, r2, r3 + 8000f56: 4b36 ldr r3, [pc, #216] @ (8001030 ) + 8000f58: 601a str r2, [r3, #0] if (total_count > INT32_MAX/2) - 8000f58: 4b28 ldr r3, [pc, #160] @ (8000ffc ) - 8000f5a: 681a ldr r2, [r3, #0] - 8000f5c: 2380 movs r3, #128 @ 0x80 - 8000f5e: 05db lsls r3, r3, #23 - 8000f60: 429a cmp r2, r3 - 8000f62: db0b blt.n 8000f7c + 8000f5a: 4b35 ldr r3, [pc, #212] @ (8001030 ) + 8000f5c: 681a ldr r2, [r3, #0] + 8000f5e: 2380 movs r3, #128 @ 0x80 + 8000f60: 05db lsls r3, r3, #23 + 8000f62: 429a cmp r2, r3 + 8000f64: db0b blt.n 8000f7e { total_count-= INT32_MAX/4; - 8000f64: 4b25 ldr r3, [pc, #148] @ (8000ffc ) - 8000f66: 681b ldr r3, [r3, #0] - 8000f68: 4925 ldr r1, [pc, #148] @ (8001000 ) - 8000f6a: 185a adds r2, r3, r1 - 8000f6c: 4b23 ldr r3, [pc, #140] @ (8000ffc ) - 8000f6e: 601a str r2, [r3, #0] + 8000f66: 4b32 ldr r3, [pc, #200] @ (8001030 ) + 8000f68: 681b ldr r3, [r3, #0] + 8000f6a: 4932 ldr r1, [pc, #200] @ (8001034 ) + 8000f6c: 185a adds r2, r3, r1 + 8000f6e: 4b30 ldr r3, [pc, #192] @ (8001030 ) + 8000f70: 601a str r2, [r3, #0] target_count-= INT32_MAX/4; - 8000f70: 4b24 ldr r3, [pc, #144] @ (8001004 ) - 8000f72: 681b ldr r3, [r3, #0] - 8000f74: 185a adds r2, r3, r1 - 8000f76: 4b23 ldr r3, [pc, #140] @ (8001004 ) - 8000f78: 601a str r2, [r3, #0] - 8000f7a: e010 b.n 8000f9e + 8000f72: 4b31 ldr r3, [pc, #196] @ (8001038 ) + 8000f74: 681b ldr r3, [r3, #0] + 8000f76: 185a adds r2, r3, r1 + 8000f78: 4b2f ldr r3, [pc, #188] @ (8001038 ) + 8000f7a: 601a str r2, [r3, #0] + 8000f7c: e010 b.n 8000fa0 } else if (total_count < INT32_MIN/2) - 8000f7c: 4b1f ldr r3, [pc, #124] @ (8000ffc ) - 8000f7e: 681a ldr r2, [r3, #0] - 8000f80: 23c0 movs r3, #192 @ 0xc0 - 8000f82: 061b lsls r3, r3, #24 - 8000f84: 429a cmp r2, r3 - 8000f86: da0a bge.n 8000f9e + 8000f7e: 4b2c ldr r3, [pc, #176] @ (8001030 ) + 8000f80: 681a ldr r2, [r3, #0] + 8000f82: 23c0 movs r3, #192 @ 0xc0 + 8000f84: 061b lsls r3, r3, #24 + 8000f86: 429a cmp r2, r3 + 8000f88: da0a bge.n 8000fa0 { total_count+= INT32_MAX/4; - 8000f88: 4b1c ldr r3, [pc, #112] @ (8000ffc ) - 8000f8a: 681b ldr r3, [r3, #0] - 8000f8c: 491e ldr r1, [pc, #120] @ (8001008 ) - 8000f8e: 185a adds r2, r3, r1 - 8000f90: 4b1a ldr r3, [pc, #104] @ (8000ffc ) - 8000f92: 601a str r2, [r3, #0] + 8000f8a: 4b29 ldr r3, [pc, #164] @ (8001030 ) + 8000f8c: 681b ldr r3, [r3, #0] + 8000f8e: 492b ldr r1, [pc, #172] @ (800103c ) + 8000f90: 185a adds r2, r3, r1 + 8000f92: 4b27 ldr r3, [pc, #156] @ (8001030 ) + 8000f94: 601a str r2, [r3, #0] target_count+= INT32_MAX/4; - 8000f94: 4b1b ldr r3, [pc, #108] @ (8001004 ) - 8000f96: 681b ldr r3, [r3, #0] - 8000f98: 185a adds r2, r3, r1 - 8000f9a: 4b1a ldr r3, [pc, #104] @ (8001004 ) - 8000f9c: 601a str r2, [r3, #0] + 8000f96: 4b28 ldr r3, [pc, #160] @ (8001038 ) + 8000f98: 681b ldr r3, [r3, #0] + 8000f9a: 185a adds r2, r3, r1 + 8000f9c: 4b26 ldr r3, [pc, #152] @ (8001038 ) + 8000f9e: 601a str r2, [r3, #0] } + + if (pid_add!=0) + 8000fa0: 4b27 ldr r3, [pc, #156] @ (8001040 ) + 8000fa2: 681b ldr r3, [r3, #0] + 8000fa4: 2b00 cmp r3, #0 + 8000fa6: d00d beq.n 8000fc4 + { + int64_t temp = target_count + pid_add; + 8000fa8: 4b23 ldr r3, [pc, #140] @ (8001038 ) + 8000faa: 681a ldr r2, [r3, #0] + 8000fac: 4b24 ldr r3, [pc, #144] @ (8001040 ) + 8000fae: 681b ldr r3, [r3, #0] + 8000fb0: 18d3 adds r3, r2, r3 + 8000fb2: 60bb str r3, [r7, #8] + 8000fb4: 17db asrs r3, r3, #31 + 8000fb6: 60fb str r3, [r7, #12] + pid_add = 0; + 8000fb8: 4b21 ldr r3, [pc, #132] @ (8001040 ) + 8000fba: 2200 movs r2, #0 + 8000fbc: 601a str r2, [r3, #0] + } + else if(temp > (INT32_MAX-10000)) + { + //todo throw error + } + target_count = temp; + 8000fbe: 68ba ldr r2, [r7, #8] + 8000fc0: 4b1d ldr r3, [pc, #116] @ (8001038 ) + 8000fc2: 601a str r2, [r3, #0] + } motor_cmd = pid_update_motor(&motor_pid,target_count,total_count); - 8000f9e: 4b19 ldr r3, [pc, #100] @ (8001004 ) - 8000fa0: 6819 ldr r1, [r3, #0] - 8000fa2: 4b16 ldr r3, [pc, #88] @ (8000ffc ) - 8000fa4: 681a ldr r2, [r3, #0] - 8000fa6: 4b19 ldr r3, [pc, #100] @ (800100c ) - 8000fa8: 0018 movs r0, r3 - 8000faa: f7ff fa63 bl 8000474 - 8000fae: 0003 movs r3, r0 - 8000fb0: 001a movs r2, r3 - 8000fb2: 4b17 ldr r3, [pc, #92] @ (8001010 ) - 8000fb4: 601a str r2, [r3, #0] + 8000fc4: 4b1c ldr r3, [pc, #112] @ (8001038 ) + 8000fc6: 6819 ldr r1, [r3, #0] + 8000fc8: 4b19 ldr r3, [pc, #100] @ (8001030 ) + 8000fca: 681a ldr r2, [r3, #0] + 8000fcc: 4b1d ldr r3, [pc, #116] @ (8001044 ) + 8000fce: 0018 movs r0, r3 + 8000fd0: f7ff fa50 bl 8000474 + 8000fd4: 0003 movs r3, r0 + 8000fd6: 001a movs r2, r3 + 8000fd8: 4b1b ldr r3, [pc, #108] @ (8001048 ) + 8000fda: 601a str r2, [r3, #0] + set_Feeder_PWM(motor_cmd.pwm,motor_cmd.dir); + 8000fdc: 4b1a ldr r3, [pc, #104] @ (8001048 ) + 8000fde: 881a ldrh r2, [r3, #0] + 8000fe0: 4b19 ldr r3, [pc, #100] @ (8001048 ) + 8000fe2: 789b ldrb r3, [r3, #2] + 8000fe4: 0019 movs r1, r3 + 8000fe6: 0010 movs r0, r2 + 8000fe8: f000 f87a bl 80010e0 } if (htim == &htim3) return; // PWM timer - 8000fb6: 687a ldr r2, [r7, #4] - 8000fb8: 4b0c ldr r3, [pc, #48] @ (8000fec ) - 8000fba: 429a cmp r2, r3 - 8000fbc: d00f beq.n 8000fde + 8000fec: 687a ldr r2, [r7, #4] + 8000fee: 4b0c ldr r3, [pc, #48] @ (8001020 ) + 8000ff0: 429a cmp r2, r3 + 8000ff2: d00f beq.n 8001014 else if (htim == &htim3) // encoder overflow { // will this fire on rising / falling overflow the same ? } if (htim == &htim16) //SW1 timer - 8000fbe: 687a ldr r2, [r7, #4] - 8000fc0: 4b14 ldr r3, [pc, #80] @ (8001014 ) - 8000fc2: 429a cmp r2, r3 - 8000fc4: d103 bne.n 8000fce + 8000ff4: 687a ldr r2, [r7, #4] + 8000ff6: 4b15 ldr r3, [pc, #84] @ (800104c ) + 8000ff8: 429a cmp r2, r3 + 8000ffa: d103 bne.n 8001004 { sw1_pressed = 0; - 8000fc6: 4b14 ldr r3, [pc, #80] @ (8001018 ) - 8000fc8: 2200 movs r2, #0 - 8000fca: 701a strb r2, [r3, #0] - 8000fcc: e008 b.n 8000fe0 + 8000ffc: 4b14 ldr r3, [pc, #80] @ (8001050 ) + 8000ffe: 2200 movs r2, #0 + 8001000: 701a strb r2, [r3, #0] + 8001002: e008 b.n 8001016 //todo handle overflow after ~65seconds (48MHz / 48000) * } else if (htim == &htim17) //SW2 timer - 8000fce: 687a ldr r2, [r7, #4] - 8000fd0: 4b12 ldr r3, [pc, #72] @ (800101c ) - 8000fd2: 429a cmp r2, r3 - 8000fd4: d104 bne.n 8000fe0 + 8001004: 687a ldr r2, [r7, #4] + 8001006: 4b13 ldr r3, [pc, #76] @ (8001054 ) + 8001008: 429a cmp r2, r3 + 800100a: d104 bne.n 8001016 { //todo sw2_pressed = 0; - 8000fd6: 4b12 ldr r3, [pc, #72] @ (8001020 ) - 8000fd8: 2200 movs r2, #0 - 8000fda: 701a strb r2, [r3, #0] - 8000fdc: e000 b.n 8000fe0 + 800100c: 4b12 ldr r3, [pc, #72] @ (8001058 ) + 800100e: 2200 movs r2, #0 + 8001010: 701a strb r2, [r3, #0] + 8001012: e000 b.n 8001016 if (htim == &htim3) return; // PWM timer - 8000fde: 46c0 nop @ (mov r8, r8) + 8001014: 46c0 nop @ (mov r8, r8) } } - 8000fe0: 46bd mov sp, r7 - 8000fe2: b004 add sp, #16 - 8000fe4: bd80 pop {r7, pc} - 8000fe6: 46c0 nop @ (mov r8, r8) - 8000fe8: 200000d8 .word 0x200000d8 - 8000fec: 2000008c .word 0x2000008c - 8000ff0: 200003a4 .word 0x200003a4 - 8000ff4: 0000fc17 .word 0x0000fc17 - 8000ff8: 200003a0 .word 0x200003a0 - 8000ffc: 20000474 .word 0x20000474 - 8001000: e0000001 .word 0xe0000001 - 8001004: 20000478 .word 0x20000478 - 8001008: 1fffffff .word 0x1fffffff - 800100c: 20000480 .word 0x20000480 - 8001010: 200004a8 .word 0x200004a8 - 8001014: 20000124 .word 0x20000124 - 8001018: 2000039c .word 0x2000039c - 800101c: 20000170 .word 0x20000170 - 8001020: 2000039d .word 0x2000039d + 8001016: 46bd mov sp, r7 + 8001018: b006 add sp, #24 + 800101a: bd80 pop {r7, pc} + 800101c: 200000d8 .word 0x200000d8 + 8001020: 2000008c .word 0x2000008c + 8001024: 200003a4 .word 0x200003a4 + 8001028: 0000fc17 .word 0x0000fc17 + 800102c: 200003a0 .word 0x200003a0 + 8001030: 20000474 .word 0x20000474 + 8001034: e0000001 .word 0xe0000001 + 8001038: 20000478 .word 0x20000478 + 800103c: 1fffffff .word 0x1fffffff + 8001040: 200004ac .word 0x200004ac + 8001044: 20000480 .word 0x20000480 + 8001048: 200004a8 .word 0x200004a8 + 800104c: 20000124 .word 0x20000124 + 8001050: 2000039c .word 0x2000039c + 8001054: 20000170 .word 0x20000170 + 8001058: 2000039d .word 0x2000039d -08001024 : +0800105c : } } } void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { - 8001024: b580 push {r7, lr} - 8001026: b082 sub sp, #8 - 8001028: af00 add r7, sp, #0 - 800102a: 6078 str r0, [r7, #4] - 800102c: 000a movs r2, r1 - 800102e: 1cbb adds r3, r7, #2 - 8001030: 801a strh r2, [r3, #0] + 800105c: b580 push {r7, lr} + 800105e: b082 sub sp, #8 + 8001060: af00 add r7, sp, #0 + 8001062: 6078 str r0, [r7, #4] + 8001064: 000a movs r2, r1 + 8001066: 1cbb adds r3, r7, #2 + 8001068: 801a strh r2, [r3, #0] if (Size > 64) return; // todo error handling - 8001032: 1cbb adds r3, r7, #2 - 8001034: 881b ldrh r3, [r3, #0] - 8001036: 2b40 cmp r3, #64 @ 0x40 - 8001038: d823 bhi.n 8001082 + 800106a: 1cbb adds r3, r7, #2 + 800106c: 881b ldrh r3, [r3, #0] + 800106e: 2b40 cmp r3, #64 @ 0x40 + 8001070: d823 bhi.n 80010ba if (msg_buffer1_empty) - 800103a: 4b15 ldr r3, [pc, #84] @ (8001090 ) - 800103c: 781b ldrb r3, [r3, #0] - 800103e: 2b00 cmp r3, #0 - 8001040: d00a beq.n 8001058 + 8001072: 4b15 ldr r3, [pc, #84] @ (80010c8 ) + 8001074: 781b ldrb r3, [r3, #0] + 8001076: 2b00 cmp r3, #0 + 8001078: d00a beq.n 8001090 { memcpy(DMA_buffer,msg_buffer1,Size); - 8001042: 1cbb adds r3, r7, #2 - 8001044: 881a ldrh r2, [r3, #0] - 8001046: 4913 ldr r1, [pc, #76] @ (8001094 ) - 8001048: 4b13 ldr r3, [pc, #76] @ (8001098 ) - 800104a: 0018 movs r0, r3 - 800104c: f003 fea0 bl 8004d90 + 800107a: 1cbb adds r3, r7, #2 + 800107c: 881a ldrh r2, [r3, #0] + 800107e: 4913 ldr r1, [pc, #76] @ (80010cc ) + 8001080: 4b13 ldr r3, [pc, #76] @ (80010d0 ) + 8001082: 0018 movs r0, r3 + 8001084: f003 fec6 bl 8004e14 msg_buffer1_empty = 0; - 8001050: 4b0f ldr r3, [pc, #60] @ (8001090 ) - 8001052: 2200 movs r2, #0 - 8001054: 701a strb r2, [r3, #0] - 8001056: e00d b.n 8001074 + 8001088: 4b0f ldr r3, [pc, #60] @ (80010c8 ) + 800108a: 2200 movs r2, #0 + 800108c: 701a strb r2, [r3, #0] + 800108e: e00d b.n 80010ac } else if (msg_buffer2_empty) - 8001058: 4b10 ldr r3, [pc, #64] @ (800109c ) - 800105a: 781b ldrb r3, [r3, #0] - 800105c: 2b00 cmp r3, #0 - 800105e: d012 beq.n 8001086 + 8001090: 4b10 ldr r3, [pc, #64] @ (80010d4 ) + 8001092: 781b ldrb r3, [r3, #0] + 8001094: 2b00 cmp r3, #0 + 8001096: d012 beq.n 80010be { memcpy(DMA_buffer,msg_buffer2,Size); - 8001060: 1cbb adds r3, r7, #2 - 8001062: 881a ldrh r2, [r3, #0] - 8001064: 490e ldr r1, [pc, #56] @ (80010a0 ) - 8001066: 4b0c ldr r3, [pc, #48] @ (8001098 ) - 8001068: 0018 movs r0, r3 - 800106a: f003 fe91 bl 8004d90 + 8001098: 1cbb adds r3, r7, #2 + 800109a: 881a ldrh r2, [r3, #0] + 800109c: 490e ldr r1, [pc, #56] @ (80010d8 ) + 800109e: 4b0c ldr r3, [pc, #48] @ (80010d0 ) + 80010a0: 0018 movs r0, r3 + 80010a2: f003 feb7 bl 8004e14 msg_buffer2_empty = 0; - 800106e: 4b0b ldr r3, [pc, #44] @ (800109c ) - 8001070: 2200 movs r2, #0 - 8001072: 701a strb r2, [r3, #0] + 80010a6: 4b0b ldr r3, [pc, #44] @ (80010d4 ) + 80010a8: 2200 movs r2, #0 + 80010aa: 701a strb r2, [r3, #0] } else // no free buffer available todo error handling { return; } HAL_UARTEx_ReceiveToIdle_DMA(&huart2, DMA_buffer, 64); - 8001074: 4908 ldr r1, [pc, #32] @ (8001098 ) - 8001076: 4b0b ldr r3, [pc, #44] @ (80010a4 ) - 8001078: 2240 movs r2, #64 @ 0x40 - 800107a: 0018 movs r0, r3 - 800107c: f003 fd96 bl 8004bac - 8001080: e002 b.n 8001088 + 80010ac: 4908 ldr r1, [pc, #32] @ (80010d0 ) + 80010ae: 4b0b ldr r3, [pc, #44] @ (80010dc ) + 80010b0: 2240 movs r2, #64 @ 0x40 + 80010b2: 0018 movs r0, r3 + 80010b4: f003 fdbc bl 8004c30 + 80010b8: e002 b.n 80010c0 if (Size > 64) return; // todo error handling - 8001082: 46c0 nop @ (mov r8, r8) - 8001084: e000 b.n 8001088 + 80010ba: 46c0 nop @ (mov r8, r8) + 80010bc: e000 b.n 80010c0 return; - 8001086: 46c0 nop @ (mov r8, r8) + 80010be: 46c0 nop @ (mov r8, r8) } - 8001088: 46bd mov sp, r7 - 800108a: b002 add sp, #8 - 800108c: bd80 pop {r7, pc} - 800108e: 46c0 nop @ (mov r8, r8) - 8001090: 20000000 .word 0x20000000 - 8001094: 200003b4 .word 0x200003b4 - 8001098: 20000434 .word 0x20000434 - 800109c: 20000001 .word 0x20000001 - 80010a0: 200003f4 .word 0x200003f4 - 80010a4: 20000250 .word 0x20000250 + 80010c0: 46bd mov sp, r7 + 80010c2: b002 add sp, #8 + 80010c4: bd80 pop {r7, pc} + 80010c6: 46c0 nop @ (mov r8, r8) + 80010c8: 20000000 .word 0x20000000 + 80010cc: 200003b4 .word 0x200003b4 + 80010d0: 20000434 .word 0x20000434 + 80010d4: 20000001 .word 0x20000001 + 80010d8: 200003f4 .word 0x200003f4 + 80010dc: 20000250 .word 0x20000250 -080010a8 : +080010e0 : +} + + + +void set_Feeder_PWM(uint16_t PWM, uint8_t direction) +{ + 80010e0: b580 push {r7, lr} + 80010e2: b082 sub sp, #8 + 80010e4: af00 add r7, sp, #0 + 80010e6: 0002 movs r2, r0 + 80010e8: 1dbb adds r3, r7, #6 + 80010ea: 801a strh r2, [r3, #0] + 80010ec: 1d7b adds r3, r7, #5 + 80010ee: 1c0a adds r2, r1, #0 + 80010f0: 701a strb r2, [r3, #0] + if (direction) + 80010f2: 1d7b adds r3, r7, #5 + 80010f4: 781b ldrb r3, [r3, #0] + 80010f6: 2b00 cmp r3, #0 + 80010f8: d009 beq.n 800110e + { + htim1.Instance->CCR1 = PWM; + 80010fa: 4b0b ldr r3, [pc, #44] @ (8001128 ) + 80010fc: 681b ldr r3, [r3, #0] + 80010fe: 1dba adds r2, r7, #6 + 8001100: 8812 ldrh r2, [r2, #0] + 8001102: 635a str r2, [r3, #52] @ 0x34 + htim1.Instance->CCR2 = 0; + 8001104: 4b08 ldr r3, [pc, #32] @ (8001128 ) + 8001106: 681b ldr r3, [r3, #0] + 8001108: 2200 movs r2, #0 + 800110a: 639a str r2, [r3, #56] @ 0x38 + else + { + htim1.Instance->CCR1 = 0; + htim1.Instance->CCR2 = PWM; + } +} + 800110c: e008 b.n 8001120 + htim1.Instance->CCR1 = 0; + 800110e: 4b06 ldr r3, [pc, #24] @ (8001128 ) + 8001110: 681b ldr r3, [r3, #0] + 8001112: 2200 movs r2, #0 + 8001114: 635a str r2, [r3, #52] @ 0x34 + htim1.Instance->CCR2 = PWM; + 8001116: 4b04 ldr r3, [pc, #16] @ (8001128 ) + 8001118: 681b ldr r3, [r3, #0] + 800111a: 1dba adds r2, r7, #6 + 800111c: 8812 ldrh r2, [r2, #0] + 800111e: 639a str r2, [r3, #56] @ 0x38 +} + 8001120: 46c0 nop @ (mov r8, r8) + 8001122: 46bd mov sp, r7 + 8001124: b002 add sp, #8 + 8001126: bd80 pop {r7, pc} + 8001128: 20000040 .word 0x20000040 + +0800112c : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { - 80010a8: b580 push {r7, lr} - 80010aa: af00 add r7, sp, #0 + 800112c: b580 push {r7, lr} + 800112e: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting special-purpose register PRIMASK. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); - 80010ac: b672 cpsid i + 8001130: b672 cpsid i } - 80010ae: 46c0 nop @ (mov r8, r8) + 8001132: 46c0 nop @ (mov r8, r8) /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) - 80010b0: 46c0 nop @ (mov r8, r8) - 80010b2: e7fd b.n 80010b0 + 8001134: 46c0 nop @ (mov r8, r8) + 8001136: e7fd b.n 8001134 -080010b4 : +08001138 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. */ void HAL_MspInit(void) { - 80010b4: b580 push {r7, lr} - 80010b6: b082 sub sp, #8 - 80010b8: af00 add r7, sp, #0 + 8001138: b580 push {r7, lr} + 800113a: b082 sub sp, #8 + 800113c: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); - 80010ba: 4b0f ldr r3, [pc, #60] @ (80010f8 ) - 80010bc: 6c1a ldr r2, [r3, #64] @ 0x40 - 80010be: 4b0e ldr r3, [pc, #56] @ (80010f8 ) - 80010c0: 2101 movs r1, #1 - 80010c2: 430a orrs r2, r1 - 80010c4: 641a str r2, [r3, #64] @ 0x40 - 80010c6: 4b0c ldr r3, [pc, #48] @ (80010f8 ) - 80010c8: 6c1b ldr r3, [r3, #64] @ 0x40 - 80010ca: 2201 movs r2, #1 - 80010cc: 4013 ands r3, r2 - 80010ce: 607b str r3, [r7, #4] - 80010d0: 687b ldr r3, [r7, #4] + 800113e: 4b0f ldr r3, [pc, #60] @ (800117c ) + 8001140: 6c1a ldr r2, [r3, #64] @ 0x40 + 8001142: 4b0e ldr r3, [pc, #56] @ (800117c ) + 8001144: 2101 movs r1, #1 + 8001146: 430a orrs r2, r1 + 8001148: 641a str r2, [r3, #64] @ 0x40 + 800114a: 4b0c ldr r3, [pc, #48] @ (800117c ) + 800114c: 6c1b ldr r3, [r3, #64] @ 0x40 + 800114e: 2201 movs r2, #1 + 8001150: 4013 ands r3, r2 + 8001152: 607b str r3, [r7, #4] + 8001154: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); - 80010d2: 4b09 ldr r3, [pc, #36] @ (80010f8 ) - 80010d4: 6bda ldr r2, [r3, #60] @ 0x3c - 80010d6: 4b08 ldr r3, [pc, #32] @ (80010f8 ) - 80010d8: 2180 movs r1, #128 @ 0x80 - 80010da: 0549 lsls r1, r1, #21 - 80010dc: 430a orrs r2, r1 - 80010de: 63da str r2, [r3, #60] @ 0x3c - 80010e0: 4b05 ldr r3, [pc, #20] @ (80010f8 ) - 80010e2: 6bda ldr r2, [r3, #60] @ 0x3c - 80010e4: 2380 movs r3, #128 @ 0x80 - 80010e6: 055b lsls r3, r3, #21 - 80010e8: 4013 ands r3, r2 - 80010ea: 603b str r3, [r7, #0] - 80010ec: 683b ldr r3, [r7, #0] + 8001156: 4b09 ldr r3, [pc, #36] @ (800117c ) + 8001158: 6bda ldr r2, [r3, #60] @ 0x3c + 800115a: 4b08 ldr r3, [pc, #32] @ (800117c ) + 800115c: 2180 movs r1, #128 @ 0x80 + 800115e: 0549 lsls r1, r1, #21 + 8001160: 430a orrs r2, r1 + 8001162: 63da str r2, [r3, #60] @ 0x3c + 8001164: 4b05 ldr r3, [pc, #20] @ (800117c ) + 8001166: 6bda ldr r2, [r3, #60] @ 0x3c + 8001168: 2380 movs r3, #128 @ 0x80 + 800116a: 055b lsls r3, r3, #21 + 800116c: 4013 ands r3, r2 + 800116e: 603b str r3, [r7, #0] + 8001170: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } - 80010ee: 46c0 nop @ (mov r8, r8) - 80010f0: 46bd mov sp, r7 - 80010f2: b002 add sp, #8 - 80010f4: bd80 pop {r7, pc} - 80010f6: 46c0 nop @ (mov r8, r8) - 80010f8: 40021000 .word 0x40021000 + 8001172: 46c0 nop @ (mov r8, r8) + 8001174: 46bd mov sp, r7 + 8001176: b002 add sp, #8 + 8001178: bd80 pop {r7, pc} + 800117a: 46c0 nop @ (mov r8, r8) + 800117c: 40021000 .word 0x40021000 -080010fc : +08001180 : * This function configures the hardware resources used in this example * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { - 80010fc: b580 push {r7, lr} - 80010fe: b086 sub sp, #24 - 8001100: af00 add r7, sp, #0 - 8001102: 6078 str r0, [r7, #4] + 8001180: b580 push {r7, lr} + 8001182: b086 sub sp, #24 + 8001184: af00 add r7, sp, #0 + 8001186: 6078 str r0, [r7, #4] if(htim_base->Instance==TIM1) - 8001104: 687b ldr r3, [r7, #4] - 8001106: 681b ldr r3, [r3, #0] - 8001108: 4a34 ldr r2, [pc, #208] @ (80011dc ) - 800110a: 4293 cmp r3, r2 - 800110c: d10e bne.n 800112c + 8001188: 687b ldr r3, [r7, #4] + 800118a: 681b ldr r3, [r3, #0] + 800118c: 4a34 ldr r2, [pc, #208] @ (8001260 ) + 800118e: 4293 cmp r3, r2 + 8001190: d10e bne.n 80011b0 { /* USER CODE BEGIN TIM1_MspInit 0 */ /* USER CODE END TIM1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM1_CLK_ENABLE(); - 800110e: 4b34 ldr r3, [pc, #208] @ (80011e0 ) - 8001110: 6c1a ldr r2, [r3, #64] @ 0x40 - 8001112: 4b33 ldr r3, [pc, #204] @ (80011e0 ) - 8001114: 2180 movs r1, #128 @ 0x80 - 8001116: 0109 lsls r1, r1, #4 - 8001118: 430a orrs r2, r1 - 800111a: 641a str r2, [r3, #64] @ 0x40 - 800111c: 4b30 ldr r3, [pc, #192] @ (80011e0 ) - 800111e: 6c1a ldr r2, [r3, #64] @ 0x40 - 8001120: 2380 movs r3, #128 @ 0x80 - 8001122: 011b lsls r3, r3, #4 - 8001124: 4013 ands r3, r2 - 8001126: 617b str r3, [r7, #20] - 8001128: 697b ldr r3, [r7, #20] + 8001192: 4b34 ldr r3, [pc, #208] @ (8001264 ) + 8001194: 6c1a ldr r2, [r3, #64] @ 0x40 + 8001196: 4b33 ldr r3, [pc, #204] @ (8001264 ) + 8001198: 2180 movs r1, #128 @ 0x80 + 800119a: 0109 lsls r1, r1, #4 + 800119c: 430a orrs r2, r1 + 800119e: 641a str r2, [r3, #64] @ 0x40 + 80011a0: 4b30 ldr r3, [pc, #192] @ (8001264 ) + 80011a2: 6c1a ldr r2, [r3, #64] @ 0x40 + 80011a4: 2380 movs r3, #128 @ 0x80 + 80011a6: 011b lsls r3, r3, #4 + 80011a8: 4013 ands r3, r2 + 80011aa: 617b str r3, [r7, #20] + 80011ac: 697b ldr r3, [r7, #20] /* USER CODE BEGIN TIM17_MspInit 1 */ /* USER CODE END TIM17_MspInit 1 */ } } - 800112a: e052 b.n 80011d2 + 80011ae: e052 b.n 8001256 else if(htim_base->Instance==TIM14) - 800112c: 687b ldr r3, [r7, #4] - 800112e: 681b ldr r3, [r3, #0] - 8001130: 4a2c ldr r2, [pc, #176] @ (80011e4 ) - 8001132: 4293 cmp r3, r2 - 8001134: d116 bne.n 8001164 + 80011b0: 687b ldr r3, [r7, #4] + 80011b2: 681b ldr r3, [r3, #0] + 80011b4: 4a2c ldr r2, [pc, #176] @ (8001268 ) + 80011b6: 4293 cmp r3, r2 + 80011b8: d116 bne.n 80011e8 __HAL_RCC_TIM14_CLK_ENABLE(); - 8001136: 4b2a ldr r3, [pc, #168] @ (80011e0 ) - 8001138: 6c1a ldr r2, [r3, #64] @ 0x40 - 800113a: 4b29 ldr r3, [pc, #164] @ (80011e0 ) - 800113c: 2180 movs r1, #128 @ 0x80 - 800113e: 0209 lsls r1, r1, #8 - 8001140: 430a orrs r2, r1 - 8001142: 641a str r2, [r3, #64] @ 0x40 - 8001144: 4b26 ldr r3, [pc, #152] @ (80011e0 ) - 8001146: 6c1a ldr r2, [r3, #64] @ 0x40 - 8001148: 2380 movs r3, #128 @ 0x80 - 800114a: 021b lsls r3, r3, #8 - 800114c: 4013 ands r3, r2 - 800114e: 613b str r3, [r7, #16] - 8001150: 693b ldr r3, [r7, #16] + 80011ba: 4b2a ldr r3, [pc, #168] @ (8001264 ) + 80011bc: 6c1a ldr r2, [r3, #64] @ 0x40 + 80011be: 4b29 ldr r3, [pc, #164] @ (8001264 ) + 80011c0: 2180 movs r1, #128 @ 0x80 + 80011c2: 0209 lsls r1, r1, #8 + 80011c4: 430a orrs r2, r1 + 80011c6: 641a str r2, [r3, #64] @ 0x40 + 80011c8: 4b26 ldr r3, [pc, #152] @ (8001264 ) + 80011ca: 6c1a ldr r2, [r3, #64] @ 0x40 + 80011cc: 2380 movs r3, #128 @ 0x80 + 80011ce: 021b lsls r3, r3, #8 + 80011d0: 4013 ands r3, r2 + 80011d2: 613b str r3, [r7, #16] + 80011d4: 693b ldr r3, [r7, #16] HAL_NVIC_SetPriority(TIM14_IRQn, 0, 0); - 8001152: 2200 movs r2, #0 - 8001154: 2100 movs r1, #0 - 8001156: 2013 movs r0, #19 - 8001158: f000 fbc0 bl 80018dc + 80011d6: 2200 movs r2, #0 + 80011d8: 2100 movs r1, #0 + 80011da: 2013 movs r0, #19 + 80011dc: f000 fbc0 bl 8001960 HAL_NVIC_EnableIRQ(TIM14_IRQn); - 800115c: 2013 movs r0, #19 - 800115e: f000 fbd2 bl 8001906 + 80011e0: 2013 movs r0, #19 + 80011e2: f000 fbd2 bl 800198a } - 8001162: e036 b.n 80011d2 + 80011e6: e036 b.n 8001256 else if(htim_base->Instance==TIM16) - 8001164: 687b ldr r3, [r7, #4] - 8001166: 681b ldr r3, [r3, #0] - 8001168: 4a1f ldr r2, [pc, #124] @ (80011e8 ) - 800116a: 4293 cmp r3, r2 - 800116c: d116 bne.n 800119c + 80011e8: 687b ldr r3, [r7, #4] + 80011ea: 681b ldr r3, [r3, #0] + 80011ec: 4a1f ldr r2, [pc, #124] @ (800126c ) + 80011ee: 4293 cmp r3, r2 + 80011f0: d116 bne.n 8001220 __HAL_RCC_TIM16_CLK_ENABLE(); - 800116e: 4b1c ldr r3, [pc, #112] @ (80011e0 ) - 8001170: 6c1a ldr r2, [r3, #64] @ 0x40 - 8001172: 4b1b ldr r3, [pc, #108] @ (80011e0 ) - 8001174: 2180 movs r1, #128 @ 0x80 - 8001176: 0289 lsls r1, r1, #10 - 8001178: 430a orrs r2, r1 - 800117a: 641a str r2, [r3, #64] @ 0x40 - 800117c: 4b18 ldr r3, [pc, #96] @ (80011e0 ) - 800117e: 6c1a ldr r2, [r3, #64] @ 0x40 - 8001180: 2380 movs r3, #128 @ 0x80 - 8001182: 029b lsls r3, r3, #10 - 8001184: 4013 ands r3, r2 - 8001186: 60fb str r3, [r7, #12] - 8001188: 68fb ldr r3, [r7, #12] + 80011f2: 4b1c ldr r3, [pc, #112] @ (8001264 ) + 80011f4: 6c1a ldr r2, [r3, #64] @ 0x40 + 80011f6: 4b1b ldr r3, [pc, #108] @ (8001264 ) + 80011f8: 2180 movs r1, #128 @ 0x80 + 80011fa: 0289 lsls r1, r1, #10 + 80011fc: 430a orrs r2, r1 + 80011fe: 641a str r2, [r3, #64] @ 0x40 + 8001200: 4b18 ldr r3, [pc, #96] @ (8001264 ) + 8001202: 6c1a ldr r2, [r3, #64] @ 0x40 + 8001204: 2380 movs r3, #128 @ 0x80 + 8001206: 029b lsls r3, r3, #10 + 8001208: 4013 ands r3, r2 + 800120a: 60fb str r3, [r7, #12] + 800120c: 68fb ldr r3, [r7, #12] HAL_NVIC_SetPriority(TIM16_IRQn, 0, 0); - 800118a: 2200 movs r2, #0 - 800118c: 2100 movs r1, #0 - 800118e: 2015 movs r0, #21 - 8001190: f000 fba4 bl 80018dc + 800120e: 2200 movs r2, #0 + 8001210: 2100 movs r1, #0 + 8001212: 2015 movs r0, #21 + 8001214: f000 fba4 bl 8001960 HAL_NVIC_EnableIRQ(TIM16_IRQn); - 8001194: 2015 movs r0, #21 - 8001196: f000 fbb6 bl 8001906 + 8001218: 2015 movs r0, #21 + 800121a: f000 fbb6 bl 800198a } - 800119a: e01a b.n 80011d2 + 800121e: e01a b.n 8001256 else if(htim_base->Instance==TIM17) - 800119c: 687b ldr r3, [r7, #4] - 800119e: 681b ldr r3, [r3, #0] - 80011a0: 4a12 ldr r2, [pc, #72] @ (80011ec ) - 80011a2: 4293 cmp r3, r2 - 80011a4: d115 bne.n 80011d2 + 8001220: 687b ldr r3, [r7, #4] + 8001222: 681b ldr r3, [r3, #0] + 8001224: 4a12 ldr r2, [pc, #72] @ (8001270 ) + 8001226: 4293 cmp r3, r2 + 8001228: d115 bne.n 8001256 __HAL_RCC_TIM17_CLK_ENABLE(); - 80011a6: 4b0e ldr r3, [pc, #56] @ (80011e0 ) - 80011a8: 6c1a ldr r2, [r3, #64] @ 0x40 - 80011aa: 4b0d ldr r3, [pc, #52] @ (80011e0 ) - 80011ac: 2180 movs r1, #128 @ 0x80 - 80011ae: 02c9 lsls r1, r1, #11 - 80011b0: 430a orrs r2, r1 - 80011b2: 641a str r2, [r3, #64] @ 0x40 - 80011b4: 4b0a ldr r3, [pc, #40] @ (80011e0 ) - 80011b6: 6c1a ldr r2, [r3, #64] @ 0x40 - 80011b8: 2380 movs r3, #128 @ 0x80 - 80011ba: 02db lsls r3, r3, #11 - 80011bc: 4013 ands r3, r2 - 80011be: 60bb str r3, [r7, #8] - 80011c0: 68bb ldr r3, [r7, #8] + 800122a: 4b0e ldr r3, [pc, #56] @ (8001264 ) + 800122c: 6c1a ldr r2, [r3, #64] @ 0x40 + 800122e: 4b0d ldr r3, [pc, #52] @ (8001264 ) + 8001230: 2180 movs r1, #128 @ 0x80 + 8001232: 02c9 lsls r1, r1, #11 + 8001234: 430a orrs r2, r1 + 8001236: 641a str r2, [r3, #64] @ 0x40 + 8001238: 4b0a ldr r3, [pc, #40] @ (8001264 ) + 800123a: 6c1a ldr r2, [r3, #64] @ 0x40 + 800123c: 2380 movs r3, #128 @ 0x80 + 800123e: 02db lsls r3, r3, #11 + 8001240: 4013 ands r3, r2 + 8001242: 60bb str r3, [r7, #8] + 8001244: 68bb ldr r3, [r7, #8] HAL_NVIC_SetPriority(TIM17_IRQn, 0, 0); - 80011c2: 2200 movs r2, #0 - 80011c4: 2100 movs r1, #0 - 80011c6: 2016 movs r0, #22 - 80011c8: f000 fb88 bl 80018dc + 8001246: 2200 movs r2, #0 + 8001248: 2100 movs r1, #0 + 800124a: 2016 movs r0, #22 + 800124c: f000 fb88 bl 8001960 HAL_NVIC_EnableIRQ(TIM17_IRQn); - 80011cc: 2016 movs r0, #22 - 80011ce: f000 fb9a bl 8001906 + 8001250: 2016 movs r0, #22 + 8001252: f000 fb9a bl 800198a } - 80011d2: 46c0 nop @ (mov r8, r8) - 80011d4: 46bd mov sp, r7 - 80011d6: b006 add sp, #24 - 80011d8: bd80 pop {r7, pc} - 80011da: 46c0 nop @ (mov r8, r8) - 80011dc: 40012c00 .word 0x40012c00 - 80011e0: 40021000 .word 0x40021000 - 80011e4: 40002000 .word 0x40002000 - 80011e8: 40014400 .word 0x40014400 - 80011ec: 40014800 .word 0x40014800 + 8001256: 46c0 nop @ (mov r8, r8) + 8001258: 46bd mov sp, r7 + 800125a: b006 add sp, #24 + 800125c: bd80 pop {r7, pc} + 800125e: 46c0 nop @ (mov r8, r8) + 8001260: 40012c00 .word 0x40012c00 + 8001264: 40021000 .word 0x40021000 + 8001268: 40002000 .word 0x40002000 + 800126c: 40014400 .word 0x40014400 + 8001270: 40014800 .word 0x40014800 -080011f0 : +08001274 : * This function configures the hardware resources used in this example * @param htim_encoder: TIM_Encoder handle pointer * @retval None */ void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* htim_encoder) { - 80011f0: b590 push {r4, r7, lr} - 80011f2: b08b sub sp, #44 @ 0x2c - 80011f4: af00 add r7, sp, #0 - 80011f6: 6078 str r0, [r7, #4] + 8001274: b590 push {r4, r7, lr} + 8001276: b08b sub sp, #44 @ 0x2c + 8001278: af00 add r7, sp, #0 + 800127a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; - 80011f8: 2414 movs r4, #20 - 80011fa: 193b adds r3, r7, r4 - 80011fc: 0018 movs r0, r3 - 80011fe: 2314 movs r3, #20 - 8001200: 001a movs r2, r3 - 8001202: 2100 movs r1, #0 - 8001204: f003 fd98 bl 8004d38 + 800127c: 2414 movs r4, #20 + 800127e: 193b adds r3, r7, r4 + 8001280: 0018 movs r0, r3 + 8001282: 2314 movs r3, #20 + 8001284: 001a movs r2, r3 + 8001286: 2100 movs r1, #0 + 8001288: f003 fd98 bl 8004dbc if(htim_encoder->Instance==TIM3) - 8001208: 687b ldr r3, [r7, #4] - 800120a: 681b ldr r3, [r3, #0] - 800120c: 4a1a ldr r2, [pc, #104] @ (8001278 ) - 800120e: 4293 cmp r3, r2 - 8001210: d12d bne.n 800126e + 800128c: 687b ldr r3, [r7, #4] + 800128e: 681b ldr r3, [r3, #0] + 8001290: 4a1a ldr r2, [pc, #104] @ (80012fc ) + 8001292: 4293 cmp r3, r2 + 8001294: d12d bne.n 80012f2 { /* USER CODE BEGIN TIM3_MspInit 0 */ /* USER CODE END TIM3_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM3_CLK_ENABLE(); - 8001212: 4b1a ldr r3, [pc, #104] @ (800127c ) - 8001214: 6bda ldr r2, [r3, #60] @ 0x3c - 8001216: 4b19 ldr r3, [pc, #100] @ (800127c ) - 8001218: 2102 movs r1, #2 - 800121a: 430a orrs r2, r1 - 800121c: 63da str r2, [r3, #60] @ 0x3c - 800121e: 4b17 ldr r3, [pc, #92] @ (800127c ) - 8001220: 6bdb ldr r3, [r3, #60] @ 0x3c - 8001222: 2202 movs r2, #2 - 8001224: 4013 ands r3, r2 - 8001226: 613b str r3, [r7, #16] - 8001228: 693b ldr r3, [r7, #16] + 8001296: 4b1a ldr r3, [pc, #104] @ (8001300 ) + 8001298: 6bda ldr r2, [r3, #60] @ 0x3c + 800129a: 4b19 ldr r3, [pc, #100] @ (8001300 ) + 800129c: 2102 movs r1, #2 + 800129e: 430a orrs r2, r1 + 80012a0: 63da str r2, [r3, #60] @ 0x3c + 80012a2: 4b17 ldr r3, [pc, #92] @ (8001300 ) + 80012a4: 6bdb ldr r3, [r3, #60] @ 0x3c + 80012a6: 2202 movs r2, #2 + 80012a8: 4013 ands r3, r2 + 80012aa: 613b str r3, [r7, #16] + 80012ac: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOC_CLK_ENABLE(); - 800122a: 4b14 ldr r3, [pc, #80] @ (800127c ) - 800122c: 6b5a ldr r2, [r3, #52] @ 0x34 - 800122e: 4b13 ldr r3, [pc, #76] @ (800127c ) - 8001230: 2104 movs r1, #4 - 8001232: 430a orrs r2, r1 - 8001234: 635a str r2, [r3, #52] @ 0x34 - 8001236: 4b11 ldr r3, [pc, #68] @ (800127c ) - 8001238: 6b5b ldr r3, [r3, #52] @ 0x34 - 800123a: 2204 movs r2, #4 - 800123c: 4013 ands r3, r2 - 800123e: 60fb str r3, [r7, #12] - 8001240: 68fb ldr r3, [r7, #12] + 80012ae: 4b14 ldr r3, [pc, #80] @ (8001300 ) + 80012b0: 6b5a ldr r2, [r3, #52] @ 0x34 + 80012b2: 4b13 ldr r3, [pc, #76] @ (8001300 ) + 80012b4: 2104 movs r1, #4 + 80012b6: 430a orrs r2, r1 + 80012b8: 635a str r2, [r3, #52] @ 0x34 + 80012ba: 4b11 ldr r3, [pc, #68] @ (8001300 ) + 80012bc: 6b5b ldr r3, [r3, #52] @ 0x34 + 80012be: 2204 movs r2, #4 + 80012c0: 4013 ands r3, r2 + 80012c2: 60fb str r3, [r7, #12] + 80012c4: 68fb ldr r3, [r7, #12] /**TIM3 GPIO Configuration PC6 ------> TIM3_CH1 PC7 ------> TIM3_CH2 */ GPIO_InitStruct.Pin = QUAD_A_Pin|QUAD_B_Pin; - 8001242: 0021 movs r1, r4 - 8001244: 187b adds r3, r7, r1 - 8001246: 22c0 movs r2, #192 @ 0xc0 - 8001248: 601a str r2, [r3, #0] + 80012c6: 0021 movs r1, r4 + 80012c8: 187b adds r3, r7, r1 + 80012ca: 22c0 movs r2, #192 @ 0xc0 + 80012cc: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - 800124a: 187b adds r3, r7, r1 - 800124c: 2202 movs r2, #2 - 800124e: 605a str r2, [r3, #4] + 80012ce: 187b adds r3, r7, r1 + 80012d0: 2202 movs r2, #2 + 80012d2: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; - 8001250: 187b adds r3, r7, r1 - 8001252: 2200 movs r2, #0 - 8001254: 609a str r2, [r3, #8] + 80012d4: 187b adds r3, r7, r1 + 80012d6: 2200 movs r2, #0 + 80012d8: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - 8001256: 187b adds r3, r7, r1 - 8001258: 2200 movs r2, #0 - 800125a: 60da str r2, [r3, #12] + 80012da: 187b adds r3, r7, r1 + 80012dc: 2200 movs r2, #0 + 80012de: 60da str r2, [r3, #12] GPIO_InitStruct.Alternate = GPIO_AF1_TIM3; - 800125c: 187b adds r3, r7, r1 - 800125e: 2201 movs r2, #1 - 8001260: 611a str r2, [r3, #16] + 80012e0: 187b adds r3, r7, r1 + 80012e2: 2201 movs r2, #1 + 80012e4: 611a str r2, [r3, #16] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - 8001262: 187b adds r3, r7, r1 - 8001264: 4a06 ldr r2, [pc, #24] @ (8001280 ) - 8001266: 0019 movs r1, r3 - 8001268: 0010 movs r0, r2 - 800126a: f000 fdbd bl 8001de8 + 80012e6: 187b adds r3, r7, r1 + 80012e8: 4a06 ldr r2, [pc, #24] @ (8001304 ) + 80012ea: 0019 movs r1, r3 + 80012ec: 0010 movs r0, r2 + 80012ee: f000 fdbd bl 8001e6c /* USER CODE END TIM3_MspInit 1 */ } } - 800126e: 46c0 nop @ (mov r8, r8) - 8001270: 46bd mov sp, r7 - 8001272: b00b add sp, #44 @ 0x2c - 8001274: bd90 pop {r4, r7, pc} - 8001276: 46c0 nop @ (mov r8, r8) - 8001278: 40000400 .word 0x40000400 - 800127c: 40021000 .word 0x40021000 - 8001280: 50000800 .word 0x50000800 + 80012f2: 46c0 nop @ (mov r8, r8) + 80012f4: 46bd mov sp, r7 + 80012f6: b00b add sp, #44 @ 0x2c + 80012f8: bd90 pop {r4, r7, pc} + 80012fa: 46c0 nop @ (mov r8, r8) + 80012fc: 40000400 .word 0x40000400 + 8001300: 40021000 .word 0x40021000 + 8001304: 50000800 .word 0x50000800 -08001284 : +08001308 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) { - 8001284: b590 push {r4, r7, lr} - 8001286: b089 sub sp, #36 @ 0x24 - 8001288: af00 add r7, sp, #0 - 800128a: 6078 str r0, [r7, #4] + 8001308: b590 push {r4, r7, lr} + 800130a: b089 sub sp, #36 @ 0x24 + 800130c: af00 add r7, sp, #0 + 800130e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; - 800128c: 240c movs r4, #12 - 800128e: 193b adds r3, r7, r4 - 8001290: 0018 movs r0, r3 - 8001292: 2314 movs r3, #20 - 8001294: 001a movs r2, r3 - 8001296: 2100 movs r1, #0 - 8001298: f003 fd4e bl 8004d38 + 8001310: 240c movs r4, #12 + 8001312: 193b adds r3, r7, r4 + 8001314: 0018 movs r0, r3 + 8001316: 2314 movs r3, #20 + 8001318: 001a movs r2, r3 + 800131a: 2100 movs r1, #0 + 800131c: f003 fd4e bl 8004dbc if(htim->Instance==TIM1) - 800129c: 687b ldr r3, [r7, #4] - 800129e: 681b ldr r3, [r3, #0] - 80012a0: 4a20 ldr r2, [pc, #128] @ (8001324 ) - 80012a2: 4293 cmp r3, r2 - 80012a4: d139 bne.n 800131a + 8001320: 687b ldr r3, [r7, #4] + 8001322: 681b ldr r3, [r3, #0] + 8001324: 4a20 ldr r2, [pc, #128] @ (80013a8 ) + 8001326: 4293 cmp r3, r2 + 8001328: d139 bne.n 800139e { /* USER CODE BEGIN TIM1_MspPostInit 0 */ /* USER CODE END TIM1_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); - 80012a6: 4b20 ldr r3, [pc, #128] @ (8001328 ) - 80012a8: 6b5a ldr r2, [r3, #52] @ 0x34 - 80012aa: 4b1f ldr r3, [pc, #124] @ (8001328 ) - 80012ac: 2101 movs r1, #1 - 80012ae: 430a orrs r2, r1 - 80012b0: 635a str r2, [r3, #52] @ 0x34 - 80012b2: 4b1d ldr r3, [pc, #116] @ (8001328 ) - 80012b4: 6b5b ldr r3, [r3, #52] @ 0x34 - 80012b6: 2201 movs r2, #1 - 80012b8: 4013 ands r3, r2 - 80012ba: 60bb str r3, [r7, #8] - 80012bc: 68bb ldr r3, [r7, #8] + 800132a: 4b20 ldr r3, [pc, #128] @ (80013ac ) + 800132c: 6b5a ldr r2, [r3, #52] @ 0x34 + 800132e: 4b1f ldr r3, [pc, #124] @ (80013ac ) + 8001330: 2101 movs r1, #1 + 8001332: 430a orrs r2, r1 + 8001334: 635a str r2, [r3, #52] @ 0x34 + 8001336: 4b1d ldr r3, [pc, #116] @ (80013ac ) + 8001338: 6b5b ldr r3, [r3, #52] @ 0x34 + 800133a: 2201 movs r2, #1 + 800133c: 4013 ands r3, r2 + 800133e: 60bb str r3, [r7, #8] + 8001340: 68bb ldr r3, [r7, #8] PA2 ------> TIM1_CH3 PA3 ------> TIM1_CH4 PA8 ------> TIM1_CH1 PA9 ------> TIM1_CH2 */ GPIO_InitStruct.Pin = PEEL1_Pin|PEEL2_Pin; - 80012be: 193b adds r3, r7, r4 - 80012c0: 220c movs r2, #12 - 80012c2: 601a str r2, [r3, #0] + 8001342: 193b adds r3, r7, r4 + 8001344: 220c movs r2, #12 + 8001346: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - 80012c4: 193b adds r3, r7, r4 - 80012c6: 2202 movs r2, #2 - 80012c8: 605a str r2, [r3, #4] + 8001348: 193b adds r3, r7, r4 + 800134a: 2202 movs r2, #2 + 800134c: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; - 80012ca: 193b adds r3, r7, r4 - 80012cc: 2200 movs r2, #0 - 80012ce: 609a str r2, [r3, #8] + 800134e: 193b adds r3, r7, r4 + 8001350: 2200 movs r2, #0 + 8001352: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - 80012d0: 193b adds r3, r7, r4 - 80012d2: 2200 movs r2, #0 - 80012d4: 60da str r2, [r3, #12] + 8001354: 193b adds r3, r7, r4 + 8001356: 2200 movs r2, #0 + 8001358: 60da str r2, [r3, #12] GPIO_InitStruct.Alternate = GPIO_AF5_TIM1; - 80012d6: 193b adds r3, r7, r4 - 80012d8: 2205 movs r2, #5 - 80012da: 611a str r2, [r3, #16] + 800135a: 193b adds r3, r7, r4 + 800135c: 2205 movs r2, #5 + 800135e: 611a str r2, [r3, #16] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - 80012dc: 193a adds r2, r7, r4 - 80012de: 23a0 movs r3, #160 @ 0xa0 - 80012e0: 05db lsls r3, r3, #23 - 80012e2: 0011 movs r1, r2 - 80012e4: 0018 movs r0, r3 - 80012e6: f000 fd7f bl 8001de8 + 8001360: 193a adds r2, r7, r4 + 8001362: 23a0 movs r3, #160 @ 0xa0 + 8001364: 05db lsls r3, r3, #23 + 8001366: 0011 movs r1, r2 + 8001368: 0018 movs r0, r3 + 800136a: f000 fd7f bl 8001e6c GPIO_InitStruct.Pin = DRIVE1_Pin|DRIVE2_Pin; - 80012ea: 0021 movs r1, r4 - 80012ec: 187b adds r3, r7, r1 - 80012ee: 22c0 movs r2, #192 @ 0xc0 - 80012f0: 0092 lsls r2, r2, #2 - 80012f2: 601a str r2, [r3, #0] + 800136e: 0021 movs r1, r4 + 8001370: 187b adds r3, r7, r1 + 8001372: 22c0 movs r2, #192 @ 0xc0 + 8001374: 0092 lsls r2, r2, #2 + 8001376: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - 80012f4: 187b adds r3, r7, r1 - 80012f6: 2202 movs r2, #2 - 80012f8: 605a str r2, [r3, #4] + 8001378: 187b adds r3, r7, r1 + 800137a: 2202 movs r2, #2 + 800137c: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; - 80012fa: 187b adds r3, r7, r1 - 80012fc: 2200 movs r2, #0 - 80012fe: 609a str r2, [r3, #8] + 800137e: 187b adds r3, r7, r1 + 8001380: 2200 movs r2, #0 + 8001382: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - 8001300: 187b adds r3, r7, r1 - 8001302: 2200 movs r2, #0 - 8001304: 60da str r2, [r3, #12] + 8001384: 187b adds r3, r7, r1 + 8001386: 2200 movs r2, #0 + 8001388: 60da str r2, [r3, #12] GPIO_InitStruct.Alternate = GPIO_AF2_TIM1; - 8001306: 187b adds r3, r7, r1 - 8001308: 2202 movs r2, #2 - 800130a: 611a str r2, [r3, #16] + 800138a: 187b adds r3, r7, r1 + 800138c: 2202 movs r2, #2 + 800138e: 611a str r2, [r3, #16] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - 800130c: 187a adds r2, r7, r1 - 800130e: 23a0 movs r3, #160 @ 0xa0 - 8001310: 05db lsls r3, r3, #23 - 8001312: 0011 movs r1, r2 - 8001314: 0018 movs r0, r3 - 8001316: f000 fd67 bl 8001de8 + 8001390: 187a adds r2, r7, r1 + 8001392: 23a0 movs r3, #160 @ 0xa0 + 8001394: 05db lsls r3, r3, #23 + 8001396: 0011 movs r1, r2 + 8001398: 0018 movs r0, r3 + 800139a: f000 fd67 bl 8001e6c /* USER CODE BEGIN TIM1_MspPostInit 1 */ /* USER CODE END TIM1_MspPostInit 1 */ } } - 800131a: 46c0 nop @ (mov r8, r8) - 800131c: 46bd mov sp, r7 - 800131e: b009 add sp, #36 @ 0x24 - 8001320: bd90 pop {r4, r7, pc} - 8001322: 46c0 nop @ (mov r8, r8) - 8001324: 40012c00 .word 0x40012c00 - 8001328: 40021000 .word 0x40021000 + 800139e: 46c0 nop @ (mov r8, r8) + 80013a0: 46bd mov sp, r7 + 80013a2: b009 add sp, #36 @ 0x24 + 80013a4: bd90 pop {r4, r7, pc} + 80013a6: 46c0 nop @ (mov r8, r8) + 80013a8: 40012c00 .word 0x40012c00 + 80013ac: 40021000 .word 0x40021000 -0800132c : +080013b0 : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { - 800132c: b590 push {r4, r7, lr} - 800132e: b093 sub sp, #76 @ 0x4c - 8001330: af00 add r7, sp, #0 - 8001332: 6078 str r0, [r7, #4] + 80013b0: b590 push {r4, r7, lr} + 80013b2: b093 sub sp, #76 @ 0x4c + 80013b4: af00 add r7, sp, #0 + 80013b6: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; - 8001334: 2334 movs r3, #52 @ 0x34 - 8001336: 18fb adds r3, r7, r3 - 8001338: 0018 movs r0, r3 - 800133a: 2314 movs r3, #20 - 800133c: 001a movs r2, r3 - 800133e: 2100 movs r1, #0 - 8001340: f003 fcfa bl 8004d38 + 80013b8: 2334 movs r3, #52 @ 0x34 + 80013ba: 18fb adds r3, r7, r3 + 80013bc: 0018 movs r0, r3 + 80013be: 2314 movs r3, #20 + 80013c0: 001a movs r2, r3 + 80013c2: 2100 movs r1, #0 + 80013c4: f003 fcfa bl 8004dbc RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - 8001344: 2418 movs r4, #24 - 8001346: 193b adds r3, r7, r4 - 8001348: 0018 movs r0, r3 - 800134a: 231c movs r3, #28 - 800134c: 001a movs r2, r3 - 800134e: 2100 movs r1, #0 - 8001350: f003 fcf2 bl 8004d38 + 80013c8: 2418 movs r4, #24 + 80013ca: 193b adds r3, r7, r4 + 80013cc: 0018 movs r0, r3 + 80013ce: 231c movs r3, #28 + 80013d0: 001a movs r2, r3 + 80013d2: 2100 movs r1, #0 + 80013d4: f003 fcf2 bl 8004dbc if(huart->Instance==USART1) - 8001354: 687b ldr r3, [r7, #4] - 8001356: 681b ldr r3, [r3, #0] - 8001358: 4a68 ldr r2, [pc, #416] @ (80014fc ) - 800135a: 4293 cmp r3, r2 - 800135c: d13e bne.n 80013dc + 80013d8: 687b ldr r3, [r7, #4] + 80013da: 681b ldr r3, [r3, #0] + 80013dc: 4a68 ldr r2, [pc, #416] @ (8001580 ) + 80013de: 4293 cmp r3, r2 + 80013e0: d13e bne.n 8001460 /* USER CODE END USART1_MspInit 0 */ /** Initializes the peripherals clocks */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1; - 800135e: 193b adds r3, r7, r4 - 8001360: 2201 movs r2, #1 - 8001362: 601a str r2, [r3, #0] + 80013e2: 193b adds r3, r7, r4 + 80013e4: 2201 movs r2, #1 + 80013e6: 601a str r2, [r3, #0] PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK1; - 8001364: 193b adds r3, r7, r4 - 8001366: 2200 movs r2, #0 - 8001368: 609a str r2, [r3, #8] + 80013e8: 193b adds r3, r7, r4 + 80013ea: 2200 movs r2, #0 + 80013ec: 609a str r2, [r3, #8] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) - 800136a: 193b adds r3, r7, r4 - 800136c: 0018 movs r0, r3 - 800136e: f001 fa99 bl 80028a4 - 8001372: 1e03 subs r3, r0, #0 - 8001374: d001 beq.n 800137a + 80013ee: 193b adds r3, r7, r4 + 80013f0: 0018 movs r0, r3 + 80013f2: f001 fa99 bl 8002928 + 80013f6: 1e03 subs r3, r0, #0 + 80013f8: d001 beq.n 80013fe { Error_Handler(); - 8001376: f7ff fe97 bl 80010a8 + 80013fa: f7ff fe97 bl 800112c } /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - 800137a: 4b61 ldr r3, [pc, #388] @ (8001500 ) - 800137c: 6c1a ldr r2, [r3, #64] @ 0x40 - 800137e: 4b60 ldr r3, [pc, #384] @ (8001500 ) - 8001380: 2180 movs r1, #128 @ 0x80 - 8001382: 01c9 lsls r1, r1, #7 - 8001384: 430a orrs r2, r1 - 8001386: 641a str r2, [r3, #64] @ 0x40 - 8001388: 4b5d ldr r3, [pc, #372] @ (8001500 ) - 800138a: 6c1a ldr r2, [r3, #64] @ 0x40 - 800138c: 2380 movs r3, #128 @ 0x80 - 800138e: 01db lsls r3, r3, #7 - 8001390: 4013 ands r3, r2 - 8001392: 617b str r3, [r7, #20] - 8001394: 697b ldr r3, [r7, #20] + 80013fe: 4b61 ldr r3, [pc, #388] @ (8001584 ) + 8001400: 6c1a ldr r2, [r3, #64] @ 0x40 + 8001402: 4b60 ldr r3, [pc, #384] @ (8001584 ) + 8001404: 2180 movs r1, #128 @ 0x80 + 8001406: 01c9 lsls r1, r1, #7 + 8001408: 430a orrs r2, r1 + 800140a: 641a str r2, [r3, #64] @ 0x40 + 800140c: 4b5d ldr r3, [pc, #372] @ (8001584 ) + 800140e: 6c1a ldr r2, [r3, #64] @ 0x40 + 8001410: 2380 movs r3, #128 @ 0x80 + 8001412: 01db lsls r3, r3, #7 + 8001414: 4013 ands r3, r2 + 8001416: 617b str r3, [r7, #20] + 8001418: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOB_CLK_ENABLE(); - 8001396: 4b5a ldr r3, [pc, #360] @ (8001500 ) - 8001398: 6b5a ldr r2, [r3, #52] @ 0x34 - 800139a: 4b59 ldr r3, [pc, #356] @ (8001500 ) - 800139c: 2102 movs r1, #2 - 800139e: 430a orrs r2, r1 - 80013a0: 635a str r2, [r3, #52] @ 0x34 - 80013a2: 4b57 ldr r3, [pc, #348] @ (8001500 ) - 80013a4: 6b5b ldr r3, [r3, #52] @ 0x34 - 80013a6: 2202 movs r2, #2 - 80013a8: 4013 ands r3, r2 - 80013aa: 613b str r3, [r7, #16] - 80013ac: 693b ldr r3, [r7, #16] + 800141a: 4b5a ldr r3, [pc, #360] @ (8001584 ) + 800141c: 6b5a ldr r2, [r3, #52] @ 0x34 + 800141e: 4b59 ldr r3, [pc, #356] @ (8001584 ) + 8001420: 2102 movs r1, #2 + 8001422: 430a orrs r2, r1 + 8001424: 635a str r2, [r3, #52] @ 0x34 + 8001426: 4b57 ldr r3, [pc, #348] @ (8001584 ) + 8001428: 6b5b ldr r3, [r3, #52] @ 0x34 + 800142a: 2202 movs r2, #2 + 800142c: 4013 ands r3, r2 + 800142e: 613b str r3, [r7, #16] + 8001430: 693b ldr r3, [r7, #16] /**USART1 GPIO Configuration PB6 ------> USART1_TX PB7 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; - 80013ae: 2134 movs r1, #52 @ 0x34 - 80013b0: 187b adds r3, r7, r1 - 80013b2: 22c0 movs r2, #192 @ 0xc0 - 80013b4: 601a str r2, [r3, #0] + 8001432: 2134 movs r1, #52 @ 0x34 + 8001434: 187b adds r3, r7, r1 + 8001436: 22c0 movs r2, #192 @ 0xc0 + 8001438: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - 80013b6: 187b adds r3, r7, r1 - 80013b8: 2202 movs r2, #2 - 80013ba: 605a str r2, [r3, #4] + 800143a: 187b adds r3, r7, r1 + 800143c: 2202 movs r2, #2 + 800143e: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; - 80013bc: 187b adds r3, r7, r1 - 80013be: 2200 movs r2, #0 - 80013c0: 609a str r2, [r3, #8] + 8001440: 187b adds r3, r7, r1 + 8001442: 2200 movs r2, #0 + 8001444: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - 80013c2: 187b adds r3, r7, r1 - 80013c4: 2200 movs r2, #0 - 80013c6: 60da str r2, [r3, #12] + 8001446: 187b adds r3, r7, r1 + 8001448: 2200 movs r2, #0 + 800144a: 60da str r2, [r3, #12] GPIO_InitStruct.Alternate = GPIO_AF0_USART1; - 80013c8: 187b adds r3, r7, r1 - 80013ca: 2200 movs r2, #0 - 80013cc: 611a str r2, [r3, #16] + 800144c: 187b adds r3, r7, r1 + 800144e: 2200 movs r2, #0 + 8001450: 611a str r2, [r3, #16] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - 80013ce: 187b adds r3, r7, r1 - 80013d0: 4a4c ldr r2, [pc, #304] @ (8001504 ) - 80013d2: 0019 movs r1, r3 - 80013d4: 0010 movs r0, r2 - 80013d6: f000 fd07 bl 8001de8 + 8001452: 187b adds r3, r7, r1 + 8001454: 4a4c ldr r2, [pc, #304] @ (8001588 ) + 8001456: 0019 movs r1, r3 + 8001458: 0010 movs r0, r2 + 800145a: f000 fd07 bl 8001e6c /* USER CODE BEGIN USART2_MspInit 1 */ /* USER CODE END USART2_MspInit 1 */ } } - 80013da: e08b b.n 80014f4 + 800145e: e08b b.n 8001578 else if(huart->Instance==USART2) - 80013dc: 687b ldr r3, [r7, #4] - 80013de: 681b ldr r3, [r3, #0] - 80013e0: 4a49 ldr r2, [pc, #292] @ (8001508 ) - 80013e2: 4293 cmp r3, r2 - 80013e4: d000 beq.n 80013e8 - 80013e6: e085 b.n 80014f4 + 8001460: 687b ldr r3, [r7, #4] + 8001462: 681b ldr r3, [r3, #0] + 8001464: 4a49 ldr r2, [pc, #292] @ (800158c ) + 8001466: 4293 cmp r3, r2 + 8001468: d000 beq.n 800146c + 800146a: e085 b.n 8001578 __HAL_RCC_USART2_CLK_ENABLE(); - 80013e8: 4b45 ldr r3, [pc, #276] @ (8001500 ) - 80013ea: 6bda ldr r2, [r3, #60] @ 0x3c - 80013ec: 4b44 ldr r3, [pc, #272] @ (8001500 ) - 80013ee: 2180 movs r1, #128 @ 0x80 - 80013f0: 0289 lsls r1, r1, #10 - 80013f2: 430a orrs r2, r1 - 80013f4: 63da str r2, [r3, #60] @ 0x3c - 80013f6: 4b42 ldr r3, [pc, #264] @ (8001500 ) - 80013f8: 6bda ldr r2, [r3, #60] @ 0x3c - 80013fa: 2380 movs r3, #128 @ 0x80 - 80013fc: 029b lsls r3, r3, #10 - 80013fe: 4013 ands r3, r2 - 8001400: 60fb str r3, [r7, #12] - 8001402: 68fb ldr r3, [r7, #12] + 800146c: 4b45 ldr r3, [pc, #276] @ (8001584 ) + 800146e: 6bda ldr r2, [r3, #60] @ 0x3c + 8001470: 4b44 ldr r3, [pc, #272] @ (8001584 ) + 8001472: 2180 movs r1, #128 @ 0x80 + 8001474: 0289 lsls r1, r1, #10 + 8001476: 430a orrs r2, r1 + 8001478: 63da str r2, [r3, #60] @ 0x3c + 800147a: 4b42 ldr r3, [pc, #264] @ (8001584 ) + 800147c: 6bda ldr r2, [r3, #60] @ 0x3c + 800147e: 2380 movs r3, #128 @ 0x80 + 8001480: 029b lsls r3, r3, #10 + 8001482: 4013 ands r3, r2 + 8001484: 60fb str r3, [r7, #12] + 8001486: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); - 8001404: 4b3e ldr r3, [pc, #248] @ (8001500 ) - 8001406: 6b5a ldr r2, [r3, #52] @ 0x34 - 8001408: 4b3d ldr r3, [pc, #244] @ (8001500 ) - 800140a: 2101 movs r1, #1 - 800140c: 430a orrs r2, r1 - 800140e: 635a str r2, [r3, #52] @ 0x34 - 8001410: 4b3b ldr r3, [pc, #236] @ (8001500 ) - 8001412: 6b5b ldr r3, [r3, #52] @ 0x34 - 8001414: 2201 movs r2, #1 - 8001416: 4013 ands r3, r2 - 8001418: 60bb str r3, [r7, #8] - 800141a: 68bb ldr r3, [r7, #8] + 8001488: 4b3e ldr r3, [pc, #248] @ (8001584 ) + 800148a: 6b5a ldr r2, [r3, #52] @ 0x34 + 800148c: 4b3d ldr r3, [pc, #244] @ (8001584 ) + 800148e: 2101 movs r1, #1 + 8001490: 430a orrs r2, r1 + 8001492: 635a str r2, [r3, #52] @ 0x34 + 8001494: 4b3b ldr r3, [pc, #236] @ (8001584 ) + 8001496: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001498: 2201 movs r2, #1 + 800149a: 4013 ands r3, r2 + 800149c: 60bb str r3, [r7, #8] + 800149e: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5; - 800141c: 2134 movs r1, #52 @ 0x34 - 800141e: 187b adds r3, r7, r1 - 8001420: 2232 movs r2, #50 @ 0x32 - 8001422: 601a str r2, [r3, #0] + 80014a0: 2134 movs r1, #52 @ 0x34 + 80014a2: 187b adds r3, r7, r1 + 80014a4: 2232 movs r2, #50 @ 0x32 + 80014a6: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - 8001424: 187b adds r3, r7, r1 - 8001426: 2202 movs r2, #2 - 8001428: 605a str r2, [r3, #4] + 80014a8: 187b adds r3, r7, r1 + 80014aa: 2202 movs r2, #2 + 80014ac: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; - 800142a: 187b adds r3, r7, r1 - 800142c: 2200 movs r2, #0 - 800142e: 609a str r2, [r3, #8] + 80014ae: 187b adds r3, r7, r1 + 80014b0: 2200 movs r2, #0 + 80014b2: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - 8001430: 187b adds r3, r7, r1 - 8001432: 2200 movs r2, #0 - 8001434: 60da str r2, [r3, #12] + 80014b4: 187b adds r3, r7, r1 + 80014b6: 2200 movs r2, #0 + 80014b8: 60da str r2, [r3, #12] GPIO_InitStruct.Alternate = GPIO_AF1_USART2; - 8001436: 187b adds r3, r7, r1 - 8001438: 2201 movs r2, #1 - 800143a: 611a str r2, [r3, #16] + 80014ba: 187b adds r3, r7, r1 + 80014bc: 2201 movs r2, #1 + 80014be: 611a str r2, [r3, #16] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - 800143c: 187a adds r2, r7, r1 - 800143e: 23a0 movs r3, #160 @ 0xa0 - 8001440: 05db lsls r3, r3, #23 - 8001442: 0011 movs r1, r2 - 8001444: 0018 movs r0, r3 - 8001446: f000 fccf bl 8001de8 + 80014c0: 187a adds r2, r7, r1 + 80014c2: 23a0 movs r3, #160 @ 0xa0 + 80014c4: 05db lsls r3, r3, #23 + 80014c6: 0011 movs r1, r2 + 80014c8: 0018 movs r0, r3 + 80014ca: f000 fccf bl 8001e6c hdma_usart2_rx.Instance = DMA1_Channel2; - 800144a: 4b30 ldr r3, [pc, #192] @ (800150c ) - 800144c: 4a30 ldr r2, [pc, #192] @ (8001510 ) - 800144e: 601a str r2, [r3, #0] + 80014ce: 4b30 ldr r3, [pc, #192] @ (8001590 ) + 80014d0: 4a30 ldr r2, [pc, #192] @ (8001594 ) + 80014d2: 601a str r2, [r3, #0] hdma_usart2_rx.Init.Request = DMA_REQUEST_USART2_RX; - 8001450: 4b2e ldr r3, [pc, #184] @ (800150c ) - 8001452: 2234 movs r2, #52 @ 0x34 - 8001454: 605a str r2, [r3, #4] + 80014d4: 4b2e ldr r3, [pc, #184] @ (8001590 ) + 80014d6: 2234 movs r2, #52 @ 0x34 + 80014d8: 605a str r2, [r3, #4] hdma_usart2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; - 8001456: 4b2d ldr r3, [pc, #180] @ (800150c ) - 8001458: 2200 movs r2, #0 - 800145a: 609a str r2, [r3, #8] + 80014da: 4b2d ldr r3, [pc, #180] @ (8001590 ) + 80014dc: 2200 movs r2, #0 + 80014de: 609a str r2, [r3, #8] hdma_usart2_rx.Init.PeriphInc = DMA_PINC_DISABLE; - 800145c: 4b2b ldr r3, [pc, #172] @ (800150c ) - 800145e: 2200 movs r2, #0 - 8001460: 60da str r2, [r3, #12] + 80014e0: 4b2b ldr r3, [pc, #172] @ (8001590 ) + 80014e2: 2200 movs r2, #0 + 80014e4: 60da str r2, [r3, #12] hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE; - 8001462: 4b2a ldr r3, [pc, #168] @ (800150c ) - 8001464: 2280 movs r2, #128 @ 0x80 - 8001466: 611a str r2, [r3, #16] + 80014e6: 4b2a ldr r3, [pc, #168] @ (8001590 ) + 80014e8: 2280 movs r2, #128 @ 0x80 + 80014ea: 611a str r2, [r3, #16] hdma_usart2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; - 8001468: 4b28 ldr r3, [pc, #160] @ (800150c ) - 800146a: 2200 movs r2, #0 - 800146c: 615a str r2, [r3, #20] + 80014ec: 4b28 ldr r3, [pc, #160] @ (8001590 ) + 80014ee: 2200 movs r2, #0 + 80014f0: 615a str r2, [r3, #20] hdma_usart2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; - 800146e: 4b27 ldr r3, [pc, #156] @ (800150c ) - 8001470: 2200 movs r2, #0 - 8001472: 619a str r2, [r3, #24] + 80014f2: 4b27 ldr r3, [pc, #156] @ (8001590 ) + 80014f4: 2200 movs r2, #0 + 80014f6: 619a str r2, [r3, #24] hdma_usart2_rx.Init.Mode = DMA_NORMAL; - 8001474: 4b25 ldr r3, [pc, #148] @ (800150c ) - 8001476: 2200 movs r2, #0 - 8001478: 61da str r2, [r3, #28] + 80014f8: 4b25 ldr r3, [pc, #148] @ (8001590 ) + 80014fa: 2200 movs r2, #0 + 80014fc: 61da str r2, [r3, #28] hdma_usart2_rx.Init.Priority = DMA_PRIORITY_MEDIUM; - 800147a: 4b24 ldr r3, [pc, #144] @ (800150c ) - 800147c: 2280 movs r2, #128 @ 0x80 - 800147e: 0152 lsls r2, r2, #5 - 8001480: 621a str r2, [r3, #32] + 80014fe: 4b24 ldr r3, [pc, #144] @ (8001590 ) + 8001500: 2280 movs r2, #128 @ 0x80 + 8001502: 0152 lsls r2, r2, #5 + 8001504: 621a str r2, [r3, #32] if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK) - 8001482: 4b22 ldr r3, [pc, #136] @ (800150c ) - 8001484: 0018 movs r0, r3 - 8001486: f000 fa5b bl 8001940 - 800148a: 1e03 subs r3, r0, #0 - 800148c: d001 beq.n 8001492 + 8001506: 4b22 ldr r3, [pc, #136] @ (8001590 ) + 8001508: 0018 movs r0, r3 + 800150a: f000 fa5b bl 80019c4 + 800150e: 1e03 subs r3, r0, #0 + 8001510: d001 beq.n 8001516 Error_Handler(); - 800148e: f7ff fe0b bl 80010a8 + 8001512: f7ff fe0b bl 800112c __HAL_LINKDMA(huart,hdmarx,hdma_usart2_rx); - 8001492: 687b ldr r3, [r7, #4] - 8001494: 2180 movs r1, #128 @ 0x80 - 8001496: 4a1d ldr r2, [pc, #116] @ (800150c ) - 8001498: 505a str r2, [r3, r1] - 800149a: 4b1c ldr r3, [pc, #112] @ (800150c ) - 800149c: 687a ldr r2, [r7, #4] - 800149e: 629a str r2, [r3, #40] @ 0x28 + 8001516: 687b ldr r3, [r7, #4] + 8001518: 2180 movs r1, #128 @ 0x80 + 800151a: 4a1d ldr r2, [pc, #116] @ (8001590 ) + 800151c: 505a str r2, [r3, r1] + 800151e: 4b1c ldr r3, [pc, #112] @ (8001590 ) + 8001520: 687a ldr r2, [r7, #4] + 8001522: 629a str r2, [r3, #40] @ 0x28 hdma_usart2_tx.Instance = DMA1_Channel1; - 80014a0: 4b1c ldr r3, [pc, #112] @ (8001514 ) - 80014a2: 4a1d ldr r2, [pc, #116] @ (8001518 ) - 80014a4: 601a str r2, [r3, #0] + 8001524: 4b1c ldr r3, [pc, #112] @ (8001598 ) + 8001526: 4a1d ldr r2, [pc, #116] @ (800159c ) + 8001528: 601a str r2, [r3, #0] hdma_usart2_tx.Init.Request = DMA_REQUEST_USART2_TX; - 80014a6: 4b1b ldr r3, [pc, #108] @ (8001514 ) - 80014a8: 2235 movs r2, #53 @ 0x35 - 80014aa: 605a str r2, [r3, #4] + 800152a: 4b1b ldr r3, [pc, #108] @ (8001598 ) + 800152c: 2235 movs r2, #53 @ 0x35 + 800152e: 605a str r2, [r3, #4] hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; - 80014ac: 4b19 ldr r3, [pc, #100] @ (8001514 ) - 80014ae: 2210 movs r2, #16 - 80014b0: 609a str r2, [r3, #8] + 8001530: 4b19 ldr r3, [pc, #100] @ (8001598 ) + 8001532: 2210 movs r2, #16 + 8001534: 609a str r2, [r3, #8] hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE; - 80014b2: 4b18 ldr r3, [pc, #96] @ (8001514 ) - 80014b4: 2200 movs r2, #0 - 80014b6: 60da str r2, [r3, #12] + 8001536: 4b18 ldr r3, [pc, #96] @ (8001598 ) + 8001538: 2200 movs r2, #0 + 800153a: 60da str r2, [r3, #12] hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE; - 80014b8: 4b16 ldr r3, [pc, #88] @ (8001514 ) - 80014ba: 2280 movs r2, #128 @ 0x80 - 80014bc: 611a str r2, [r3, #16] + 800153c: 4b16 ldr r3, [pc, #88] @ (8001598 ) + 800153e: 2280 movs r2, #128 @ 0x80 + 8001540: 611a str r2, [r3, #16] hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; - 80014be: 4b15 ldr r3, [pc, #84] @ (8001514 ) - 80014c0: 2200 movs r2, #0 - 80014c2: 615a str r2, [r3, #20] + 8001542: 4b15 ldr r3, [pc, #84] @ (8001598 ) + 8001544: 2200 movs r2, #0 + 8001546: 615a str r2, [r3, #20] hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; - 80014c4: 4b13 ldr r3, [pc, #76] @ (8001514 ) - 80014c6: 2200 movs r2, #0 - 80014c8: 619a str r2, [r3, #24] + 8001548: 4b13 ldr r3, [pc, #76] @ (8001598 ) + 800154a: 2200 movs r2, #0 + 800154c: 619a str r2, [r3, #24] hdma_usart2_tx.Init.Mode = DMA_NORMAL; - 80014ca: 4b12 ldr r3, [pc, #72] @ (8001514 ) - 80014cc: 2200 movs r2, #0 - 80014ce: 61da str r2, [r3, #28] + 800154e: 4b12 ldr r3, [pc, #72] @ (8001598 ) + 8001550: 2200 movs r2, #0 + 8001552: 61da str r2, [r3, #28] hdma_usart2_tx.Init.Priority = DMA_PRIORITY_HIGH; - 80014d0: 4b10 ldr r3, [pc, #64] @ (8001514 ) - 80014d2: 2280 movs r2, #128 @ 0x80 - 80014d4: 0192 lsls r2, r2, #6 - 80014d6: 621a str r2, [r3, #32] + 8001554: 4b10 ldr r3, [pc, #64] @ (8001598 ) + 8001556: 2280 movs r2, #128 @ 0x80 + 8001558: 0192 lsls r2, r2, #6 + 800155a: 621a str r2, [r3, #32] if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK) - 80014d8: 4b0e ldr r3, [pc, #56] @ (8001514 ) - 80014da: 0018 movs r0, r3 - 80014dc: f000 fa30 bl 8001940 - 80014e0: 1e03 subs r3, r0, #0 - 80014e2: d001 beq.n 80014e8 + 800155c: 4b0e ldr r3, [pc, #56] @ (8001598 ) + 800155e: 0018 movs r0, r3 + 8001560: f000 fa30 bl 80019c4 + 8001564: 1e03 subs r3, r0, #0 + 8001566: d001 beq.n 800156c Error_Handler(); - 80014e4: f7ff fde0 bl 80010a8 + 8001568: f7ff fde0 bl 800112c __HAL_LINKDMA(huart,hdmatx,hdma_usart2_tx); - 80014e8: 687b ldr r3, [r7, #4] - 80014ea: 4a0a ldr r2, [pc, #40] @ (8001514 ) - 80014ec: 67da str r2, [r3, #124] @ 0x7c - 80014ee: 4b09 ldr r3, [pc, #36] @ (8001514 ) - 80014f0: 687a ldr r2, [r7, #4] - 80014f2: 629a str r2, [r3, #40] @ 0x28 + 800156c: 687b ldr r3, [r7, #4] + 800156e: 4a0a ldr r2, [pc, #40] @ (8001598 ) + 8001570: 67da str r2, [r3, #124] @ 0x7c + 8001572: 4b09 ldr r3, [pc, #36] @ (8001598 ) + 8001574: 687a ldr r2, [r7, #4] + 8001576: 629a str r2, [r3, #40] @ 0x28 } - 80014f4: 46c0 nop @ (mov r8, r8) - 80014f6: 46bd mov sp, r7 - 80014f8: b013 add sp, #76 @ 0x4c - 80014fa: bd90 pop {r4, r7, pc} - 80014fc: 40013800 .word 0x40013800 - 8001500: 40021000 .word 0x40021000 - 8001504: 50000400 .word 0x50000400 - 8001508: 40004400 .word 0x40004400 - 800150c: 200002e4 .word 0x200002e4 - 8001510: 4002001c .word 0x4002001c - 8001514: 20000340 .word 0x20000340 - 8001518: 40020008 .word 0x40020008 + 8001578: 46c0 nop @ (mov r8, r8) + 800157a: 46bd mov sp, r7 + 800157c: b013 add sp, #76 @ 0x4c + 800157e: bd90 pop {r4, r7, pc} + 8001580: 40013800 .word 0x40013800 + 8001584: 40021000 .word 0x40021000 + 8001588: 50000400 .word 0x50000400 + 800158c: 40004400 .word 0x40004400 + 8001590: 200002e4 .word 0x200002e4 + 8001594: 4002001c .word 0x4002001c + 8001598: 20000340 .word 0x20000340 + 800159c: 40020008 .word 0x40020008 -0800151c : +080015a0 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { - 800151c: b580 push {r7, lr} - 800151e: af00 add r7, sp, #0 + 80015a0: b580 push {r7, lr} + 80015a2: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) - 8001520: 46c0 nop @ (mov r8, r8) - 8001522: e7fd b.n 8001520 + 80015a4: 46c0 nop @ (mov r8, r8) + 80015a6: e7fd b.n 80015a4 -08001524 : +080015a8 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { - 8001524: b580 push {r7, lr} - 8001526: af00 add r7, sp, #0 + 80015a8: b580 push {r7, lr} + 80015aa: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) - 8001528: 46c0 nop @ (mov r8, r8) - 800152a: e7fd b.n 8001528 + 80015ac: 46c0 nop @ (mov r8, r8) + 80015ae: e7fd b.n 80015ac -0800152c : +080015b0 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { - 800152c: b580 push {r7, lr} - 800152e: af00 add r7, sp, #0 + 80015b0: b580 push {r7, lr} + 80015b2: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } - 8001530: 46c0 nop @ (mov r8, r8) - 8001532: 46bd mov sp, r7 - 8001534: bd80 pop {r7, pc} + 80015b4: 46c0 nop @ (mov r8, r8) + 80015b6: 46bd mov sp, r7 + 80015b8: bd80 pop {r7, pc} -08001536 : +080015ba : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { - 8001536: b580 push {r7, lr} - 8001538: af00 add r7, sp, #0 + 80015ba: b580 push {r7, lr} + 80015bc: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } - 800153a: 46c0 nop @ (mov r8, r8) - 800153c: 46bd mov sp, r7 - 800153e: bd80 pop {r7, pc} + 80015be: 46c0 nop @ (mov r8, r8) + 80015c0: 46bd mov sp, r7 + 80015c2: bd80 pop {r7, pc} -08001540 : +080015c4 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { - 8001540: b580 push {r7, lr} - 8001542: af00 add r7, sp, #0 + 80015c4: b580 push {r7, lr} + 80015c6: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); - 8001544: f000 f8e4 bl 8001710 + 80015c8: f000 f8e4 bl 8001794 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } - 8001548: 46c0 nop @ (mov r8, r8) - 800154a: 46bd mov sp, r7 - 800154c: bd80 pop {r7, pc} + 80015cc: 46c0 nop @ (mov r8, r8) + 80015ce: 46bd mov sp, r7 + 80015d0: bd80 pop {r7, pc} -0800154e : +080015d2 : /** * @brief This function handles EXTI line 4 to 15 interrupts. */ void EXTI4_15_IRQHandler(void) { - 800154e: b580 push {r7, lr} - 8001550: af00 add r7, sp, #0 + 80015d2: b580 push {r7, lr} + 80015d4: af00 add r7, sp, #0 /* USER CODE BEGIN EXTI4_15_IRQn 0 */ /* USER CODE END EXTI4_15_IRQn 0 */ HAL_GPIO_EXTI_IRQHandler(SW2_Pin); - 8001552: 2380 movs r3, #128 @ 0x80 - 8001554: 005b lsls r3, r3, #1 - 8001556: 0018 movs r0, r3 - 8001558: f000 fdf2 bl 8002140 + 80015d6: 2380 movs r3, #128 @ 0x80 + 80015d8: 005b lsls r3, r3, #1 + 80015da: 0018 movs r0, r3 + 80015dc: f000 fdf2 bl 80021c4 HAL_GPIO_EXTI_IRQHandler(SW1_Pin); - 800155c: 2380 movs r3, #128 @ 0x80 - 800155e: 009b lsls r3, r3, #2 - 8001560: 0018 movs r0, r3 - 8001562: f000 fded bl 8002140 + 80015e0: 2380 movs r3, #128 @ 0x80 + 80015e2: 009b lsls r3, r3, #2 + 80015e4: 0018 movs r0, r3 + 80015e6: f000 fded bl 80021c4 /* USER CODE BEGIN EXTI4_15_IRQn 1 */ /* USER CODE END EXTI4_15_IRQn 1 */ } - 8001566: 46c0 nop @ (mov r8, r8) - 8001568: 46bd mov sp, r7 - 800156a: bd80 pop {r7, pc} + 80015ea: 46c0 nop @ (mov r8, r8) + 80015ec: 46bd mov sp, r7 + 80015ee: bd80 pop {r7, pc} -0800156c : +080015f0 : /** * @brief This function handles DMA1 channel 1 interrupt. */ void DMA1_Channel1_IRQHandler(void) { - 800156c: b580 push {r7, lr} - 800156e: af00 add r7, sp, #0 + 80015f0: b580 push {r7, lr} + 80015f2: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */ /* USER CODE END DMA1_Channel1_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart2_tx); - 8001570: 4b03 ldr r3, [pc, #12] @ (8001580 ) - 8001572: 0018 movs r0, r3 - 8001574: f000 faf6 bl 8001b64 + 80015f4: 4b03 ldr r3, [pc, #12] @ (8001604 ) + 80015f6: 0018 movs r0, r3 + 80015f8: f000 faf6 bl 8001be8 /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */ /* USER CODE END DMA1_Channel1_IRQn 1 */ } - 8001578: 46c0 nop @ (mov r8, r8) - 800157a: 46bd mov sp, r7 - 800157c: bd80 pop {r7, pc} - 800157e: 46c0 nop @ (mov r8, r8) - 8001580: 20000340 .word 0x20000340 + 80015fc: 46c0 nop @ (mov r8, r8) + 80015fe: 46bd mov sp, r7 + 8001600: bd80 pop {r7, pc} + 8001602: 46c0 nop @ (mov r8, r8) + 8001604: 20000340 .word 0x20000340 -08001584 : +08001608 : /** * @brief This function handles DMA1 channel 2 and channel 3 interrupts. */ void DMA1_Channel2_3_IRQHandler(void) { - 8001584: b580 push {r7, lr} - 8001586: af00 add r7, sp, #0 + 8001608: b580 push {r7, lr} + 800160a: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Channel2_3_IRQn 0 */ /* USER CODE END DMA1_Channel2_3_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart2_rx); - 8001588: 4b03 ldr r3, [pc, #12] @ (8001598 ) - 800158a: 0018 movs r0, r3 - 800158c: f000 faea bl 8001b64 + 800160c: 4b03 ldr r3, [pc, #12] @ (800161c ) + 800160e: 0018 movs r0, r3 + 8001610: f000 faea bl 8001be8 /* USER CODE BEGIN DMA1_Channel2_3_IRQn 1 */ /* USER CODE END DMA1_Channel2_3_IRQn 1 */ } - 8001590: 46c0 nop @ (mov r8, r8) - 8001592: 46bd mov sp, r7 - 8001594: bd80 pop {r7, pc} - 8001596: 46c0 nop @ (mov r8, r8) - 8001598: 200002e4 .word 0x200002e4 + 8001614: 46c0 nop @ (mov r8, r8) + 8001616: 46bd mov sp, r7 + 8001618: bd80 pop {r7, pc} + 800161a: 46c0 nop @ (mov r8, r8) + 800161c: 200002e4 .word 0x200002e4 -0800159c : +08001620 : /** * @brief This function handles TIM14 global interrupt. */ void TIM14_IRQHandler(void) { - 800159c: b580 push {r7, lr} - 800159e: af00 add r7, sp, #0 + 8001620: b580 push {r7, lr} + 8001622: af00 add r7, sp, #0 /* USER CODE BEGIN TIM14_IRQn 0 */ /* USER CODE END TIM14_IRQn 0 */ HAL_TIM_IRQHandler(&htim14); - 80015a0: 4b03 ldr r3, [pc, #12] @ (80015b0 ) - 80015a2: 0018 movs r0, r3 - 80015a4: f001 fbca bl 8002d3c + 8001624: 4b03 ldr r3, [pc, #12] @ (8001634 ) + 8001626: 0018 movs r0, r3 + 8001628: f001 fbca bl 8002dc0 /* USER CODE BEGIN TIM14_IRQn 1 */ /* USER CODE END TIM14_IRQn 1 */ } - 80015a8: 46c0 nop @ (mov r8, r8) - 80015aa: 46bd mov sp, r7 - 80015ac: bd80 pop {r7, pc} - 80015ae: 46c0 nop @ (mov r8, r8) - 80015b0: 200000d8 .word 0x200000d8 + 800162c: 46c0 nop @ (mov r8, r8) + 800162e: 46bd mov sp, r7 + 8001630: bd80 pop {r7, pc} + 8001632: 46c0 nop @ (mov r8, r8) + 8001634: 200000d8 .word 0x200000d8 -080015b4 : +08001638 : /** * @brief This function handles TIM16 global interrupt. */ void TIM16_IRQHandler(void) { - 80015b4: b580 push {r7, lr} - 80015b6: af00 add r7, sp, #0 + 8001638: b580 push {r7, lr} + 800163a: af00 add r7, sp, #0 /* USER CODE BEGIN TIM16_IRQn 0 */ /* USER CODE END TIM16_IRQn 0 */ HAL_TIM_IRQHandler(&htim16); - 80015b8: 4b03 ldr r3, [pc, #12] @ (80015c8 ) - 80015ba: 0018 movs r0, r3 - 80015bc: f001 fbbe bl 8002d3c + 800163c: 4b03 ldr r3, [pc, #12] @ (800164c ) + 800163e: 0018 movs r0, r3 + 8001640: f001 fbbe bl 8002dc0 /* USER CODE BEGIN TIM16_IRQn 1 */ /* USER CODE END TIM16_IRQn 1 */ } - 80015c0: 46c0 nop @ (mov r8, r8) - 80015c2: 46bd mov sp, r7 - 80015c4: bd80 pop {r7, pc} - 80015c6: 46c0 nop @ (mov r8, r8) - 80015c8: 20000124 .word 0x20000124 + 8001644: 46c0 nop @ (mov r8, r8) + 8001646: 46bd mov sp, r7 + 8001648: bd80 pop {r7, pc} + 800164a: 46c0 nop @ (mov r8, r8) + 800164c: 20000124 .word 0x20000124 -080015cc : +08001650 : /** * @brief This function handles TIM17 global interrupt. */ void TIM17_IRQHandler(void) { - 80015cc: b580 push {r7, lr} - 80015ce: af00 add r7, sp, #0 + 8001650: b580 push {r7, lr} + 8001652: af00 add r7, sp, #0 /* USER CODE BEGIN TIM17_IRQn 0 */ /* USER CODE END TIM17_IRQn 0 */ HAL_TIM_IRQHandler(&htim17); - 80015d0: 4b03 ldr r3, [pc, #12] @ (80015e0 ) - 80015d2: 0018 movs r0, r3 - 80015d4: f001 fbb2 bl 8002d3c + 8001654: 4b03 ldr r3, [pc, #12] @ (8001664 ) + 8001656: 0018 movs r0, r3 + 8001658: f001 fbb2 bl 8002dc0 /* USER CODE BEGIN TIM17_IRQn 1 */ /* USER CODE END TIM17_IRQn 1 */ } - 80015d8: 46c0 nop @ (mov r8, r8) - 80015da: 46bd mov sp, r7 - 80015dc: bd80 pop {r7, pc} - 80015de: 46c0 nop @ (mov r8, r8) - 80015e0: 20000170 .word 0x20000170 + 800165c: 46c0 nop @ (mov r8, r8) + 800165e: 46bd mov sp, r7 + 8001660: bd80 pop {r7, pc} + 8001662: 46c0 nop @ (mov r8, r8) + 8001664: 20000170 .word 0x20000170 -080015e4 : +08001668 : * @brief Setup the microcontroller system. * @param None * @retval None */ void SystemInit(void) { - 80015e4: b580 push {r7, lr} - 80015e6: af00 add r7, sp, #0 + 8001668: b580 push {r7, lr} + 800166a: af00 add r7, sp, #0 /* Configure the Vector Table location add offset address ------------------*/ #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #else SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ - 80015e8: 4b03 ldr r3, [pc, #12] @ (80015f8 ) - 80015ea: 2280 movs r2, #128 @ 0x80 - 80015ec: 0512 lsls r2, r2, #20 - 80015ee: 609a str r2, [r3, #8] + 800166c: 4b03 ldr r3, [pc, #12] @ (800167c ) + 800166e: 2280 movs r2, #128 @ 0x80 + 8001670: 0512 lsls r2, r2, #20 + 8001672: 609a str r2, [r3, #8] #endif } - 80015f0: 46c0 nop @ (mov r8, r8) - 80015f2: 46bd mov sp, r7 - 80015f4: bd80 pop {r7, pc} - 80015f6: 46c0 nop @ (mov r8, r8) - 80015f8: e000ed00 .word 0xe000ed00 + 8001674: 46c0 nop @ (mov r8, r8) + 8001676: 46bd mov sp, r7 + 8001678: bd80 pop {r7, pc} + 800167a: 46c0 nop @ (mov r8, r8) + 800167c: e000ed00 .word 0xe000ed00 -080015fc : +08001680 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr r0, =_estack - 80015fc: 480d ldr r0, [pc, #52] @ (8001634 ) + 8001680: 480d ldr r0, [pc, #52] @ (80016b8 ) mov sp, r0 /* set stack pointer */ - 80015fe: 4685 mov sp, r0 + 8001682: 4685 mov sp, r0 /* Call the clock system initialization function.*/ bl SystemInit - 8001600: f7ff fff0 bl 80015e4 + 8001684: f7ff fff0 bl 8001668 /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 - 8001604: 2100 movs r1, #0 + 8001688: 2100 movs r1, #0 b LoopCopyDataInit - 8001606: e003 b.n 8001610 + 800168a: e003 b.n 8001694 -08001608 : +0800168c : CopyDataInit: ldr r3, =_sidata - 8001608: 4b0b ldr r3, [pc, #44] @ (8001638 ) + 800168c: 4b0b ldr r3, [pc, #44] @ (80016bc ) ldr r3, [r3, r1] - 800160a: 585b ldr r3, [r3, r1] + 800168e: 585b ldr r3, [r3, r1] str r3, [r0, r1] - 800160c: 5043 str r3, [r0, r1] + 8001690: 5043 str r3, [r0, r1] adds r1, r1, #4 - 800160e: 3104 adds r1, #4 + 8001692: 3104 adds r1, #4 -08001610 : +08001694 : LoopCopyDataInit: ldr r0, =_sdata - 8001610: 480a ldr r0, [pc, #40] @ (800163c ) + 8001694: 480a ldr r0, [pc, #40] @ (80016c0 ) ldr r3, =_edata - 8001612: 4b0b ldr r3, [pc, #44] @ (8001640 ) + 8001696: 4b0b ldr r3, [pc, #44] @ (80016c4 ) adds r2, r0, r1 - 8001614: 1842 adds r2, r0, r1 + 8001698: 1842 adds r2, r0, r1 cmp r2, r3 - 8001616: 429a cmp r2, r3 + 800169a: 429a cmp r2, r3 bcc CopyDataInit - 8001618: d3f6 bcc.n 8001608 + 800169c: d3f6 bcc.n 800168c ldr r2, =_sbss - 800161a: 4a0a ldr r2, [pc, #40] @ (8001644 ) + 800169e: 4a0a ldr r2, [pc, #40] @ (80016c8 ) b LoopFillZerobss - 800161c: e002 b.n 8001624 + 80016a0: e002 b.n 80016a8 -0800161e : +080016a2 : /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 - 800161e: 2300 movs r3, #0 + 80016a2: 2300 movs r3, #0 str r3, [r2] - 8001620: 6013 str r3, [r2, #0] + 80016a4: 6013 str r3, [r2, #0] adds r2, r2, #4 - 8001622: 3204 adds r2, #4 + 80016a6: 3204 adds r2, #4 -08001624 : +080016a8 : LoopFillZerobss: ldr r3, = _ebss - 8001624: 4b08 ldr r3, [pc, #32] @ (8001648 ) + 80016a8: 4b08 ldr r3, [pc, #32] @ (80016cc ) cmp r2, r3 - 8001626: 429a cmp r2, r3 + 80016aa: 429a cmp r2, r3 bcc FillZerobss - 8001628: d3f9 bcc.n 800161e + 80016ac: d3f9 bcc.n 80016a2 /* Call static constructors */ bl __libc_init_array - 800162a: f003 fb8d bl 8004d48 <__libc_init_array> + 80016ae: f003 fb8d bl 8004dcc <__libc_init_array> /* Call the application's entry point.*/ bl main - 800162e: f7fe ffcb bl 80005c8
+ 80016b2: f7fe ff89 bl 80005c8
-08001632 : +080016b6 : LoopForever: b LoopForever - 8001632: e7fe b.n 8001632 + 80016b6: e7fe b.n 80016b6 ldr r0, =_estack - 8001634: 20003000 .word 0x20003000 + 80016b8: 20003000 .word 0x20003000 ldr r3, =_sidata - 8001638: 08004ea0 .word 0x08004ea0 + 80016bc: 08004f24 .word 0x08004f24 ldr r0, =_sdata - 800163c: 20000000 .word 0x20000000 + 80016c0: 20000000 .word 0x20000000 ldr r3, =_edata - 8001640: 20000024 .word 0x20000024 + 80016c4: 20000024 .word 0x20000024 ldr r2, =_sbss - 8001644: 20000024 .word 0x20000024 + 80016c8: 20000024 .word 0x20000024 ldr r3, = _ebss - 8001648: 200004b0 .word 0x200004b0 + 80016cc: 200004b4 .word 0x200004b4 -0800164c : +080016d0 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop - 800164c: e7fe b.n 800164c + 80016d0: e7fe b.n 80016d0 -0800164e : +080016d2 : * each 1ms in the SysTick_Handler() interrupt handler. * * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { - 800164e: b580 push {r7, lr} - 8001650: b082 sub sp, #8 - 8001652: af00 add r7, sp, #0 + 80016d2: b580 push {r7, lr} + 80016d4: b082 sub sp, #8 + 80016d6: af00 add r7, sp, #0 HAL_StatusTypeDef status = HAL_OK; - 8001654: 1dfb adds r3, r7, #7 - 8001656: 2200 movs r2, #0 - 8001658: 701a strb r2, [r3, #0] + 80016d8: 1dfb adds r3, r7, #7 + 80016da: 2200 movs r2, #0 + 80016dc: 701a strb r2, [r3, #0] #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); #endif /* PREFETCH_ENABLE */ /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */ if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) - 800165a: 2003 movs r0, #3 - 800165c: f000 f80e bl 800167c - 8001660: 1e03 subs r3, r0, #0 - 8001662: d003 beq.n 800166c + 80016de: 2003 movs r0, #3 + 80016e0: f000 f80e bl 8001700 + 80016e4: 1e03 subs r3, r0, #0 + 80016e6: d003 beq.n 80016f0 { status = HAL_ERROR; - 8001664: 1dfb adds r3, r7, #7 - 8001666: 2201 movs r2, #1 - 8001668: 701a strb r2, [r3, #0] - 800166a: e001 b.n 8001670 + 80016e8: 1dfb adds r3, r7, #7 + 80016ea: 2201 movs r2, #1 + 80016ec: 701a strb r2, [r3, #0] + 80016ee: e001 b.n 80016f4 } else { /* Init the low level hardware */ HAL_MspInit(); - 800166c: f7ff fd22 bl 80010b4 + 80016f0: f7ff fd22 bl 8001138 } /* Return function status */ return status; - 8001670: 1dfb adds r3, r7, #7 - 8001672: 781b ldrb r3, [r3, #0] + 80016f4: 1dfb adds r3, r7, #7 + 80016f6: 781b ldrb r3, [r3, #0] } - 8001674: 0018 movs r0, r3 - 8001676: 46bd mov sp, r7 - 8001678: b002 add sp, #8 - 800167a: bd80 pop {r7, pc} + 80016f8: 0018 movs r0, r3 + 80016fa: 46bd mov sp, r7 + 80016fc: b002 add sp, #8 + 80016fe: bd80 pop {r7, pc} -0800167c : +08001700 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { - 800167c: b590 push {r4, r7, lr} - 800167e: b085 sub sp, #20 - 8001680: af00 add r7, sp, #0 - 8001682: 6078 str r0, [r7, #4] + 8001700: b590 push {r4, r7, lr} + 8001702: b085 sub sp, #20 + 8001704: af00 add r7, sp, #0 + 8001706: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; - 8001684: 230f movs r3, #15 - 8001686: 18fb adds r3, r7, r3 - 8001688: 2200 movs r2, #0 - 800168a: 701a strb r2, [r3, #0] + 8001708: 230f movs r3, #15 + 800170a: 18fb adds r3, r7, r3 + 800170c: 2200 movs r2, #0 + 800170e: 701a strb r2, [r3, #0] if ((uint32_t)uwTickFreq != 0UL) - 800168c: 4b1d ldr r3, [pc, #116] @ (8001704 ) - 800168e: 781b ldrb r3, [r3, #0] - 8001690: 2b00 cmp r3, #0 - 8001692: d02b beq.n 80016ec + 8001710: 4b1d ldr r3, [pc, #116] @ (8001788 ) + 8001712: 781b ldrb r3, [r3, #0] + 8001714: 2b00 cmp r3, #0 + 8001716: d02b beq.n 8001770 { /*Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) == 0U) - 8001694: 4b1c ldr r3, [pc, #112] @ (8001708 ) - 8001696: 681c ldr r4, [r3, #0] - 8001698: 4b1a ldr r3, [pc, #104] @ (8001704 ) - 800169a: 781b ldrb r3, [r3, #0] - 800169c: 0019 movs r1, r3 - 800169e: 23fa movs r3, #250 @ 0xfa - 80016a0: 0098 lsls r0, r3, #2 - 80016a2: f7fe fd31 bl 8000108 <__udivsi3> - 80016a6: 0003 movs r3, r0 - 80016a8: 0019 movs r1, r3 - 80016aa: 0020 movs r0, r4 - 80016ac: f7fe fd2c bl 8000108 <__udivsi3> - 80016b0: 0003 movs r3, r0 - 80016b2: 0018 movs r0, r3 - 80016b4: f000 f937 bl 8001926 - 80016b8: 1e03 subs r3, r0, #0 - 80016ba: d112 bne.n 80016e2 + 8001718: 4b1c ldr r3, [pc, #112] @ (800178c ) + 800171a: 681c ldr r4, [r3, #0] + 800171c: 4b1a ldr r3, [pc, #104] @ (8001788 ) + 800171e: 781b ldrb r3, [r3, #0] + 8001720: 0019 movs r1, r3 + 8001722: 23fa movs r3, #250 @ 0xfa + 8001724: 0098 lsls r0, r3, #2 + 8001726: f7fe fcef bl 8000108 <__udivsi3> + 800172a: 0003 movs r3, r0 + 800172c: 0019 movs r1, r3 + 800172e: 0020 movs r0, r4 + 8001730: f7fe fcea bl 8000108 <__udivsi3> + 8001734: 0003 movs r3, r0 + 8001736: 0018 movs r0, r3 + 8001738: f000 f937 bl 80019aa + 800173c: 1e03 subs r3, r0, #0 + 800173e: d112 bne.n 8001766 { /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) - 80016bc: 687b ldr r3, [r7, #4] - 80016be: 2b03 cmp r3, #3 - 80016c0: d80a bhi.n 80016d8 + 8001740: 687b ldr r3, [r7, #4] + 8001742: 2b03 cmp r3, #3 + 8001744: d80a bhi.n 800175c { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); - 80016c2: 6879 ldr r1, [r7, #4] - 80016c4: 2301 movs r3, #1 - 80016c6: 425b negs r3, r3 - 80016c8: 2200 movs r2, #0 - 80016ca: 0018 movs r0, r3 - 80016cc: f000 f906 bl 80018dc + 8001746: 6879 ldr r1, [r7, #4] + 8001748: 2301 movs r3, #1 + 800174a: 425b negs r3, r3 + 800174c: 2200 movs r2, #0 + 800174e: 0018 movs r0, r3 + 8001750: f000 f906 bl 8001960 uwTickPrio = TickPriority; - 80016d0: 4b0e ldr r3, [pc, #56] @ (800170c ) - 80016d2: 687a ldr r2, [r7, #4] - 80016d4: 601a str r2, [r3, #0] - 80016d6: e00d b.n 80016f4 + 8001754: 4b0e ldr r3, [pc, #56] @ (8001790 ) + 8001756: 687a ldr r2, [r7, #4] + 8001758: 601a str r2, [r3, #0] + 800175a: e00d b.n 8001778 } else { status = HAL_ERROR; - 80016d8: 230f movs r3, #15 - 80016da: 18fb adds r3, r7, r3 - 80016dc: 2201 movs r2, #1 - 80016de: 701a strb r2, [r3, #0] - 80016e0: e008 b.n 80016f4 + 800175c: 230f movs r3, #15 + 800175e: 18fb adds r3, r7, r3 + 8001760: 2201 movs r2, #1 + 8001762: 701a strb r2, [r3, #0] + 8001764: e008 b.n 8001778 } } else { status = HAL_ERROR; - 80016e2: 230f movs r3, #15 - 80016e4: 18fb adds r3, r7, r3 - 80016e6: 2201 movs r2, #1 - 80016e8: 701a strb r2, [r3, #0] - 80016ea: e003 b.n 80016f4 + 8001766: 230f movs r3, #15 + 8001768: 18fb adds r3, r7, r3 + 800176a: 2201 movs r2, #1 + 800176c: 701a strb r2, [r3, #0] + 800176e: e003 b.n 8001778 } } else { status = HAL_ERROR; - 80016ec: 230f movs r3, #15 - 80016ee: 18fb adds r3, r7, r3 - 80016f0: 2201 movs r2, #1 - 80016f2: 701a strb r2, [r3, #0] + 8001770: 230f movs r3, #15 + 8001772: 18fb adds r3, r7, r3 + 8001774: 2201 movs r2, #1 + 8001776: 701a strb r2, [r3, #0] } /* Return function status */ return status; - 80016f4: 230f movs r3, #15 - 80016f6: 18fb adds r3, r7, r3 - 80016f8: 781b ldrb r3, [r3, #0] + 8001778: 230f movs r3, #15 + 800177a: 18fb adds r3, r7, r3 + 800177c: 781b ldrb r3, [r3, #0] } - 80016fa: 0018 movs r0, r3 - 80016fc: 46bd mov sp, r7 - 80016fe: b005 add sp, #20 - 8001700: bd90 pop {r4, r7, pc} - 8001702: 46c0 nop @ (mov r8, r8) - 8001704: 20000020 .word 0x20000020 - 8001708: 20000018 .word 0x20000018 - 800170c: 2000001c .word 0x2000001c + 800177e: 0018 movs r0, r3 + 8001780: 46bd mov sp, r7 + 8001782: b005 add sp, #20 + 8001784: bd90 pop {r4, r7, pc} + 8001786: 46c0 nop @ (mov r8, r8) + 8001788: 20000020 .word 0x20000020 + 800178c: 20000018 .word 0x20000018 + 8001790: 2000001c .word 0x2000001c -08001710 : +08001794 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { - 8001710: b580 push {r7, lr} - 8001712: af00 add r7, sp, #0 + 8001794: b580 push {r7, lr} + 8001796: af00 add r7, sp, #0 uwTick += (uint32_t)uwTickFreq; - 8001714: 4b05 ldr r3, [pc, #20] @ (800172c ) - 8001716: 781b ldrb r3, [r3, #0] - 8001718: 001a movs r2, r3 - 800171a: 4b05 ldr r3, [pc, #20] @ (8001730 ) - 800171c: 681b ldr r3, [r3, #0] - 800171e: 18d2 adds r2, r2, r3 - 8001720: 4b03 ldr r3, [pc, #12] @ (8001730 ) - 8001722: 601a str r2, [r3, #0] + 8001798: 4b05 ldr r3, [pc, #20] @ (80017b0 ) + 800179a: 781b ldrb r3, [r3, #0] + 800179c: 001a movs r2, r3 + 800179e: 4b05 ldr r3, [pc, #20] @ (80017b4 ) + 80017a0: 681b ldr r3, [r3, #0] + 80017a2: 18d2 adds r2, r2, r3 + 80017a4: 4b03 ldr r3, [pc, #12] @ (80017b4 ) + 80017a6: 601a str r2, [r3, #0] } - 8001724: 46c0 nop @ (mov r8, r8) - 8001726: 46bd mov sp, r7 - 8001728: bd80 pop {r7, pc} - 800172a: 46c0 nop @ (mov r8, r8) - 800172c: 20000020 .word 0x20000020 - 8001730: 200004ac .word 0x200004ac + 80017a8: 46c0 nop @ (mov r8, r8) + 80017aa: 46bd mov sp, r7 + 80017ac: bd80 pop {r7, pc} + 80017ae: 46c0 nop @ (mov r8, r8) + 80017b0: 20000020 .word 0x20000020 + 80017b4: 200004b0 .word 0x200004b0 -08001734 : +080017b8 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { - 8001734: b580 push {r7, lr} - 8001736: af00 add r7, sp, #0 + 80017b8: b580 push {r7, lr} + 80017ba: af00 add r7, sp, #0 return uwTick; - 8001738: 4b02 ldr r3, [pc, #8] @ (8001744 ) - 800173a: 681b ldr r3, [r3, #0] + 80017bc: 4b02 ldr r3, [pc, #8] @ (80017c8 ) + 80017be: 681b ldr r3, [r3, #0] } - 800173c: 0018 movs r0, r3 - 800173e: 46bd mov sp, r7 - 8001740: bd80 pop {r7, pc} - 8001742: 46c0 nop @ (mov r8, r8) - 8001744: 200004ac .word 0x200004ac + 80017c0: 0018 movs r0, r3 + 80017c2: 46bd mov sp, r7 + 80017c4: bd80 pop {r7, pc} + 80017c6: 46c0 nop @ (mov r8, r8) + 80017c8: 200004b0 .word 0x200004b0 -08001748 : +080017cc : /** * @brief Returns first word of the unique device identifier (UID based on 96 bits) * @retval Device identifier */ uint32_t HAL_GetUIDw0(void) { - 8001748: b580 push {r7, lr} - 800174a: af00 add r7, sp, #0 + 80017cc: b580 push {r7, lr} + 80017ce: af00 add r7, sp, #0 return (READ_REG(*((uint32_t *)UID_BASE))); - 800174c: 4b02 ldr r3, [pc, #8] @ (8001758 ) - 800174e: 681b ldr r3, [r3, #0] + 80017d0: 4b02 ldr r3, [pc, #8] @ (80017dc ) + 80017d2: 681b ldr r3, [r3, #0] } - 8001750: 0018 movs r0, r3 - 8001752: 46bd mov sp, r7 - 8001754: bd80 pop {r7, pc} - 8001756: 46c0 nop @ (mov r8, r8) - 8001758: 1fff7550 .word 0x1fff7550 + 80017d4: 0018 movs r0, r3 + 80017d6: 46bd mov sp, r7 + 80017d8: bd80 pop {r7, pc} + 80017da: 46c0 nop @ (mov r8, r8) + 80017dc: 1fff7550 .word 0x1fff7550 -0800175c : +080017e0 : /** * @brief Returns second word of the unique device identifier (UID based on 96 bits) * @retval Device identifier */ uint32_t HAL_GetUIDw1(void) { - 800175c: b580 push {r7, lr} - 800175e: af00 add r7, sp, #0 + 80017e0: b580 push {r7, lr} + 80017e2: af00 add r7, sp, #0 return (READ_REG(*((uint32_t *)(UID_BASE + 4U)))); - 8001760: 4b02 ldr r3, [pc, #8] @ (800176c ) - 8001762: 681b ldr r3, [r3, #0] + 80017e4: 4b02 ldr r3, [pc, #8] @ (80017f0 ) + 80017e6: 681b ldr r3, [r3, #0] } - 8001764: 0018 movs r0, r3 - 8001766: 46bd mov sp, r7 - 8001768: bd80 pop {r7, pc} - 800176a: 46c0 nop @ (mov r8, r8) - 800176c: 1fff7554 .word 0x1fff7554 + 80017e8: 0018 movs r0, r3 + 80017ea: 46bd mov sp, r7 + 80017ec: bd80 pop {r7, pc} + 80017ee: 46c0 nop @ (mov r8, r8) + 80017f0: 1fff7554 .word 0x1fff7554 -08001770 : +080017f4 : /** * @brief Returns third word of the unique device identifier (UID based on 96 bits) * @retval Device identifier */ uint32_t HAL_GetUIDw2(void) { - 8001770: b580 push {r7, lr} - 8001772: af00 add r7, sp, #0 + 80017f4: b580 push {r7, lr} + 80017f6: af00 add r7, sp, #0 return (READ_REG(*((uint32_t *)(UID_BASE + 8U)))); - 8001774: 4b02 ldr r3, [pc, #8] @ (8001780 ) - 8001776: 681b ldr r3, [r3, #0] + 80017f8: 4b02 ldr r3, [pc, #8] @ (8001804 ) + 80017fa: 681b ldr r3, [r3, #0] } - 8001778: 0018 movs r0, r3 - 800177a: 46bd mov sp, r7 - 800177c: bd80 pop {r7, pc} - 800177e: 46c0 nop @ (mov r8, r8) - 8001780: 1fff7558 .word 0x1fff7558 + 80017fc: 0018 movs r0, r3 + 80017fe: 46bd mov sp, r7 + 8001800: bd80 pop {r7, pc} + 8001802: 46c0 nop @ (mov r8, r8) + 8001804: 1fff7558 .word 0x1fff7558 -08001784 <__NVIC_EnableIRQ>: +08001808 <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { - 8001784: b580 push {r7, lr} - 8001786: b082 sub sp, #8 - 8001788: af00 add r7, sp, #0 - 800178a: 0002 movs r2, r0 - 800178c: 1dfb adds r3, r7, #7 - 800178e: 701a strb r2, [r3, #0] + 8001808: b580 push {r7, lr} + 800180a: b082 sub sp, #8 + 800180c: af00 add r7, sp, #0 + 800180e: 0002 movs r2, r0 + 8001810: 1dfb adds r3, r7, #7 + 8001812: 701a strb r2, [r3, #0] if ((int32_t)(IRQn) >= 0) - 8001790: 1dfb adds r3, r7, #7 - 8001792: 781b ldrb r3, [r3, #0] - 8001794: 2b7f cmp r3, #127 @ 0x7f - 8001796: d809 bhi.n 80017ac <__NVIC_EnableIRQ+0x28> + 8001814: 1dfb adds r3, r7, #7 + 8001816: 781b ldrb r3, [r3, #0] + 8001818: 2b7f cmp r3, #127 @ 0x7f + 800181a: d809 bhi.n 8001830 <__NVIC_EnableIRQ+0x28> { __COMPILER_BARRIER(); NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - 8001798: 1dfb adds r3, r7, #7 - 800179a: 781b ldrb r3, [r3, #0] - 800179c: 001a movs r2, r3 - 800179e: 231f movs r3, #31 - 80017a0: 401a ands r2, r3 - 80017a2: 4b04 ldr r3, [pc, #16] @ (80017b4 <__NVIC_EnableIRQ+0x30>) - 80017a4: 2101 movs r1, #1 - 80017a6: 4091 lsls r1, r2 - 80017a8: 000a movs r2, r1 - 80017aa: 601a str r2, [r3, #0] + 800181c: 1dfb adds r3, r7, #7 + 800181e: 781b ldrb r3, [r3, #0] + 8001820: 001a movs r2, r3 + 8001822: 231f movs r3, #31 + 8001824: 401a ands r2, r3 + 8001826: 4b04 ldr r3, [pc, #16] @ (8001838 <__NVIC_EnableIRQ+0x30>) + 8001828: 2101 movs r1, #1 + 800182a: 4091 lsls r1, r2 + 800182c: 000a movs r2, r1 + 800182e: 601a str r2, [r3, #0] __COMPILER_BARRIER(); } } - 80017ac: 46c0 nop @ (mov r8, r8) - 80017ae: 46bd mov sp, r7 - 80017b0: b002 add sp, #8 - 80017b2: bd80 pop {r7, pc} - 80017b4: e000e100 .word 0xe000e100 + 8001830: 46c0 nop @ (mov r8, r8) + 8001832: 46bd mov sp, r7 + 8001834: b002 add sp, #8 + 8001836: bd80 pop {r7, pc} + 8001838: e000e100 .word 0xe000e100 -080017b8 <__NVIC_SetPriority>: +0800183c <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { - 80017b8: b590 push {r4, r7, lr} - 80017ba: b083 sub sp, #12 - 80017bc: af00 add r7, sp, #0 - 80017be: 0002 movs r2, r0 - 80017c0: 6039 str r1, [r7, #0] - 80017c2: 1dfb adds r3, r7, #7 - 80017c4: 701a strb r2, [r3, #0] + 800183c: b590 push {r4, r7, lr} + 800183e: b083 sub sp, #12 + 8001840: af00 add r7, sp, #0 + 8001842: 0002 movs r2, r0 + 8001844: 6039 str r1, [r7, #0] + 8001846: 1dfb adds r3, r7, #7 + 8001848: 701a strb r2, [r3, #0] if ((int32_t)(IRQn) >= 0) - 80017c6: 1dfb adds r3, r7, #7 - 80017c8: 781b ldrb r3, [r3, #0] - 80017ca: 2b7f cmp r3, #127 @ 0x7f - 80017cc: d828 bhi.n 8001820 <__NVIC_SetPriority+0x68> + 800184a: 1dfb adds r3, r7, #7 + 800184c: 781b ldrb r3, [r3, #0] + 800184e: 2b7f cmp r3, #127 @ 0x7f + 8001850: d828 bhi.n 80018a4 <__NVIC_SetPriority+0x68> { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - 80017ce: 4a2f ldr r2, [pc, #188] @ (800188c <__NVIC_SetPriority+0xd4>) - 80017d0: 1dfb adds r3, r7, #7 - 80017d2: 781b ldrb r3, [r3, #0] - 80017d4: b25b sxtb r3, r3 - 80017d6: 089b lsrs r3, r3, #2 - 80017d8: 33c0 adds r3, #192 @ 0xc0 - 80017da: 009b lsls r3, r3, #2 - 80017dc: 589b ldr r3, [r3, r2] - 80017de: 1dfa adds r2, r7, #7 - 80017e0: 7812 ldrb r2, [r2, #0] - 80017e2: 0011 movs r1, r2 - 80017e4: 2203 movs r2, #3 - 80017e6: 400a ands r2, r1 - 80017e8: 00d2 lsls r2, r2, #3 - 80017ea: 21ff movs r1, #255 @ 0xff - 80017ec: 4091 lsls r1, r2 - 80017ee: 000a movs r2, r1 - 80017f0: 43d2 mvns r2, r2 - 80017f2: 401a ands r2, r3 - 80017f4: 0011 movs r1, r2 + 8001852: 4a2f ldr r2, [pc, #188] @ (8001910 <__NVIC_SetPriority+0xd4>) + 8001854: 1dfb adds r3, r7, #7 + 8001856: 781b ldrb r3, [r3, #0] + 8001858: b25b sxtb r3, r3 + 800185a: 089b lsrs r3, r3, #2 + 800185c: 33c0 adds r3, #192 @ 0xc0 + 800185e: 009b lsls r3, r3, #2 + 8001860: 589b ldr r3, [r3, r2] + 8001862: 1dfa adds r2, r7, #7 + 8001864: 7812 ldrb r2, [r2, #0] + 8001866: 0011 movs r1, r2 + 8001868: 2203 movs r2, #3 + 800186a: 400a ands r2, r1 + 800186c: 00d2 lsls r2, r2, #3 + 800186e: 21ff movs r1, #255 @ 0xff + 8001870: 4091 lsls r1, r2 + 8001872: 000a movs r2, r1 + 8001874: 43d2 mvns r2, r2 + 8001876: 401a ands r2, r3 + 8001878: 0011 movs r1, r2 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - 80017f6: 683b ldr r3, [r7, #0] - 80017f8: 019b lsls r3, r3, #6 - 80017fa: 22ff movs r2, #255 @ 0xff - 80017fc: 401a ands r2, r3 - 80017fe: 1dfb adds r3, r7, #7 - 8001800: 781b ldrb r3, [r3, #0] - 8001802: 0018 movs r0, r3 - 8001804: 2303 movs r3, #3 - 8001806: 4003 ands r3, r0 - 8001808: 00db lsls r3, r3, #3 - 800180a: 409a lsls r2, r3 + 800187a: 683b ldr r3, [r7, #0] + 800187c: 019b lsls r3, r3, #6 + 800187e: 22ff movs r2, #255 @ 0xff + 8001880: 401a ands r2, r3 + 8001882: 1dfb adds r3, r7, #7 + 8001884: 781b ldrb r3, [r3, #0] + 8001886: 0018 movs r0, r3 + 8001888: 2303 movs r3, #3 + 800188a: 4003 ands r3, r0 + 800188c: 00db lsls r3, r3, #3 + 800188e: 409a lsls r2, r3 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - 800180c: 481f ldr r0, [pc, #124] @ (800188c <__NVIC_SetPriority+0xd4>) - 800180e: 1dfb adds r3, r7, #7 - 8001810: 781b ldrb r3, [r3, #0] - 8001812: b25b sxtb r3, r3 - 8001814: 089b lsrs r3, r3, #2 - 8001816: 430a orrs r2, r1 - 8001818: 33c0 adds r3, #192 @ 0xc0 - 800181a: 009b lsls r3, r3, #2 - 800181c: 501a str r2, [r3, r0] + 8001890: 481f ldr r0, [pc, #124] @ (8001910 <__NVIC_SetPriority+0xd4>) + 8001892: 1dfb adds r3, r7, #7 + 8001894: 781b ldrb r3, [r3, #0] + 8001896: b25b sxtb r3, r3 + 8001898: 089b lsrs r3, r3, #2 + 800189a: 430a orrs r2, r1 + 800189c: 33c0 adds r3, #192 @ 0xc0 + 800189e: 009b lsls r3, r3, #2 + 80018a0: 501a str r2, [r3, r0] else { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } - 800181e: e031 b.n 8001884 <__NVIC_SetPriority+0xcc> + 80018a2: e031 b.n 8001908 <__NVIC_SetPriority+0xcc> SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - 8001820: 4a1b ldr r2, [pc, #108] @ (8001890 <__NVIC_SetPriority+0xd8>) - 8001822: 1dfb adds r3, r7, #7 - 8001824: 781b ldrb r3, [r3, #0] - 8001826: 0019 movs r1, r3 - 8001828: 230f movs r3, #15 - 800182a: 400b ands r3, r1 - 800182c: 3b08 subs r3, #8 - 800182e: 089b lsrs r3, r3, #2 - 8001830: 3306 adds r3, #6 - 8001832: 009b lsls r3, r3, #2 - 8001834: 18d3 adds r3, r2, r3 - 8001836: 3304 adds r3, #4 - 8001838: 681b ldr r3, [r3, #0] - 800183a: 1dfa adds r2, r7, #7 - 800183c: 7812 ldrb r2, [r2, #0] - 800183e: 0011 movs r1, r2 - 8001840: 2203 movs r2, #3 - 8001842: 400a ands r2, r1 - 8001844: 00d2 lsls r2, r2, #3 - 8001846: 21ff movs r1, #255 @ 0xff - 8001848: 4091 lsls r1, r2 - 800184a: 000a movs r2, r1 - 800184c: 43d2 mvns r2, r2 - 800184e: 401a ands r2, r3 - 8001850: 0011 movs r1, r2 + 80018a4: 4a1b ldr r2, [pc, #108] @ (8001914 <__NVIC_SetPriority+0xd8>) + 80018a6: 1dfb adds r3, r7, #7 + 80018a8: 781b ldrb r3, [r3, #0] + 80018aa: 0019 movs r1, r3 + 80018ac: 230f movs r3, #15 + 80018ae: 400b ands r3, r1 + 80018b0: 3b08 subs r3, #8 + 80018b2: 089b lsrs r3, r3, #2 + 80018b4: 3306 adds r3, #6 + 80018b6: 009b lsls r3, r3, #2 + 80018b8: 18d3 adds r3, r2, r3 + 80018ba: 3304 adds r3, #4 + 80018bc: 681b ldr r3, [r3, #0] + 80018be: 1dfa adds r2, r7, #7 + 80018c0: 7812 ldrb r2, [r2, #0] + 80018c2: 0011 movs r1, r2 + 80018c4: 2203 movs r2, #3 + 80018c6: 400a ands r2, r1 + 80018c8: 00d2 lsls r2, r2, #3 + 80018ca: 21ff movs r1, #255 @ 0xff + 80018cc: 4091 lsls r1, r2 + 80018ce: 000a movs r2, r1 + 80018d0: 43d2 mvns r2, r2 + 80018d2: 401a ands r2, r3 + 80018d4: 0011 movs r1, r2 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - 8001852: 683b ldr r3, [r7, #0] - 8001854: 019b lsls r3, r3, #6 - 8001856: 22ff movs r2, #255 @ 0xff - 8001858: 401a ands r2, r3 - 800185a: 1dfb adds r3, r7, #7 - 800185c: 781b ldrb r3, [r3, #0] - 800185e: 0018 movs r0, r3 - 8001860: 2303 movs r3, #3 - 8001862: 4003 ands r3, r0 - 8001864: 00db lsls r3, r3, #3 - 8001866: 409a lsls r2, r3 + 80018d6: 683b ldr r3, [r7, #0] + 80018d8: 019b lsls r3, r3, #6 + 80018da: 22ff movs r2, #255 @ 0xff + 80018dc: 401a ands r2, r3 + 80018de: 1dfb adds r3, r7, #7 + 80018e0: 781b ldrb r3, [r3, #0] + 80018e2: 0018 movs r0, r3 + 80018e4: 2303 movs r3, #3 + 80018e6: 4003 ands r3, r0 + 80018e8: 00db lsls r3, r3, #3 + 80018ea: 409a lsls r2, r3 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - 8001868: 4809 ldr r0, [pc, #36] @ (8001890 <__NVIC_SetPriority+0xd8>) - 800186a: 1dfb adds r3, r7, #7 - 800186c: 781b ldrb r3, [r3, #0] - 800186e: 001c movs r4, r3 - 8001870: 230f movs r3, #15 - 8001872: 4023 ands r3, r4 - 8001874: 3b08 subs r3, #8 - 8001876: 089b lsrs r3, r3, #2 - 8001878: 430a orrs r2, r1 - 800187a: 3306 adds r3, #6 - 800187c: 009b lsls r3, r3, #2 - 800187e: 18c3 adds r3, r0, r3 - 8001880: 3304 adds r3, #4 - 8001882: 601a str r2, [r3, #0] + 80018ec: 4809 ldr r0, [pc, #36] @ (8001914 <__NVIC_SetPriority+0xd8>) + 80018ee: 1dfb adds r3, r7, #7 + 80018f0: 781b ldrb r3, [r3, #0] + 80018f2: 001c movs r4, r3 + 80018f4: 230f movs r3, #15 + 80018f6: 4023 ands r3, r4 + 80018f8: 3b08 subs r3, #8 + 80018fa: 089b lsrs r3, r3, #2 + 80018fc: 430a orrs r2, r1 + 80018fe: 3306 adds r3, #6 + 8001900: 009b lsls r3, r3, #2 + 8001902: 18c3 adds r3, r0, r3 + 8001904: 3304 adds r3, #4 + 8001906: 601a str r2, [r3, #0] } - 8001884: 46c0 nop @ (mov r8, r8) - 8001886: 46bd mov sp, r7 - 8001888: b003 add sp, #12 - 800188a: bd90 pop {r4, r7, pc} - 800188c: e000e100 .word 0xe000e100 - 8001890: e000ed00 .word 0xe000ed00 + 8001908: 46c0 nop @ (mov r8, r8) + 800190a: 46bd mov sp, r7 + 800190c: b003 add sp, #12 + 800190e: bd90 pop {r4, r7, pc} + 8001910: e000e100 .word 0xe000e100 + 8001914: e000ed00 .word 0xe000ed00 -08001894 : +08001918 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { - 8001894: b580 push {r7, lr} - 8001896: b082 sub sp, #8 - 8001898: af00 add r7, sp, #0 - 800189a: 6078 str r0, [r7, #4] + 8001918: b580 push {r7, lr} + 800191a: b082 sub sp, #8 + 800191c: af00 add r7, sp, #0 + 800191e: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - 800189c: 687b ldr r3, [r7, #4] - 800189e: 1e5a subs r2, r3, #1 - 80018a0: 2380 movs r3, #128 @ 0x80 - 80018a2: 045b lsls r3, r3, #17 - 80018a4: 429a cmp r2, r3 - 80018a6: d301 bcc.n 80018ac + 8001920: 687b ldr r3, [r7, #4] + 8001922: 1e5a subs r2, r3, #1 + 8001924: 2380 movs r3, #128 @ 0x80 + 8001926: 045b lsls r3, r3, #17 + 8001928: 429a cmp r2, r3 + 800192a: d301 bcc.n 8001930 { return (1UL); /* Reload value impossible */ - 80018a8: 2301 movs r3, #1 - 80018aa: e010 b.n 80018ce + 800192c: 2301 movs r3, #1 + 800192e: e010 b.n 8001952 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - 80018ac: 4b0a ldr r3, [pc, #40] @ (80018d8 ) - 80018ae: 687a ldr r2, [r7, #4] - 80018b0: 3a01 subs r2, #1 - 80018b2: 605a str r2, [r3, #4] + 8001930: 4b0a ldr r3, [pc, #40] @ (800195c ) + 8001932: 687a ldr r2, [r7, #4] + 8001934: 3a01 subs r2, #1 + 8001936: 605a str r2, [r3, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - 80018b4: 2301 movs r3, #1 - 80018b6: 425b negs r3, r3 - 80018b8: 2103 movs r1, #3 - 80018ba: 0018 movs r0, r3 - 80018bc: f7ff ff7c bl 80017b8 <__NVIC_SetPriority> + 8001938: 2301 movs r3, #1 + 800193a: 425b negs r3, r3 + 800193c: 2103 movs r1, #3 + 800193e: 0018 movs r0, r3 + 8001940: f7ff ff7c bl 800183c <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - 80018c0: 4b05 ldr r3, [pc, #20] @ (80018d8 ) - 80018c2: 2200 movs r2, #0 - 80018c4: 609a str r2, [r3, #8] + 8001944: 4b05 ldr r3, [pc, #20] @ (800195c ) + 8001946: 2200 movs r2, #0 + 8001948: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - 80018c6: 4b04 ldr r3, [pc, #16] @ (80018d8 ) - 80018c8: 2207 movs r2, #7 - 80018ca: 601a str r2, [r3, #0] + 800194a: 4b04 ldr r3, [pc, #16] @ (800195c ) + 800194c: 2207 movs r2, #7 + 800194e: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ - 80018cc: 2300 movs r3, #0 + 8001950: 2300 movs r3, #0 } - 80018ce: 0018 movs r0, r3 - 80018d0: 46bd mov sp, r7 - 80018d2: b002 add sp, #8 - 80018d4: bd80 pop {r7, pc} - 80018d6: 46c0 nop @ (mov r8, r8) - 80018d8: e000e010 .word 0xe000e010 + 8001952: 0018 movs r0, r3 + 8001954: 46bd mov sp, r7 + 8001956: b002 add sp, #8 + 8001958: bd80 pop {r7, pc} + 800195a: 46c0 nop @ (mov r8, r8) + 800195c: e000e010 .word 0xe000e010 -080018dc : +08001960 : * with stm32c0xx devices, this parameter is a dummy value and it is ignored, because * no subpriority supported in Cortex M0+ based products. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { - 80018dc: b580 push {r7, lr} - 80018de: b084 sub sp, #16 - 80018e0: af00 add r7, sp, #0 - 80018e2: 60b9 str r1, [r7, #8] - 80018e4: 607a str r2, [r7, #4] - 80018e6: 210f movs r1, #15 - 80018e8: 187b adds r3, r7, r1 - 80018ea: 1c02 adds r2, r0, #0 - 80018ec: 701a strb r2, [r3, #0] + 8001960: b580 push {r7, lr} + 8001962: b084 sub sp, #16 + 8001964: af00 add r7, sp, #0 + 8001966: 60b9 str r1, [r7, #8] + 8001968: 607a str r2, [r7, #4] + 800196a: 210f movs r1, #15 + 800196c: 187b adds r3, r7, r1 + 800196e: 1c02 adds r2, r0, #0 + 8001970: 701a strb r2, [r3, #0] /* Prevent unused argument(s) compilation warning */ UNUSED(SubPriority); /* Check the parameters */ assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); NVIC_SetPriority(IRQn, PreemptPriority); - 80018ee: 68ba ldr r2, [r7, #8] - 80018f0: 187b adds r3, r7, r1 - 80018f2: 781b ldrb r3, [r3, #0] - 80018f4: b25b sxtb r3, r3 - 80018f6: 0011 movs r1, r2 - 80018f8: 0018 movs r0, r3 - 80018fa: f7ff ff5d bl 80017b8 <__NVIC_SetPriority> + 8001972: 68ba ldr r2, [r7, #8] + 8001974: 187b adds r3, r7, r1 + 8001976: 781b ldrb r3, [r3, #0] + 8001978: b25b sxtb r3, r3 + 800197a: 0011 movs r1, r2 + 800197c: 0018 movs r0, r3 + 800197e: f7ff ff5d bl 800183c <__NVIC_SetPriority> } - 80018fe: 46c0 nop @ (mov r8, r8) - 8001900: 46bd mov sp, r7 - 8001902: b004 add sp, #16 - 8001904: bd80 pop {r7, pc} + 8001982: 46c0 nop @ (mov r8, r8) + 8001984: 46bd mov sp, r7 + 8001986: b004 add sp, #16 + 8001988: bd80 pop {r7, pc} -08001906 : +0800198a : * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate * CMSIS device file (stm32c0xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { - 8001906: b580 push {r7, lr} - 8001908: b082 sub sp, #8 - 800190a: af00 add r7, sp, #0 - 800190c: 0002 movs r2, r0 - 800190e: 1dfb adds r3, r7, #7 - 8001910: 701a strb r2, [r3, #0] + 800198a: b580 push {r7, lr} + 800198c: b082 sub sp, #8 + 800198e: af00 add r7, sp, #0 + 8001990: 0002 movs r2, r0 + 8001992: 1dfb adds r3, r7, #7 + 8001994: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); - 8001912: 1dfb adds r3, r7, #7 - 8001914: 781b ldrb r3, [r3, #0] - 8001916: b25b sxtb r3, r3 - 8001918: 0018 movs r0, r3 - 800191a: f7ff ff33 bl 8001784 <__NVIC_EnableIRQ> + 8001996: 1dfb adds r3, r7, #7 + 8001998: 781b ldrb r3, [r3, #0] + 800199a: b25b sxtb r3, r3 + 800199c: 0018 movs r0, r3 + 800199e: f7ff ff33 bl 8001808 <__NVIC_EnableIRQ> } - 800191e: 46c0 nop @ (mov r8, r8) - 8001920: 46bd mov sp, r7 - 8001922: b002 add sp, #8 - 8001924: bd80 pop {r7, pc} + 80019a2: 46c0 nop @ (mov r8, r8) + 80019a4: 46bd mov sp, r7 + 80019a6: b002 add sp, #8 + 80019a8: bd80 pop {r7, pc} -08001926 : +080019aa : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { - 8001926: b580 push {r7, lr} - 8001928: b082 sub sp, #8 - 800192a: af00 add r7, sp, #0 - 800192c: 6078 str r0, [r7, #4] + 80019aa: b580 push {r7, lr} + 80019ac: b082 sub sp, #8 + 80019ae: af00 add r7, sp, #0 + 80019b0: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); - 800192e: 687b ldr r3, [r7, #4] - 8001930: 0018 movs r0, r3 - 8001932: f7ff ffaf bl 8001894 - 8001936: 0003 movs r3, r0 + 80019b2: 687b ldr r3, [r7, #4] + 80019b4: 0018 movs r0, r3 + 80019b6: f7ff ffaf bl 8001918 + 80019ba: 0003 movs r3, r0 } - 8001938: 0018 movs r0, r3 - 800193a: 46bd mov sp, r7 - 800193c: b002 add sp, #8 - 800193e: bd80 pop {r7, pc} + 80019bc: 0018 movs r0, r3 + 80019be: 46bd mov sp, r7 + 80019c0: b002 add sp, #8 + 80019c2: bd80 pop {r7, pc} -08001940 : +080019c4 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { - 8001940: b580 push {r7, lr} - 8001942: b082 sub sp, #8 - 8001944: af00 add r7, sp, #0 - 8001946: 6078 str r0, [r7, #4] + 80019c4: b580 push {r7, lr} + 80019c6: b082 sub sp, #8 + 80019c8: af00 add r7, sp, #0 + 80019ca: 6078 str r0, [r7, #4] /* Check the DMA handle allocation */ if (hdma == NULL) - 8001948: 687b ldr r3, [r7, #4] - 800194a: 2b00 cmp r3, #0 - 800194c: d101 bne.n 8001952 + 80019cc: 687b ldr r3, [r7, #4] + 80019ce: 2b00 cmp r3, #0 + 80019d0: d101 bne.n 80019d6 { return HAL_ERROR; - 800194e: 2301 movs r3, #1 - 8001950: e077 b.n 8001a42 + 80019d2: 2301 movs r3, #1 + 80019d4: e077 b.n 8001ac6 assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); /* calculation of the channel index */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - \ - 8001952: 687b ldr r3, [r7, #4] - 8001954: 681b ldr r3, [r3, #0] - 8001956: 4a3d ldr r2, [pc, #244] @ (8001a4c ) - 8001958: 4694 mov ip, r2 - 800195a: 4463 add r3, ip - 800195c: 2114 movs r1, #20 - 800195e: 0018 movs r0, r3 - 8001960: f7fe fbd2 bl 8000108 <__udivsi3> - 8001964: 0003 movs r3, r0 + 80019d6: 687b ldr r3, [r7, #4] + 80019d8: 681b ldr r3, [r3, #0] + 80019da: 4a3d ldr r2, [pc, #244] @ (8001ad0 ) + 80019dc: 4694 mov ip, r2 + 80019de: 4463 add r3, ip + 80019e0: 2114 movs r1, #20 + 80019e2: 0018 movs r0, r3 + 80019e4: f7fe fb90 bl 8000108 <__udivsi3> + 80019e8: 0003 movs r3, r0 (uint32_t)DMA1_Channel1)) << 2U; - 8001966: 009a lsls r2, r3, #2 + 80019ea: 009a lsls r2, r3, #2 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - \ - 8001968: 687b ldr r3, [r7, #4] - 800196a: 641a str r2, [r3, #64] @ 0x40 + 80019ec: 687b ldr r3, [r7, #4] + 80019ee: 641a str r2, [r3, #64] @ 0x40 /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; - 800196c: 687b ldr r3, [r7, #4] - 800196e: 2225 movs r2, #37 @ 0x25 - 8001970: 2102 movs r1, #2 - 8001972: 5499 strb r1, [r3, r2] + 80019f0: 687b ldr r3, [r7, #4] + 80019f2: 2225 movs r2, #37 @ 0x25 + 80019f4: 2102 movs r1, #2 + 80019f6: 5499 strb r1, [r3, r2] /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */ CLEAR_BIT(hdma->Instance->CCR, (DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ - 8001974: 687b ldr r3, [r7, #4] - 8001976: 681b ldr r3, [r3, #0] - 8001978: 681a ldr r2, [r3, #0] - 800197a: 687b ldr r3, [r7, #4] - 800197c: 681b ldr r3, [r3, #0] - 800197e: 4934 ldr r1, [pc, #208] @ (8001a50 ) - 8001980: 400a ands r2, r1 - 8001982: 601a str r2, [r3, #0] + 80019f8: 687b ldr r3, [r7, #4] + 80019fa: 681b ldr r3, [r3, #0] + 80019fc: 681a ldr r2, [r3, #0] + 80019fe: 687b ldr r3, [r7, #4] + 8001a00: 681b ldr r3, [r3, #0] + 8001a02: 4934 ldr r1, [pc, #208] @ (8001ad4 ) + 8001a04: 400a ands r2, r1 + 8001a06: 601a str r2, [r3, #0] DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ DMA_CCR_DIR | DMA_CCR_MEM2MEM)); /* Set the DMA Channel configuration */ SET_BIT(hdma->Instance->CCR, (hdma->Init.Direction | \ - 8001984: 687b ldr r3, [r7, #4] - 8001986: 681b ldr r3, [r3, #0] - 8001988: 6819 ldr r1, [r3, #0] - 800198a: 687b ldr r3, [r7, #4] - 800198c: 689a ldr r2, [r3, #8] - 800198e: 687b ldr r3, [r7, #4] - 8001990: 68db ldr r3, [r3, #12] - 8001992: 431a orrs r2, r3 - 8001994: 687b ldr r3, [r7, #4] - 8001996: 691b ldr r3, [r3, #16] - 8001998: 431a orrs r2, r3 - 800199a: 687b ldr r3, [r7, #4] - 800199c: 695b ldr r3, [r3, #20] - 800199e: 431a orrs r2, r3 - 80019a0: 687b ldr r3, [r7, #4] - 80019a2: 699b ldr r3, [r3, #24] - 80019a4: 431a orrs r2, r3 - 80019a6: 687b ldr r3, [r7, #4] - 80019a8: 69db ldr r3, [r3, #28] - 80019aa: 431a orrs r2, r3 - 80019ac: 687b ldr r3, [r7, #4] - 80019ae: 6a1b ldr r3, [r3, #32] - 80019b0: 431a orrs r2, r3 - 80019b2: 687b ldr r3, [r7, #4] - 80019b4: 681b ldr r3, [r3, #0] - 80019b6: 430a orrs r2, r1 - 80019b8: 601a str r2, [r3, #0] + 8001a08: 687b ldr r3, [r7, #4] + 8001a0a: 681b ldr r3, [r3, #0] + 8001a0c: 6819 ldr r1, [r3, #0] + 8001a0e: 687b ldr r3, [r7, #4] + 8001a10: 689a ldr r2, [r3, #8] + 8001a12: 687b ldr r3, [r7, #4] + 8001a14: 68db ldr r3, [r3, #12] + 8001a16: 431a orrs r2, r3 + 8001a18: 687b ldr r3, [r7, #4] + 8001a1a: 691b ldr r3, [r3, #16] + 8001a1c: 431a orrs r2, r3 + 8001a1e: 687b ldr r3, [r7, #4] + 8001a20: 695b ldr r3, [r3, #20] + 8001a22: 431a orrs r2, r3 + 8001a24: 687b ldr r3, [r7, #4] + 8001a26: 699b ldr r3, [r3, #24] + 8001a28: 431a orrs r2, r3 + 8001a2a: 687b ldr r3, [r7, #4] + 8001a2c: 69db ldr r3, [r3, #28] + 8001a2e: 431a orrs r2, r3 + 8001a30: 687b ldr r3, [r7, #4] + 8001a32: 6a1b ldr r3, [r3, #32] + 8001a34: 431a orrs r2, r3 + 8001a36: 687b ldr r3, [r7, #4] + 8001a38: 681b ldr r3, [r3, #0] + 8001a3a: 430a orrs r2, r1 + 8001a3c: 601a str r2, [r3, #0] hdma->Init.Mode | hdma->Init.Priority)); /* Initialize parameters for DMAMUX channel : DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ DMA_CalcDMAMUXChannelBaseAndMask(hdma); - 80019ba: 687b ldr r3, [r7, #4] - 80019bc: 0018 movs r0, r3 - 80019be: f000 f9c3 bl 8001d48 + 8001a3e: 687b ldr r3, [r7, #4] + 8001a40: 0018 movs r0, r3 + 8001a42: f000 f9c3 bl 8001dcc if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) - 80019c2: 687b ldr r3, [r7, #4] - 80019c4: 689a ldr r2, [r3, #8] - 80019c6: 2380 movs r3, #128 @ 0x80 - 80019c8: 01db lsls r3, r3, #7 - 80019ca: 429a cmp r2, r3 - 80019cc: d102 bne.n 80019d4 + 8001a46: 687b ldr r3, [r7, #4] + 8001a48: 689a ldr r2, [r3, #8] + 8001a4a: 2380 movs r3, #128 @ 0x80 + 8001a4c: 01db lsls r3, r3, #7 + 8001a4e: 429a cmp r2, r3 + 8001a50: d102 bne.n 8001a58 { /* if memory to memory force the request to 0*/ hdma->Init.Request = DMA_REQUEST_MEM2MEM; - 80019ce: 687b ldr r3, [r7, #4] - 80019d0: 2200 movs r2, #0 - 80019d2: 605a str r2, [r3, #4] + 8001a52: 687b ldr r3, [r7, #4] + 8001a54: 2200 movs r2, #0 + 8001a56: 605a str r2, [r3, #4] } /* Set peripheral request to DMAMUX channel */ hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); - 80019d4: 687b ldr r3, [r7, #4] - 80019d6: 685a ldr r2, [r3, #4] - 80019d8: 687b ldr r3, [r7, #4] - 80019da: 6c5b ldr r3, [r3, #68] @ 0x44 - 80019dc: 21ff movs r1, #255 @ 0xff - 80019de: 400a ands r2, r1 - 80019e0: 601a str r2, [r3, #0] + 8001a58: 687b ldr r3, [r7, #4] + 8001a5a: 685a ldr r2, [r3, #4] + 8001a5c: 687b ldr r3, [r7, #4] + 8001a5e: 6c5b ldr r3, [r3, #68] @ 0x44 + 8001a60: 21ff movs r1, #255 @ 0xff + 8001a62: 400a ands r2, r1 + 8001a64: 601a str r2, [r3, #0] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; - 80019e2: 687b ldr r3, [r7, #4] - 80019e4: 6c9b ldr r3, [r3, #72] @ 0x48 - 80019e6: 687a ldr r2, [r7, #4] - 80019e8: 6cd2 ldr r2, [r2, #76] @ 0x4c - 80019ea: 605a str r2, [r3, #4] + 8001a66: 687b ldr r3, [r7, #4] + 8001a68: 6c9b ldr r3, [r3, #72] @ 0x48 + 8001a6a: 687a ldr r2, [r7, #4] + 8001a6c: 6cd2 ldr r2, [r2, #76] @ 0x4c + 8001a6e: 605a str r2, [r3, #4] if (((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) - 80019ec: 687b ldr r3, [r7, #4] - 80019ee: 685b ldr r3, [r3, #4] - 80019f0: 2b00 cmp r3, #0 - 80019f2: d011 beq.n 8001a18 - 80019f4: 687b ldr r3, [r7, #4] - 80019f6: 685b ldr r3, [r3, #4] - 80019f8: 2b04 cmp r3, #4 - 80019fa: d80d bhi.n 8001a18 + 8001a70: 687b ldr r3, [r7, #4] + 8001a72: 685b ldr r3, [r3, #4] + 8001a74: 2b00 cmp r3, #0 + 8001a76: d011 beq.n 8001a9c + 8001a78: 687b ldr r3, [r7, #4] + 8001a7a: 685b ldr r3, [r3, #4] + 8001a7c: 2b04 cmp r3, #4 + 8001a7e: d80d bhi.n 8001a9c { /* Initialize parameters for DMAMUX request generator : DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); - 80019fc: 687b ldr r3, [r7, #4] - 80019fe: 0018 movs r0, r3 - 8001a00: f000 f9ce bl 8001da0 + 8001a80: 687b ldr r3, [r7, #4] + 8001a82: 0018 movs r0, r3 + 8001a84: f000 f9ce bl 8001e24 /* Reset the DMAMUX request generator register*/ hdma->DMAmuxRequestGen->RGCR = 0U; - 8001a04: 687b ldr r3, [r7, #4] - 8001a06: 6d1b ldr r3, [r3, #80] @ 0x50 - 8001a08: 2200 movs r2, #0 - 8001a0a: 601a str r2, [r3, #0] + 8001a88: 687b ldr r3, [r7, #4] + 8001a8a: 6d1b ldr r3, [r3, #80] @ 0x50 + 8001a8c: 2200 movs r2, #0 + 8001a8e: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; - 8001a0c: 687b ldr r3, [r7, #4] - 8001a0e: 6d5b ldr r3, [r3, #84] @ 0x54 - 8001a10: 687a ldr r2, [r7, #4] - 8001a12: 6d92 ldr r2, [r2, #88] @ 0x58 - 8001a14: 605a str r2, [r3, #4] - 8001a16: e008 b.n 8001a2a + 8001a90: 687b ldr r3, [r7, #4] + 8001a92: 6d5b ldr r3, [r3, #84] @ 0x54 + 8001a94: 687a ldr r2, [r7, #4] + 8001a96: 6d92 ldr r2, [r2, #88] @ 0x58 + 8001a98: 605a str r2, [r3, #4] + 8001a9a: e008 b.n 8001aae } else { hdma->DMAmuxRequestGen = 0U; - 8001a18: 687b ldr r3, [r7, #4] - 8001a1a: 2200 movs r2, #0 - 8001a1c: 651a str r2, [r3, #80] @ 0x50 + 8001a9c: 687b ldr r3, [r7, #4] + 8001a9e: 2200 movs r2, #0 + 8001aa0: 651a str r2, [r3, #80] @ 0x50 hdma->DMAmuxRequestGenStatus = 0U; - 8001a1e: 687b ldr r3, [r7, #4] - 8001a20: 2200 movs r2, #0 - 8001a22: 655a str r2, [r3, #84] @ 0x54 + 8001aa2: 687b ldr r3, [r7, #4] + 8001aa4: 2200 movs r2, #0 + 8001aa6: 655a str r2, [r3, #84] @ 0x54 hdma->DMAmuxRequestGenStatusMask = 0U; - 8001a24: 687b ldr r3, [r7, #4] - 8001a26: 2200 movs r2, #0 - 8001a28: 659a str r2, [r3, #88] @ 0x58 + 8001aa8: 687b ldr r3, [r7, #4] + 8001aaa: 2200 movs r2, #0 + 8001aac: 659a str r2, [r3, #88] @ 0x58 } /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; - 8001a2a: 687b ldr r3, [r7, #4] - 8001a2c: 2200 movs r2, #0 - 8001a2e: 63da str r2, [r3, #60] @ 0x3c + 8001aae: 687b ldr r3, [r7, #4] + 8001ab0: 2200 movs r2, #0 + 8001ab2: 63da str r2, [r3, #60] @ 0x3c /* Initialize the DMA state*/ hdma->State = HAL_DMA_STATE_READY; - 8001a30: 687b ldr r3, [r7, #4] - 8001a32: 2225 movs r2, #37 @ 0x25 - 8001a34: 2101 movs r1, #1 - 8001a36: 5499 strb r1, [r3, r2] + 8001ab4: 687b ldr r3, [r7, #4] + 8001ab6: 2225 movs r2, #37 @ 0x25 + 8001ab8: 2101 movs r1, #1 + 8001aba: 5499 strb r1, [r3, r2] /* Release Lock */ __HAL_UNLOCK(hdma); - 8001a38: 687b ldr r3, [r7, #4] - 8001a3a: 2224 movs r2, #36 @ 0x24 - 8001a3c: 2100 movs r1, #0 - 8001a3e: 5499 strb r1, [r3, r2] + 8001abc: 687b ldr r3, [r7, #4] + 8001abe: 2224 movs r2, #36 @ 0x24 + 8001ac0: 2100 movs r1, #0 + 8001ac2: 5499 strb r1, [r3, r2] return HAL_OK; - 8001a40: 2300 movs r3, #0 + 8001ac4: 2300 movs r3, #0 } - 8001a42: 0018 movs r0, r3 - 8001a44: 46bd mov sp, r7 - 8001a46: b002 add sp, #8 - 8001a48: bd80 pop {r7, pc} - 8001a4a: 46c0 nop @ (mov r8, r8) - 8001a4c: bffdfff8 .word 0xbffdfff8 - 8001a50: ffff800f .word 0xffff800f + 8001ac6: 0018 movs r0, r3 + 8001ac8: 46bd mov sp, r7 + 8001aca: b002 add sp, #8 + 8001acc: bd80 pop {r7, pc} + 8001ace: 46c0 nop @ (mov r8, r8) + 8001ad0: bffdfff8 .word 0xbffdfff8 + 8001ad4: ffff800f .word 0xffff800f -08001a54 : +08001ad8 : * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { - 8001a54: b580 push {r7, lr} - 8001a56: b086 sub sp, #24 - 8001a58: af00 add r7, sp, #0 - 8001a5a: 60f8 str r0, [r7, #12] - 8001a5c: 60b9 str r1, [r7, #8] - 8001a5e: 607a str r2, [r7, #4] - 8001a60: 603b str r3, [r7, #0] + 8001ad8: b580 push {r7, lr} + 8001ada: b086 sub sp, #24 + 8001adc: af00 add r7, sp, #0 + 8001ade: 60f8 str r0, [r7, #12] + 8001ae0: 60b9 str r1, [r7, #8] + 8001ae2: 607a str r2, [r7, #4] + 8001ae4: 603b str r3, [r7, #0] HAL_StatusTypeDef status = HAL_OK; - 8001a62: 2317 movs r3, #23 - 8001a64: 18fb adds r3, r7, r3 - 8001a66: 2200 movs r2, #0 - 8001a68: 701a strb r2, [r3, #0] + 8001ae6: 2317 movs r3, #23 + 8001ae8: 18fb adds r3, r7, r3 + 8001aea: 2200 movs r2, #0 + 8001aec: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); - 8001a6a: 68fb ldr r3, [r7, #12] - 8001a6c: 2224 movs r2, #36 @ 0x24 - 8001a6e: 5c9b ldrb r3, [r3, r2] - 8001a70: 2b01 cmp r3, #1 - 8001a72: d101 bne.n 8001a78 - 8001a74: 2302 movs r3, #2 - 8001a76: e070 b.n 8001b5a - 8001a78: 68fb ldr r3, [r7, #12] - 8001a7a: 2224 movs r2, #36 @ 0x24 - 8001a7c: 2101 movs r1, #1 - 8001a7e: 5499 strb r1, [r3, r2] + 8001aee: 68fb ldr r3, [r7, #12] + 8001af0: 2224 movs r2, #36 @ 0x24 + 8001af2: 5c9b ldrb r3, [r3, r2] + 8001af4: 2b01 cmp r3, #1 + 8001af6: d101 bne.n 8001afc + 8001af8: 2302 movs r3, #2 + 8001afa: e070 b.n 8001bde + 8001afc: 68fb ldr r3, [r7, #12] + 8001afe: 2224 movs r2, #36 @ 0x24 + 8001b00: 2101 movs r1, #1 + 8001b02: 5499 strb r1, [r3, r2] if (HAL_DMA_STATE_READY == hdma->State) - 8001a80: 68fb ldr r3, [r7, #12] - 8001a82: 2225 movs r2, #37 @ 0x25 - 8001a84: 5c9b ldrb r3, [r3, r2] - 8001a86: b2db uxtb r3, r3 - 8001a88: 2b01 cmp r3, #1 - 8001a8a: d157 bne.n 8001b3c + 8001b04: 68fb ldr r3, [r7, #12] + 8001b06: 2225 movs r2, #37 @ 0x25 + 8001b08: 5c9b ldrb r3, [r3, r2] + 8001b0a: b2db uxtb r3, r3 + 8001b0c: 2b01 cmp r3, #1 + 8001b0e: d157 bne.n 8001bc0 { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; - 8001a8c: 68fb ldr r3, [r7, #12] - 8001a8e: 2225 movs r2, #37 @ 0x25 - 8001a90: 2102 movs r1, #2 - 8001a92: 5499 strb r1, [r3, r2] + 8001b10: 68fb ldr r3, [r7, #12] + 8001b12: 2225 movs r2, #37 @ 0x25 + 8001b14: 2102 movs r1, #2 + 8001b16: 5499 strb r1, [r3, r2] hdma->ErrorCode = HAL_DMA_ERROR_NONE; - 8001a94: 68fb ldr r3, [r7, #12] - 8001a96: 2200 movs r2, #0 - 8001a98: 63da str r2, [r3, #60] @ 0x3c + 8001b18: 68fb ldr r3, [r7, #12] + 8001b1a: 2200 movs r2, #0 + 8001b1c: 63da str r2, [r3, #60] @ 0x3c /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); - 8001a9a: 68fb ldr r3, [r7, #12] - 8001a9c: 681b ldr r3, [r3, #0] - 8001a9e: 681a ldr r2, [r3, #0] - 8001aa0: 68fb ldr r3, [r7, #12] - 8001aa2: 681b ldr r3, [r3, #0] - 8001aa4: 2101 movs r1, #1 - 8001aa6: 438a bics r2, r1 - 8001aa8: 601a str r2, [r3, #0] + 8001b1e: 68fb ldr r3, [r7, #12] + 8001b20: 681b ldr r3, [r3, #0] + 8001b22: 681a ldr r2, [r3, #0] + 8001b24: 68fb ldr r3, [r7, #12] + 8001b26: 681b ldr r3, [r3, #0] + 8001b28: 2101 movs r1, #1 + 8001b2a: 438a bics r2, r1 + 8001b2c: 601a str r2, [r3, #0] /* Configure the source, destination address and the data length & clear flags*/ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); - 8001aaa: 683b ldr r3, [r7, #0] - 8001aac: 687a ldr r2, [r7, #4] - 8001aae: 68b9 ldr r1, [r7, #8] - 8001ab0: 68f8 ldr r0, [r7, #12] - 8001ab2: f000 f909 bl 8001cc8 + 8001b2e: 683b ldr r3, [r7, #0] + 8001b30: 687a ldr r2, [r7, #4] + 8001b32: 68b9 ldr r1, [r7, #8] + 8001b34: 68f8 ldr r0, [r7, #12] + 8001b36: f000 f909 bl 8001d4c /* Enable the transfer complete interrupt */ /* Enable the transfer Error interrupt */ if (NULL != hdma->XferHalfCpltCallback) - 8001ab6: 68fb ldr r3, [r7, #12] - 8001ab8: 6b1b ldr r3, [r3, #48] @ 0x30 - 8001aba: 2b00 cmp r3, #0 - 8001abc: d008 beq.n 8001ad0 + 8001b3a: 68fb ldr r3, [r7, #12] + 8001b3c: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001b3e: 2b00 cmp r3, #0 + 8001b40: d008 beq.n 8001b54 { /* Enable the Half transfer complete interrupt as well */ __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); - 8001abe: 68fb ldr r3, [r7, #12] - 8001ac0: 681b ldr r3, [r3, #0] - 8001ac2: 681a ldr r2, [r3, #0] - 8001ac4: 68fb ldr r3, [r7, #12] - 8001ac6: 681b ldr r3, [r3, #0] - 8001ac8: 210e movs r1, #14 - 8001aca: 430a orrs r2, r1 - 8001acc: 601a str r2, [r3, #0] - 8001ace: e00f b.n 8001af0 + 8001b42: 68fb ldr r3, [r7, #12] + 8001b44: 681b ldr r3, [r3, #0] + 8001b46: 681a ldr r2, [r3, #0] + 8001b48: 68fb ldr r3, [r7, #12] + 8001b4a: 681b ldr r3, [r3, #0] + 8001b4c: 210e movs r1, #14 + 8001b4e: 430a orrs r2, r1 + 8001b50: 601a str r2, [r3, #0] + 8001b52: e00f b.n 8001b74 } else { __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); - 8001ad0: 68fb ldr r3, [r7, #12] - 8001ad2: 681b ldr r3, [r3, #0] - 8001ad4: 681a ldr r2, [r3, #0] - 8001ad6: 68fb ldr r3, [r7, #12] - 8001ad8: 681b ldr r3, [r3, #0] - 8001ada: 2104 movs r1, #4 - 8001adc: 438a bics r2, r1 - 8001ade: 601a str r2, [r3, #0] + 8001b54: 68fb ldr r3, [r7, #12] + 8001b56: 681b ldr r3, [r3, #0] + 8001b58: 681a ldr r2, [r3, #0] + 8001b5a: 68fb ldr r3, [r7, #12] + 8001b5c: 681b ldr r3, [r3, #0] + 8001b5e: 2104 movs r1, #4 + 8001b60: 438a bics r2, r1 + 8001b62: 601a str r2, [r3, #0] __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); - 8001ae0: 68fb ldr r3, [r7, #12] - 8001ae2: 681b ldr r3, [r3, #0] - 8001ae4: 681a ldr r2, [r3, #0] - 8001ae6: 68fb ldr r3, [r7, #12] - 8001ae8: 681b ldr r3, [r3, #0] - 8001aea: 210a movs r1, #10 - 8001aec: 430a orrs r2, r1 - 8001aee: 601a str r2, [r3, #0] + 8001b64: 68fb ldr r3, [r7, #12] + 8001b66: 681b ldr r3, [r3, #0] + 8001b68: 681a ldr r2, [r3, #0] + 8001b6a: 68fb ldr r3, [r7, #12] + 8001b6c: 681b ldr r3, [r3, #0] + 8001b6e: 210a movs r1, #10 + 8001b70: 430a orrs r2, r1 + 8001b72: 601a str r2, [r3, #0] } /* Check if DMAMUX Synchronization is enabled*/ if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) - 8001af0: 68fb ldr r3, [r7, #12] - 8001af2: 6c5b ldr r3, [r3, #68] @ 0x44 - 8001af4: 681a ldr r2, [r3, #0] - 8001af6: 2380 movs r3, #128 @ 0x80 - 8001af8: 025b lsls r3, r3, #9 - 8001afa: 4013 ands r3, r2 - 8001afc: d008 beq.n 8001b10 + 8001b74: 68fb ldr r3, [r7, #12] + 8001b76: 6c5b ldr r3, [r3, #68] @ 0x44 + 8001b78: 681a ldr r2, [r3, #0] + 8001b7a: 2380 movs r3, #128 @ 0x80 + 8001b7c: 025b lsls r3, r3, #9 + 8001b7e: 4013 ands r3, r2 + 8001b80: d008 beq.n 8001b94 { /* Enable DMAMUX sync overrun IT*/ hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; - 8001afe: 68fb ldr r3, [r7, #12] - 8001b00: 6c5b ldr r3, [r3, #68] @ 0x44 - 8001b02: 681a ldr r2, [r3, #0] - 8001b04: 68fb ldr r3, [r7, #12] - 8001b06: 6c5b ldr r3, [r3, #68] @ 0x44 - 8001b08: 2180 movs r1, #128 @ 0x80 - 8001b0a: 0049 lsls r1, r1, #1 - 8001b0c: 430a orrs r2, r1 - 8001b0e: 601a str r2, [r3, #0] + 8001b82: 68fb ldr r3, [r7, #12] + 8001b84: 6c5b ldr r3, [r3, #68] @ 0x44 + 8001b86: 681a ldr r2, [r3, #0] + 8001b88: 68fb ldr r3, [r7, #12] + 8001b8a: 6c5b ldr r3, [r3, #68] @ 0x44 + 8001b8c: 2180 movs r1, #128 @ 0x80 + 8001b8e: 0049 lsls r1, r1, #1 + 8001b90: 430a orrs r2, r1 + 8001b92: 601a str r2, [r3, #0] } if (hdma->DMAmuxRequestGen != 0U) - 8001b10: 68fb ldr r3, [r7, #12] - 8001b12: 6d1b ldr r3, [r3, #80] @ 0x50 - 8001b14: 2b00 cmp r3, #0 - 8001b16: d008 beq.n 8001b2a + 8001b94: 68fb ldr r3, [r7, #12] + 8001b96: 6d1b ldr r3, [r3, #80] @ 0x50 + 8001b98: 2b00 cmp r3, #0 + 8001b9a: d008 beq.n 8001bae { /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ /* enable the request gen overrun IT*/ hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; - 8001b18: 68fb ldr r3, [r7, #12] - 8001b1a: 6d1b ldr r3, [r3, #80] @ 0x50 - 8001b1c: 681a ldr r2, [r3, #0] - 8001b1e: 68fb ldr r3, [r7, #12] - 8001b20: 6d1b ldr r3, [r3, #80] @ 0x50 - 8001b22: 2180 movs r1, #128 @ 0x80 - 8001b24: 0049 lsls r1, r1, #1 - 8001b26: 430a orrs r2, r1 - 8001b28: 601a str r2, [r3, #0] + 8001b9c: 68fb ldr r3, [r7, #12] + 8001b9e: 6d1b ldr r3, [r3, #80] @ 0x50 + 8001ba0: 681a ldr r2, [r3, #0] + 8001ba2: 68fb ldr r3, [r7, #12] + 8001ba4: 6d1b ldr r3, [r3, #80] @ 0x50 + 8001ba6: 2180 movs r1, #128 @ 0x80 + 8001ba8: 0049 lsls r1, r1, #1 + 8001baa: 430a orrs r2, r1 + 8001bac: 601a str r2, [r3, #0] } /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); - 8001b2a: 68fb ldr r3, [r7, #12] - 8001b2c: 681b ldr r3, [r3, #0] - 8001b2e: 681a ldr r2, [r3, #0] - 8001b30: 68fb ldr r3, [r7, #12] - 8001b32: 681b ldr r3, [r3, #0] - 8001b34: 2101 movs r1, #1 - 8001b36: 430a orrs r2, r1 - 8001b38: 601a str r2, [r3, #0] - 8001b3a: e007 b.n 8001b4c + 8001bae: 68fb ldr r3, [r7, #12] + 8001bb0: 681b ldr r3, [r3, #0] + 8001bb2: 681a ldr r2, [r3, #0] + 8001bb4: 68fb ldr r3, [r7, #12] + 8001bb6: 681b ldr r3, [r3, #0] + 8001bb8: 2101 movs r1, #1 + 8001bba: 430a orrs r2, r1 + 8001bbc: 601a str r2, [r3, #0] + 8001bbe: e007 b.n 8001bd0 } else { /* Process Unlocked */ __HAL_UNLOCK(hdma); - 8001b3c: 68fb ldr r3, [r7, #12] - 8001b3e: 2224 movs r2, #36 @ 0x24 - 8001b40: 2100 movs r1, #0 - 8001b42: 5499 strb r1, [r3, r2] + 8001bc0: 68fb ldr r3, [r7, #12] + 8001bc2: 2224 movs r2, #36 @ 0x24 + 8001bc4: 2100 movs r1, #0 + 8001bc6: 5499 strb r1, [r3, r2] /* Remain BUSY */ status = HAL_BUSY; - 8001b44: 2317 movs r3, #23 - 8001b46: 18fb adds r3, r7, r3 - 8001b48: 2202 movs r2, #2 - 8001b4a: 701a strb r2, [r3, #0] + 8001bc8: 2317 movs r3, #23 + 8001bca: 18fb adds r3, r7, r3 + 8001bcc: 2202 movs r2, #2 + 8001bce: 701a strb r2, [r3, #0] } /* Process unlocked */ __HAL_UNLOCK(hdma); - 8001b4c: 68fb ldr r3, [r7, #12] - 8001b4e: 2224 movs r2, #36 @ 0x24 - 8001b50: 2100 movs r1, #0 - 8001b52: 5499 strb r1, [r3, r2] + 8001bd0: 68fb ldr r3, [r7, #12] + 8001bd2: 2224 movs r2, #36 @ 0x24 + 8001bd4: 2100 movs r1, #0 + 8001bd6: 5499 strb r1, [r3, r2] return status; - 8001b54: 2317 movs r3, #23 - 8001b56: 18fb adds r3, r7, r3 - 8001b58: 781b ldrb r3, [r3, #0] + 8001bd8: 2317 movs r3, #23 + 8001bda: 18fb adds r3, r7, r3 + 8001bdc: 781b ldrb r3, [r3, #0] } - 8001b5a: 0018 movs r0, r3 - 8001b5c: 46bd mov sp, r7 - 8001b5e: b006 add sp, #24 - 8001b60: bd80 pop {r7, pc} + 8001bde: 0018 movs r0, r3 + 8001be0: 46bd mov sp, r7 + 8001be2: b006 add sp, #24 + 8001be4: bd80 pop {r7, pc} ... -08001b64 : +08001be8 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { - 8001b64: b580 push {r7, lr} - 8001b66: b084 sub sp, #16 - 8001b68: af00 add r7, sp, #0 - 8001b6a: 6078 str r0, [r7, #4] + 8001be8: b580 push {r7, lr} + 8001bea: b084 sub sp, #16 + 8001bec: af00 add r7, sp, #0 + 8001bee: 6078 str r0, [r7, #4] uint32_t flag_it = DMA1->ISR; - 8001b6c: 4b55 ldr r3, [pc, #340] @ (8001cc4 ) - 8001b6e: 681b ldr r3, [r3, #0] - 8001b70: 60fb str r3, [r7, #12] + 8001bf0: 4b55 ldr r3, [pc, #340] @ (8001d48 ) + 8001bf2: 681b ldr r3, [r3, #0] + 8001bf4: 60fb str r3, [r7, #12] uint32_t source_it = hdma->Instance->CCR; - 8001b72: 687b ldr r3, [r7, #4] - 8001b74: 681b ldr r3, [r3, #0] - 8001b76: 681b ldr r3, [r3, #0] - 8001b78: 60bb str r3, [r7, #8] + 8001bf6: 687b ldr r3, [r7, #4] + 8001bf8: 681b ldr r3, [r3, #0] + 8001bfa: 681b ldr r3, [r3, #0] + 8001bfc: 60bb str r3, [r7, #8] /* Half Transfer Complete Interrupt management ******************************/ if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_HT) != 0U)) - 8001b7a: 687b ldr r3, [r7, #4] - 8001b7c: 6c1b ldr r3, [r3, #64] @ 0x40 - 8001b7e: 221c movs r2, #28 - 8001b80: 4013 ands r3, r2 - 8001b82: 2204 movs r2, #4 - 8001b84: 409a lsls r2, r3 - 8001b86: 0013 movs r3, r2 - 8001b88: 68fa ldr r2, [r7, #12] - 8001b8a: 4013 ands r3, r2 - 8001b8c: d027 beq.n 8001bde - 8001b8e: 68bb ldr r3, [r7, #8] - 8001b90: 2204 movs r2, #4 - 8001b92: 4013 ands r3, r2 - 8001b94: d023 beq.n 8001bde + 8001bfe: 687b ldr r3, [r7, #4] + 8001c00: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001c02: 221c movs r2, #28 + 8001c04: 4013 ands r3, r2 + 8001c06: 2204 movs r2, #4 + 8001c08: 409a lsls r2, r3 + 8001c0a: 0013 movs r3, r2 + 8001c0c: 68fa ldr r2, [r7, #12] + 8001c0e: 4013 ands r3, r2 + 8001c10: d027 beq.n 8001c62 + 8001c12: 68bb ldr r3, [r7, #8] + 8001c14: 2204 movs r2, #4 + 8001c16: 4013 ands r3, r2 + 8001c18: d023 beq.n 8001c62 { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) - 8001b96: 687b ldr r3, [r7, #4] - 8001b98: 681b ldr r3, [r3, #0] - 8001b9a: 681b ldr r3, [r3, #0] - 8001b9c: 2220 movs r2, #32 - 8001b9e: 4013 ands r3, r2 - 8001ba0: d107 bne.n 8001bb2 + 8001c1a: 687b ldr r3, [r7, #4] + 8001c1c: 681b ldr r3, [r3, #0] + 8001c1e: 681b ldr r3, [r3, #0] + 8001c20: 2220 movs r2, #32 + 8001c22: 4013 ands r3, r2 + 8001c24: d107 bne.n 8001c36 { /* Disable the half transfer interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); - 8001ba2: 687b ldr r3, [r7, #4] - 8001ba4: 681b ldr r3, [r3, #0] - 8001ba6: 681a ldr r2, [r3, #0] - 8001ba8: 687b ldr r3, [r7, #4] - 8001baa: 681b ldr r3, [r3, #0] - 8001bac: 2104 movs r1, #4 - 8001bae: 438a bics r2, r1 - 8001bb0: 601a str r2, [r3, #0] + 8001c26: 687b ldr r3, [r7, #4] + 8001c28: 681b ldr r3, [r3, #0] + 8001c2a: 681a ldr r2, [r3, #0] + 8001c2c: 687b ldr r3, [r7, #4] + 8001c2e: 681b ldr r3, [r3, #0] + 8001c30: 2104 movs r1, #4 + 8001c32: 438a bics r2, r1 + 8001c34: 601a str r2, [r3, #0] } /* Clear the half transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU))); - 8001bb2: 4b44 ldr r3, [pc, #272] @ (8001cc4 ) - 8001bb4: 6859 ldr r1, [r3, #4] - 8001bb6: 687b ldr r3, [r7, #4] - 8001bb8: 6c1b ldr r3, [r3, #64] @ 0x40 - 8001bba: 221c movs r2, #28 - 8001bbc: 4013 ands r3, r2 - 8001bbe: 2204 movs r2, #4 - 8001bc0: 409a lsls r2, r3 - 8001bc2: 4b40 ldr r3, [pc, #256] @ (8001cc4 ) - 8001bc4: 430a orrs r2, r1 - 8001bc6: 605a str r2, [r3, #4] + 8001c36: 4b44 ldr r3, [pc, #272] @ (8001d48 ) + 8001c38: 6859 ldr r1, [r3, #4] + 8001c3a: 687b ldr r3, [r7, #4] + 8001c3c: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001c3e: 221c movs r2, #28 + 8001c40: 4013 ands r3, r2 + 8001c42: 2204 movs r2, #4 + 8001c44: 409a lsls r2, r3 + 8001c46: 4b40 ldr r3, [pc, #256] @ (8001d48 ) + 8001c48: 430a orrs r2, r1 + 8001c4a: 605a str r2, [r3, #4] /* DMA peripheral state is not updated in Half Transfer */ /* but in Transfer Complete case */ if (hdma->XferHalfCpltCallback != NULL) - 8001bc8: 687b ldr r3, [r7, #4] - 8001bca: 6b1b ldr r3, [r3, #48] @ 0x30 - 8001bcc: 2b00 cmp r3, #0 - 8001bce: d100 bne.n 8001bd2 - 8001bd0: e073 b.n 8001cba + 8001c4c: 687b ldr r3, [r7, #4] + 8001c4e: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001c50: 2b00 cmp r3, #0 + 8001c52: d100 bne.n 8001c56 + 8001c54: e073 b.n 8001d3e { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); - 8001bd2: 687b ldr r3, [r7, #4] - 8001bd4: 6b1b ldr r3, [r3, #48] @ 0x30 - 8001bd6: 687a ldr r2, [r7, #4] - 8001bd8: 0010 movs r0, r2 - 8001bda: 4798 blx r3 + 8001c56: 687b ldr r3, [r7, #4] + 8001c58: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001c5a: 687a ldr r2, [r7, #4] + 8001c5c: 0010 movs r0, r2 + 8001c5e: 4798 blx r3 if (hdma->XferHalfCpltCallback != NULL) - 8001bdc: e06d b.n 8001cba + 8001c60: e06d b.n 8001d3e } } /* Transfer Complete Interrupt management ***********************************/ else if ((0U != (flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU)))) && (0U != (source_it & DMA_IT_TC))) - 8001bde: 687b ldr r3, [r7, #4] - 8001be0: 6c1b ldr r3, [r3, #64] @ 0x40 - 8001be2: 221c movs r2, #28 - 8001be4: 4013 ands r3, r2 - 8001be6: 2202 movs r2, #2 - 8001be8: 409a lsls r2, r3 - 8001bea: 0013 movs r3, r2 - 8001bec: 68fa ldr r2, [r7, #12] - 8001bee: 4013 ands r3, r2 - 8001bf0: d02e beq.n 8001c50 - 8001bf2: 68bb ldr r3, [r7, #8] - 8001bf4: 2202 movs r2, #2 - 8001bf6: 4013 ands r3, r2 - 8001bf8: d02a beq.n 8001c50 + 8001c62: 687b ldr r3, [r7, #4] + 8001c64: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001c66: 221c movs r2, #28 + 8001c68: 4013 ands r3, r2 + 8001c6a: 2202 movs r2, #2 + 8001c6c: 409a lsls r2, r3 + 8001c6e: 0013 movs r3, r2 + 8001c70: 68fa ldr r2, [r7, #12] + 8001c72: 4013 ands r3, r2 + 8001c74: d02e beq.n 8001cd4 + 8001c76: 68bb ldr r3, [r7, #8] + 8001c78: 2202 movs r2, #2 + 8001c7a: 4013 ands r3, r2 + 8001c7c: d02a beq.n 8001cd4 { if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) - 8001bfa: 687b ldr r3, [r7, #4] - 8001bfc: 681b ldr r3, [r3, #0] - 8001bfe: 681b ldr r3, [r3, #0] - 8001c00: 2220 movs r2, #32 - 8001c02: 4013 ands r3, r2 - 8001c04: d10b bne.n 8001c1e + 8001c7e: 687b ldr r3, [r7, #4] + 8001c80: 681b ldr r3, [r3, #0] + 8001c82: 681b ldr r3, [r3, #0] + 8001c84: 2220 movs r2, #32 + 8001c86: 4013 ands r3, r2 + 8001c88: d10b bne.n 8001ca2 { /* Disable the transfer complete and error interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); - 8001c06: 687b ldr r3, [r7, #4] - 8001c08: 681b ldr r3, [r3, #0] - 8001c0a: 681a ldr r2, [r3, #0] - 8001c0c: 687b ldr r3, [r7, #4] - 8001c0e: 681b ldr r3, [r3, #0] - 8001c10: 210a movs r1, #10 - 8001c12: 438a bics r2, r1 - 8001c14: 601a str r2, [r3, #0] + 8001c8a: 687b ldr r3, [r7, #4] + 8001c8c: 681b ldr r3, [r3, #0] + 8001c8e: 681a ldr r2, [r3, #0] + 8001c90: 687b ldr r3, [r7, #4] + 8001c92: 681b ldr r3, [r3, #0] + 8001c94: 210a movs r1, #10 + 8001c96: 438a bics r2, r1 + 8001c98: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; - 8001c16: 687b ldr r3, [r7, #4] - 8001c18: 2225 movs r2, #37 @ 0x25 - 8001c1a: 2101 movs r1, #1 - 8001c1c: 5499 strb r1, [r3, r2] + 8001c9a: 687b ldr r3, [r7, #4] + 8001c9c: 2225 movs r2, #37 @ 0x25 + 8001c9e: 2101 movs r1, #1 + 8001ca0: 5499 strb r1, [r3, r2] } /* Clear the transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU))); - 8001c1e: 4b29 ldr r3, [pc, #164] @ (8001cc4 ) - 8001c20: 6859 ldr r1, [r3, #4] - 8001c22: 687b ldr r3, [r7, #4] - 8001c24: 6c1b ldr r3, [r3, #64] @ 0x40 - 8001c26: 221c movs r2, #28 - 8001c28: 4013 ands r3, r2 - 8001c2a: 2202 movs r2, #2 - 8001c2c: 409a lsls r2, r3 - 8001c2e: 4b25 ldr r3, [pc, #148] @ (8001cc4 ) - 8001c30: 430a orrs r2, r1 - 8001c32: 605a str r2, [r3, #4] + 8001ca2: 4b29 ldr r3, [pc, #164] @ (8001d48 ) + 8001ca4: 6859 ldr r1, [r3, #4] + 8001ca6: 687b ldr r3, [r7, #4] + 8001ca8: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001caa: 221c movs r2, #28 + 8001cac: 4013 ands r3, r2 + 8001cae: 2202 movs r2, #2 + 8001cb0: 409a lsls r2, r3 + 8001cb2: 4b25 ldr r3, [pc, #148] @ (8001d48 ) + 8001cb4: 430a orrs r2, r1 + 8001cb6: 605a str r2, [r3, #4] /* Process Unlocked */ __HAL_UNLOCK(hdma); - 8001c34: 687b ldr r3, [r7, #4] - 8001c36: 2224 movs r2, #36 @ 0x24 - 8001c38: 2100 movs r1, #0 - 8001c3a: 5499 strb r1, [r3, r2] + 8001cb8: 687b ldr r3, [r7, #4] + 8001cba: 2224 movs r2, #36 @ 0x24 + 8001cbc: 2100 movs r1, #0 + 8001cbe: 5499 strb r1, [r3, r2] if (hdma->XferCpltCallback != NULL) - 8001c3c: 687b ldr r3, [r7, #4] - 8001c3e: 6adb ldr r3, [r3, #44] @ 0x2c - 8001c40: 2b00 cmp r3, #0 - 8001c42: d03a beq.n 8001cba + 8001cc0: 687b ldr r3, [r7, #4] + 8001cc2: 6adb ldr r3, [r3, #44] @ 0x2c + 8001cc4: 2b00 cmp r3, #0 + 8001cc6: d03a beq.n 8001d3e { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); - 8001c44: 687b ldr r3, [r7, #4] - 8001c46: 6adb ldr r3, [r3, #44] @ 0x2c - 8001c48: 687a ldr r2, [r7, #4] - 8001c4a: 0010 movs r0, r2 - 8001c4c: 4798 blx r3 + 8001cc8: 687b ldr r3, [r7, #4] + 8001cca: 6adb ldr r3, [r3, #44] @ 0x2c + 8001ccc: 687a ldr r2, [r7, #4] + 8001cce: 0010 movs r0, r2 + 8001cd0: 4798 blx r3 if (hdma->XferCpltCallback != NULL) - 8001c4e: e034 b.n 8001cba + 8001cd2: e034 b.n 8001d3e } } /* Transfer Error Interrupt management **************************************/ else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_TE) != 0U)) - 8001c50: 687b ldr r3, [r7, #4] - 8001c52: 6c1b ldr r3, [r3, #64] @ 0x40 - 8001c54: 221c movs r2, #28 - 8001c56: 4013 ands r3, r2 - 8001c58: 2208 movs r2, #8 - 8001c5a: 409a lsls r2, r3 - 8001c5c: 0013 movs r3, r2 - 8001c5e: 68fa ldr r2, [r7, #12] - 8001c60: 4013 ands r3, r2 - 8001c62: d02b beq.n 8001cbc - 8001c64: 68bb ldr r3, [r7, #8] - 8001c66: 2208 movs r2, #8 - 8001c68: 4013 ands r3, r2 - 8001c6a: d027 beq.n 8001cbc + 8001cd4: 687b ldr r3, [r7, #4] + 8001cd6: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001cd8: 221c movs r2, #28 + 8001cda: 4013 ands r3, r2 + 8001cdc: 2208 movs r2, #8 + 8001cde: 409a lsls r2, r3 + 8001ce0: 0013 movs r3, r2 + 8001ce2: 68fa ldr r2, [r7, #12] + 8001ce4: 4013 ands r3, r2 + 8001ce6: d02b beq.n 8001d40 + 8001ce8: 68bb ldr r3, [r7, #8] + 8001cea: 2208 movs r2, #8 + 8001cec: 4013 ands r3, r2 + 8001cee: d027 beq.n 8001d40 { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Disable ALL DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); - 8001c6c: 687b ldr r3, [r7, #4] - 8001c6e: 681b ldr r3, [r3, #0] - 8001c70: 681a ldr r2, [r3, #0] - 8001c72: 687b ldr r3, [r7, #4] - 8001c74: 681b ldr r3, [r3, #0] - 8001c76: 210e movs r1, #14 - 8001c78: 438a bics r2, r1 - 8001c7a: 601a str r2, [r3, #0] + 8001cf0: 687b ldr r3, [r7, #4] + 8001cf2: 681b ldr r3, [r3, #0] + 8001cf4: 681a ldr r2, [r3, #0] + 8001cf6: 687b ldr r3, [r7, #4] + 8001cf8: 681b ldr r3, [r3, #0] + 8001cfa: 210e movs r1, #14 + 8001cfc: 438a bics r2, r1 + 8001cfe: 601a str r2, [r3, #0] /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1cU))); - 8001c7c: 4b11 ldr r3, [pc, #68] @ (8001cc4 ) - 8001c7e: 6859 ldr r1, [r3, #4] - 8001c80: 687b ldr r3, [r7, #4] - 8001c82: 6c1b ldr r3, [r3, #64] @ 0x40 - 8001c84: 221c movs r2, #28 - 8001c86: 4013 ands r3, r2 - 8001c88: 2201 movs r2, #1 - 8001c8a: 409a lsls r2, r3 - 8001c8c: 4b0d ldr r3, [pc, #52] @ (8001cc4 ) - 8001c8e: 430a orrs r2, r1 - 8001c90: 605a str r2, [r3, #4] + 8001d00: 4b11 ldr r3, [pc, #68] @ (8001d48 ) + 8001d02: 6859 ldr r1, [r3, #4] + 8001d04: 687b ldr r3, [r7, #4] + 8001d06: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001d08: 221c movs r2, #28 + 8001d0a: 4013 ands r3, r2 + 8001d0c: 2201 movs r2, #1 + 8001d0e: 409a lsls r2, r3 + 8001d10: 4b0d ldr r3, [pc, #52] @ (8001d48 ) + 8001d12: 430a orrs r2, r1 + 8001d14: 605a str r2, [r3, #4] /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; - 8001c92: 687b ldr r3, [r7, #4] - 8001c94: 2201 movs r2, #1 - 8001c96: 63da str r2, [r3, #60] @ 0x3c + 8001d16: 687b ldr r3, [r7, #4] + 8001d18: 2201 movs r2, #1 + 8001d1a: 63da str r2, [r3, #60] @ 0x3c /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; - 8001c98: 687b ldr r3, [r7, #4] - 8001c9a: 2225 movs r2, #37 @ 0x25 - 8001c9c: 2101 movs r1, #1 - 8001c9e: 5499 strb r1, [r3, r2] + 8001d1c: 687b ldr r3, [r7, #4] + 8001d1e: 2225 movs r2, #37 @ 0x25 + 8001d20: 2101 movs r1, #1 + 8001d22: 5499 strb r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(hdma); - 8001ca0: 687b ldr r3, [r7, #4] - 8001ca2: 2224 movs r2, #36 @ 0x24 - 8001ca4: 2100 movs r1, #0 - 8001ca6: 5499 strb r1, [r3, r2] + 8001d24: 687b ldr r3, [r7, #4] + 8001d26: 2224 movs r2, #36 @ 0x24 + 8001d28: 2100 movs r1, #0 + 8001d2a: 5499 strb r1, [r3, r2] if (hdma->XferErrorCallback != NULL) - 8001ca8: 687b ldr r3, [r7, #4] - 8001caa: 6b5b ldr r3, [r3, #52] @ 0x34 - 8001cac: 2b00 cmp r3, #0 - 8001cae: d005 beq.n 8001cbc + 8001d2c: 687b ldr r3, [r7, #4] + 8001d2e: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001d30: 2b00 cmp r3, #0 + 8001d32: d005 beq.n 8001d40 { /* Transfer error callback */ hdma->XferErrorCallback(hdma); - 8001cb0: 687b ldr r3, [r7, #4] - 8001cb2: 6b5b ldr r3, [r3, #52] @ 0x34 - 8001cb4: 687a ldr r2, [r7, #4] - 8001cb6: 0010 movs r0, r2 - 8001cb8: 4798 blx r3 + 8001d34: 687b ldr r3, [r7, #4] + 8001d36: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001d38: 687a ldr r2, [r7, #4] + 8001d3a: 0010 movs r0, r2 + 8001d3c: 4798 blx r3 } else { /* Nothing To Do */ } return; - 8001cba: 46c0 nop @ (mov r8, r8) - 8001cbc: 46c0 nop @ (mov r8, r8) + 8001d3e: 46c0 nop @ (mov r8, r8) + 8001d40: 46c0 nop @ (mov r8, r8) } - 8001cbe: 46bd mov sp, r7 - 8001cc0: b004 add sp, #16 - 8001cc2: bd80 pop {r7, pc} - 8001cc4: 40020000 .word 0x40020000 + 8001d42: 46bd mov sp, r7 + 8001d44: b004 add sp, #16 + 8001d46: bd80 pop {r7, pc} + 8001d48: 40020000 .word 0x40020000 -08001cc8 : +08001d4c : * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { - 8001cc8: b580 push {r7, lr} - 8001cca: b084 sub sp, #16 - 8001ccc: af00 add r7, sp, #0 - 8001cce: 60f8 str r0, [r7, #12] - 8001cd0: 60b9 str r1, [r7, #8] - 8001cd2: 607a str r2, [r7, #4] - 8001cd4: 603b str r3, [r7, #0] + 8001d4c: b580 push {r7, lr} + 8001d4e: b084 sub sp, #16 + 8001d50: af00 add r7, sp, #0 + 8001d52: 60f8 str r0, [r7, #12] + 8001d54: 60b9 str r1, [r7, #8] + 8001d56: 607a str r2, [r7, #4] + 8001d58: 603b str r3, [r7, #0] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; - 8001cd6: 68fb ldr r3, [r7, #12] - 8001cd8: 6c9b ldr r3, [r3, #72] @ 0x48 - 8001cda: 68fa ldr r2, [r7, #12] - 8001cdc: 6cd2 ldr r2, [r2, #76] @ 0x4c - 8001cde: 605a str r2, [r3, #4] + 8001d5a: 68fb ldr r3, [r7, #12] + 8001d5c: 6c9b ldr r3, [r3, #72] @ 0x48 + 8001d5e: 68fa ldr r2, [r7, #12] + 8001d60: 6cd2 ldr r2, [r2, #76] @ 0x4c + 8001d62: 605a str r2, [r3, #4] if (hdma->DMAmuxRequestGen != 0U) - 8001ce0: 68fb ldr r3, [r7, #12] - 8001ce2: 6d1b ldr r3, [r3, #80] @ 0x50 - 8001ce4: 2b00 cmp r3, #0 - 8001ce6: d004 beq.n 8001cf2 + 8001d64: 68fb ldr r3, [r7, #12] + 8001d66: 6d1b ldr r3, [r3, #80] @ 0x50 + 8001d68: 2b00 cmp r3, #0 + 8001d6a: d004 beq.n 8001d76 { /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; - 8001ce8: 68fb ldr r3, [r7, #12] - 8001cea: 6d5b ldr r3, [r3, #84] @ 0x54 - 8001cec: 68fa ldr r2, [r7, #12] - 8001cee: 6d92 ldr r2, [r2, #88] @ 0x58 - 8001cf0: 605a str r2, [r3, #4] + 8001d6c: 68fb ldr r3, [r7, #12] + 8001d6e: 6d5b ldr r3, [r3, #84] @ 0x54 + 8001d70: 68fa ldr r2, [r7, #12] + 8001d72: 6d92 ldr r2, [r2, #88] @ 0x58 + 8001d74: 605a str r2, [r3, #4] } /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1cU))); - 8001cf2: 4b14 ldr r3, [pc, #80] @ (8001d44 ) - 8001cf4: 6859 ldr r1, [r3, #4] - 8001cf6: 68fb ldr r3, [r7, #12] - 8001cf8: 6c1b ldr r3, [r3, #64] @ 0x40 - 8001cfa: 221c movs r2, #28 - 8001cfc: 4013 ands r3, r2 - 8001cfe: 2201 movs r2, #1 - 8001d00: 409a lsls r2, r3 - 8001d02: 4b10 ldr r3, [pc, #64] @ (8001d44 ) - 8001d04: 430a orrs r2, r1 - 8001d06: 605a str r2, [r3, #4] + 8001d76: 4b14 ldr r3, [pc, #80] @ (8001dc8 ) + 8001d78: 6859 ldr r1, [r3, #4] + 8001d7a: 68fb ldr r3, [r7, #12] + 8001d7c: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001d7e: 221c movs r2, #28 + 8001d80: 4013 ands r3, r2 + 8001d82: 2201 movs r2, #1 + 8001d84: 409a lsls r2, r3 + 8001d86: 4b10 ldr r3, [pc, #64] @ (8001dc8 ) + 8001d88: 430a orrs r2, r1 + 8001d8a: 605a str r2, [r3, #4] /* Configure DMA Channel data length */ hdma->Instance->CNDTR = DataLength; - 8001d08: 68fb ldr r3, [r7, #12] - 8001d0a: 681b ldr r3, [r3, #0] - 8001d0c: 683a ldr r2, [r7, #0] - 8001d0e: 605a str r2, [r3, #4] + 8001d8c: 68fb ldr r3, [r7, #12] + 8001d8e: 681b ldr r3, [r3, #0] + 8001d90: 683a ldr r2, [r7, #0] + 8001d92: 605a str r2, [r3, #4] /* Peripheral to Memory */ if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) - 8001d10: 68fb ldr r3, [r7, #12] - 8001d12: 689b ldr r3, [r3, #8] - 8001d14: 2b10 cmp r3, #16 - 8001d16: d108 bne.n 8001d2a + 8001d94: 68fb ldr r3, [r7, #12] + 8001d96: 689b ldr r3, [r3, #8] + 8001d98: 2b10 cmp r3, #16 + 8001d9a: d108 bne.n 8001dae { /* Configure DMA Channel destination address */ hdma->Instance->CPAR = DstAddress; - 8001d18: 68fb ldr r3, [r7, #12] - 8001d1a: 681b ldr r3, [r3, #0] - 8001d1c: 687a ldr r2, [r7, #4] - 8001d1e: 609a str r2, [r3, #8] + 8001d9c: 68fb ldr r3, [r7, #12] + 8001d9e: 681b ldr r3, [r3, #0] + 8001da0: 687a ldr r2, [r7, #4] + 8001da2: 609a str r2, [r3, #8] /* Configure DMA Channel source address */ hdma->Instance->CMAR = SrcAddress; - 8001d20: 68fb ldr r3, [r7, #12] - 8001d22: 681b ldr r3, [r3, #0] - 8001d24: 68ba ldr r2, [r7, #8] - 8001d26: 60da str r2, [r3, #12] + 8001da4: 68fb ldr r3, [r7, #12] + 8001da6: 681b ldr r3, [r3, #0] + 8001da8: 68ba ldr r2, [r7, #8] + 8001daa: 60da str r2, [r3, #12] hdma->Instance->CPAR = SrcAddress; /* Configure DMA Channel destination address */ hdma->Instance->CMAR = DstAddress; } } - 8001d28: e007 b.n 8001d3a + 8001dac: e007 b.n 8001dbe hdma->Instance->CPAR = SrcAddress; - 8001d2a: 68fb ldr r3, [r7, #12] - 8001d2c: 681b ldr r3, [r3, #0] - 8001d2e: 68ba ldr r2, [r7, #8] - 8001d30: 609a str r2, [r3, #8] + 8001dae: 68fb ldr r3, [r7, #12] + 8001db0: 681b ldr r3, [r3, #0] + 8001db2: 68ba ldr r2, [r7, #8] + 8001db4: 609a str r2, [r3, #8] hdma->Instance->CMAR = DstAddress; - 8001d32: 68fb ldr r3, [r7, #12] - 8001d34: 681b ldr r3, [r3, #0] - 8001d36: 687a ldr r2, [r7, #4] - 8001d38: 60da str r2, [r3, #12] + 8001db6: 68fb ldr r3, [r7, #12] + 8001db8: 681b ldr r3, [r3, #0] + 8001dba: 687a ldr r2, [r7, #4] + 8001dbc: 60da str r2, [r3, #12] } - 8001d3a: 46c0 nop @ (mov r8, r8) - 8001d3c: 46bd mov sp, r7 - 8001d3e: b004 add sp, #16 - 8001d40: bd80 pop {r7, pc} - 8001d42: 46c0 nop @ (mov r8, r8) - 8001d44: 40020000 .word 0x40020000 + 8001dbe: 46c0 nop @ (mov r8, r8) + 8001dc0: 46bd mov sp, r7 + 8001dc2: b004 add sp, #16 + 8001dc4: bd80 pop {r7, pc} + 8001dc6: 46c0 nop @ (mov r8, r8) + 8001dc8: 40020000 .word 0x40020000 -08001d48 : +08001dcc : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) { - 8001d48: b580 push {r7, lr} - 8001d4a: b084 sub sp, #16 - 8001d4c: af00 add r7, sp, #0 - 8001d4e: 6078 str r0, [r7, #4] + 8001dcc: b580 push {r7, lr} + 8001dce: b084 sub sp, #16 + 8001dd0: af00 add r7, sp, #0 + 8001dd2: 6078 str r0, [r7, #4] uint32_t channel_number; channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U; - 8001d50: 687b ldr r3, [r7, #4] - 8001d52: 681b ldr r3, [r3, #0] - 8001d54: 001a movs r2, r3 - 8001d56: 23ff movs r3, #255 @ 0xff - 8001d58: 4013 ands r3, r2 - 8001d5a: 3b08 subs r3, #8 - 8001d5c: 2114 movs r1, #20 - 8001d5e: 0018 movs r0, r3 - 8001d60: f7fe f9d2 bl 8000108 <__udivsi3> - 8001d64: 0003 movs r3, r0 - 8001d66: 60fb str r3, [r7, #12] + 8001dd4: 687b ldr r3, [r7, #4] + 8001dd6: 681b ldr r3, [r3, #0] + 8001dd8: 001a movs r2, r3 + 8001dda: 23ff movs r3, #255 @ 0xff + 8001ddc: 4013 ands r3, r2 + 8001dde: 3b08 subs r3, #8 + 8001de0: 2114 movs r1, #20 + 8001de2: 0018 movs r0, r3 + 8001de4: f7fe f990 bl 8000108 <__udivsi3> + 8001de8: 0003 movs r3, r0 + 8001dea: 60fb str r3, [r7, #12] hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + \ ((hdma->ChannelIndex >> 2U) * \ - 8001d68: 687b ldr r3, [r7, #4] - 8001d6a: 6c1b ldr r3, [r3, #64] @ 0x40 - 8001d6c: 089b lsrs r3, r3, #2 + 8001dec: 687b ldr r3, [r7, #4] + 8001dee: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001df0: 089b lsrs r3, r3, #2 hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + \ - 8001d6e: 4a0a ldr r2, [pc, #40] @ (8001d98 ) - 8001d70: 4694 mov ip, r2 - 8001d72: 4463 add r3, ip - 8001d74: 009b lsls r3, r3, #2 - 8001d76: 001a movs r2, r3 - 8001d78: 687b ldr r3, [r7, #4] - 8001d7a: 645a str r2, [r3, #68] @ 0x44 + 8001df2: 4a0a ldr r2, [pc, #40] @ (8001e1c ) + 8001df4: 4694 mov ip, r2 + 8001df6: 4463 add r3, ip + 8001df8: 009b lsls r3, r3, #2 + 8001dfa: 001a movs r2, r3 + 8001dfc: 687b ldr r3, [r7, #4] + 8001dfe: 645a str r2, [r3, #68] @ 0x44 ((uint32_t)DMAMUX1_Channel1 - \ (uint32_t)DMAMUX1_Channel0))); hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; - 8001d7c: 687b ldr r3, [r7, #4] - 8001d7e: 4a07 ldr r2, [pc, #28] @ (8001d9c ) - 8001d80: 649a str r2, [r3, #72] @ 0x48 + 8001e00: 687b ldr r3, [r7, #4] + 8001e02: 4a07 ldr r2, [pc, #28] @ (8001e20 ) + 8001e04: 649a str r2, [r3, #72] @ 0x48 hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1cU); - 8001d82: 68fb ldr r3, [r7, #12] - 8001d84: 221c movs r2, #28 - 8001d86: 4013 ands r3, r2 - 8001d88: 2201 movs r2, #1 - 8001d8a: 409a lsls r2, r3 - 8001d8c: 687b ldr r3, [r7, #4] - 8001d8e: 64da str r2, [r3, #76] @ 0x4c + 8001e06: 68fb ldr r3, [r7, #12] + 8001e08: 221c movs r2, #28 + 8001e0a: 4013 ands r3, r2 + 8001e0c: 2201 movs r2, #1 + 8001e0e: 409a lsls r2, r3 + 8001e10: 687b ldr r3, [r7, #4] + 8001e12: 64da str r2, [r3, #76] @ 0x4c } - 8001d90: 46c0 nop @ (mov r8, r8) - 8001d92: 46bd mov sp, r7 - 8001d94: b004 add sp, #16 - 8001d96: bd80 pop {r7, pc} - 8001d98: 10008200 .word 0x10008200 - 8001d9c: 40020880 .word 0x40020880 + 8001e14: 46c0 nop @ (mov r8, r8) + 8001e16: 46bd mov sp, r7 + 8001e18: b004 add sp, #16 + 8001e1a: bd80 pop {r7, pc} + 8001e1c: 10008200 .word 0x10008200 + 8001e20: 40020880 .word 0x40020880 -08001da0 : +08001e24 : * the configuration information for the specified DMA Stream. * @retval None */ static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) { - 8001da0: b580 push {r7, lr} - 8001da2: b084 sub sp, #16 - 8001da4: af00 add r7, sp, #0 - 8001da6: 6078 str r0, [r7, #4] + 8001e24: b580 push {r7, lr} + 8001e26: b084 sub sp, #16 + 8001e28: af00 add r7, sp, #0 + 8001e2a: 6078 str r0, [r7, #4] uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; - 8001da8: 687b ldr r3, [r7, #4] - 8001daa: 685b ldr r3, [r3, #4] - 8001dac: 22ff movs r2, #255 @ 0xff - 8001dae: 4013 ands r3, r2 - 8001db0: 60fb str r3, [r7, #12] + 8001e2c: 687b ldr r3, [r7, #4] + 8001e2e: 685b ldr r3, [r3, #4] + 8001e30: 22ff movs r2, #255 @ 0xff + 8001e32: 4013 ands r3, r2 + 8001e34: 60fb str r3, [r7, #12] /* DMA Channels are connected to DMAMUX1 request generator blocks*/ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + \ - 8001db2: 68fb ldr r3, [r7, #12] - 8001db4: 4a0a ldr r2, [pc, #40] @ (8001de0 ) - 8001db6: 4694 mov ip, r2 - 8001db8: 4463 add r3, ip - 8001dba: 009b lsls r3, r3, #2 - 8001dbc: 001a movs r2, r3 - 8001dbe: 687b ldr r3, [r7, #4] - 8001dc0: 651a str r2, [r3, #80] @ 0x50 + 8001e36: 68fb ldr r3, [r7, #12] + 8001e38: 4a0a ldr r2, [pc, #40] @ (8001e64 ) + 8001e3a: 4694 mov ip, r2 + 8001e3c: 4463 add r3, ip + 8001e3e: 009b lsls r3, r3, #2 + 8001e40: 001a movs r2, r3 + 8001e42: 687b ldr r3, [r7, #4] + 8001e44: 651a str r2, [r3, #80] @ 0x50 ((request - 1U) * 4U))); hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; - 8001dc2: 687b ldr r3, [r7, #4] - 8001dc4: 4a07 ldr r2, [pc, #28] @ (8001de4 ) - 8001dc6: 655a str r2, [r3, #84] @ 0x54 + 8001e46: 687b ldr r3, [r7, #4] + 8001e48: 4a07 ldr r2, [pc, #28] @ (8001e68 ) + 8001e4a: 655a str r2, [r3, #84] @ 0x54 /* here "Request" is either DMA_REQUEST_GENERATOR0 to 4, i.e. <= 4*/ hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U); - 8001dc8: 68fb ldr r3, [r7, #12] - 8001dca: 3b01 subs r3, #1 - 8001dcc: 2203 movs r2, #3 - 8001dce: 4013 ands r3, r2 - 8001dd0: 2201 movs r2, #1 - 8001dd2: 409a lsls r2, r3 - 8001dd4: 687b ldr r3, [r7, #4] - 8001dd6: 659a str r2, [r3, #88] @ 0x58 + 8001e4c: 68fb ldr r3, [r7, #12] + 8001e4e: 3b01 subs r3, #1 + 8001e50: 2203 movs r2, #3 + 8001e52: 4013 ands r3, r2 + 8001e54: 2201 movs r2, #1 + 8001e56: 409a lsls r2, r3 + 8001e58: 687b ldr r3, [r7, #4] + 8001e5a: 659a str r2, [r3, #88] @ 0x58 } - 8001dd8: 46c0 nop @ (mov r8, r8) - 8001dda: 46bd mov sp, r7 - 8001ddc: b004 add sp, #16 - 8001dde: bd80 pop {r7, pc} - 8001de0: 1000823f .word 0x1000823f - 8001de4: 40020940 .word 0x40020940 + 8001e5c: 46c0 nop @ (mov r8, r8) + 8001e5e: 46bd mov sp, r7 + 8001e60: b004 add sp, #16 + 8001e62: bd80 pop {r7, pc} + 8001e64: 1000823f .word 0x1000823f + 8001e68: 40020940 .word 0x40020940 -08001de8 : +08001e6c : * @param pGPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init) { - 8001de8: b580 push {r7, lr} - 8001dea: b086 sub sp, #24 - 8001dec: af00 add r7, sp, #0 - 8001dee: 6078 str r0, [r7, #4] - 8001df0: 6039 str r1, [r7, #0] + 8001e6c: b580 push {r7, lr} + 8001e6e: b086 sub sp, #24 + 8001e70: af00 add r7, sp, #0 + 8001e72: 6078 str r0, [r7, #4] + 8001e74: 6039 str r1, [r7, #0] uint32_t tmp; uint32_t iocurrent; uint32_t position = 0U; - 8001df2: 2300 movs r3, #0 - 8001df4: 613b str r3, [r7, #16] + 8001e76: 2300 movs r3, #0 + 8001e78: 613b str r3, [r7, #16] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(pGPIO_Init->Pin)); assert_param(IS_GPIO_MODE(pGPIO_Init->Mode)); /* Configure the port pins */ while (((pGPIO_Init->Pin) >> position) != 0U) - 8001df6: e153 b.n 80020a0 + 8001e7a: e153 b.n 8002124 { /* Get current io position */ iocurrent = (pGPIO_Init->Pin) & (1UL << position); - 8001df8: 683b ldr r3, [r7, #0] - 8001dfa: 681b ldr r3, [r3, #0] - 8001dfc: 2101 movs r1, #1 - 8001dfe: 693a ldr r2, [r7, #16] - 8001e00: 4091 lsls r1, r2 - 8001e02: 000a movs r2, r1 - 8001e04: 4013 ands r3, r2 - 8001e06: 60fb str r3, [r7, #12] + 8001e7c: 683b ldr r3, [r7, #0] + 8001e7e: 681b ldr r3, [r3, #0] + 8001e80: 2101 movs r1, #1 + 8001e82: 693a ldr r2, [r7, #16] + 8001e84: 4091 lsls r1, r2 + 8001e86: 000a movs r2, r1 + 8001e88: 4013 ands r3, r2 + 8001e8a: 60fb str r3, [r7, #12] if (iocurrent != 0U) - 8001e08: 68fb ldr r3, [r7, #12] - 8001e0a: 2b00 cmp r3, #0 - 8001e0c: d100 bne.n 8001e10 - 8001e0e: e144 b.n 800209a + 8001e8c: 68fb ldr r3, [r7, #12] + 8001e8e: 2b00 cmp r3, #0 + 8001e90: d100 bne.n 8001e94 + 8001e92: e144 b.n 800211e { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Alternate function mode selection */ if ((pGPIO_Init->Mode == GPIO_MODE_AF_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_OD)) - 8001e10: 683b ldr r3, [r7, #0] - 8001e12: 685b ldr r3, [r3, #4] - 8001e14: 2b02 cmp r3, #2 - 8001e16: d003 beq.n 8001e20 - 8001e18: 683b ldr r3, [r7, #0] - 8001e1a: 685b ldr r3, [r3, #4] - 8001e1c: 2b12 cmp r3, #18 - 8001e1e: d125 bne.n 8001e6c + 8001e94: 683b ldr r3, [r7, #0] + 8001e96: 685b ldr r3, [r3, #4] + 8001e98: 2b02 cmp r3, #2 + 8001e9a: d003 beq.n 8001ea4 + 8001e9c: 683b ldr r3, [r7, #0] + 8001e9e: 685b ldr r3, [r3, #4] + 8001ea0: 2b12 cmp r3, #18 + 8001ea2: d125 bne.n 8001ef0 /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(pGPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ tmp = GPIOx->AFR[position >> 3U]; - 8001e20: 693b ldr r3, [r7, #16] - 8001e22: 08da lsrs r2, r3, #3 - 8001e24: 687b ldr r3, [r7, #4] - 8001e26: 3208 adds r2, #8 - 8001e28: 0092 lsls r2, r2, #2 - 8001e2a: 58d3 ldr r3, [r2, r3] - 8001e2c: 617b str r3, [r7, #20] + 8001ea4: 693b ldr r3, [r7, #16] + 8001ea6: 08da lsrs r2, r3, #3 + 8001ea8: 687b ldr r3, [r7, #4] + 8001eaa: 3208 adds r2, #8 + 8001eac: 0092 lsls r2, r2, #2 + 8001eae: 58d3 ldr r3, [r2, r3] + 8001eb0: 617b str r3, [r7, #20] tmp &= ~(0xFUL << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)) ; - 8001e2e: 693b ldr r3, [r7, #16] - 8001e30: 2207 movs r2, #7 - 8001e32: 4013 ands r3, r2 - 8001e34: 009b lsls r3, r3, #2 - 8001e36: 220f movs r2, #15 - 8001e38: 409a lsls r2, r3 - 8001e3a: 0013 movs r3, r2 - 8001e3c: 43da mvns r2, r3 - 8001e3e: 697b ldr r3, [r7, #20] - 8001e40: 4013 ands r3, r2 - 8001e42: 617b str r3, [r7, #20] + 8001eb2: 693b ldr r3, [r7, #16] + 8001eb4: 2207 movs r2, #7 + 8001eb6: 4013 ands r3, r2 + 8001eb8: 009b lsls r3, r3, #2 + 8001eba: 220f movs r2, #15 + 8001ebc: 409a lsls r2, r3 + 8001ebe: 0013 movs r3, r2 + 8001ec0: 43da mvns r2, r3 + 8001ec2: 697b ldr r3, [r7, #20] + 8001ec4: 4013 ands r3, r2 + 8001ec6: 617b str r3, [r7, #20] tmp |= ((pGPIO_Init->Alternate & 0x0FUL) << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)); - 8001e44: 683b ldr r3, [r7, #0] - 8001e46: 691b ldr r3, [r3, #16] - 8001e48: 220f movs r2, #15 - 8001e4a: 401a ands r2, r3 - 8001e4c: 693b ldr r3, [r7, #16] - 8001e4e: 2107 movs r1, #7 - 8001e50: 400b ands r3, r1 - 8001e52: 009b lsls r3, r3, #2 - 8001e54: 409a lsls r2, r3 - 8001e56: 0013 movs r3, r2 - 8001e58: 697a ldr r2, [r7, #20] - 8001e5a: 4313 orrs r3, r2 - 8001e5c: 617b str r3, [r7, #20] + 8001ec8: 683b ldr r3, [r7, #0] + 8001eca: 691b ldr r3, [r3, #16] + 8001ecc: 220f movs r2, #15 + 8001ece: 401a ands r2, r3 + 8001ed0: 693b ldr r3, [r7, #16] + 8001ed2: 2107 movs r1, #7 + 8001ed4: 400b ands r3, r1 + 8001ed6: 009b lsls r3, r3, #2 + 8001ed8: 409a lsls r2, r3 + 8001eda: 0013 movs r3, r2 + 8001edc: 697a ldr r2, [r7, #20] + 8001ede: 4313 orrs r3, r2 + 8001ee0: 617b str r3, [r7, #20] GPIOx->AFR[position >> 3U] = tmp; - 8001e5e: 693b ldr r3, [r7, #16] - 8001e60: 08da lsrs r2, r3, #3 - 8001e62: 687b ldr r3, [r7, #4] - 8001e64: 3208 adds r2, #8 - 8001e66: 0092 lsls r2, r2, #2 - 8001e68: 6979 ldr r1, [r7, #20] - 8001e6a: 50d1 str r1, [r2, r3] + 8001ee2: 693b ldr r3, [r7, #16] + 8001ee4: 08da lsrs r2, r3, #3 + 8001ee6: 687b ldr r3, [r7, #4] + 8001ee8: 3208 adds r2, #8 + 8001eea: 0092 lsls r2, r2, #2 + 8001eec: 6979 ldr r1, [r7, #20] + 8001eee: 50d1 str r1, [r2, r3] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ tmp = GPIOx->MODER; - 8001e6c: 687b ldr r3, [r7, #4] - 8001e6e: 681b ldr r3, [r3, #0] - 8001e70: 617b str r3, [r7, #20] + 8001ef0: 687b ldr r3, [r7, #4] + 8001ef2: 681b ldr r3, [r3, #0] + 8001ef4: 617b str r3, [r7, #20] tmp &= ~(GPIO_MODER_MODE0 << (position * GPIO_MODER_MODE1_Pos)); - 8001e72: 693b ldr r3, [r7, #16] - 8001e74: 005b lsls r3, r3, #1 - 8001e76: 2203 movs r2, #3 - 8001e78: 409a lsls r2, r3 - 8001e7a: 0013 movs r3, r2 - 8001e7c: 43da mvns r2, r3 - 8001e7e: 697b ldr r3, [r7, #20] - 8001e80: 4013 ands r3, r2 - 8001e82: 617b str r3, [r7, #20] + 8001ef6: 693b ldr r3, [r7, #16] + 8001ef8: 005b lsls r3, r3, #1 + 8001efa: 2203 movs r2, #3 + 8001efc: 409a lsls r2, r3 + 8001efe: 0013 movs r3, r2 + 8001f00: 43da mvns r2, r3 + 8001f02: 697b ldr r3, [r7, #20] + 8001f04: 4013 ands r3, r2 + 8001f06: 617b str r3, [r7, #20] tmp |= ((pGPIO_Init->Mode & GPIO_MODE) << (position * GPIO_MODER_MODE1_Pos)); - 8001e84: 683b ldr r3, [r7, #0] - 8001e86: 685b ldr r3, [r3, #4] - 8001e88: 2203 movs r2, #3 - 8001e8a: 401a ands r2, r3 - 8001e8c: 693b ldr r3, [r7, #16] - 8001e8e: 005b lsls r3, r3, #1 - 8001e90: 409a lsls r2, r3 - 8001e92: 0013 movs r3, r2 - 8001e94: 697a ldr r2, [r7, #20] - 8001e96: 4313 orrs r3, r2 - 8001e98: 617b str r3, [r7, #20] + 8001f08: 683b ldr r3, [r7, #0] + 8001f0a: 685b ldr r3, [r3, #4] + 8001f0c: 2203 movs r2, #3 + 8001f0e: 401a ands r2, r3 + 8001f10: 693b ldr r3, [r7, #16] + 8001f12: 005b lsls r3, r3, #1 + 8001f14: 409a lsls r2, r3 + 8001f16: 0013 movs r3, r2 + 8001f18: 697a ldr r2, [r7, #20] + 8001f1a: 4313 orrs r3, r2 + 8001f1c: 617b str r3, [r7, #20] GPIOx->MODER = tmp; - 8001e9a: 687b ldr r3, [r7, #4] - 8001e9c: 697a ldr r2, [r7, #20] - 8001e9e: 601a str r2, [r3, #0] + 8001f1e: 687b ldr r3, [r7, #4] + 8001f20: 697a ldr r2, [r7, #20] + 8001f22: 601a str r2, [r3, #0] /* In case of Output or Alternate function mode selection */ if ((pGPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_PP) || - 8001ea0: 683b ldr r3, [r7, #0] - 8001ea2: 685b ldr r3, [r3, #4] - 8001ea4: 2b01 cmp r3, #1 - 8001ea6: d00b beq.n 8001ec0 - 8001ea8: 683b ldr r3, [r7, #0] - 8001eaa: 685b ldr r3, [r3, #4] - 8001eac: 2b02 cmp r3, #2 - 8001eae: d007 beq.n 8001ec0 + 8001f24: 683b ldr r3, [r7, #0] + 8001f26: 685b ldr r3, [r3, #4] + 8001f28: 2b01 cmp r3, #1 + 8001f2a: d00b beq.n 8001f44 + 8001f2c: 683b ldr r3, [r7, #0] + 8001f2e: 685b ldr r3, [r3, #4] + 8001f30: 2b02 cmp r3, #2 + 8001f32: d007 beq.n 8001f44 (pGPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (pGPIO_Init->Mode == GPIO_MODE_AF_OD)) - 8001eb0: 683b ldr r3, [r7, #0] - 8001eb2: 685b ldr r3, [r3, #4] + 8001f34: 683b ldr r3, [r7, #0] + 8001f36: 685b ldr r3, [r3, #4] if ((pGPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_PP) || - 8001eb4: 2b11 cmp r3, #17 - 8001eb6: d003 beq.n 8001ec0 + 8001f38: 2b11 cmp r3, #17 + 8001f3a: d003 beq.n 8001f44 (pGPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (pGPIO_Init->Mode == GPIO_MODE_AF_OD)) - 8001eb8: 683b ldr r3, [r7, #0] - 8001eba: 685b ldr r3, [r3, #4] - 8001ebc: 2b12 cmp r3, #18 - 8001ebe: d130 bne.n 8001f22 + 8001f3c: 683b ldr r3, [r7, #0] + 8001f3e: 685b ldr r3, [r3, #4] + 8001f40: 2b12 cmp r3, #18 + 8001f42: d130 bne.n 8001fa6 { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(pGPIO_Init->Speed)); /* Configure the IO Speed */ tmp = GPIOx->OSPEEDR; - 8001ec0: 687b ldr r3, [r7, #4] - 8001ec2: 689b ldr r3, [r3, #8] - 8001ec4: 617b str r3, [r7, #20] + 8001f44: 687b ldr r3, [r7, #4] + 8001f46: 689b ldr r3, [r3, #8] + 8001f48: 617b str r3, [r7, #20] tmp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * GPIO_OSPEEDR_OSPEED1_Pos)); - 8001ec6: 693b ldr r3, [r7, #16] - 8001ec8: 005b lsls r3, r3, #1 - 8001eca: 2203 movs r2, #3 - 8001ecc: 409a lsls r2, r3 - 8001ece: 0013 movs r3, r2 - 8001ed0: 43da mvns r2, r3 - 8001ed2: 697b ldr r3, [r7, #20] - 8001ed4: 4013 ands r3, r2 - 8001ed6: 617b str r3, [r7, #20] + 8001f4a: 693b ldr r3, [r7, #16] + 8001f4c: 005b lsls r3, r3, #1 + 8001f4e: 2203 movs r2, #3 + 8001f50: 409a lsls r2, r3 + 8001f52: 0013 movs r3, r2 + 8001f54: 43da mvns r2, r3 + 8001f56: 697b ldr r3, [r7, #20] + 8001f58: 4013 ands r3, r2 + 8001f5a: 617b str r3, [r7, #20] tmp |= (pGPIO_Init->Speed << (position * GPIO_OSPEEDR_OSPEED1_Pos)); - 8001ed8: 683b ldr r3, [r7, #0] - 8001eda: 68da ldr r2, [r3, #12] - 8001edc: 693b ldr r3, [r7, #16] - 8001ede: 005b lsls r3, r3, #1 - 8001ee0: 409a lsls r2, r3 - 8001ee2: 0013 movs r3, r2 - 8001ee4: 697a ldr r2, [r7, #20] - 8001ee6: 4313 orrs r3, r2 - 8001ee8: 617b str r3, [r7, #20] + 8001f5c: 683b ldr r3, [r7, #0] + 8001f5e: 68da ldr r2, [r3, #12] + 8001f60: 693b ldr r3, [r7, #16] + 8001f62: 005b lsls r3, r3, #1 + 8001f64: 409a lsls r2, r3 + 8001f66: 0013 movs r3, r2 + 8001f68: 697a ldr r2, [r7, #20] + 8001f6a: 4313 orrs r3, r2 + 8001f6c: 617b str r3, [r7, #20] GPIOx->OSPEEDR = tmp; - 8001eea: 687b ldr r3, [r7, #4] - 8001eec: 697a ldr r2, [r7, #20] - 8001eee: 609a str r2, [r3, #8] + 8001f6e: 687b ldr r3, [r7, #4] + 8001f70: 697a ldr r2, [r7, #20] + 8001f72: 609a str r2, [r3, #8] /* Configure the IO Output Type */ tmp = GPIOx->OTYPER; - 8001ef0: 687b ldr r3, [r7, #4] - 8001ef2: 685b ldr r3, [r3, #4] - 8001ef4: 617b str r3, [r7, #20] + 8001f74: 687b ldr r3, [r7, #4] + 8001f76: 685b ldr r3, [r3, #4] + 8001f78: 617b str r3, [r7, #20] tmp &= ~(GPIO_OTYPER_OT0 << position) ; - 8001ef6: 2201 movs r2, #1 - 8001ef8: 693b ldr r3, [r7, #16] - 8001efa: 409a lsls r2, r3 - 8001efc: 0013 movs r3, r2 - 8001efe: 43da mvns r2, r3 - 8001f00: 697b ldr r3, [r7, #20] - 8001f02: 4013 ands r3, r2 - 8001f04: 617b str r3, [r7, #20] + 8001f7a: 2201 movs r2, #1 + 8001f7c: 693b ldr r3, [r7, #16] + 8001f7e: 409a lsls r2, r3 + 8001f80: 0013 movs r3, r2 + 8001f82: 43da mvns r2, r3 + 8001f84: 697b ldr r3, [r7, #20] + 8001f86: 4013 ands r3, r2 + 8001f88: 617b str r3, [r7, #20] tmp |= (((pGPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position); - 8001f06: 683b ldr r3, [r7, #0] - 8001f08: 685b ldr r3, [r3, #4] - 8001f0a: 091b lsrs r3, r3, #4 - 8001f0c: 2201 movs r2, #1 - 8001f0e: 401a ands r2, r3 - 8001f10: 693b ldr r3, [r7, #16] - 8001f12: 409a lsls r2, r3 - 8001f14: 0013 movs r3, r2 - 8001f16: 697a ldr r2, [r7, #20] - 8001f18: 4313 orrs r3, r2 - 8001f1a: 617b str r3, [r7, #20] + 8001f8a: 683b ldr r3, [r7, #0] + 8001f8c: 685b ldr r3, [r3, #4] + 8001f8e: 091b lsrs r3, r3, #4 + 8001f90: 2201 movs r2, #1 + 8001f92: 401a ands r2, r3 + 8001f94: 693b ldr r3, [r7, #16] + 8001f96: 409a lsls r2, r3 + 8001f98: 0013 movs r3, r2 + 8001f9a: 697a ldr r2, [r7, #20] + 8001f9c: 4313 orrs r3, r2 + 8001f9e: 617b str r3, [r7, #20] GPIOx->OTYPER = tmp; - 8001f1c: 687b ldr r3, [r7, #4] - 8001f1e: 697a ldr r2, [r7, #20] - 8001f20: 605a str r2, [r3, #4] + 8001fa0: 687b ldr r3, [r7, #4] + 8001fa2: 697a ldr r2, [r7, #20] + 8001fa4: 605a str r2, [r3, #4] } if (pGPIO_Init->Mode != GPIO_MODE_ANALOG) - 8001f22: 683b ldr r3, [r7, #0] - 8001f24: 685b ldr r3, [r3, #4] - 8001f26: 2b03 cmp r3, #3 - 8001f28: d017 beq.n 8001f5a + 8001fa6: 683b ldr r3, [r7, #0] + 8001fa8: 685b ldr r3, [r3, #4] + 8001faa: 2b03 cmp r3, #3 + 8001fac: d017 beq.n 8001fde { /* Check the Pull parameters */ assert_param(IS_GPIO_PULL(pGPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ tmp = GPIOx->PUPDR; - 8001f2a: 687b ldr r3, [r7, #4] - 8001f2c: 68db ldr r3, [r3, #12] - 8001f2e: 617b str r3, [r7, #20] + 8001fae: 687b ldr r3, [r7, #4] + 8001fb0: 68db ldr r3, [r3, #12] + 8001fb2: 617b str r3, [r7, #20] tmp &= ~(GPIO_PUPDR_PUPD0 << (position * GPIO_PUPDR_PUPD1_Pos)); - 8001f30: 693b ldr r3, [r7, #16] - 8001f32: 005b lsls r3, r3, #1 - 8001f34: 2203 movs r2, #3 - 8001f36: 409a lsls r2, r3 - 8001f38: 0013 movs r3, r2 - 8001f3a: 43da mvns r2, r3 - 8001f3c: 697b ldr r3, [r7, #20] - 8001f3e: 4013 ands r3, r2 - 8001f40: 617b str r3, [r7, #20] + 8001fb4: 693b ldr r3, [r7, #16] + 8001fb6: 005b lsls r3, r3, #1 + 8001fb8: 2203 movs r2, #3 + 8001fba: 409a lsls r2, r3 + 8001fbc: 0013 movs r3, r2 + 8001fbe: 43da mvns r2, r3 + 8001fc0: 697b ldr r3, [r7, #20] + 8001fc2: 4013 ands r3, r2 + 8001fc4: 617b str r3, [r7, #20] tmp |= ((pGPIO_Init->Pull) << (position * GPIO_PUPDR_PUPD1_Pos)); - 8001f42: 683b ldr r3, [r7, #0] - 8001f44: 689a ldr r2, [r3, #8] - 8001f46: 693b ldr r3, [r7, #16] - 8001f48: 005b lsls r3, r3, #1 - 8001f4a: 409a lsls r2, r3 - 8001f4c: 0013 movs r3, r2 - 8001f4e: 697a ldr r2, [r7, #20] - 8001f50: 4313 orrs r3, r2 - 8001f52: 617b str r3, [r7, #20] + 8001fc6: 683b ldr r3, [r7, #0] + 8001fc8: 689a ldr r2, [r3, #8] + 8001fca: 693b ldr r3, [r7, #16] + 8001fcc: 005b lsls r3, r3, #1 + 8001fce: 409a lsls r2, r3 + 8001fd0: 0013 movs r3, r2 + 8001fd2: 697a ldr r2, [r7, #20] + 8001fd4: 4313 orrs r3, r2 + 8001fd6: 617b str r3, [r7, #20] GPIOx->PUPDR = tmp; - 8001f54: 687b ldr r3, [r7, #4] - 8001f56: 697a ldr r2, [r7, #20] - 8001f58: 60da str r2, [r3, #12] + 8001fd8: 687b ldr r3, [r7, #4] + 8001fda: 697a ldr r2, [r7, #20] + 8001fdc: 60da str r2, [r3, #12] } /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((pGPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) - 8001f5a: 683b ldr r3, [r7, #0] - 8001f5c: 685a ldr r2, [r3, #4] - 8001f5e: 2380 movs r3, #128 @ 0x80 - 8001f60: 055b lsls r3, r3, #21 - 8001f62: 4013 ands r3, r2 - 8001f64: d100 bne.n 8001f68 - 8001f66: e098 b.n 800209a + 8001fde: 683b ldr r3, [r7, #0] + 8001fe0: 685a ldr r2, [r3, #4] + 8001fe2: 2380 movs r3, #128 @ 0x80 + 8001fe4: 055b lsls r3, r3, #21 + 8001fe6: 4013 ands r3, r2 + 8001fe8: d100 bne.n 8001fec + 8001fea: e098 b.n 800211e { tmp = EXTI->EXTICR[position >> 2U]; - 8001f68: 4a53 ldr r2, [pc, #332] @ (80020b8 ) - 8001f6a: 693b ldr r3, [r7, #16] - 8001f6c: 089b lsrs r3, r3, #2 - 8001f6e: 3318 adds r3, #24 - 8001f70: 009b lsls r3, r3, #2 - 8001f72: 589b ldr r3, [r3, r2] - 8001f74: 617b str r3, [r7, #20] + 8001fec: 4a53 ldr r2, [pc, #332] @ (800213c ) + 8001fee: 693b ldr r3, [r7, #16] + 8001ff0: 089b lsrs r3, r3, #2 + 8001ff2: 3318 adds r3, #24 + 8001ff4: 009b lsls r3, r3, #2 + 8001ff6: 589b ldr r3, [r3, r2] + 8001ff8: 617b str r3, [r7, #20] tmp &= ~((0x0FUL) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos)); - 8001f76: 693b ldr r3, [r7, #16] - 8001f78: 2203 movs r2, #3 - 8001f7a: 4013 ands r3, r2 - 8001f7c: 00db lsls r3, r3, #3 - 8001f7e: 220f movs r2, #15 - 8001f80: 409a lsls r2, r3 - 8001f82: 0013 movs r3, r2 - 8001f84: 43da mvns r2, r3 - 8001f86: 697b ldr r3, [r7, #20] - 8001f88: 4013 ands r3, r2 - 8001f8a: 617b str r3, [r7, #20] + 8001ffa: 693b ldr r3, [r7, #16] + 8001ffc: 2203 movs r2, #3 + 8001ffe: 4013 ands r3, r2 + 8002000: 00db lsls r3, r3, #3 + 8002002: 220f movs r2, #15 + 8002004: 409a lsls r2, r3 + 8002006: 0013 movs r3, r2 + 8002008: 43da mvns r2, r3 + 800200a: 697b ldr r3, [r7, #20] + 800200c: 4013 ands r3, r2 + 800200e: 617b str r3, [r7, #20] tmp |= (GPIO_GET_INDEX(GPIOx) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos)); - 8001f8c: 687a ldr r2, [r7, #4] - 8001f8e: 23a0 movs r3, #160 @ 0xa0 - 8001f90: 05db lsls r3, r3, #23 - 8001f92: 429a cmp r2, r3 - 8001f94: d019 beq.n 8001fca - 8001f96: 687b ldr r3, [r7, #4] - 8001f98: 4a48 ldr r2, [pc, #288] @ (80020bc ) - 8001f9a: 4293 cmp r3, r2 - 8001f9c: d013 beq.n 8001fc6 - 8001f9e: 687b ldr r3, [r7, #4] - 8001fa0: 4a47 ldr r2, [pc, #284] @ (80020c0 ) - 8001fa2: 4293 cmp r3, r2 - 8001fa4: d00d beq.n 8001fc2 - 8001fa6: 687b ldr r3, [r7, #4] - 8001fa8: 4a46 ldr r2, [pc, #280] @ (80020c4 ) - 8001faa: 4293 cmp r3, r2 - 8001fac: d007 beq.n 8001fbe - 8001fae: 687b ldr r3, [r7, #4] - 8001fb0: 4a45 ldr r2, [pc, #276] @ (80020c8 ) - 8001fb2: 4293 cmp r3, r2 - 8001fb4: d101 bne.n 8001fba - 8001fb6: 2305 movs r3, #5 - 8001fb8: e008 b.n 8001fcc - 8001fba: 2306 movs r3, #6 - 8001fbc: e006 b.n 8001fcc - 8001fbe: 2303 movs r3, #3 - 8001fc0: e004 b.n 8001fcc - 8001fc2: 2302 movs r3, #2 - 8001fc4: e002 b.n 8001fcc - 8001fc6: 2301 movs r3, #1 - 8001fc8: e000 b.n 8001fcc - 8001fca: 2300 movs r3, #0 - 8001fcc: 693a ldr r2, [r7, #16] - 8001fce: 2103 movs r1, #3 - 8001fd0: 400a ands r2, r1 - 8001fd2: 00d2 lsls r2, r2, #3 - 8001fd4: 4093 lsls r3, r2 - 8001fd6: 697a ldr r2, [r7, #20] - 8001fd8: 4313 orrs r3, r2 - 8001fda: 617b str r3, [r7, #20] + 8002010: 687a ldr r2, [r7, #4] + 8002012: 23a0 movs r3, #160 @ 0xa0 + 8002014: 05db lsls r3, r3, #23 + 8002016: 429a cmp r2, r3 + 8002018: d019 beq.n 800204e + 800201a: 687b ldr r3, [r7, #4] + 800201c: 4a48 ldr r2, [pc, #288] @ (8002140 ) + 800201e: 4293 cmp r3, r2 + 8002020: d013 beq.n 800204a + 8002022: 687b ldr r3, [r7, #4] + 8002024: 4a47 ldr r2, [pc, #284] @ (8002144 ) + 8002026: 4293 cmp r3, r2 + 8002028: d00d beq.n 8002046 + 800202a: 687b ldr r3, [r7, #4] + 800202c: 4a46 ldr r2, [pc, #280] @ (8002148 ) + 800202e: 4293 cmp r3, r2 + 8002030: d007 beq.n 8002042 + 8002032: 687b ldr r3, [r7, #4] + 8002034: 4a45 ldr r2, [pc, #276] @ (800214c ) + 8002036: 4293 cmp r3, r2 + 8002038: d101 bne.n 800203e + 800203a: 2305 movs r3, #5 + 800203c: e008 b.n 8002050 + 800203e: 2306 movs r3, #6 + 8002040: e006 b.n 8002050 + 8002042: 2303 movs r3, #3 + 8002044: e004 b.n 8002050 + 8002046: 2302 movs r3, #2 + 8002048: e002 b.n 8002050 + 800204a: 2301 movs r3, #1 + 800204c: e000 b.n 8002050 + 800204e: 2300 movs r3, #0 + 8002050: 693a ldr r2, [r7, #16] + 8002052: 2103 movs r1, #3 + 8002054: 400a ands r2, r1 + 8002056: 00d2 lsls r2, r2, #3 + 8002058: 4093 lsls r3, r2 + 800205a: 697a ldr r2, [r7, #20] + 800205c: 4313 orrs r3, r2 + 800205e: 617b str r3, [r7, #20] EXTI->EXTICR[position >> 2U] = tmp; - 8001fdc: 4936 ldr r1, [pc, #216] @ (80020b8 ) - 8001fde: 693b ldr r3, [r7, #16] - 8001fe0: 089b lsrs r3, r3, #2 - 8001fe2: 3318 adds r3, #24 - 8001fe4: 009b lsls r3, r3, #2 - 8001fe6: 697a ldr r2, [r7, #20] - 8001fe8: 505a str r2, [r3, r1] + 8002060: 4936 ldr r1, [pc, #216] @ (800213c ) + 8002062: 693b ldr r3, [r7, #16] + 8002064: 089b lsrs r3, r3, #2 + 8002066: 3318 adds r3, #24 + 8002068: 009b lsls r3, r3, #2 + 800206a: 697a ldr r2, [r7, #20] + 800206c: 505a str r2, [r3, r1] /* Clear EXTI line configuration */ tmp = EXTI->IMR1; - 8001fea: 4a33 ldr r2, [pc, #204] @ (80020b8 ) - 8001fec: 2380 movs r3, #128 @ 0x80 - 8001fee: 58d3 ldr r3, [r2, r3] - 8001ff0: 617b str r3, [r7, #20] - tmp &= ~((uint32_t)iocurrent); - 8001ff2: 68fb ldr r3, [r7, #12] - 8001ff4: 43da mvns r2, r3 - 8001ff6: 697b ldr r3, [r7, #20] - 8001ff8: 4013 ands r3, r2 - 8001ffa: 617b str r3, [r7, #20] - if ((pGPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) - 8001ffc: 683b ldr r3, [r7, #0] - 8001ffe: 685a ldr r2, [r3, #4] - 8002000: 2380 movs r3, #128 @ 0x80 - 8002002: 025b lsls r3, r3, #9 - 8002004: 4013 ands r3, r2 - 8002006: d003 beq.n 8002010 - { - tmp |= iocurrent; - 8002008: 697a ldr r2, [r7, #20] - 800200a: 68fb ldr r3, [r7, #12] - 800200c: 4313 orrs r3, r2 - 800200e: 617b str r3, [r7, #20] - } - EXTI->IMR1 = tmp; - 8002010: 4929 ldr r1, [pc, #164] @ (80020b8 ) - 8002012: 2280 movs r2, #128 @ 0x80 - 8002014: 697b ldr r3, [r7, #20] - 8002016: 508b str r3, [r1, r2] - - tmp = EXTI->EMR1; - 8002018: 4a27 ldr r2, [pc, #156] @ (80020b8 ) - 800201a: 2384 movs r3, #132 @ 0x84 - 800201c: 58d3 ldr r3, [r2, r3] - 800201e: 617b str r3, [r7, #20] - tmp &= ~((uint32_t)iocurrent); - 8002020: 68fb ldr r3, [r7, #12] - 8002022: 43da mvns r2, r3 - 8002024: 697b ldr r3, [r7, #20] - 8002026: 4013 ands r3, r2 - 8002028: 617b str r3, [r7, #20] - if ((pGPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) - 800202a: 683b ldr r3, [r7, #0] - 800202c: 685a ldr r2, [r3, #4] - 800202e: 2380 movs r3, #128 @ 0x80 - 8002030: 029b lsls r3, r3, #10 - 8002032: 4013 ands r3, r2 - 8002034: d003 beq.n 800203e - { - tmp |= iocurrent; - 8002036: 697a ldr r2, [r7, #20] - 8002038: 68fb ldr r3, [r7, #12] - 800203a: 4313 orrs r3, r2 - 800203c: 617b str r3, [r7, #20] - } - EXTI->EMR1 = tmp; - 800203e: 491e ldr r1, [pc, #120] @ (80020b8 ) - 8002040: 2284 movs r2, #132 @ 0x84 - 8002042: 697b ldr r3, [r7, #20] - 8002044: 508b str r3, [r1, r2] - - /* Clear Rising Falling edge configuration */ - tmp = EXTI->RTSR1; - 8002046: 4b1c ldr r3, [pc, #112] @ (80020b8 ) - 8002048: 681b ldr r3, [r3, #0] - 800204a: 617b str r3, [r7, #20] - tmp &= ~((uint32_t)iocurrent); - 800204c: 68fb ldr r3, [r7, #12] - 800204e: 43da mvns r2, r3 - 8002050: 697b ldr r3, [r7, #20] - 8002052: 4013 ands r3, r2 - 8002054: 617b str r3, [r7, #20] - if ((pGPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) - 8002056: 683b ldr r3, [r7, #0] - 8002058: 685a ldr r2, [r3, #4] - 800205a: 2380 movs r3, #128 @ 0x80 - 800205c: 035b lsls r3, r3, #13 - 800205e: 4013 ands r3, r2 - 8002060: d003 beq.n 800206a - { - tmp |= iocurrent; - 8002062: 697a ldr r2, [r7, #20] - 8002064: 68fb ldr r3, [r7, #12] - 8002066: 4313 orrs r3, r2 - 8002068: 617b str r3, [r7, #20] - } - EXTI->RTSR1 = tmp; - 800206a: 4b13 ldr r3, [pc, #76] @ (80020b8 ) - 800206c: 697a ldr r2, [r7, #20] - 800206e: 601a str r2, [r3, #0] - - tmp = EXTI->FTSR1; - 8002070: 4b11 ldr r3, [pc, #68] @ (80020b8 ) - 8002072: 685b ldr r3, [r3, #4] + 800206e: 4a33 ldr r2, [pc, #204] @ (800213c ) + 8002070: 2380 movs r3, #128 @ 0x80 + 8002072: 58d3 ldr r3, [r2, r3] 8002074: 617b str r3, [r7, #20] tmp &= ~((uint32_t)iocurrent); 8002076: 68fb ldr r3, [r7, #12] @@ -5694,7657 +5700,7645 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init) 800207a: 697b ldr r3, [r7, #20] 800207c: 4013 ands r3, r2 800207e: 617b str r3, [r7, #20] - if ((pGPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) + if ((pGPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 8002080: 683b ldr r3, [r7, #0] 8002082: 685a ldr r2, [r3, #4] 8002084: 2380 movs r3, #128 @ 0x80 - 8002086: 039b lsls r3, r3, #14 + 8002086: 025b lsls r3, r3, #9 8002088: 4013 ands r3, r2 - 800208a: d003 beq.n 8002094 + 800208a: d003 beq.n 8002094 { tmp |= iocurrent; 800208c: 697a ldr r2, [r7, #20] 800208e: 68fb ldr r3, [r7, #12] 8002090: 4313 orrs r3, r2 8002092: 617b str r3, [r7, #20] + } + EXTI->IMR1 = tmp; + 8002094: 4929 ldr r1, [pc, #164] @ (800213c ) + 8002096: 2280 movs r2, #128 @ 0x80 + 8002098: 697b ldr r3, [r7, #20] + 800209a: 508b str r3, [r1, r2] + + tmp = EXTI->EMR1; + 800209c: 4a27 ldr r2, [pc, #156] @ (800213c ) + 800209e: 2384 movs r3, #132 @ 0x84 + 80020a0: 58d3 ldr r3, [r2, r3] + 80020a2: 617b str r3, [r7, #20] + tmp &= ~((uint32_t)iocurrent); + 80020a4: 68fb ldr r3, [r7, #12] + 80020a6: 43da mvns r2, r3 + 80020a8: 697b ldr r3, [r7, #20] + 80020aa: 4013 ands r3, r2 + 80020ac: 617b str r3, [r7, #20] + if ((pGPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) + 80020ae: 683b ldr r3, [r7, #0] + 80020b0: 685a ldr r2, [r3, #4] + 80020b2: 2380 movs r3, #128 @ 0x80 + 80020b4: 029b lsls r3, r3, #10 + 80020b6: 4013 ands r3, r2 + 80020b8: d003 beq.n 80020c2 + { + tmp |= iocurrent; + 80020ba: 697a ldr r2, [r7, #20] + 80020bc: 68fb ldr r3, [r7, #12] + 80020be: 4313 orrs r3, r2 + 80020c0: 617b str r3, [r7, #20] + } + EXTI->EMR1 = tmp; + 80020c2: 491e ldr r1, [pc, #120] @ (800213c ) + 80020c4: 2284 movs r2, #132 @ 0x84 + 80020c6: 697b ldr r3, [r7, #20] + 80020c8: 508b str r3, [r1, r2] + + /* Clear Rising Falling edge configuration */ + tmp = EXTI->RTSR1; + 80020ca: 4b1c ldr r3, [pc, #112] @ (800213c ) + 80020cc: 681b ldr r3, [r3, #0] + 80020ce: 617b str r3, [r7, #20] + tmp &= ~((uint32_t)iocurrent); + 80020d0: 68fb ldr r3, [r7, #12] + 80020d2: 43da mvns r2, r3 + 80020d4: 697b ldr r3, [r7, #20] + 80020d6: 4013 ands r3, r2 + 80020d8: 617b str r3, [r7, #20] + if ((pGPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) + 80020da: 683b ldr r3, [r7, #0] + 80020dc: 685a ldr r2, [r3, #4] + 80020de: 2380 movs r3, #128 @ 0x80 + 80020e0: 035b lsls r3, r3, #13 + 80020e2: 4013 ands r3, r2 + 80020e4: d003 beq.n 80020ee + { + tmp |= iocurrent; + 80020e6: 697a ldr r2, [r7, #20] + 80020e8: 68fb ldr r3, [r7, #12] + 80020ea: 4313 orrs r3, r2 + 80020ec: 617b str r3, [r7, #20] + } + EXTI->RTSR1 = tmp; + 80020ee: 4b13 ldr r3, [pc, #76] @ (800213c ) + 80020f0: 697a ldr r2, [r7, #20] + 80020f2: 601a str r2, [r3, #0] + + tmp = EXTI->FTSR1; + 80020f4: 4b11 ldr r3, [pc, #68] @ (800213c ) + 80020f6: 685b ldr r3, [r3, #4] + 80020f8: 617b str r3, [r7, #20] + tmp &= ~((uint32_t)iocurrent); + 80020fa: 68fb ldr r3, [r7, #12] + 80020fc: 43da mvns r2, r3 + 80020fe: 697b ldr r3, [r7, #20] + 8002100: 4013 ands r3, r2 + 8002102: 617b str r3, [r7, #20] + if ((pGPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) + 8002104: 683b ldr r3, [r7, #0] + 8002106: 685a ldr r2, [r3, #4] + 8002108: 2380 movs r3, #128 @ 0x80 + 800210a: 039b lsls r3, r3, #14 + 800210c: 4013 ands r3, r2 + 800210e: d003 beq.n 8002118 + { + tmp |= iocurrent; + 8002110: 697a ldr r2, [r7, #20] + 8002112: 68fb ldr r3, [r7, #12] + 8002114: 4313 orrs r3, r2 + 8002116: 617b str r3, [r7, #20] } EXTI->FTSR1 = tmp; - 8002094: 4b08 ldr r3, [pc, #32] @ (80020b8 ) - 8002096: 697a ldr r2, [r7, #20] - 8002098: 605a str r2, [r3, #4] + 8002118: 4b08 ldr r3, [pc, #32] @ (800213c ) + 800211a: 697a ldr r2, [r7, #20] + 800211c: 605a str r2, [r3, #4] } } position++; - 800209a: 693b ldr r3, [r7, #16] - 800209c: 3301 adds r3, #1 - 800209e: 613b str r3, [r7, #16] + 800211e: 693b ldr r3, [r7, #16] + 8002120: 3301 adds r3, #1 + 8002122: 613b str r3, [r7, #16] while (((pGPIO_Init->Pin) >> position) != 0U) - 80020a0: 683b ldr r3, [r7, #0] - 80020a2: 681a ldr r2, [r3, #0] - 80020a4: 693b ldr r3, [r7, #16] - 80020a6: 40da lsrs r2, r3 - 80020a8: 1e13 subs r3, r2, #0 - 80020aa: d000 beq.n 80020ae - 80020ac: e6a4 b.n 8001df8 + 8002124: 683b ldr r3, [r7, #0] + 8002126: 681a ldr r2, [r3, #0] + 8002128: 693b ldr r3, [r7, #16] + 800212a: 40da lsrs r2, r3 + 800212c: 1e13 subs r3, r2, #0 + 800212e: d000 beq.n 8002132 + 8002130: e6a4 b.n 8001e7c } } - 80020ae: 46c0 nop @ (mov r8, r8) - 80020b0: 46c0 nop @ (mov r8, r8) - 80020b2: 46bd mov sp, r7 - 80020b4: b006 add sp, #24 - 80020b6: bd80 pop {r7, pc} - 80020b8: 40021800 .word 0x40021800 - 80020bc: 50000400 .word 0x50000400 - 80020c0: 50000800 .word 0x50000800 - 80020c4: 50000c00 .word 0x50000c00 - 80020c8: 50001400 .word 0x50001400 + 8002132: 46c0 nop @ (mov r8, r8) + 8002134: 46c0 nop @ (mov r8, r8) + 8002136: 46bd mov sp, r7 + 8002138: b006 add sp, #24 + 800213a: bd80 pop {r7, pc} + 800213c: 40021800 .word 0x40021800 + 8002140: 50000400 .word 0x50000400 + 8002144: 50000800 .word 0x50000800 + 8002148: 50000c00 .word 0x50000c00 + 800214c: 50001400 .word 0x50001400 -080020cc : +08002150 : * @param GPIO_Pin specifies the port bit to read. * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { - 80020cc: b580 push {r7, lr} - 80020ce: b084 sub sp, #16 - 80020d0: af00 add r7, sp, #0 - 80020d2: 6078 str r0, [r7, #4] - 80020d4: 000a movs r2, r1 - 80020d6: 1cbb adds r3, r7, #2 - 80020d8: 801a strh r2, [r3, #0] + 8002150: b580 push {r7, lr} + 8002152: b084 sub sp, #16 + 8002154: af00 add r7, sp, #0 + 8002156: 6078 str r0, [r7, #4] + 8002158: 000a movs r2, r1 + 800215a: 1cbb adds r3, r7, #2 + 800215c: 801a strh r2, [r3, #0] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != 0U) - 80020da: 687b ldr r3, [r7, #4] - 80020dc: 691b ldr r3, [r3, #16] - 80020de: 1cba adds r2, r7, #2 - 80020e0: 8812 ldrh r2, [r2, #0] - 80020e2: 4013 ands r3, r2 - 80020e4: d004 beq.n 80020f0 + 800215e: 687b ldr r3, [r7, #4] + 8002160: 691b ldr r3, [r3, #16] + 8002162: 1cba adds r2, r7, #2 + 8002164: 8812 ldrh r2, [r2, #0] + 8002166: 4013 ands r3, r2 + 8002168: d004 beq.n 8002174 { bitstatus = GPIO_PIN_SET; - 80020e6: 230f movs r3, #15 - 80020e8: 18fb adds r3, r7, r3 - 80020ea: 2201 movs r2, #1 - 80020ec: 701a strb r2, [r3, #0] - 80020ee: e003 b.n 80020f8 + 800216a: 230f movs r3, #15 + 800216c: 18fb adds r3, r7, r3 + 800216e: 2201 movs r2, #1 + 8002170: 701a strb r2, [r3, #0] + 8002172: e003 b.n 800217c } else { bitstatus = GPIO_PIN_RESET; - 80020f0: 230f movs r3, #15 - 80020f2: 18fb adds r3, r7, r3 - 80020f4: 2200 movs r2, #0 - 80020f6: 701a strb r2, [r3, #0] + 8002174: 230f movs r3, #15 + 8002176: 18fb adds r3, r7, r3 + 8002178: 2200 movs r2, #0 + 800217a: 701a strb r2, [r3, #0] } return bitstatus; - 80020f8: 230f movs r3, #15 - 80020fa: 18fb adds r3, r7, r3 - 80020fc: 781b ldrb r3, [r3, #0] + 800217c: 230f movs r3, #15 + 800217e: 18fb adds r3, r7, r3 + 8002180: 781b ldrb r3, [r3, #0] } - 80020fe: 0018 movs r0, r3 - 8002100: 46bd mov sp, r7 - 8002102: b004 add sp, #16 - 8002104: bd80 pop {r7, pc} + 8002182: 0018 movs r0, r3 + 8002184: 46bd mov sp, r7 + 8002186: b004 add sp, #16 + 8002188: bd80 pop {r7, pc} -08002106 : +0800218a : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { - 8002106: b580 push {r7, lr} - 8002108: b082 sub sp, #8 - 800210a: af00 add r7, sp, #0 - 800210c: 6078 str r0, [r7, #4] - 800210e: 0008 movs r0, r1 - 8002110: 0011 movs r1, r2 - 8002112: 1cbb adds r3, r7, #2 - 8002114: 1c02 adds r2, r0, #0 - 8002116: 801a strh r2, [r3, #0] - 8002118: 1c7b adds r3, r7, #1 - 800211a: 1c0a adds r2, r1, #0 - 800211c: 701a strb r2, [r3, #0] + 800218a: b580 push {r7, lr} + 800218c: b082 sub sp, #8 + 800218e: af00 add r7, sp, #0 + 8002190: 6078 str r0, [r7, #4] + 8002192: 0008 movs r0, r1 + 8002194: 0011 movs r1, r2 + 8002196: 1cbb adds r3, r7, #2 + 8002198: 1c02 adds r2, r0, #0 + 800219a: 801a strh r2, [r3, #0] + 800219c: 1c7b adds r3, r7, #1 + 800219e: 1c0a adds r2, r1, #0 + 80021a0: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) - 800211e: 1c7b adds r3, r7, #1 - 8002120: 781b ldrb r3, [r3, #0] - 8002122: 2b00 cmp r3, #0 - 8002124: d004 beq.n 8002130 + 80021a2: 1c7b adds r3, r7, #1 + 80021a4: 781b ldrb r3, [r3, #0] + 80021a6: 2b00 cmp r3, #0 + 80021a8: d004 beq.n 80021b4 { GPIOx->BSRR = (uint32_t)GPIO_Pin; - 8002126: 1cbb adds r3, r7, #2 - 8002128: 881a ldrh r2, [r3, #0] - 800212a: 687b ldr r3, [r7, #4] - 800212c: 619a str r2, [r3, #24] + 80021aa: 1cbb adds r3, r7, #2 + 80021ac: 881a ldrh r2, [r3, #0] + 80021ae: 687b ldr r3, [r7, #4] + 80021b0: 619a str r2, [r3, #24] } else { GPIOx->BRR = (uint32_t)GPIO_Pin; } } - 800212e: e003 b.n 8002138 + 80021b2: e003 b.n 80021bc GPIOx->BRR = (uint32_t)GPIO_Pin; - 8002130: 1cbb adds r3, r7, #2 - 8002132: 881a ldrh r2, [r3, #0] - 8002134: 687b ldr r3, [r7, #4] - 8002136: 629a str r2, [r3, #40] @ 0x28 + 80021b4: 1cbb adds r3, r7, #2 + 80021b6: 881a ldrh r2, [r3, #0] + 80021b8: 687b ldr r3, [r7, #4] + 80021ba: 629a str r2, [r3, #40] @ 0x28 } - 8002138: 46c0 nop @ (mov r8, r8) - 800213a: 46bd mov sp, r7 - 800213c: b002 add sp, #8 - 800213e: bd80 pop {r7, pc} + 80021bc: 46c0 nop @ (mov r8, r8) + 80021be: 46bd mov sp, r7 + 80021c0: b002 add sp, #8 + 80021c2: bd80 pop {r7, pc} -08002140 : +080021c4 : * @brief Handle EXTI interrupt request. * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) { - 8002140: b580 push {r7, lr} - 8002142: b082 sub sp, #8 - 8002144: af00 add r7, sp, #0 - 8002146: 0002 movs r2, r0 - 8002148: 1dbb adds r3, r7, #6 - 800214a: 801a strh r2, [r3, #0] + 80021c4: b580 push {r7, lr} + 80021c6: b082 sub sp, #8 + 80021c8: af00 add r7, sp, #0 + 80021ca: 0002 movs r2, r0 + 80021cc: 1dbb adds r3, r7, #6 + 80021ce: 801a strh r2, [r3, #0] /* EXTI line interrupt detected */ if (__HAL_GPIO_EXTI_GET_RISING_IT(GPIO_Pin) != 0U) - 800214c: 4b10 ldr r3, [pc, #64] @ (8002190 ) - 800214e: 68db ldr r3, [r3, #12] - 8002150: 1dba adds r2, r7, #6 - 8002152: 8812 ldrh r2, [r2, #0] - 8002154: 4013 ands r3, r2 - 8002156: d008 beq.n 800216a + 80021d0: 4b10 ldr r3, [pc, #64] @ (8002214 ) + 80021d2: 68db ldr r3, [r3, #12] + 80021d4: 1dba adds r2, r7, #6 + 80021d6: 8812 ldrh r2, [r2, #0] + 80021d8: 4013 ands r3, r2 + 80021da: d008 beq.n 80021ee { __HAL_GPIO_EXTI_CLEAR_RISING_IT(GPIO_Pin); - 8002158: 4b0d ldr r3, [pc, #52] @ (8002190 ) - 800215a: 1dba adds r2, r7, #6 - 800215c: 8812 ldrh r2, [r2, #0] - 800215e: 60da str r2, [r3, #12] + 80021dc: 4b0d ldr r3, [pc, #52] @ (8002214 ) + 80021de: 1dba adds r2, r7, #6 + 80021e0: 8812 ldrh r2, [r2, #0] + 80021e2: 60da str r2, [r3, #12] HAL_GPIO_EXTI_Rising_Callback(GPIO_Pin); - 8002160: 1dbb adds r3, r7, #6 - 8002162: 881b ldrh r3, [r3, #0] - 8002164: 0018 movs r0, r3 - 8002166: f000 f815 bl 8002194 + 80021e4: 1dbb adds r3, r7, #6 + 80021e6: 881b ldrh r3, [r3, #0] + 80021e8: 0018 movs r0, r3 + 80021ea: f000 f815 bl 8002218 } if (__HAL_GPIO_EXTI_GET_FALLING_IT(GPIO_Pin) != 0U) - 800216a: 4b09 ldr r3, [pc, #36] @ (8002190 ) - 800216c: 691b ldr r3, [r3, #16] - 800216e: 1dba adds r2, r7, #6 - 8002170: 8812 ldrh r2, [r2, #0] - 8002172: 4013 ands r3, r2 - 8002174: d008 beq.n 8002188 + 80021ee: 4b09 ldr r3, [pc, #36] @ (8002214 ) + 80021f0: 691b ldr r3, [r3, #16] + 80021f2: 1dba adds r2, r7, #6 + 80021f4: 8812 ldrh r2, [r2, #0] + 80021f6: 4013 ands r3, r2 + 80021f8: d008 beq.n 800220c { __HAL_GPIO_EXTI_CLEAR_FALLING_IT(GPIO_Pin); - 8002176: 4b06 ldr r3, [pc, #24] @ (8002190 ) - 8002178: 1dba adds r2, r7, #6 - 800217a: 8812 ldrh r2, [r2, #0] - 800217c: 611a str r2, [r3, #16] + 80021fa: 4b06 ldr r3, [pc, #24] @ (8002214 ) + 80021fc: 1dba adds r2, r7, #6 + 80021fe: 8812 ldrh r2, [r2, #0] + 8002200: 611a str r2, [r3, #16] HAL_GPIO_EXTI_Falling_Callback(GPIO_Pin); - 800217e: 1dbb adds r3, r7, #6 - 8002180: 881b ldrh r3, [r3, #0] - 8002182: 0018 movs r0, r3 - 8002184: f000 f810 bl 80021a8 + 8002202: 1dbb adds r3, r7, #6 + 8002204: 881b ldrh r3, [r3, #0] + 8002206: 0018 movs r0, r3 + 8002208: f000 f810 bl 800222c } } - 8002188: 46c0 nop @ (mov r8, r8) - 800218a: 46bd mov sp, r7 - 800218c: b002 add sp, #8 - 800218e: bd80 pop {r7, pc} - 8002190: 40021800 .word 0x40021800 + 800220c: 46c0 nop @ (mov r8, r8) + 800220e: 46bd mov sp, r7 + 8002210: b002 add sp, #8 + 8002212: bd80 pop {r7, pc} + 8002214: 40021800 .word 0x40021800 -08002194 : +08002218 : * @brief EXTI line detection callback. * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. * @retval None */ __weak void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin) { - 8002194: b580 push {r7, lr} - 8002196: b082 sub sp, #8 - 8002198: af00 add r7, sp, #0 - 800219a: 0002 movs r2, r0 - 800219c: 1dbb adds r3, r7, #6 - 800219e: 801a strh r2, [r3, #0] + 8002218: b580 push {r7, lr} + 800221a: b082 sub sp, #8 + 800221c: af00 add r7, sp, #0 + 800221e: 0002 movs r2, r0 + 8002220: 1dbb adds r3, r7, #6 + 8002222: 801a strh r2, [r3, #0] UNUSED(GPIO_Pin); /* NOTE: This function should not be modified, when the callback is needed, the HAL_GPIO_EXTI_Rising_Callback could be implemented in the user file */ } - 80021a0: 46c0 nop @ (mov r8, r8) - 80021a2: 46bd mov sp, r7 - 80021a4: b002 add sp, #8 - 80021a6: bd80 pop {r7, pc} + 8002224: 46c0 nop @ (mov r8, r8) + 8002226: 46bd mov sp, r7 + 8002228: b002 add sp, #8 + 800222a: bd80 pop {r7, pc} -080021a8 : +0800222c : * @brief EXTI line detection callback. * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. * @retval None */ __weak void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin) { - 80021a8: b580 push {r7, lr} - 80021aa: b082 sub sp, #8 - 80021ac: af00 add r7, sp, #0 - 80021ae: 0002 movs r2, r0 - 80021b0: 1dbb adds r3, r7, #6 - 80021b2: 801a strh r2, [r3, #0] + 800222c: b580 push {r7, lr} + 800222e: b082 sub sp, #8 + 8002230: af00 add r7, sp, #0 + 8002232: 0002 movs r2, r0 + 8002234: 1dbb adds r3, r7, #6 + 8002236: 801a strh r2, [r3, #0] UNUSED(GPIO_Pin); /* NOTE: This function should not be modified, when the callback is needed, the HAL_GPIO_EXTI_Falling_Callback could be implemented in the user file */ } - 80021b4: 46c0 nop @ (mov r8, r8) - 80021b6: 46bd mov sp, r7 - 80021b8: b002 add sp, #8 - 80021ba: bd80 pop {r7, pc} + 8002238: 46c0 nop @ (mov r8, r8) + 800223a: 46bd mov sp, r7 + 800223c: b002 add sp, #8 + 800223e: bd80 pop {r7, pc} -080021bc : +08002240 : must adjust the number of CPU wait states in their application (SystemClock_Config() API) before calling the HAL_RCC_OscConfig() API to update the HSI48 clock division factor. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct) { - 80021bc: b580 push {r7, lr} - 80021be: b086 sub sp, #24 - 80021c0: af00 add r7, sp, #0 - 80021c2: 6078 str r0, [r7, #4] + 8002240: b580 push {r7, lr} + 8002242: b086 sub sp, #24 + 8002244: af00 add r7, sp, #0 + 8002246: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t temp_sysclksrc; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) - 80021c4: 687b ldr r3, [r7, #4] - 80021c6: 2b00 cmp r3, #0 - 80021c8: d101 bne.n 80021ce + 8002248: 687b ldr r3, [r7, #4] + 800224a: 2b00 cmp r3, #0 + 800224c: d101 bne.n 8002252 { return HAL_ERROR; - 80021ca: 2301 movs r3, #1 - 80021cc: e1d0 b.n 8002570 + 800224e: 2301 movs r3, #1 + 8002250: e1d0 b.n 80025f4 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) - 80021ce: 687b ldr r3, [r7, #4] - 80021d0: 681b ldr r3, [r3, #0] - 80021d2: 2201 movs r2, #1 - 80021d4: 4013 ands r3, r2 - 80021d6: d100 bne.n 80021da - 80021d8: e069 b.n 80022ae + 8002252: 687b ldr r3, [r7, #4] + 8002254: 681b ldr r3, [r3, #0] + 8002256: 2201 movs r2, #1 + 8002258: 4013 ands r3, r2 + 800225a: d100 bne.n 800225e + 800225c: e069 b.n 8002332 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); - 80021da: 4bc8 ldr r3, [pc, #800] @ (80024fc ) - 80021dc: 689b ldr r3, [r3, #8] - 80021de: 2238 movs r2, #56 @ 0x38 - 80021e0: 4013 ands r3, r2 - 80021e2: 617b str r3, [r7, #20] + 800225e: 4bc8 ldr r3, [pc, #800] @ (8002580 ) + 8002260: 689b ldr r3, [r3, #8] + 8002262: 2238 movs r2, #56 @ 0x38 + 8002264: 4013 ands r3, r2 + 8002266: 617b str r3, [r7, #20] /* When the HSE is used as system clock in these cases it is not allowed to be disabled */ if (temp_sysclksrc == RCC_CFGR_SWS_HSE) - 80021e4: 697b ldr r3, [r7, #20] - 80021e6: 2b08 cmp r3, #8 - 80021e8: d105 bne.n 80021f6 + 8002268: 697b ldr r3, [r7, #20] + 800226a: 2b08 cmp r3, #8 + 800226c: d105 bne.n 800227a { if (RCC_OscInitStruct->HSEState == RCC_HSE_OFF) - 80021ea: 687b ldr r3, [r7, #4] - 80021ec: 685b ldr r3, [r3, #4] - 80021ee: 2b00 cmp r3, #0 - 80021f0: d15d bne.n 80022ae + 800226e: 687b ldr r3, [r7, #4] + 8002270: 685b ldr r3, [r3, #4] + 8002272: 2b00 cmp r3, #0 + 8002274: d15d bne.n 8002332 { return HAL_ERROR; - 80021f2: 2301 movs r3, #1 - 80021f4: e1bc b.n 8002570 + 8002276: 2301 movs r3, #1 + 8002278: e1bc b.n 80025f4 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); - 80021f6: 687b ldr r3, [r7, #4] - 80021f8: 685a ldr r2, [r3, #4] - 80021fa: 2380 movs r3, #128 @ 0x80 - 80021fc: 025b lsls r3, r3, #9 - 80021fe: 429a cmp r2, r3 - 8002200: d107 bne.n 8002212 - 8002202: 4bbe ldr r3, [pc, #760] @ (80024fc ) - 8002204: 681a ldr r2, [r3, #0] - 8002206: 4bbd ldr r3, [pc, #756] @ (80024fc ) - 8002208: 2180 movs r1, #128 @ 0x80 - 800220a: 0249 lsls r1, r1, #9 - 800220c: 430a orrs r2, r1 - 800220e: 601a str r2, [r3, #0] - 8002210: e020 b.n 8002254 - 8002212: 687b ldr r3, [r7, #4] - 8002214: 685a ldr r2, [r3, #4] - 8002216: 23a0 movs r3, #160 @ 0xa0 - 8002218: 02db lsls r3, r3, #11 - 800221a: 429a cmp r2, r3 - 800221c: d10e bne.n 800223c - 800221e: 4bb7 ldr r3, [pc, #732] @ (80024fc ) - 8002220: 681a ldr r2, [r3, #0] - 8002222: 4bb6 ldr r3, [pc, #728] @ (80024fc ) - 8002224: 2180 movs r1, #128 @ 0x80 - 8002226: 02c9 lsls r1, r1, #11 - 8002228: 430a orrs r2, r1 - 800222a: 601a str r2, [r3, #0] - 800222c: 4bb3 ldr r3, [pc, #716] @ (80024fc ) - 800222e: 681a ldr r2, [r3, #0] - 8002230: 4bb2 ldr r3, [pc, #712] @ (80024fc ) - 8002232: 2180 movs r1, #128 @ 0x80 - 8002234: 0249 lsls r1, r1, #9 - 8002236: 430a orrs r2, r1 - 8002238: 601a str r2, [r3, #0] - 800223a: e00b b.n 8002254 - 800223c: 4baf ldr r3, [pc, #700] @ (80024fc ) - 800223e: 681a ldr r2, [r3, #0] - 8002240: 4bae ldr r3, [pc, #696] @ (80024fc ) - 8002242: 49af ldr r1, [pc, #700] @ (8002500 ) - 8002244: 400a ands r2, r1 - 8002246: 601a str r2, [r3, #0] - 8002248: 4bac ldr r3, [pc, #688] @ (80024fc ) - 800224a: 681a ldr r2, [r3, #0] - 800224c: 4bab ldr r3, [pc, #684] @ (80024fc ) - 800224e: 49ad ldr r1, [pc, #692] @ (8002504 ) - 8002250: 400a ands r2, r1 - 8002252: 601a str r2, [r3, #0] + 800227a: 687b ldr r3, [r7, #4] + 800227c: 685a ldr r2, [r3, #4] + 800227e: 2380 movs r3, #128 @ 0x80 + 8002280: 025b lsls r3, r3, #9 + 8002282: 429a cmp r2, r3 + 8002284: d107 bne.n 8002296 + 8002286: 4bbe ldr r3, [pc, #760] @ (8002580 ) + 8002288: 681a ldr r2, [r3, #0] + 800228a: 4bbd ldr r3, [pc, #756] @ (8002580 ) + 800228c: 2180 movs r1, #128 @ 0x80 + 800228e: 0249 lsls r1, r1, #9 + 8002290: 430a orrs r2, r1 + 8002292: 601a str r2, [r3, #0] + 8002294: e020 b.n 80022d8 + 8002296: 687b ldr r3, [r7, #4] + 8002298: 685a ldr r2, [r3, #4] + 800229a: 23a0 movs r3, #160 @ 0xa0 + 800229c: 02db lsls r3, r3, #11 + 800229e: 429a cmp r2, r3 + 80022a0: d10e bne.n 80022c0 + 80022a2: 4bb7 ldr r3, [pc, #732] @ (8002580 ) + 80022a4: 681a ldr r2, [r3, #0] + 80022a6: 4bb6 ldr r3, [pc, #728] @ (8002580 ) + 80022a8: 2180 movs r1, #128 @ 0x80 + 80022aa: 02c9 lsls r1, r1, #11 + 80022ac: 430a orrs r2, r1 + 80022ae: 601a str r2, [r3, #0] + 80022b0: 4bb3 ldr r3, [pc, #716] @ (8002580 ) + 80022b2: 681a ldr r2, [r3, #0] + 80022b4: 4bb2 ldr r3, [pc, #712] @ (8002580 ) + 80022b6: 2180 movs r1, #128 @ 0x80 + 80022b8: 0249 lsls r1, r1, #9 + 80022ba: 430a orrs r2, r1 + 80022bc: 601a str r2, [r3, #0] + 80022be: e00b b.n 80022d8 + 80022c0: 4baf ldr r3, [pc, #700] @ (8002580 ) + 80022c2: 681a ldr r2, [r3, #0] + 80022c4: 4bae ldr r3, [pc, #696] @ (8002580 ) + 80022c6: 49af ldr r1, [pc, #700] @ (8002584 ) + 80022c8: 400a ands r2, r1 + 80022ca: 601a str r2, [r3, #0] + 80022cc: 4bac ldr r3, [pc, #688] @ (8002580 ) + 80022ce: 681a ldr r2, [r3, #0] + 80022d0: 4bab ldr r3, [pc, #684] @ (8002580 ) + 80022d2: 49ad ldr r1, [pc, #692] @ (8002588 ) + 80022d4: 400a ands r2, r1 + 80022d6: 601a str r2, [r3, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) - 8002254: 687b ldr r3, [r7, #4] - 8002256: 685b ldr r3, [r3, #4] - 8002258: 2b00 cmp r3, #0 - 800225a: d014 beq.n 8002286 + 80022d8: 687b ldr r3, [r7, #4] + 80022da: 685b ldr r3, [r3, #4] + 80022dc: 2b00 cmp r3, #0 + 80022de: d014 beq.n 800230a { /* Get Start Tick*/ tickstart = HAL_GetTick(); - 800225c: f7ff fa6a bl 8001734 - 8002260: 0003 movs r3, r0 - 8002262: 613b str r3, [r7, #16] + 80022e0: f7ff fa6a bl 80017b8 + 80022e4: 0003 movs r3, r0 + 80022e6: 613b str r3, [r7, #16] /* Wait till HSE is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) - 8002264: e008 b.n 8002278 + 80022e8: e008 b.n 80022fc { if ((HAL_GetTick() - tickstart) > RCC_HSE_TIMEOUT_VALUE) - 8002266: f7ff fa65 bl 8001734 - 800226a: 0002 movs r2, r0 - 800226c: 693b ldr r3, [r7, #16] - 800226e: 1ad3 subs r3, r2, r3 - 8002270: 2b64 cmp r3, #100 @ 0x64 - 8002272: d901 bls.n 8002278 + 80022ea: f7ff fa65 bl 80017b8 + 80022ee: 0002 movs r2, r0 + 80022f0: 693b ldr r3, [r7, #16] + 80022f2: 1ad3 subs r3, r2, r3 + 80022f4: 2b64 cmp r3, #100 @ 0x64 + 80022f6: d901 bls.n 80022fc { return HAL_TIMEOUT; - 8002274: 2303 movs r3, #3 - 8002276: e17b b.n 8002570 + 80022f8: 2303 movs r3, #3 + 80022fa: e17b b.n 80025f4 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) - 8002278: 4ba0 ldr r3, [pc, #640] @ (80024fc ) - 800227a: 681a ldr r2, [r3, #0] - 800227c: 2380 movs r3, #128 @ 0x80 - 800227e: 029b lsls r3, r3, #10 - 8002280: 4013 ands r3, r2 - 8002282: d0f0 beq.n 8002266 - 8002284: e013 b.n 80022ae + 80022fc: 4ba0 ldr r3, [pc, #640] @ (8002580 ) + 80022fe: 681a ldr r2, [r3, #0] + 8002300: 2380 movs r3, #128 @ 0x80 + 8002302: 029b lsls r3, r3, #10 + 8002304: 4013 ands r3, r2 + 8002306: d0f0 beq.n 80022ea + 8002308: e013 b.n 8002332 } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8002286: f7ff fa55 bl 8001734 - 800228a: 0003 movs r3, r0 - 800228c: 613b str r3, [r7, #16] + 800230a: f7ff fa55 bl 80017b8 + 800230e: 0003 movs r3, r0 + 8002310: 613b str r3, [r7, #16] /* Wait till HSE is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) - 800228e: e008 b.n 80022a2 + 8002312: e008 b.n 8002326 { if ((HAL_GetTick() - tickstart) > RCC_HSE_TIMEOUT_VALUE) - 8002290: f7ff fa50 bl 8001734 - 8002294: 0002 movs r2, r0 - 8002296: 693b ldr r3, [r7, #16] - 8002298: 1ad3 subs r3, r2, r3 - 800229a: 2b64 cmp r3, #100 @ 0x64 - 800229c: d901 bls.n 80022a2 + 8002314: f7ff fa50 bl 80017b8 + 8002318: 0002 movs r2, r0 + 800231a: 693b ldr r3, [r7, #16] + 800231c: 1ad3 subs r3, r2, r3 + 800231e: 2b64 cmp r3, #100 @ 0x64 + 8002320: d901 bls.n 8002326 { return HAL_TIMEOUT; - 800229e: 2303 movs r3, #3 - 80022a0: e166 b.n 8002570 + 8002322: 2303 movs r3, #3 + 8002324: e166 b.n 80025f4 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) - 80022a2: 4b96 ldr r3, [pc, #600] @ (80024fc ) - 80022a4: 681a ldr r2, [r3, #0] - 80022a6: 2380 movs r3, #128 @ 0x80 - 80022a8: 029b lsls r3, r3, #10 - 80022aa: 4013 ands r3, r2 - 80022ac: d1f0 bne.n 8002290 + 8002326: 4b96 ldr r3, [pc, #600] @ (8002580 ) + 8002328: 681a ldr r2, [r3, #0] + 800232a: 2380 movs r3, #128 @ 0x80 + 800232c: 029b lsls r3, r3, #10 + 800232e: 4013 ands r3, r2 + 8002330: d1f0 bne.n 8002314 } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) - 80022ae: 687b ldr r3, [r7, #4] - 80022b0: 681b ldr r3, [r3, #0] - 80022b2: 2202 movs r2, #2 - 80022b4: 4013 ands r3, r2 - 80022b6: d100 bne.n 80022ba - 80022b8: e086 b.n 80023c8 + 8002332: 687b ldr r3, [r7, #4] + 8002334: 681b ldr r3, [r3, #0] + 8002336: 2202 movs r2, #2 + 8002338: 4013 ands r3, r2 + 800233a: d100 bne.n 800233e + 800233c: e086 b.n 800244c assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); assert_param(IS_RCC_HSIDIV(RCC_OscInitStruct->HSIDiv)); /* Check if HSI48 is used as system clock */ temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); - 80022ba: 4b90 ldr r3, [pc, #576] @ (80024fc ) - 80022bc: 689b ldr r3, [r3, #8] - 80022be: 2238 movs r2, #56 @ 0x38 - 80022c0: 4013 ands r3, r2 - 80022c2: 617b str r3, [r7, #20] + 800233e: 4b90 ldr r3, [pc, #576] @ (8002580 ) + 8002340: 689b ldr r3, [r3, #8] + 8002342: 2238 movs r2, #56 @ 0x38 + 8002344: 4013 ands r3, r2 + 8002346: 617b str r3, [r7, #20] if (temp_sysclksrc == RCC_CFGR_SWS_HSI) - 80022c4: 697b ldr r3, [r7, #20] - 80022c6: 2b00 cmp r3, #0 - 80022c8: d12f bne.n 800232a + 8002348: 697b ldr r3, [r7, #20] + 800234a: 2b00 cmp r3, #0 + 800234c: d12f bne.n 80023ae { /* When HSI is used as system clock it can not be disabled */ if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF) - 80022ca: 687b ldr r3, [r7, #4] - 80022cc: 68db ldr r3, [r3, #12] - 80022ce: 2b00 cmp r3, #0 - 80022d0: d101 bne.n 80022d6 + 800234e: 687b ldr r3, [r7, #4] + 8002350: 68db ldr r3, [r3, #12] + 8002352: 2b00 cmp r3, #0 + 8002354: d101 bne.n 800235a { return HAL_ERROR; - 80022d2: 2301 movs r3, #1 - 80022d4: e14c b.n 8002570 + 8002356: 2301 movs r3, #1 + 8002358: e14c b.n 80025f4 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - 80022d6: 4b89 ldr r3, [pc, #548] @ (80024fc ) - 80022d8: 685b ldr r3, [r3, #4] - 80022da: 4a8b ldr r2, [pc, #556] @ (8002508 ) - 80022dc: 4013 ands r3, r2 - 80022de: 0019 movs r1, r3 - 80022e0: 687b ldr r3, [r7, #4] - 80022e2: 695b ldr r3, [r3, #20] - 80022e4: 021a lsls r2, r3, #8 - 80022e6: 4b85 ldr r3, [pc, #532] @ (80024fc ) - 80022e8: 430a orrs r2, r1 - 80022ea: 605a str r2, [r3, #4] + 800235a: 4b89 ldr r3, [pc, #548] @ (8002580 ) + 800235c: 685b ldr r3, [r3, #4] + 800235e: 4a8b ldr r2, [pc, #556] @ (800258c ) + 8002360: 4013 ands r3, r2 + 8002362: 0019 movs r1, r3 + 8002364: 687b ldr r3, [r7, #4] + 8002366: 695b ldr r3, [r3, #20] + 8002368: 021a lsls r2, r3, #8 + 800236a: 4b85 ldr r3, [pc, #532] @ (8002580 ) + 800236c: 430a orrs r2, r1 + 800236e: 605a str r2, [r3, #4] if (temp_sysclksrc == RCC_CFGR_SWS_HSI) - 80022ec: 697b ldr r3, [r7, #20] - 80022ee: 2b00 cmp r3, #0 - 80022f0: d112 bne.n 8002318 + 8002370: 697b ldr r3, [r7, #20] + 8002372: 2b00 cmp r3, #0 + 8002374: d112 bne.n 800239c { /* Adjust the HSI48 division factor */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv); - 80022f2: 4b82 ldr r3, [pc, #520] @ (80024fc ) - 80022f4: 681b ldr r3, [r3, #0] - 80022f6: 4a85 ldr r2, [pc, #532] @ (800250c ) - 80022f8: 4013 ands r3, r2 - 80022fa: 0019 movs r1, r3 - 80022fc: 687b ldr r3, [r7, #4] - 80022fe: 691a ldr r2, [r3, #16] - 8002300: 4b7e ldr r3, [pc, #504] @ (80024fc ) - 8002302: 430a orrs r2, r1 - 8002304: 601a str r2, [r3, #0] + 8002376: 4b82 ldr r3, [pc, #520] @ (8002580 ) + 8002378: 681b ldr r3, [r3, #0] + 800237a: 4a85 ldr r2, [pc, #532] @ (8002590 ) + 800237c: 4013 ands r3, r2 + 800237e: 0019 movs r1, r3 + 8002380: 687b ldr r3, [r7, #4] + 8002382: 691a ldr r2, [r3, #16] + 8002384: 4b7e ldr r3, [pc, #504] @ (8002580 ) + 8002386: 430a orrs r2, r1 + 8002388: 601a str r2, [r3, #0] /* Update the SystemCoreClock global variable with HSISYS value */ SystemCoreClock = (HSI_VALUE / (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos))); - 8002306: 4b7d ldr r3, [pc, #500] @ (80024fc ) - 8002308: 681b ldr r3, [r3, #0] - 800230a: 0adb lsrs r3, r3, #11 - 800230c: 2207 movs r2, #7 - 800230e: 4013 ands r3, r2 - 8002310: 4a7f ldr r2, [pc, #508] @ (8002510 ) - 8002312: 40da lsrs r2, r3 - 8002314: 4b7f ldr r3, [pc, #508] @ (8002514 ) - 8002316: 601a str r2, [r3, #0] + 800238a: 4b7d ldr r3, [pc, #500] @ (8002580 ) + 800238c: 681b ldr r3, [r3, #0] + 800238e: 0adb lsrs r3, r3, #11 + 8002390: 2207 movs r2, #7 + 8002392: 4013 ands r3, r2 + 8002394: 4a7f ldr r2, [pc, #508] @ (8002594 ) + 8002396: 40da lsrs r2, r3 + 8002398: 4b7f ldr r3, [pc, #508] @ (8002598 ) + 800239a: 601a str r2, [r3, #0] } /* Adapt Systick interrupt period */ if (HAL_InitTick(uwTickPrio) != HAL_OK) - 8002318: 4b7f ldr r3, [pc, #508] @ (8002518 ) - 800231a: 681b ldr r3, [r3, #0] - 800231c: 0018 movs r0, r3 - 800231e: f7ff f9ad bl 800167c - 8002322: 1e03 subs r3, r0, #0 - 8002324: d050 beq.n 80023c8 + 800239c: 4b7f ldr r3, [pc, #508] @ (800259c ) + 800239e: 681b ldr r3, [r3, #0] + 80023a0: 0018 movs r0, r3 + 80023a2: f7ff f9ad bl 8001700 + 80023a6: 1e03 subs r3, r0, #0 + 80023a8: d050 beq.n 800244c { return HAL_ERROR; - 8002326: 2301 movs r3, #1 - 8002328: e122 b.n 8002570 + 80023aa: 2301 movs r3, #1 + 80023ac: e122 b.n 80025f4 } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) - 800232a: 687b ldr r3, [r7, #4] - 800232c: 68db ldr r3, [r3, #12] - 800232e: 2b00 cmp r3, #0 - 8002330: d030 beq.n 8002394 + 80023ae: 687b ldr r3, [r7, #4] + 80023b0: 68db ldr r3, [r3, #12] + 80023b2: 2b00 cmp r3, #0 + 80023b4: d030 beq.n 8002418 { /* Configure the HSI48 division factor */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv); - 8002332: 4b72 ldr r3, [pc, #456] @ (80024fc ) - 8002334: 681b ldr r3, [r3, #0] - 8002336: 4a75 ldr r2, [pc, #468] @ (800250c ) - 8002338: 4013 ands r3, r2 - 800233a: 0019 movs r1, r3 - 800233c: 687b ldr r3, [r7, #4] - 800233e: 691a ldr r2, [r3, #16] - 8002340: 4b6e ldr r3, [pc, #440] @ (80024fc ) - 8002342: 430a orrs r2, r1 - 8002344: 601a str r2, [r3, #0] + 80023b6: 4b72 ldr r3, [pc, #456] @ (8002580 ) + 80023b8: 681b ldr r3, [r3, #0] + 80023ba: 4a75 ldr r2, [pc, #468] @ (8002590 ) + 80023bc: 4013 ands r3, r2 + 80023be: 0019 movs r1, r3 + 80023c0: 687b ldr r3, [r7, #4] + 80023c2: 691a ldr r2, [r3, #16] + 80023c4: 4b6e ldr r3, [pc, #440] @ (8002580 ) + 80023c6: 430a orrs r2, r1 + 80023c8: 601a str r2, [r3, #0] /* Enable the Internal High Speed oscillator (HSI48). */ __HAL_RCC_HSI_ENABLE(); - 8002346: 4b6d ldr r3, [pc, #436] @ (80024fc ) - 8002348: 681a ldr r2, [r3, #0] - 800234a: 4b6c ldr r3, [pc, #432] @ (80024fc ) - 800234c: 2180 movs r1, #128 @ 0x80 - 800234e: 0049 lsls r1, r1, #1 - 8002350: 430a orrs r2, r1 - 8002352: 601a str r2, [r3, #0] + 80023ca: 4b6d ldr r3, [pc, #436] @ (8002580 ) + 80023cc: 681a ldr r2, [r3, #0] + 80023ce: 4b6c ldr r3, [pc, #432] @ (8002580 ) + 80023d0: 2180 movs r1, #128 @ 0x80 + 80023d2: 0049 lsls r1, r1, #1 + 80023d4: 430a orrs r2, r1 + 80023d6: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8002354: f7ff f9ee bl 8001734 - 8002358: 0003 movs r3, r0 - 800235a: 613b str r3, [r7, #16] + 80023d8: f7ff f9ee bl 80017b8 + 80023dc: 0003 movs r3, r0 + 80023de: 613b str r3, [r7, #16] /* Wait till HSI is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) - 800235c: e008 b.n 8002370 + 80023e0: e008 b.n 80023f4 { if ((HAL_GetTick() - tickstart) > RCC_HSI_TIMEOUT_VALUE) - 800235e: f7ff f9e9 bl 8001734 - 8002362: 0002 movs r2, r0 - 8002364: 693b ldr r3, [r7, #16] - 8002366: 1ad3 subs r3, r2, r3 - 8002368: 2b02 cmp r3, #2 - 800236a: d901 bls.n 8002370 + 80023e2: f7ff f9e9 bl 80017b8 + 80023e6: 0002 movs r2, r0 + 80023e8: 693b ldr r3, [r7, #16] + 80023ea: 1ad3 subs r3, r2, r3 + 80023ec: 2b02 cmp r3, #2 + 80023ee: d901 bls.n 80023f4 { return HAL_TIMEOUT; - 800236c: 2303 movs r3, #3 - 800236e: e0ff b.n 8002570 + 80023f0: 2303 movs r3, #3 + 80023f2: e0ff b.n 80025f4 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) - 8002370: 4b62 ldr r3, [pc, #392] @ (80024fc ) - 8002372: 681a ldr r2, [r3, #0] - 8002374: 2380 movs r3, #128 @ 0x80 - 8002376: 00db lsls r3, r3, #3 - 8002378: 4013 ands r3, r2 - 800237a: d0f0 beq.n 800235e + 80023f4: 4b62 ldr r3, [pc, #392] @ (8002580 ) + 80023f6: 681a ldr r2, [r3, #0] + 80023f8: 2380 movs r3, #128 @ 0x80 + 80023fa: 00db lsls r3, r3, #3 + 80023fc: 4013 ands r3, r2 + 80023fe: d0f0 beq.n 80023e2 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - 800237c: 4b5f ldr r3, [pc, #380] @ (80024fc ) - 800237e: 685b ldr r3, [r3, #4] - 8002380: 4a61 ldr r2, [pc, #388] @ (8002508 ) - 8002382: 4013 ands r3, r2 - 8002384: 0019 movs r1, r3 - 8002386: 687b ldr r3, [r7, #4] - 8002388: 695b ldr r3, [r3, #20] - 800238a: 021a lsls r2, r3, #8 - 800238c: 4b5b ldr r3, [pc, #364] @ (80024fc ) - 800238e: 430a orrs r2, r1 - 8002390: 605a str r2, [r3, #4] - 8002392: e019 b.n 80023c8 + 8002400: 4b5f ldr r3, [pc, #380] @ (8002580 ) + 8002402: 685b ldr r3, [r3, #4] + 8002404: 4a61 ldr r2, [pc, #388] @ (800258c ) + 8002406: 4013 ands r3, r2 + 8002408: 0019 movs r1, r3 + 800240a: 687b ldr r3, [r7, #4] + 800240c: 695b ldr r3, [r3, #20] + 800240e: 021a lsls r2, r3, #8 + 8002410: 4b5b ldr r3, [pc, #364] @ (8002580 ) + 8002412: 430a orrs r2, r1 + 8002414: 605a str r2, [r3, #4] + 8002416: e019 b.n 800244c } else { /* Disable the Internal High Speed oscillator (HSI48). */ __HAL_RCC_HSI_DISABLE(); - 8002394: 4b59 ldr r3, [pc, #356] @ (80024fc ) - 8002396: 681a ldr r2, [r3, #0] - 8002398: 4b58 ldr r3, [pc, #352] @ (80024fc ) - 800239a: 4960 ldr r1, [pc, #384] @ (800251c ) - 800239c: 400a ands r2, r1 - 800239e: 601a str r2, [r3, #0] + 8002418: 4b59 ldr r3, [pc, #356] @ (8002580 ) + 800241a: 681a ldr r2, [r3, #0] + 800241c: 4b58 ldr r3, [pc, #352] @ (8002580 ) + 800241e: 4960 ldr r1, [pc, #384] @ (80025a0 ) + 8002420: 400a ands r2, r1 + 8002422: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 80023a0: f7ff f9c8 bl 8001734 - 80023a4: 0003 movs r3, r0 - 80023a6: 613b str r3, [r7, #16] + 8002424: f7ff f9c8 bl 80017b8 + 8002428: 0003 movs r3, r0 + 800242a: 613b str r3, [r7, #16] /* Wait till HSI is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) - 80023a8: e008 b.n 80023bc + 800242c: e008 b.n 8002440 { if ((HAL_GetTick() - tickstart) > RCC_HSI_TIMEOUT_VALUE) - 80023aa: f7ff f9c3 bl 8001734 - 80023ae: 0002 movs r2, r0 - 80023b0: 693b ldr r3, [r7, #16] - 80023b2: 1ad3 subs r3, r2, r3 - 80023b4: 2b02 cmp r3, #2 - 80023b6: d901 bls.n 80023bc + 800242e: f7ff f9c3 bl 80017b8 + 8002432: 0002 movs r2, r0 + 8002434: 693b ldr r3, [r7, #16] + 8002436: 1ad3 subs r3, r2, r3 + 8002438: 2b02 cmp r3, #2 + 800243a: d901 bls.n 8002440 { return HAL_TIMEOUT; - 80023b8: 2303 movs r3, #3 - 80023ba: e0d9 b.n 8002570 + 800243c: 2303 movs r3, #3 + 800243e: e0d9 b.n 80025f4 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) - 80023bc: 4b4f ldr r3, [pc, #316] @ (80024fc ) - 80023be: 681a ldr r2, [r3, #0] - 80023c0: 2380 movs r3, #128 @ 0x80 - 80023c2: 00db lsls r3, r3, #3 - 80023c4: 4013 ands r3, r2 - 80023c6: d1f0 bne.n 80023aa + 8002440: 4b4f ldr r3, [pc, #316] @ (8002580 ) + 8002442: 681a ldr r2, [r3, #0] + 8002444: 2380 movs r3, #128 @ 0x80 + 8002446: 00db lsls r3, r3, #3 + 8002448: 4013 ands r3, r2 + 800244a: d1f0 bne.n 800242e } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) - 80023c8: 687b ldr r3, [r7, #4] - 80023ca: 681b ldr r3, [r3, #0] - 80023cc: 2208 movs r2, #8 - 80023ce: 4013 ands r3, r2 - 80023d0: d042 beq.n 8002458 + 800244c: 687b ldr r3, [r7, #4] + 800244e: 681b ldr r3, [r3, #0] + 8002450: 2208 movs r2, #8 + 8002452: 4013 ands r3, r2 + 8002454: d042 beq.n 80024dc { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check if LSI is used as system clock */ if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSI) - 80023d2: 4b4a ldr r3, [pc, #296] @ (80024fc ) - 80023d4: 689b ldr r3, [r3, #8] - 80023d6: 2238 movs r2, #56 @ 0x38 - 80023d8: 4013 ands r3, r2 - 80023da: 2b18 cmp r3, #24 - 80023dc: d105 bne.n 80023ea + 8002456: 4b4a ldr r3, [pc, #296] @ (8002580 ) + 8002458: 689b ldr r3, [r3, #8] + 800245a: 2238 movs r2, #56 @ 0x38 + 800245c: 4013 ands r3, r2 + 800245e: 2b18 cmp r3, #24 + 8002460: d105 bne.n 800246e { /* When LSI is used as system clock it will not be disabled */ if (RCC_OscInitStruct->LSIState == RCC_LSI_OFF) - 80023de: 687b ldr r3, [r7, #4] - 80023e0: 699b ldr r3, [r3, #24] - 80023e2: 2b00 cmp r3, #0 - 80023e4: d138 bne.n 8002458 + 8002462: 687b ldr r3, [r7, #4] + 8002464: 699b ldr r3, [r3, #24] + 8002466: 2b00 cmp r3, #0 + 8002468: d138 bne.n 80024dc { return HAL_ERROR; - 80023e6: 2301 movs r3, #1 - 80023e8: e0c2 b.n 8002570 + 800246a: 2301 movs r3, #1 + 800246c: e0c2 b.n 80025f4 } } else { /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) - 80023ea: 687b ldr r3, [r7, #4] - 80023ec: 699b ldr r3, [r3, #24] - 80023ee: 2b00 cmp r3, #0 - 80023f0: d019 beq.n 8002426 + 800246e: 687b ldr r3, [r7, #4] + 8002470: 699b ldr r3, [r3, #24] + 8002472: 2b00 cmp r3, #0 + 8002474: d019 beq.n 80024aa { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); - 80023f2: 4b42 ldr r3, [pc, #264] @ (80024fc ) - 80023f4: 6e1a ldr r2, [r3, #96] @ 0x60 - 80023f6: 4b41 ldr r3, [pc, #260] @ (80024fc ) - 80023f8: 2101 movs r1, #1 - 80023fa: 430a orrs r2, r1 - 80023fc: 661a str r2, [r3, #96] @ 0x60 + 8002476: 4b42 ldr r3, [pc, #264] @ (8002580 ) + 8002478: 6e1a ldr r2, [r3, #96] @ 0x60 + 800247a: 4b41 ldr r3, [pc, #260] @ (8002580 ) + 800247c: 2101 movs r1, #1 + 800247e: 430a orrs r2, r1 + 8002480: 661a str r2, [r3, #96] @ 0x60 /* Get Start Tick*/ tickstart = HAL_GetTick(); - 80023fe: f7ff f999 bl 8001734 - 8002402: 0003 movs r3, r0 - 8002404: 613b str r3, [r7, #16] + 8002482: f7ff f999 bl 80017b8 + 8002486: 0003 movs r3, r0 + 8002488: 613b str r3, [r7, #16] /* Wait till LSI is ready */ while (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) == 0U) - 8002406: e008 b.n 800241a + 800248a: e008 b.n 800249e { if ((HAL_GetTick() - tickstart) > RCC_LSI_TIMEOUT_VALUE) - 8002408: f7ff f994 bl 8001734 - 800240c: 0002 movs r2, r0 - 800240e: 693b ldr r3, [r7, #16] - 8002410: 1ad3 subs r3, r2, r3 - 8002412: 2b02 cmp r3, #2 - 8002414: d901 bls.n 800241a + 800248c: f7ff f994 bl 80017b8 + 8002490: 0002 movs r2, r0 + 8002492: 693b ldr r3, [r7, #16] + 8002494: 1ad3 subs r3, r2, r3 + 8002496: 2b02 cmp r3, #2 + 8002498: d901 bls.n 800249e { return HAL_TIMEOUT; - 8002416: 2303 movs r3, #3 - 8002418: e0aa b.n 8002570 + 800249a: 2303 movs r3, #3 + 800249c: e0aa b.n 80025f4 while (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) == 0U) - 800241a: 4b38 ldr r3, [pc, #224] @ (80024fc ) - 800241c: 6e1b ldr r3, [r3, #96] @ 0x60 - 800241e: 2202 movs r2, #2 - 8002420: 4013 ands r3, r2 - 8002422: d0f1 beq.n 8002408 - 8002424: e018 b.n 8002458 + 800249e: 4b38 ldr r3, [pc, #224] @ (8002580 ) + 80024a0: 6e1b ldr r3, [r3, #96] @ 0x60 + 80024a2: 2202 movs r2, #2 + 80024a4: 4013 ands r3, r2 + 80024a6: d0f1 beq.n 800248c + 80024a8: e018 b.n 80024dc } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); - 8002426: 4b35 ldr r3, [pc, #212] @ (80024fc ) - 8002428: 6e1a ldr r2, [r3, #96] @ 0x60 - 800242a: 4b34 ldr r3, [pc, #208] @ (80024fc ) - 800242c: 2101 movs r1, #1 - 800242e: 438a bics r2, r1 - 8002430: 661a str r2, [r3, #96] @ 0x60 + 80024aa: 4b35 ldr r3, [pc, #212] @ (8002580 ) + 80024ac: 6e1a ldr r2, [r3, #96] @ 0x60 + 80024ae: 4b34 ldr r3, [pc, #208] @ (8002580 ) + 80024b0: 2101 movs r1, #1 + 80024b2: 438a bics r2, r1 + 80024b4: 661a str r2, [r3, #96] @ 0x60 /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8002432: f7ff f97f bl 8001734 - 8002436: 0003 movs r3, r0 - 8002438: 613b str r3, [r7, #16] + 80024b6: f7ff f97f bl 80017b8 + 80024ba: 0003 movs r3, r0 + 80024bc: 613b str r3, [r7, #16] /* Wait till LSI is disabled */ while (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) != 0U) - 800243a: e008 b.n 800244e + 80024be: e008 b.n 80024d2 { if ((HAL_GetTick() - tickstart) > RCC_LSI_TIMEOUT_VALUE) - 800243c: f7ff f97a bl 8001734 - 8002440: 0002 movs r2, r0 - 8002442: 693b ldr r3, [r7, #16] - 8002444: 1ad3 subs r3, r2, r3 - 8002446: 2b02 cmp r3, #2 - 8002448: d901 bls.n 800244e + 80024c0: f7ff f97a bl 80017b8 + 80024c4: 0002 movs r2, r0 + 80024c6: 693b ldr r3, [r7, #16] + 80024c8: 1ad3 subs r3, r2, r3 + 80024ca: 2b02 cmp r3, #2 + 80024cc: d901 bls.n 80024d2 { return HAL_TIMEOUT; - 800244a: 2303 movs r3, #3 - 800244c: e090 b.n 8002570 + 80024ce: 2303 movs r3, #3 + 80024d0: e090 b.n 80025f4 while (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) != 0U) - 800244e: 4b2b ldr r3, [pc, #172] @ (80024fc ) - 8002450: 6e1b ldr r3, [r3, #96] @ 0x60 - 8002452: 2202 movs r2, #2 - 8002454: 4013 ands r3, r2 - 8002456: d1f1 bne.n 800243c + 80024d2: 4b2b ldr r3, [pc, #172] @ (8002580 ) + 80024d4: 6e1b ldr r3, [r3, #96] @ 0x60 + 80024d6: 2202 movs r2, #2 + 80024d8: 4013 ands r3, r2 + 80024da: d1f1 bne.n 80024c0 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) - 8002458: 687b ldr r3, [r7, #4] - 800245a: 681b ldr r3, [r3, #0] - 800245c: 2204 movs r2, #4 - 800245e: 4013 ands r3, r2 - 8002460: d100 bne.n 8002464 - 8002462: e084 b.n 800256e + 80024dc: 687b ldr r3, [r7, #4] + 80024de: 681b ldr r3, [r3, #0] + 80024e0: 2204 movs r2, #4 + 80024e2: 4013 ands r3, r2 + 80024e4: d100 bne.n 80024e8 + 80024e6: e084 b.n 80025f2 { FlagStatus pwrclkchanged = RESET; - 8002464: 230f movs r3, #15 - 8002466: 18fb adds r3, r7, r3 - 8002468: 2200 movs r2, #0 - 800246a: 701a strb r2, [r3, #0] + 80024e8: 230f movs r3, #15 + 80024ea: 18fb adds r3, r7, r3 + 80024ec: 2200 movs r2, #0 + 80024ee: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* When the LSE is used as system clock, it is not allowed disable it */ if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSE) - 800246c: 4b23 ldr r3, [pc, #140] @ (80024fc ) - 800246e: 689b ldr r3, [r3, #8] - 8002470: 2238 movs r2, #56 @ 0x38 - 8002472: 4013 ands r3, r2 - 8002474: 2b20 cmp r3, #32 - 8002476: d106 bne.n 8002486 + 80024f0: 4b23 ldr r3, [pc, #140] @ (8002580 ) + 80024f2: 689b ldr r3, [r3, #8] + 80024f4: 2238 movs r2, #56 @ 0x38 + 80024f6: 4013 ands r3, r2 + 80024f8: 2b20 cmp r3, #32 + 80024fa: d106 bne.n 800250a { if (RCC_OscInitStruct->LSEState == RCC_LSE_OFF) - 8002478: 687b ldr r3, [r7, #4] - 800247a: 689b ldr r3, [r3, #8] - 800247c: 2b00 cmp r3, #0 - 800247e: d000 beq.n 8002482 - 8002480: e075 b.n 800256e + 80024fc: 687b ldr r3, [r7, #4] + 80024fe: 689b ldr r3, [r3, #8] + 8002500: 2b00 cmp r3, #0 + 8002502: d000 beq.n 8002506 + 8002504: e075 b.n 80025f2 { return HAL_ERROR; - 8002482: 2301 movs r3, #1 - 8002484: e074 b.n 8002570 + 8002506: 2301 movs r3, #1 + 8002508: e074 b.n 80025f4 } else { /* Update LSE configuration in RTC Domain control register */ /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); - 8002486: 687b ldr r3, [r7, #4] - 8002488: 689b ldr r3, [r3, #8] - 800248a: 2b01 cmp r3, #1 - 800248c: d106 bne.n 800249c - 800248e: 4b1b ldr r3, [pc, #108] @ (80024fc ) - 8002490: 6dda ldr r2, [r3, #92] @ 0x5c - 8002492: 4b1a ldr r3, [pc, #104] @ (80024fc ) - 8002494: 2101 movs r1, #1 - 8002496: 430a orrs r2, r1 - 8002498: 65da str r2, [r3, #92] @ 0x5c - 800249a: e01c b.n 80024d6 - 800249c: 687b ldr r3, [r7, #4] - 800249e: 689b ldr r3, [r3, #8] - 80024a0: 2b05 cmp r3, #5 - 80024a2: d10c bne.n 80024be - 80024a4: 4b15 ldr r3, [pc, #84] @ (80024fc ) - 80024a6: 6dda ldr r2, [r3, #92] @ 0x5c - 80024a8: 4b14 ldr r3, [pc, #80] @ (80024fc ) - 80024aa: 2104 movs r1, #4 - 80024ac: 430a orrs r2, r1 - 80024ae: 65da str r2, [r3, #92] @ 0x5c - 80024b0: 4b12 ldr r3, [pc, #72] @ (80024fc ) - 80024b2: 6dda ldr r2, [r3, #92] @ 0x5c - 80024b4: 4b11 ldr r3, [pc, #68] @ (80024fc ) - 80024b6: 2101 movs r1, #1 - 80024b8: 430a orrs r2, r1 - 80024ba: 65da str r2, [r3, #92] @ 0x5c - 80024bc: e00b b.n 80024d6 - 80024be: 4b0f ldr r3, [pc, #60] @ (80024fc ) - 80024c0: 6dda ldr r2, [r3, #92] @ 0x5c - 80024c2: 4b0e ldr r3, [pc, #56] @ (80024fc ) - 80024c4: 2101 movs r1, #1 - 80024c6: 438a bics r2, r1 - 80024c8: 65da str r2, [r3, #92] @ 0x5c - 80024ca: 4b0c ldr r3, [pc, #48] @ (80024fc ) - 80024cc: 6dda ldr r2, [r3, #92] @ 0x5c - 80024ce: 4b0b ldr r3, [pc, #44] @ (80024fc ) - 80024d0: 2104 movs r1, #4 - 80024d2: 438a bics r2, r1 - 80024d4: 65da str r2, [r3, #92] @ 0x5c + 800250a: 687b ldr r3, [r7, #4] + 800250c: 689b ldr r3, [r3, #8] + 800250e: 2b01 cmp r3, #1 + 8002510: d106 bne.n 8002520 + 8002512: 4b1b ldr r3, [pc, #108] @ (8002580 ) + 8002514: 6dda ldr r2, [r3, #92] @ 0x5c + 8002516: 4b1a ldr r3, [pc, #104] @ (8002580 ) + 8002518: 2101 movs r1, #1 + 800251a: 430a orrs r2, r1 + 800251c: 65da str r2, [r3, #92] @ 0x5c + 800251e: e01c b.n 800255a + 8002520: 687b ldr r3, [r7, #4] + 8002522: 689b ldr r3, [r3, #8] + 8002524: 2b05 cmp r3, #5 + 8002526: d10c bne.n 8002542 + 8002528: 4b15 ldr r3, [pc, #84] @ (8002580 ) + 800252a: 6dda ldr r2, [r3, #92] @ 0x5c + 800252c: 4b14 ldr r3, [pc, #80] @ (8002580 ) + 800252e: 2104 movs r1, #4 + 8002530: 430a orrs r2, r1 + 8002532: 65da str r2, [r3, #92] @ 0x5c + 8002534: 4b12 ldr r3, [pc, #72] @ (8002580 ) + 8002536: 6dda ldr r2, [r3, #92] @ 0x5c + 8002538: 4b11 ldr r3, [pc, #68] @ (8002580 ) + 800253a: 2101 movs r1, #1 + 800253c: 430a orrs r2, r1 + 800253e: 65da str r2, [r3, #92] @ 0x5c + 8002540: e00b b.n 800255a + 8002542: 4b0f ldr r3, [pc, #60] @ (8002580 ) + 8002544: 6dda ldr r2, [r3, #92] @ 0x5c + 8002546: 4b0e ldr r3, [pc, #56] @ (8002580 ) + 8002548: 2101 movs r1, #1 + 800254a: 438a bics r2, r1 + 800254c: 65da str r2, [r3, #92] @ 0x5c + 800254e: 4b0c ldr r3, [pc, #48] @ (8002580 ) + 8002550: 6dda ldr r2, [r3, #92] @ 0x5c + 8002552: 4b0b ldr r3, [pc, #44] @ (8002580 ) + 8002554: 2104 movs r1, #4 + 8002556: 438a bics r2, r1 + 8002558: 65da str r2, [r3, #92] @ 0x5c /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) - 80024d6: 687b ldr r3, [r7, #4] - 80024d8: 689b ldr r3, [r3, #8] - 80024da: 2b00 cmp r3, #0 - 80024dc: d028 beq.n 8002530 + 800255a: 687b ldr r3, [r7, #4] + 800255c: 689b ldr r3, [r3, #8] + 800255e: 2b00 cmp r3, #0 + 8002560: d028 beq.n 80025b4 { /* Get Start Tick*/ tickstart = HAL_GetTick(); - 80024de: f7ff f929 bl 8001734 - 80024e2: 0003 movs r3, r0 - 80024e4: 613b str r3, [r7, #16] + 8002562: f7ff f929 bl 80017b8 + 8002566: 0003 movs r3, r0 + 8002568: 613b str r3, [r7, #16] /* Wait till LSE is ready */ while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U) - 80024e6: e01d b.n 8002524 + 800256a: e01d b.n 80025a8 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - 80024e8: f7ff f924 bl 8001734 - 80024ec: 0002 movs r2, r0 - 80024ee: 693b ldr r3, [r7, #16] - 80024f0: 1ad3 subs r3, r2, r3 - 80024f2: 4a0b ldr r2, [pc, #44] @ (8002520 ) - 80024f4: 4293 cmp r3, r2 - 80024f6: d915 bls.n 8002524 + 800256c: f7ff f924 bl 80017b8 + 8002570: 0002 movs r2, r0 + 8002572: 693b ldr r3, [r7, #16] + 8002574: 1ad3 subs r3, r2, r3 + 8002576: 4a0b ldr r2, [pc, #44] @ (80025a4 ) + 8002578: 4293 cmp r3, r2 + 800257a: d915 bls.n 80025a8 { return HAL_TIMEOUT; - 80024f8: 2303 movs r3, #3 - 80024fa: e039 b.n 8002570 - 80024fc: 40021000 .word 0x40021000 - 8002500: fffeffff .word 0xfffeffff - 8002504: fffbffff .word 0xfffbffff - 8002508: ffff80ff .word 0xffff80ff - 800250c: ffffc7ff .word 0xffffc7ff - 8002510: 02dc6c00 .word 0x02dc6c00 - 8002514: 20000018 .word 0x20000018 - 8002518: 2000001c .word 0x2000001c - 800251c: fffffeff .word 0xfffffeff - 8002520: 00001388 .word 0x00001388 + 800257c: 2303 movs r3, #3 + 800257e: e039 b.n 80025f4 + 8002580: 40021000 .word 0x40021000 + 8002584: fffeffff .word 0xfffeffff + 8002588: fffbffff .word 0xfffbffff + 800258c: ffff80ff .word 0xffff80ff + 8002590: ffffc7ff .word 0xffffc7ff + 8002594: 02dc6c00 .word 0x02dc6c00 + 8002598: 20000018 .word 0x20000018 + 800259c: 2000001c .word 0x2000001c + 80025a0: fffffeff .word 0xfffffeff + 80025a4: 00001388 .word 0x00001388 while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U) - 8002524: 4b14 ldr r3, [pc, #80] @ (8002578 ) - 8002526: 6ddb ldr r3, [r3, #92] @ 0x5c - 8002528: 2202 movs r2, #2 - 800252a: 4013 ands r3, r2 - 800252c: d0dc beq.n 80024e8 - 800252e: e013 b.n 8002558 + 80025a8: 4b14 ldr r3, [pc, #80] @ (80025fc ) + 80025aa: 6ddb ldr r3, [r3, #92] @ 0x5c + 80025ac: 2202 movs r2, #2 + 80025ae: 4013 ands r3, r2 + 80025b0: d0dc beq.n 800256c + 80025b2: e013 b.n 80025dc } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8002530: f7ff f900 bl 8001734 - 8002534: 0003 movs r3, r0 - 8002536: 613b str r3, [r7, #16] + 80025b4: f7ff f900 bl 80017b8 + 80025b8: 0003 movs r3, r0 + 80025ba: 613b str r3, [r7, #16] /* Wait till LSE is disabled */ while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) != 0U) - 8002538: e009 b.n 800254e + 80025bc: e009 b.n 80025d2 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - 800253a: f7ff f8fb bl 8001734 - 800253e: 0002 movs r2, r0 - 8002540: 693b ldr r3, [r7, #16] - 8002542: 1ad3 subs r3, r2, r3 - 8002544: 4a0d ldr r2, [pc, #52] @ (800257c ) - 8002546: 4293 cmp r3, r2 - 8002548: d901 bls.n 800254e + 80025be: f7ff f8fb bl 80017b8 + 80025c2: 0002 movs r2, r0 + 80025c4: 693b ldr r3, [r7, #16] + 80025c6: 1ad3 subs r3, r2, r3 + 80025c8: 4a0d ldr r2, [pc, #52] @ (8002600 ) + 80025ca: 4293 cmp r3, r2 + 80025cc: d901 bls.n 80025d2 { return HAL_TIMEOUT; - 800254a: 2303 movs r3, #3 - 800254c: e010 b.n 8002570 + 80025ce: 2303 movs r3, #3 + 80025d0: e010 b.n 80025f4 while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) != 0U) - 800254e: 4b0a ldr r3, [pc, #40] @ (8002578 ) - 8002550: 6ddb ldr r3, [r3, #92] @ 0x5c - 8002552: 2202 movs r2, #2 - 8002554: 4013 ands r3, r2 - 8002556: d1f0 bne.n 800253a + 80025d2: 4b0a ldr r3, [pc, #40] @ (80025fc ) + 80025d4: 6ddb ldr r3, [r3, #92] @ 0x5c + 80025d6: 2202 movs r2, #2 + 80025d8: 4013 ands r3, r2 + 80025da: d1f0 bne.n 80025be } } } /* Restore clock configuration if changed */ if (pwrclkchanged == SET) - 8002558: 230f movs r3, #15 - 800255a: 18fb adds r3, r7, r3 - 800255c: 781b ldrb r3, [r3, #0] - 800255e: 2b01 cmp r3, #1 - 8002560: d105 bne.n 800256e + 80025dc: 230f movs r3, #15 + 80025de: 18fb adds r3, r7, r3 + 80025e0: 781b ldrb r3, [r3, #0] + 80025e2: 2b01 cmp r3, #1 + 80025e4: d105 bne.n 80025f2 { __HAL_RCC_PWR_CLK_DISABLE(); - 8002562: 4b05 ldr r3, [pc, #20] @ (8002578 ) - 8002564: 6bda ldr r2, [r3, #60] @ 0x3c - 8002566: 4b04 ldr r3, [pc, #16] @ (8002578 ) - 8002568: 4905 ldr r1, [pc, #20] @ (8002580 ) - 800256a: 400a ands r2, r1 - 800256c: 63da str r2, [r3, #60] @ 0x3c + 80025e6: 4b05 ldr r3, [pc, #20] @ (80025fc ) + 80025e8: 6bda ldr r2, [r3, #60] @ 0x3c + 80025ea: 4b04 ldr r3, [pc, #16] @ (80025fc ) + 80025ec: 4905 ldr r1, [pc, #20] @ (8002604 ) + 80025ee: 400a ands r2, r1 + 80025f0: 63da str r2, [r3, #60] @ 0x3c } } } } #endif /* RCC_CR_HSIUSB48ON */ return HAL_OK; - 800256e: 2300 movs r3, #0 + 80025f2: 2300 movs r3, #0 } - 8002570: 0018 movs r0, r3 - 8002572: 46bd mov sp, r7 - 8002574: b006 add sp, #24 - 8002576: bd80 pop {r7, pc} - 8002578: 40021000 .word 0x40021000 - 800257c: 00001388 .word 0x00001388 - 8002580: efffffff .word 0xefffffff + 80025f4: 0018 movs r0, r3 + 80025f6: 46bd mov sp, r7 + 80025f8: b006 add sp, #24 + 80025fa: bd80 pop {r7, pc} + 80025fc: 40021000 .word 0x40021000 + 8002600: 00001388 .word 0x00001388 + 8002604: efffffff .word 0xefffffff -08002584 : +08002608 : * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { - 8002584: b580 push {r7, lr} - 8002586: b084 sub sp, #16 - 8002588: af00 add r7, sp, #0 - 800258a: 6078 str r0, [r7, #4] - 800258c: 6039 str r1, [r7, #0] + 8002608: b580 push {r7, lr} + 800260a: b084 sub sp, #16 + 800260c: af00 add r7, sp, #0 + 800260e: 6078 str r0, [r7, #4] + 8002610: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) - 800258e: 687b ldr r3, [r7, #4] - 8002590: 2b00 cmp r3, #0 - 8002592: d101 bne.n 8002598 + 8002612: 687b ldr r3, [r7, #4] + 8002614: 2b00 cmp r3, #0 + 8002616: d101 bne.n 800261c { return HAL_ERROR; - 8002594: 2301 movs r3, #1 - 8002596: e0e9 b.n 800276c + 8002618: 2301 movs r3, #1 + 800261a: e0e9 b.n 80027f0 /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the FLASH clock (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) - 8002598: 4b76 ldr r3, [pc, #472] @ (8002774 ) - 800259a: 681b ldr r3, [r3, #0] - 800259c: 2207 movs r2, #7 - 800259e: 4013 ands r3, r2 - 80025a0: 683a ldr r2, [r7, #0] - 80025a2: 429a cmp r2, r3 - 80025a4: d91e bls.n 80025e4 + 800261c: 4b76 ldr r3, [pc, #472] @ (80027f8 ) + 800261e: 681b ldr r3, [r3, #0] + 8002620: 2207 movs r2, #7 + 8002622: 4013 ands r3, r2 + 8002624: 683a ldr r2, [r7, #0] + 8002626: 429a cmp r2, r3 + 8002628: d91e bls.n 8002668 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); - 80025a6: 4b73 ldr r3, [pc, #460] @ (8002774 ) - 80025a8: 681b ldr r3, [r3, #0] - 80025aa: 2207 movs r2, #7 - 80025ac: 4393 bics r3, r2 - 80025ae: 0019 movs r1, r3 - 80025b0: 4b70 ldr r3, [pc, #448] @ (8002774 ) - 80025b2: 683a ldr r2, [r7, #0] - 80025b4: 430a orrs r2, r1 - 80025b6: 601a str r2, [r3, #0] + 800262a: 4b73 ldr r3, [pc, #460] @ (80027f8 ) + 800262c: 681b ldr r3, [r3, #0] + 800262e: 2207 movs r2, #7 + 8002630: 4393 bics r3, r2 + 8002632: 0019 movs r1, r3 + 8002634: 4b70 ldr r3, [pc, #448] @ (80027f8 ) + 8002636: 683a ldr r2, [r7, #0] + 8002638: 430a orrs r2, r1 + 800263a: 601a str r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by polling the FLASH_ACR register */ tickstart = HAL_GetTick(); - 80025b8: f7ff f8bc bl 8001734 - 80025bc: 0003 movs r3, r0 - 80025be: 60fb str r3, [r7, #12] + 800263c: f7ff f8bc bl 80017b8 + 8002640: 0003 movs r3, r0 + 8002642: 60fb str r3, [r7, #12] while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) - 80025c0: e009 b.n 80025d6 + 8002644: e009 b.n 800265a { if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE) - 80025c2: f7ff f8b7 bl 8001734 - 80025c6: 0002 movs r2, r0 - 80025c8: 68fb ldr r3, [r7, #12] - 80025ca: 1ad3 subs r3, r2, r3 - 80025cc: 4a6a ldr r2, [pc, #424] @ (8002778 ) - 80025ce: 4293 cmp r3, r2 - 80025d0: d901 bls.n 80025d6 + 8002646: f7ff f8b7 bl 80017b8 + 800264a: 0002 movs r2, r0 + 800264c: 68fb ldr r3, [r7, #12] + 800264e: 1ad3 subs r3, r2, r3 + 8002650: 4a6a ldr r2, [pc, #424] @ (80027fc ) + 8002652: 4293 cmp r3, r2 + 8002654: d901 bls.n 800265a { return HAL_TIMEOUT; - 80025d2: 2303 movs r3, #3 - 80025d4: e0ca b.n 800276c + 8002656: 2303 movs r3, #3 + 8002658: e0ca b.n 80027f0 while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) - 80025d6: 4b67 ldr r3, [pc, #412] @ (8002774 ) - 80025d8: 681b ldr r3, [r3, #0] - 80025da: 2207 movs r2, #7 - 80025dc: 4013 ands r3, r2 - 80025de: 683a ldr r2, [r7, #0] - 80025e0: 429a cmp r2, r3 - 80025e2: d1ee bne.n 80025c2 + 800265a: 4b67 ldr r3, [pc, #412] @ (80027f8 ) + 800265c: 681b ldr r3, [r3, #0] + 800265e: 2207 movs r2, #7 + 8002660: 4013 ands r3, r2 + 8002662: 683a ldr r2, [r7, #0] + 8002664: 429a cmp r2, r3 + 8002666: d1ee bne.n 8002646 } } } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) - 80025e4: 687b ldr r3, [r7, #4] - 80025e6: 681b ldr r3, [r3, #0] - 80025e8: 2202 movs r2, #2 - 80025ea: 4013 ands r3, r2 - 80025ec: d017 beq.n 800261e + 8002668: 687b ldr r3, [r7, #4] + 800266a: 681b ldr r3, [r3, #0] + 800266c: 2202 movs r2, #2 + 800266e: 4013 ands r3, r2 + 8002670: d017 beq.n 80026a2 { /* Set the highest APB divider in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - 80025ee: 687b ldr r3, [r7, #4] - 80025f0: 681b ldr r3, [r3, #0] - 80025f2: 2204 movs r2, #4 - 80025f4: 4013 ands r3, r2 - 80025f6: d008 beq.n 800260a + 8002672: 687b ldr r3, [r7, #4] + 8002674: 681b ldr r3, [r3, #0] + 8002676: 2204 movs r2, #4 + 8002678: 4013 ands r3, r2 + 800267a: d008 beq.n 800268e { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16); - 80025f8: 4b60 ldr r3, [pc, #384] @ (800277c ) - 80025fa: 689b ldr r3, [r3, #8] - 80025fc: 4a60 ldr r2, [pc, #384] @ (8002780 ) - 80025fe: 401a ands r2, r3 - 8002600: 4b5e ldr r3, [pc, #376] @ (800277c ) - 8002602: 21b0 movs r1, #176 @ 0xb0 - 8002604: 0109 lsls r1, r1, #4 - 8002606: 430a orrs r2, r1 - 8002608: 609a str r2, [r3, #8] + 800267c: 4b60 ldr r3, [pc, #384] @ (8002800 ) + 800267e: 689b ldr r3, [r3, #8] + 8002680: 4a60 ldr r2, [pc, #384] @ (8002804 ) + 8002682: 401a ands r2, r3 + 8002684: 4b5e ldr r3, [pc, #376] @ (8002800 ) + 8002686: 21b0 movs r1, #176 @ 0xb0 + 8002688: 0109 lsls r1, r1, #4 + 800268a: 430a orrs r2, r1 + 800268c: 609a str r2, [r3, #8] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); - 800260a: 4b5c ldr r3, [pc, #368] @ (800277c ) - 800260c: 689b ldr r3, [r3, #8] - 800260e: 4a5d ldr r2, [pc, #372] @ (8002784 ) - 8002610: 4013 ands r3, r2 - 8002612: 0019 movs r1, r3 - 8002614: 687b ldr r3, [r7, #4] - 8002616: 68da ldr r2, [r3, #12] - 8002618: 4b58 ldr r3, [pc, #352] @ (800277c ) - 800261a: 430a orrs r2, r1 - 800261c: 609a str r2, [r3, #8] + 800268e: 4b5c ldr r3, [pc, #368] @ (8002800 ) + 8002690: 689b ldr r3, [r3, #8] + 8002692: 4a5d ldr r2, [pc, #372] @ (8002808 ) + 8002694: 4013 ands r3, r2 + 8002696: 0019 movs r1, r3 + 8002698: 687b ldr r3, [r7, #4] + 800269a: 68da ldr r2, [r3, #12] + 800269c: 4b58 ldr r3, [pc, #352] @ (8002800 ) + 800269e: 430a orrs r2, r1 + 80026a0: 609a str r2, [r3, #8] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) - 800261e: 687b ldr r3, [r7, #4] - 8002620: 681b ldr r3, [r3, #0] - 8002622: 2201 movs r2, #1 - 8002624: 4013 ands r3, r2 - 8002626: d055 beq.n 80026d4 + 80026a2: 687b ldr r3, [r7, #4] + 80026a4: 681b ldr r3, [r3, #0] + 80026a6: 2201 movs r2, #1 + 80026a8: 4013 ands r3, r2 + 80026aa: d055 beq.n 8002758 { assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider)); assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); #if defined(RCC_CR_SYSDIV) MODIFY_REG(RCC->CR, RCC_CR_SYSDIV, RCC_ClkInitStruct->SYSCLKDivider); - 8002628: 4b54 ldr r3, [pc, #336] @ (800277c ) - 800262a: 681b ldr r3, [r3, #0] - 800262c: 221c movs r2, #28 - 800262e: 4393 bics r3, r2 - 8002630: 0019 movs r1, r3 - 8002632: 687b ldr r3, [r7, #4] - 8002634: 689a ldr r2, [r3, #8] - 8002636: 4b51 ldr r3, [pc, #324] @ (800277c ) - 8002638: 430a orrs r2, r1 - 800263a: 601a str r2, [r3, #0] + 80026ac: 4b54 ldr r3, [pc, #336] @ (8002800 ) + 80026ae: 681b ldr r3, [r3, #0] + 80026b0: 221c movs r2, #28 + 80026b2: 4393 bics r3, r2 + 80026b4: 0019 movs r1, r3 + 80026b6: 687b ldr r3, [r7, #4] + 80026b8: 689a ldr r2, [r3, #8] + 80026ba: 4b51 ldr r3, [pc, #324] @ (8002800 ) + 80026bc: 430a orrs r2, r1 + 80026be: 601a str r2, [r3, #0] #endif /* RCC_CR_SYSDIV */ /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - 800263c: 687b ldr r3, [r7, #4] - 800263e: 685b ldr r3, [r3, #4] - 8002640: 2b01 cmp r3, #1 - 8002642: d107 bne.n 8002654 + 80026c0: 687b ldr r3, [r7, #4] + 80026c2: 685b ldr r3, [r3, #4] + 80026c4: 2b01 cmp r3, #1 + 80026c6: d107 bne.n 80026d8 { /* Check the HSE ready flag */ if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) - 8002644: 4b4d ldr r3, [pc, #308] @ (800277c ) - 8002646: 681a ldr r2, [r3, #0] - 8002648: 2380 movs r3, #128 @ 0x80 - 800264a: 029b lsls r3, r3, #10 - 800264c: 4013 ands r3, r2 - 800264e: d11f bne.n 8002690 + 80026c8: 4b4d ldr r3, [pc, #308] @ (8002800 ) + 80026ca: 681a ldr r2, [r3, #0] + 80026cc: 2380 movs r3, #128 @ 0x80 + 80026ce: 029b lsls r3, r3, #10 + 80026d0: 4013 ands r3, r2 + 80026d2: d11f bne.n 8002714 { return HAL_ERROR; - 8002650: 2301 movs r3, #1 - 8002652: e08b b.n 800276c + 80026d4: 2301 movs r3, #1 + 80026d6: e08b b.n 80027f0 } } /* HSI is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) - 8002654: 687b ldr r3, [r7, #4] - 8002656: 685b ldr r3, [r3, #4] - 8002658: 2b00 cmp r3, #0 - 800265a: d107 bne.n 800266c + 80026d8: 687b ldr r3, [r7, #4] + 80026da: 685b ldr r3, [r3, #4] + 80026dc: 2b00 cmp r3, #0 + 80026de: d107 bne.n 80026f0 { /* Check the HSI ready flag */ if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) - 800265c: 4b47 ldr r3, [pc, #284] @ (800277c ) - 800265e: 681a ldr r2, [r3, #0] - 8002660: 2380 movs r3, #128 @ 0x80 - 8002662: 00db lsls r3, r3, #3 - 8002664: 4013 ands r3, r2 - 8002666: d113 bne.n 8002690 + 80026e0: 4b47 ldr r3, [pc, #284] @ (8002800 ) + 80026e2: 681a ldr r2, [r3, #0] + 80026e4: 2380 movs r3, #128 @ 0x80 + 80026e6: 00db lsls r3, r3, #3 + 80026e8: 4013 ands r3, r2 + 80026ea: d113 bne.n 8002714 { return HAL_ERROR; - 8002668: 2301 movs r3, #1 - 800266a: e07f b.n 800276c + 80026ec: 2301 movs r3, #1 + 80026ee: e07f b.n 80027f0 return HAL_ERROR; } } #endif /* RCC_HSI48_SUPPORT */ /* LSI is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_LSI) - 800266c: 687b ldr r3, [r7, #4] - 800266e: 685b ldr r3, [r3, #4] - 8002670: 2b03 cmp r3, #3 - 8002672: d106 bne.n 8002682 + 80026f0: 687b ldr r3, [r7, #4] + 80026f2: 685b ldr r3, [r3, #4] + 80026f4: 2b03 cmp r3, #3 + 80026f6: d106 bne.n 8002706 { /* Check the LSI ready flag */ if (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) == 0U) - 8002674: 4b41 ldr r3, [pc, #260] @ (800277c ) - 8002676: 6e1b ldr r3, [r3, #96] @ 0x60 - 8002678: 2202 movs r2, #2 - 800267a: 4013 ands r3, r2 - 800267c: d108 bne.n 8002690 + 80026f8: 4b41 ldr r3, [pc, #260] @ (8002800 ) + 80026fa: 6e1b ldr r3, [r3, #96] @ 0x60 + 80026fc: 2202 movs r2, #2 + 80026fe: 4013 ands r3, r2 + 8002700: d108 bne.n 8002714 { return HAL_ERROR; - 800267e: 2301 movs r3, #1 - 8002680: e074 b.n 800276c + 8002702: 2301 movs r3, #1 + 8002704: e074 b.n 80027f0 } /* LSE is selected as System Clock Source */ else { /* Check the LSE ready flag */ if (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U) - 8002682: 4b3e ldr r3, [pc, #248] @ (800277c ) - 8002684: 6ddb ldr r3, [r3, #92] @ 0x5c - 8002686: 2202 movs r2, #2 - 8002688: 4013 ands r3, r2 - 800268a: d101 bne.n 8002690 + 8002706: 4b3e ldr r3, [pc, #248] @ (8002800 ) + 8002708: 6ddb ldr r3, [r3, #92] @ 0x5c + 800270a: 2202 movs r2, #2 + 800270c: 4013 ands r3, r2 + 800270e: d101 bne.n 8002714 { return HAL_ERROR; - 800268c: 2301 movs r3, #1 - 800268e: e06d b.n 800276c + 8002710: 2301 movs r3, #1 + 8002712: e06d b.n 80027f0 } } MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); - 8002690: 4b3a ldr r3, [pc, #232] @ (800277c ) - 8002692: 689b ldr r3, [r3, #8] - 8002694: 2207 movs r2, #7 - 8002696: 4393 bics r3, r2 - 8002698: 0019 movs r1, r3 - 800269a: 687b ldr r3, [r7, #4] - 800269c: 685a ldr r2, [r3, #4] - 800269e: 4b37 ldr r3, [pc, #220] @ (800277c ) - 80026a0: 430a orrs r2, r1 - 80026a2: 609a str r2, [r3, #8] + 8002714: 4b3a ldr r3, [pc, #232] @ (8002800 ) + 8002716: 689b ldr r3, [r3, #8] + 8002718: 2207 movs r2, #7 + 800271a: 4393 bics r3, r2 + 800271c: 0019 movs r1, r3 + 800271e: 687b ldr r3, [r7, #4] + 8002720: 685a ldr r2, [r3, #4] + 8002722: 4b37 ldr r3, [pc, #220] @ (8002800 ) + 8002724: 430a orrs r2, r1 + 8002726: 609a str r2, [r3, #8] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 80026a4: f7ff f846 bl 8001734 - 80026a8: 0003 movs r3, r0 - 80026aa: 60fb str r3, [r7, #12] + 8002728: f7ff f846 bl 80017b8 + 800272c: 0003 movs r3, r0 + 800272e: 60fb str r3, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) - 80026ac: e009 b.n 80026c2 + 8002730: e009 b.n 8002746 { if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE) - 80026ae: f7ff f841 bl 8001734 - 80026b2: 0002 movs r2, r0 - 80026b4: 68fb ldr r3, [r7, #12] - 80026b6: 1ad3 subs r3, r2, r3 - 80026b8: 4a2f ldr r2, [pc, #188] @ (8002778 ) - 80026ba: 4293 cmp r3, r2 - 80026bc: d901 bls.n 80026c2 + 8002732: f7ff f841 bl 80017b8 + 8002736: 0002 movs r2, r0 + 8002738: 68fb ldr r3, [r7, #12] + 800273a: 1ad3 subs r3, r2, r3 + 800273c: 4a2f ldr r2, [pc, #188] @ (80027fc ) + 800273e: 4293 cmp r3, r2 + 8002740: d901 bls.n 8002746 { return HAL_TIMEOUT; - 80026be: 2303 movs r3, #3 - 80026c0: e054 b.n 800276c + 8002742: 2303 movs r3, #3 + 8002744: e054 b.n 80027f0 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) - 80026c2: 4b2e ldr r3, [pc, #184] @ (800277c ) - 80026c4: 689b ldr r3, [r3, #8] - 80026c6: 2238 movs r2, #56 @ 0x38 - 80026c8: 401a ands r2, r3 - 80026ca: 687b ldr r3, [r7, #4] - 80026cc: 685b ldr r3, [r3, #4] - 80026ce: 00db lsls r3, r3, #3 - 80026d0: 429a cmp r2, r3 - 80026d2: d1ec bne.n 80026ae + 8002746: 4b2e ldr r3, [pc, #184] @ (8002800 ) + 8002748: 689b ldr r3, [r3, #8] + 800274a: 2238 movs r2, #56 @ 0x38 + 800274c: 401a ands r2, r3 + 800274e: 687b ldr r3, [r7, #4] + 8002750: 685b ldr r3, [r3, #4] + 8002752: 00db lsls r3, r3, #3 + 8002754: 429a cmp r2, r3 + 8002756: d1ec bne.n 8002732 } } } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) - 80026d4: 4b27 ldr r3, [pc, #156] @ (8002774 ) - 80026d6: 681b ldr r3, [r3, #0] - 80026d8: 2207 movs r2, #7 - 80026da: 4013 ands r3, r2 - 80026dc: 683a ldr r2, [r7, #0] - 80026de: 429a cmp r2, r3 - 80026e0: d21e bcs.n 8002720 + 8002758: 4b27 ldr r3, [pc, #156] @ (80027f8 ) + 800275a: 681b ldr r3, [r3, #0] + 800275c: 2207 movs r2, #7 + 800275e: 4013 ands r3, r2 + 8002760: 683a ldr r2, [r7, #0] + 8002762: 429a cmp r2, r3 + 8002764: d21e bcs.n 80027a4 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); - 80026e2: 4b24 ldr r3, [pc, #144] @ (8002774 ) - 80026e4: 681b ldr r3, [r3, #0] - 80026e6: 2207 movs r2, #7 - 80026e8: 4393 bics r3, r2 - 80026ea: 0019 movs r1, r3 - 80026ec: 4b21 ldr r3, [pc, #132] @ (8002774 ) - 80026ee: 683a ldr r2, [r7, #0] - 80026f0: 430a orrs r2, r1 - 80026f2: 601a str r2, [r3, #0] + 8002766: 4b24 ldr r3, [pc, #144] @ (80027f8 ) + 8002768: 681b ldr r3, [r3, #0] + 800276a: 2207 movs r2, #7 + 800276c: 4393 bics r3, r2 + 800276e: 0019 movs r1, r3 + 8002770: 4b21 ldr r3, [pc, #132] @ (80027f8 ) + 8002772: 683a ldr r2, [r7, #0] + 8002774: 430a orrs r2, r1 + 8002776: 601a str r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by polling the FLASH_ACR register */ tickstart = HAL_GetTick(); - 80026f4: f7ff f81e bl 8001734 - 80026f8: 0003 movs r3, r0 - 80026fa: 60fb str r3, [r7, #12] + 8002778: f7ff f81e bl 80017b8 + 800277c: 0003 movs r3, r0 + 800277e: 60fb str r3, [r7, #12] while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) - 80026fc: e009 b.n 8002712 + 8002780: e009 b.n 8002796 { if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE) - 80026fe: f7ff f819 bl 8001734 - 8002702: 0002 movs r2, r0 - 8002704: 68fb ldr r3, [r7, #12] - 8002706: 1ad3 subs r3, r2, r3 - 8002708: 4a1b ldr r2, [pc, #108] @ (8002778 ) - 800270a: 4293 cmp r3, r2 - 800270c: d901 bls.n 8002712 + 8002782: f7ff f819 bl 80017b8 + 8002786: 0002 movs r2, r0 + 8002788: 68fb ldr r3, [r7, #12] + 800278a: 1ad3 subs r3, r2, r3 + 800278c: 4a1b ldr r2, [pc, #108] @ (80027fc ) + 800278e: 4293 cmp r3, r2 + 8002790: d901 bls.n 8002796 { return HAL_TIMEOUT; - 800270e: 2303 movs r3, #3 - 8002710: e02c b.n 800276c + 8002792: 2303 movs r3, #3 + 8002794: e02c b.n 80027f0 while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) - 8002712: 4b18 ldr r3, [pc, #96] @ (8002774 ) - 8002714: 681b ldr r3, [r3, #0] - 8002716: 2207 movs r2, #7 - 8002718: 4013 ands r3, r2 - 800271a: 683a ldr r2, [r7, #0] - 800271c: 429a cmp r2, r3 - 800271e: d1ee bne.n 80026fe + 8002796: 4b18 ldr r3, [pc, #96] @ (80027f8 ) + 8002798: 681b ldr r3, [r3, #0] + 800279a: 2207 movs r2, #7 + 800279c: 4013 ands r3, r2 + 800279e: 683a ldr r2, [r7, #0] + 80027a0: 429a cmp r2, r3 + 80027a2: d1ee bne.n 8002782 } } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - 8002720: 687b ldr r3, [r7, #4] - 8002722: 681b ldr r3, [r3, #0] - 8002724: 2204 movs r2, #4 - 8002726: 4013 ands r3, r2 - 8002728: d009 beq.n 800273e + 80027a4: 687b ldr r3, [r7, #4] + 80027a6: 681b ldr r3, [r3, #0] + 80027a8: 2204 movs r2, #4 + 80027aa: 4013 ands r3, r2 + 80027ac: d009 beq.n 80027c2 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider); - 800272a: 4b14 ldr r3, [pc, #80] @ (800277c ) - 800272c: 689b ldr r3, [r3, #8] - 800272e: 4a16 ldr r2, [pc, #88] @ (8002788 ) - 8002730: 4013 ands r3, r2 - 8002732: 0019 movs r1, r3 - 8002734: 687b ldr r3, [r7, #4] - 8002736: 691a ldr r2, [r3, #16] - 8002738: 4b10 ldr r3, [pc, #64] @ (800277c ) - 800273a: 430a orrs r2, r1 - 800273c: 609a str r2, [r3, #8] + 80027ae: 4b14 ldr r3, [pc, #80] @ (8002800 ) + 80027b0: 689b ldr r3, [r3, #8] + 80027b2: 4a16 ldr r2, [pc, #88] @ (800280c ) + 80027b4: 4013 ands r3, r2 + 80027b6: 0019 movs r1, r3 + 80027b8: 687b ldr r3, [r7, #4] + 80027ba: 691a ldr r2, [r3, #16] + 80027bc: 4b10 ldr r3, [pc, #64] @ (8002800 ) + 80027be: 430a orrs r2, r1 + 80027c0: 609a str r2, [r3, #8] } /* Update the SystemCoreClock global variable */ SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \ - 800273e: f000 f82b bl 8002798 - 8002742: 0001 movs r1, r0 - 8002744: 4b0d ldr r3, [pc, #52] @ (800277c ) - 8002746: 689b ldr r3, [r3, #8] + 80027c2: f000 f82b bl 800281c + 80027c6: 0001 movs r1, r0 + 80027c8: 4b0d ldr r3, [pc, #52] @ (8002800 ) + 80027ca: 689b ldr r3, [r3, #8] >> RCC_CFGR_HPRE_Pos]) & 0x1FU)); - 8002748: 0a1b lsrs r3, r3, #8 - 800274a: 220f movs r2, #15 - 800274c: 401a ands r2, r3 + 80027cc: 0a1b lsrs r3, r3, #8 + 80027ce: 220f movs r2, #15 + 80027d0: 401a ands r2, r3 SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \ - 800274e: 4b0f ldr r3, [pc, #60] @ (800278c ) - 8002750: 0092 lsls r2, r2, #2 - 8002752: 58d3 ldr r3, [r2, r3] + 80027d2: 4b0f ldr r3, [pc, #60] @ (8002810 ) + 80027d4: 0092 lsls r2, r2, #2 + 80027d6: 58d3 ldr r3, [r2, r3] >> RCC_CFGR_HPRE_Pos]) & 0x1FU)); - 8002754: 221f movs r2, #31 - 8002756: 4013 ands r3, r2 + 80027d8: 221f movs r2, #31 + 80027da: 4013 ands r3, r2 SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \ - 8002758: 000a movs r2, r1 - 800275a: 40da lsrs r2, r3 - 800275c: 4b0c ldr r3, [pc, #48] @ (8002790 ) - 800275e: 601a str r2, [r3, #0] + 80027dc: 000a movs r2, r1 + 80027de: 40da lsrs r2, r3 + 80027e0: 4b0c ldr r3, [pc, #48] @ (8002814 ) + 80027e2: 601a str r2, [r3, #0] /* Configure the source of time base considering new system clocks settings*/ return HAL_InitTick(uwTickPrio); - 8002760: 4b0c ldr r3, [pc, #48] @ (8002794 ) - 8002762: 681b ldr r3, [r3, #0] - 8002764: 0018 movs r0, r3 - 8002766: f7fe ff89 bl 800167c - 800276a: 0003 movs r3, r0 + 80027e4: 4b0c ldr r3, [pc, #48] @ (8002818 ) + 80027e6: 681b ldr r3, [r3, #0] + 80027e8: 0018 movs r0, r3 + 80027ea: f7fe ff89 bl 8001700 + 80027ee: 0003 movs r3, r0 } - 800276c: 0018 movs r0, r3 - 800276e: 46bd mov sp, r7 - 8002770: b004 add sp, #16 - 8002772: bd80 pop {r7, pc} - 8002774: 40022000 .word 0x40022000 - 8002778: 00001388 .word 0x00001388 - 800277c: 40021000 .word 0x40021000 - 8002780: ffff84ff .word 0xffff84ff - 8002784: fffff0ff .word 0xfffff0ff - 8002788: ffff8fff .word 0xffff8fff - 800278c: 08004dbc .word 0x08004dbc - 8002790: 20000018 .word 0x20000018 - 8002794: 2000001c .word 0x2000001c + 80027f0: 0018 movs r0, r3 + 80027f2: 46bd mov sp, r7 + 80027f4: b004 add sp, #16 + 80027f6: bd80 pop {r7, pc} + 80027f8: 40022000 .word 0x40022000 + 80027fc: 00001388 .word 0x00001388 + 8002800: 40021000 .word 0x40021000 + 8002804: ffff84ff .word 0xffff84ff + 8002808: fffff0ff .word 0xfffff0ff + 800280c: ffff8fff .word 0xffff8fff + 8002810: 08004e40 .word 0x08004e40 + 8002814: 20000018 .word 0x20000018 + 8002818: 2000001c .word 0x2000001c -08002798 : +0800281c : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { - 8002798: b580 push {r7, lr} - 800279a: b084 sub sp, #16 - 800279c: af00 add r7, sp, #0 + 800281c: b580 push {r7, lr} + 800281e: b084 sub sp, #16 + 8002820: af00 add r7, sp, #0 uint32_t hsidiv; uint32_t sysclockfreq; #if defined(RCC_CR_SYSDIV) uint32_t sysclockdiv = (uint32_t)(((RCC->CR & RCC_CR_SYSDIV) >> RCC_CR_SYSDIV_Pos) + 1U); - 800279e: 4b23 ldr r3, [pc, #140] @ (800282c ) - 80027a0: 681b ldr r3, [r3, #0] - 80027a2: 089b lsrs r3, r3, #2 - 80027a4: 2207 movs r2, #7 - 80027a6: 4013 ands r3, r2 - 80027a8: 3301 adds r3, #1 - 80027aa: 60bb str r3, [r7, #8] + 8002822: 4b23 ldr r3, [pc, #140] @ (80028b0 ) + 8002824: 681b ldr r3, [r3, #0] + 8002826: 089b lsrs r3, r3, #2 + 8002828: 2207 movs r2, #7 + 800282a: 4013 ands r3, r2 + 800282c: 3301 adds r3, #1 + 800282e: 60bb str r3, [r7, #8] #endif /* RCC_CR_SYSDIV */ if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) - 80027ac: 4b1f ldr r3, [pc, #124] @ (800282c ) - 80027ae: 689b ldr r3, [r3, #8] - 80027b0: 2238 movs r2, #56 @ 0x38 - 80027b2: 4013 ands r3, r2 - 80027b4: d10f bne.n 80027d6 + 8002830: 4b1f ldr r3, [pc, #124] @ (80028b0 ) + 8002832: 689b ldr r3, [r3, #8] + 8002834: 2238 movs r2, #56 @ 0x38 + 8002836: 4013 ands r3, r2 + 8002838: d10f bne.n 800285a { /* HSISYS can be derived for HSI48 */ hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos)); - 80027b6: 4b1d ldr r3, [pc, #116] @ (800282c ) - 80027b8: 681b ldr r3, [r3, #0] - 80027ba: 0adb lsrs r3, r3, #11 - 80027bc: 2207 movs r2, #7 - 80027be: 4013 ands r3, r2 - 80027c0: 2201 movs r2, #1 - 80027c2: 409a lsls r2, r3 - 80027c4: 0013 movs r3, r2 - 80027c6: 607b str r3, [r7, #4] + 800283a: 4b1d ldr r3, [pc, #116] @ (80028b0 ) + 800283c: 681b ldr r3, [r3, #0] + 800283e: 0adb lsrs r3, r3, #11 + 8002840: 2207 movs r2, #7 + 8002842: 4013 ands r3, r2 + 8002844: 2201 movs r2, #1 + 8002846: 409a lsls r2, r3 + 8002848: 0013 movs r3, r2 + 800284a: 607b str r3, [r7, #4] /* HSI used as system clock source */ sysclockfreq = (HSI_VALUE / hsidiv); - 80027c8: 6879 ldr r1, [r7, #4] - 80027ca: 4819 ldr r0, [pc, #100] @ (8002830 ) - 80027cc: f7fd fc9c bl 8000108 <__udivsi3> - 80027d0: 0003 movs r3, r0 - 80027d2: 60fb str r3, [r7, #12] - 80027d4: e01e b.n 8002814 + 800284c: 6879 ldr r1, [r7, #4] + 800284e: 4819 ldr r0, [pc, #100] @ (80028b4 ) + 8002850: f7fd fc5a bl 8000108 <__udivsi3> + 8002854: 0003 movs r3, r0 + 8002856: 60fb str r3, [r7, #12] + 8002858: e01e b.n 8002898 } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) - 80027d6: 4b15 ldr r3, [pc, #84] @ (800282c ) - 80027d8: 689b ldr r3, [r3, #8] - 80027da: 2238 movs r2, #56 @ 0x38 - 80027dc: 4013 ands r3, r2 - 80027de: 2b08 cmp r3, #8 - 80027e0: d102 bne.n 80027e8 + 800285a: 4b15 ldr r3, [pc, #84] @ (80028b0 ) + 800285c: 689b ldr r3, [r3, #8] + 800285e: 2238 movs r2, #56 @ 0x38 + 8002860: 4013 ands r3, r2 + 8002862: 2b08 cmp r3, #8 + 8002864: d102 bne.n 800286c { /* HSE used as system clock source */ sysclockfreq = HSE_VALUE; - 80027e2: 4b14 ldr r3, [pc, #80] @ (8002834 ) - 80027e4: 60fb str r3, [r7, #12] - 80027e6: e015 b.n 8002814 + 8002866: 4b14 ldr r3, [pc, #80] @ (80028b8 ) + 8002868: 60fb str r3, [r7, #12] + 800286a: e015 b.n 8002898 } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSE) - 80027e8: 4b10 ldr r3, [pc, #64] @ (800282c ) - 80027ea: 689b ldr r3, [r3, #8] - 80027ec: 2238 movs r2, #56 @ 0x38 - 80027ee: 4013 ands r3, r2 - 80027f0: 2b20 cmp r3, #32 - 80027f2: d103 bne.n 80027fc + 800286c: 4b10 ldr r3, [pc, #64] @ (80028b0 ) + 800286e: 689b ldr r3, [r3, #8] + 8002870: 2238 movs r2, #56 @ 0x38 + 8002872: 4013 ands r3, r2 + 8002874: 2b20 cmp r3, #32 + 8002876: d103 bne.n 8002880 { /* LSE used as system clock source */ sysclockfreq = LSE_VALUE; - 80027f4: 2380 movs r3, #128 @ 0x80 - 80027f6: 021b lsls r3, r3, #8 - 80027f8: 60fb str r3, [r7, #12] - 80027fa: e00b b.n 8002814 + 8002878: 2380 movs r3, #128 @ 0x80 + 800287a: 021b lsls r3, r3, #8 + 800287c: 60fb str r3, [r7, #12] + 800287e: e00b b.n 8002898 } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSI) - 80027fc: 4b0b ldr r3, [pc, #44] @ (800282c ) - 80027fe: 689b ldr r3, [r3, #8] - 8002800: 2238 movs r2, #56 @ 0x38 - 8002802: 4013 ands r3, r2 - 8002804: 2b18 cmp r3, #24 - 8002806: d103 bne.n 8002810 + 8002880: 4b0b ldr r3, [pc, #44] @ (80028b0 ) + 8002882: 689b ldr r3, [r3, #8] + 8002884: 2238 movs r2, #56 @ 0x38 + 8002886: 4013 ands r3, r2 + 8002888: 2b18 cmp r3, #24 + 800288a: d103 bne.n 8002894 { /* LSI used as system clock source */ sysclockfreq = LSI_VALUE; - 8002808: 23fa movs r3, #250 @ 0xfa - 800280a: 01db lsls r3, r3, #7 - 800280c: 60fb str r3, [r7, #12] - 800280e: e001 b.n 8002814 + 800288c: 23fa movs r3, #250 @ 0xfa + 800288e: 01db lsls r3, r3, #7 + 8002890: 60fb str r3, [r7, #12] + 8002892: e001 b.n 8002898 sysclockfreq = HSI48_VALUE; } #endif /* RCC_HSI48_SUPPORT */ else { sysclockfreq = 0U; - 8002810: 2300 movs r3, #0 - 8002812: 60fb str r3, [r7, #12] + 8002894: 2300 movs r3, #0 + 8002896: 60fb str r3, [r7, #12] } #if defined(RCC_CR_SYSDIV) sysclockfreq = sysclockfreq / sysclockdiv; - 8002814: 68b9 ldr r1, [r7, #8] - 8002816: 68f8 ldr r0, [r7, #12] - 8002818: f7fd fc76 bl 8000108 <__udivsi3> - 800281c: 0003 movs r3, r0 - 800281e: 60fb str r3, [r7, #12] + 8002898: 68b9 ldr r1, [r7, #8] + 800289a: 68f8 ldr r0, [r7, #12] + 800289c: f7fd fc34 bl 8000108 <__udivsi3> + 80028a0: 0003 movs r3, r0 + 80028a2: 60fb str r3, [r7, #12] #endif /* RCC_CR_SYSDIV */ return sysclockfreq; - 8002820: 68fb ldr r3, [r7, #12] + 80028a4: 68fb ldr r3, [r7, #12] } - 8002822: 0018 movs r0, r3 - 8002824: 46bd mov sp, r7 - 8002826: b004 add sp, #16 - 8002828: bd80 pop {r7, pc} - 800282a: 46c0 nop @ (mov r8, r8) - 800282c: 40021000 .word 0x40021000 - 8002830: 02dc6c00 .word 0x02dc6c00 - 8002834: 007a1200 .word 0x007a1200 + 80028a6: 0018 movs r0, r3 + 80028a8: 46bd mov sp, r7 + 80028aa: b004 add sp, #16 + 80028ac: bd80 pop {r7, pc} + 80028ae: 46c0 nop @ (mov r8, r8) + 80028b0: 40021000 .word 0x40021000 + 80028b4: 02dc6c00 .word 0x02dc6c00 + 80028b8: 007a1200 .word 0x007a1200 -08002838 : +080028bc : * * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. * @retval HCLK frequency in Hz */ uint32_t HAL_RCC_GetHCLKFreq(void) { - 8002838: b580 push {r7, lr} - 800283a: af00 add r7, sp, #0 + 80028bc: b580 push {r7, lr} + 80028be: af00 add r7, sp, #0 SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \ - 800283c: f7ff ffac bl 8002798 - 8002840: 0001 movs r1, r0 - 8002842: 4b09 ldr r3, [pc, #36] @ (8002868 ) - 8002844: 689b ldr r3, [r3, #8] + 80028c0: f7ff ffac bl 800281c + 80028c4: 0001 movs r1, r0 + 80028c6: 4b09 ldr r3, [pc, #36] @ (80028ec ) + 80028c8: 689b ldr r3, [r3, #8] >> RCC_CFGR_HPRE_Pos]) & 0x1FU)); - 8002846: 0a1b lsrs r3, r3, #8 - 8002848: 220f movs r2, #15 - 800284a: 401a ands r2, r3 + 80028ca: 0a1b lsrs r3, r3, #8 + 80028cc: 220f movs r2, #15 + 80028ce: 401a ands r2, r3 SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \ - 800284c: 4b07 ldr r3, [pc, #28] @ (800286c ) - 800284e: 0092 lsls r2, r2, #2 - 8002850: 58d3 ldr r3, [r2, r3] + 80028d0: 4b07 ldr r3, [pc, #28] @ (80028f0 ) + 80028d2: 0092 lsls r2, r2, #2 + 80028d4: 58d3 ldr r3, [r2, r3] >> RCC_CFGR_HPRE_Pos]) & 0x1FU)); - 8002852: 221f movs r2, #31 - 8002854: 4013 ands r3, r2 + 80028d6: 221f movs r2, #31 + 80028d8: 4013 ands r3, r2 SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \ - 8002856: 000a movs r2, r1 - 8002858: 40da lsrs r2, r3 - 800285a: 4b05 ldr r3, [pc, #20] @ (8002870 ) - 800285c: 601a str r2, [r3, #0] + 80028da: 000a movs r2, r1 + 80028dc: 40da lsrs r2, r3 + 80028de: 4b05 ldr r3, [pc, #20] @ (80028f4 ) + 80028e0: 601a str r2, [r3, #0] return SystemCoreClock; - 800285e: 4b04 ldr r3, [pc, #16] @ (8002870 ) - 8002860: 681b ldr r3, [r3, #0] + 80028e2: 4b04 ldr r3, [pc, #16] @ (80028f4 ) + 80028e4: 681b ldr r3, [r3, #0] } - 8002862: 0018 movs r0, r3 - 8002864: 46bd mov sp, r7 - 8002866: bd80 pop {r7, pc} - 8002868: 40021000 .word 0x40021000 - 800286c: 08004dbc .word 0x08004dbc - 8002870: 20000018 .word 0x20000018 + 80028e6: 0018 movs r0, r3 + 80028e8: 46bd mov sp, r7 + 80028ea: bd80 pop {r7, pc} + 80028ec: 40021000 .word 0x40021000 + 80028f0: 08004e40 .word 0x08004e40 + 80028f4: 20000018 .word 0x20000018 -08002874 : +080028f8 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency in Hz */ uint32_t HAL_RCC_GetPCLK1Freq(void) { - 8002874: b580 push {r7, lr} - 8002876: af00 add r7, sp, #0 + 80028f8: b580 push {r7, lr} + 80028fa: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> ((APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE) >> RCC_CFGR_PPRE_Pos]) & 0x1FU)); - 8002878: f7ff ffde bl 8002838 - 800287c: 0001 movs r1, r0 - 800287e: 4b07 ldr r3, [pc, #28] @ (800289c ) - 8002880: 689b ldr r3, [r3, #8] - 8002882: 0b1b lsrs r3, r3, #12 - 8002884: 2207 movs r2, #7 - 8002886: 401a ands r2, r3 - 8002888: 4b05 ldr r3, [pc, #20] @ (80028a0 ) - 800288a: 0092 lsls r2, r2, #2 - 800288c: 58d3 ldr r3, [r2, r3] - 800288e: 221f movs r2, #31 - 8002890: 4013 ands r3, r2 - 8002892: 40d9 lsrs r1, r3 - 8002894: 000b movs r3, r1 + 80028fc: f7ff ffde bl 80028bc + 8002900: 0001 movs r1, r0 + 8002902: 4b07 ldr r3, [pc, #28] @ (8002920 ) + 8002904: 689b ldr r3, [r3, #8] + 8002906: 0b1b lsrs r3, r3, #12 + 8002908: 2207 movs r2, #7 + 800290a: 401a ands r2, r3 + 800290c: 4b05 ldr r3, [pc, #20] @ (8002924 ) + 800290e: 0092 lsls r2, r2, #2 + 8002910: 58d3 ldr r3, [r2, r3] + 8002912: 221f movs r2, #31 + 8002914: 4013 ands r3, r2 + 8002916: 40d9 lsrs r1, r3 + 8002918: 000b movs r3, r1 } - 8002896: 0018 movs r0, r3 - 8002898: 46bd mov sp, r7 - 800289a: bd80 pop {r7, pc} - 800289c: 40021000 .word 0x40021000 - 80028a0: 08004dfc .word 0x08004dfc + 800291a: 0018 movs r0, r3 + 800291c: 46bd mov sp, r7 + 800291e: bd80 pop {r7, pc} + 8002920: 40021000 .word 0x40021000 + 8002924: 08004e80 .word 0x08004e80 -080028a4 : +08002928 : * @note (*) not available on all devices * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *PeriphClkInit) { - 80028a4: b580 push {r7, lr} - 80028a6: b086 sub sp, #24 - 80028a8: af00 add r7, sp, #0 - 80028aa: 6078 str r0, [r7, #4] + 8002928: b580 push {r7, lr} + 800292a: b086 sub sp, #24 + 800292c: af00 add r7, sp, #0 + 800292e: 6078 str r0, [r7, #4] uint32_t tmpregister; uint32_t tickstart; HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ - 80028ac: 2313 movs r3, #19 - 80028ae: 18fb adds r3, r7, r3 - 80028b0: 2200 movs r2, #0 - 80028b2: 701a strb r2, [r3, #0] + 8002930: 2313 movs r3, #19 + 8002932: 18fb adds r3, r7, r3 + 8002934: 2200 movs r2, #0 + 8002936: 701a strb r2, [r3, #0] HAL_StatusTypeDef status = HAL_OK; /* Final status */ - 80028b4: 2312 movs r3, #18 - 80028b6: 18fb adds r3, r7, r3 - 80028b8: 2200 movs r2, #0 - 80028ba: 701a strb r2, [r3, #0] + 8002938: 2312 movs r3, #18 + 800293a: 18fb adds r3, r7, r3 + 800293c: 2200 movs r2, #0 + 800293e: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*-------------------------- RTC clock source configuration ----------------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) - 80028bc: 687b ldr r3, [r7, #4] - 80028be: 681b ldr r3, [r3, #0] - 80028c0: 2240 movs r2, #64 @ 0x40 - 80028c2: 4013 ands r3, r2 - 80028c4: d100 bne.n 80028c8 - 80028c6: e079 b.n 80029bc + 8002940: 687b ldr r3, [r7, #4] + 8002942: 681b ldr r3, [r3, #0] + 8002944: 2240 movs r2, #64 @ 0x40 + 8002946: 4013 ands r3, r2 + 8002948: d100 bne.n 800294c + 800294a: e079 b.n 8002a40 { FlagStatus pwrclkchanged = RESET; - 80028c8: 2011 movs r0, #17 - 80028ca: 183b adds r3, r7, r0 - 80028cc: 2200 movs r2, #0 - 80028ce: 701a strb r2, [r3, #0] + 800294c: 2011 movs r0, #17 + 800294e: 183b adds r3, r7, r0 + 8002950: 2200 movs r2, #0 + 8002952: 701a strb r2, [r3, #0] /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable Power Clock */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) - 80028d0: 4b63 ldr r3, [pc, #396] @ (8002a60 ) - 80028d2: 6bda ldr r2, [r3, #60] @ 0x3c - 80028d4: 2380 movs r3, #128 @ 0x80 - 80028d6: 055b lsls r3, r3, #21 - 80028d8: 4013 ands r3, r2 - 80028da: d110 bne.n 80028fe + 8002954: 4b63 ldr r3, [pc, #396] @ (8002ae4 ) + 8002956: 6bda ldr r2, [r3, #60] @ 0x3c + 8002958: 2380 movs r3, #128 @ 0x80 + 800295a: 055b lsls r3, r3, #21 + 800295c: 4013 ands r3, r2 + 800295e: d110 bne.n 8002982 { __HAL_RCC_PWR_CLK_ENABLE(); - 80028dc: 4b60 ldr r3, [pc, #384] @ (8002a60 ) - 80028de: 6bda ldr r2, [r3, #60] @ 0x3c - 80028e0: 4b5f ldr r3, [pc, #380] @ (8002a60 ) - 80028e2: 2180 movs r1, #128 @ 0x80 - 80028e4: 0549 lsls r1, r1, #21 - 80028e6: 430a orrs r2, r1 - 80028e8: 63da str r2, [r3, #60] @ 0x3c - 80028ea: 4b5d ldr r3, [pc, #372] @ (8002a60 ) - 80028ec: 6bda ldr r2, [r3, #60] @ 0x3c - 80028ee: 2380 movs r3, #128 @ 0x80 - 80028f0: 055b lsls r3, r3, #21 - 80028f2: 4013 ands r3, r2 - 80028f4: 60bb str r3, [r7, #8] - 80028f6: 68bb ldr r3, [r7, #8] + 8002960: 4b60 ldr r3, [pc, #384] @ (8002ae4 ) + 8002962: 6bda ldr r2, [r3, #60] @ 0x3c + 8002964: 4b5f ldr r3, [pc, #380] @ (8002ae4 ) + 8002966: 2180 movs r1, #128 @ 0x80 + 8002968: 0549 lsls r1, r1, #21 + 800296a: 430a orrs r2, r1 + 800296c: 63da str r2, [r3, #60] @ 0x3c + 800296e: 4b5d ldr r3, [pc, #372] @ (8002ae4 ) + 8002970: 6bda ldr r2, [r3, #60] @ 0x3c + 8002972: 2380 movs r3, #128 @ 0x80 + 8002974: 055b lsls r3, r3, #21 + 8002976: 4013 ands r3, r2 + 8002978: 60bb str r3, [r7, #8] + 800297a: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; - 80028f8: 183b adds r3, r7, r0 - 80028fa: 2201 movs r2, #1 - 80028fc: 701a strb r2, [r3, #0] + 800297c: 183b adds r3, r7, r0 + 800297e: 2201 movs r2, #1 + 8002980: 701a strb r2, [r3, #0] } /* Reset the RTC domain only if the RTC Clock source selection is modified from default */ tmpregister = READ_BIT(RCC->CSR1, RCC_CSR1_RTCSEL); - 80028fe: 4b58 ldr r3, [pc, #352] @ (8002a60 ) - 8002900: 6dda ldr r2, [r3, #92] @ 0x5c - 8002902: 23c0 movs r3, #192 @ 0xc0 - 8002904: 009b lsls r3, r3, #2 - 8002906: 4013 ands r3, r2 - 8002908: 617b str r3, [r7, #20] + 8002982: 4b58 ldr r3, [pc, #352] @ (8002ae4 ) + 8002984: 6dda ldr r2, [r3, #92] @ 0x5c + 8002986: 23c0 movs r3, #192 @ 0xc0 + 8002988: 009b lsls r3, r3, #2 + 800298a: 4013 ands r3, r2 + 800298c: 617b str r3, [r7, #20] /* Reset the RTC domain only if the RTC Clock source selection is modified */ if ((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection)) - 800290a: 697b ldr r3, [r7, #20] - 800290c: 2b00 cmp r3, #0 - 800290e: d019 beq.n 8002944 - 8002910: 687b ldr r3, [r7, #4] - 8002912: 699b ldr r3, [r3, #24] - 8002914: 697a ldr r2, [r7, #20] - 8002916: 429a cmp r2, r3 - 8002918: d014 beq.n 8002944 + 800298e: 697b ldr r3, [r7, #20] + 8002990: 2b00 cmp r3, #0 + 8002992: d019 beq.n 80029c8 + 8002994: 687b ldr r3, [r7, #4] + 8002996: 699b ldr r3, [r3, #24] + 8002998: 697a ldr r2, [r7, #20] + 800299a: 429a cmp r2, r3 + 800299c: d014 beq.n 80029c8 { /* Store the content of CSR1 register before the reset of RTC Domain */ tmpregister = READ_BIT(RCC->CSR1, ~(RCC_CSR1_RTCSEL)); - 800291a: 4b51 ldr r3, [pc, #324] @ (8002a60 ) - 800291c: 6ddb ldr r3, [r3, #92] @ 0x5c - 800291e: 4a51 ldr r2, [pc, #324] @ (8002a64 ) - 8002920: 4013 ands r3, r2 - 8002922: 617b str r3, [r7, #20] + 800299e: 4b51 ldr r3, [pc, #324] @ (8002ae4 ) + 80029a0: 6ddb ldr r3, [r3, #92] @ 0x5c + 80029a2: 4a51 ldr r2, [pc, #324] @ (8002ae8 ) + 80029a4: 4013 ands r3, r2 + 80029a6: 617b str r3, [r7, #20] /* RTC Clock selection can be changed only if the RTC Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); - 8002924: 4b4e ldr r3, [pc, #312] @ (8002a60 ) - 8002926: 6dda ldr r2, [r3, #92] @ 0x5c - 8002928: 4b4d ldr r3, [pc, #308] @ (8002a60 ) - 800292a: 2180 movs r1, #128 @ 0x80 - 800292c: 0249 lsls r1, r1, #9 - 800292e: 430a orrs r2, r1 - 8002930: 65da str r2, [r3, #92] @ 0x5c + 80029a8: 4b4e ldr r3, [pc, #312] @ (8002ae4 ) + 80029aa: 6dda ldr r2, [r3, #92] @ 0x5c + 80029ac: 4b4d ldr r3, [pc, #308] @ (8002ae4 ) + 80029ae: 2180 movs r1, #128 @ 0x80 + 80029b0: 0249 lsls r1, r1, #9 + 80029b2: 430a orrs r2, r1 + 80029b4: 65da str r2, [r3, #92] @ 0x5c __HAL_RCC_BACKUPRESET_RELEASE(); - 8002932: 4b4b ldr r3, [pc, #300] @ (8002a60 ) - 8002934: 6dda ldr r2, [r3, #92] @ 0x5c - 8002936: 4b4a ldr r3, [pc, #296] @ (8002a60 ) - 8002938: 494b ldr r1, [pc, #300] @ (8002a68 ) - 800293a: 400a ands r2, r1 - 800293c: 65da str r2, [r3, #92] @ 0x5c + 80029b6: 4b4b ldr r3, [pc, #300] @ (8002ae4 ) + 80029b8: 6dda ldr r2, [r3, #92] @ 0x5c + 80029ba: 4b4a ldr r3, [pc, #296] @ (8002ae4 ) + 80029bc: 494b ldr r1, [pc, #300] @ (8002aec ) + 80029be: 400a ands r2, r1 + 80029c0: 65da str r2, [r3, #92] @ 0x5c /* Restore the Content of CSR1 register */ RCC->CSR1 = tmpregister; - 800293e: 4b48 ldr r3, [pc, #288] @ (8002a60 ) - 8002940: 697a ldr r2, [r7, #20] - 8002942: 65da str r2, [r3, #92] @ 0x5c + 80029c2: 4b48 ldr r3, [pc, #288] @ (8002ae4 ) + 80029c4: 697a ldr r2, [r7, #20] + 80029c6: 65da str r2, [r3, #92] @ 0x5c } /* Wait for LSE reactivation if LSE was enable prior to RTC Domain reset */ if (HAL_IS_BIT_SET(tmpregister, RCC_CSR1_LSEON)) - 8002944: 697b ldr r3, [r7, #20] - 8002946: 2201 movs r2, #1 - 8002948: 4013 ands r3, r2 - 800294a: d016 beq.n 800297a + 80029c8: 697b ldr r3, [r7, #20] + 80029ca: 2201 movs r2, #1 + 80029cc: 4013 ands r3, r2 + 80029ce: d016 beq.n 80029fe { /* Get Start Tick*/ tickstart = HAL_GetTick(); - 800294c: f7fe fef2 bl 8001734 - 8002950: 0003 movs r3, r0 - 8002952: 60fb str r3, [r7, #12] + 80029d0: f7fe fef2 bl 80017b8 + 80029d4: 0003 movs r3, r0 + 80029d6: 60fb str r3, [r7, #12] /* Wait till LSE is ready */ while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U) - 8002954: e00c b.n 8002970 + 80029d8: e00c b.n 80029f4 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - 8002956: f7fe feed bl 8001734 - 800295a: 0002 movs r2, r0 - 800295c: 68fb ldr r3, [r7, #12] - 800295e: 1ad3 subs r3, r2, r3 - 8002960: 4a42 ldr r2, [pc, #264] @ (8002a6c ) - 8002962: 4293 cmp r3, r2 - 8002964: d904 bls.n 8002970 + 80029da: f7fe feed bl 80017b8 + 80029de: 0002 movs r2, r0 + 80029e0: 68fb ldr r3, [r7, #12] + 80029e2: 1ad3 subs r3, r2, r3 + 80029e4: 4a42 ldr r2, [pc, #264] @ (8002af0 ) + 80029e6: 4293 cmp r3, r2 + 80029e8: d904 bls.n 80029f4 { ret = HAL_TIMEOUT; - 8002966: 2313 movs r3, #19 - 8002968: 18fb adds r3, r7, r3 - 800296a: 2203 movs r2, #3 - 800296c: 701a strb r2, [r3, #0] + 80029ea: 2313 movs r3, #19 + 80029ec: 18fb adds r3, r7, r3 + 80029ee: 2203 movs r2, #3 + 80029f0: 701a strb r2, [r3, #0] break; - 800296e: e004 b.n 800297a + 80029f2: e004 b.n 80029fe while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U) - 8002970: 4b3b ldr r3, [pc, #236] @ (8002a60 ) - 8002972: 6ddb ldr r3, [r3, #92] @ 0x5c - 8002974: 2202 movs r2, #2 - 8002976: 4013 ands r3, r2 - 8002978: d0ed beq.n 8002956 + 80029f4: 4b3b ldr r3, [pc, #236] @ (8002ae4 ) + 80029f6: 6ddb ldr r3, [r3, #92] @ 0x5c + 80029f8: 2202 movs r2, #2 + 80029fa: 4013 ands r3, r2 + 80029fc: d0ed beq.n 80029da } } } if (ret == HAL_OK) - 800297a: 2313 movs r3, #19 - 800297c: 18fb adds r3, r7, r3 - 800297e: 781b ldrb r3, [r3, #0] - 8002980: 2b00 cmp r3, #0 - 8002982: d10a bne.n 800299a + 80029fe: 2313 movs r3, #19 + 8002a00: 18fb adds r3, r7, r3 + 8002a02: 781b ldrb r3, [r3, #0] + 8002a04: 2b00 cmp r3, #0 + 8002a06: d10a bne.n 8002a1e { /* Apply new RTC clock source selection */ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); - 8002984: 4b36 ldr r3, [pc, #216] @ (8002a60 ) - 8002986: 6ddb ldr r3, [r3, #92] @ 0x5c - 8002988: 4a36 ldr r2, [pc, #216] @ (8002a64 ) - 800298a: 4013 ands r3, r2 - 800298c: 0019 movs r1, r3 - 800298e: 687b ldr r3, [r7, #4] - 8002990: 699a ldr r2, [r3, #24] - 8002992: 4b33 ldr r3, [pc, #204] @ (8002a60 ) - 8002994: 430a orrs r2, r1 - 8002996: 65da str r2, [r3, #92] @ 0x5c - 8002998: e005 b.n 80029a6 + 8002a08: 4b36 ldr r3, [pc, #216] @ (8002ae4 ) + 8002a0a: 6ddb ldr r3, [r3, #92] @ 0x5c + 8002a0c: 4a36 ldr r2, [pc, #216] @ (8002ae8 ) + 8002a0e: 4013 ands r3, r2 + 8002a10: 0019 movs r1, r3 + 8002a12: 687b ldr r3, [r7, #4] + 8002a14: 699a ldr r2, [r3, #24] + 8002a16: 4b33 ldr r3, [pc, #204] @ (8002ae4 ) + 8002a18: 430a orrs r2, r1 + 8002a1a: 65da str r2, [r3, #92] @ 0x5c + 8002a1c: e005 b.n 8002a2a } else { /* set overall return value */ status = ret; - 800299a: 2312 movs r3, #18 - 800299c: 18fb adds r3, r7, r3 - 800299e: 2213 movs r2, #19 - 80029a0: 18ba adds r2, r7, r2 - 80029a2: 7812 ldrb r2, [r2, #0] - 80029a4: 701a strb r2, [r3, #0] + 8002a1e: 2312 movs r3, #18 + 8002a20: 18fb adds r3, r7, r3 + 8002a22: 2213 movs r2, #19 + 8002a24: 18ba adds r2, r7, r2 + 8002a26: 7812 ldrb r2, [r2, #0] + 8002a28: 701a strb r2, [r3, #0] } /* Restore clock configuration if changed */ if (pwrclkchanged == SET) - 80029a6: 2311 movs r3, #17 - 80029a8: 18fb adds r3, r7, r3 - 80029aa: 781b ldrb r3, [r3, #0] - 80029ac: 2b01 cmp r3, #1 - 80029ae: d105 bne.n 80029bc + 8002a2a: 2311 movs r3, #17 + 8002a2c: 18fb adds r3, r7, r3 + 8002a2e: 781b ldrb r3, [r3, #0] + 8002a30: 2b01 cmp r3, #1 + 8002a32: d105 bne.n 8002a40 { __HAL_RCC_PWR_CLK_DISABLE(); - 80029b0: 4b2b ldr r3, [pc, #172] @ (8002a60 ) - 80029b2: 6bda ldr r2, [r3, #60] @ 0x3c - 80029b4: 4b2a ldr r3, [pc, #168] @ (8002a60 ) - 80029b6: 492e ldr r1, [pc, #184] @ (8002a70 ) - 80029b8: 400a ands r2, r1 - 80029ba: 63da str r2, [r3, #60] @ 0x3c + 8002a34: 4b2b ldr r3, [pc, #172] @ (8002ae4 ) + 8002a36: 6bda ldr r2, [r3, #60] @ 0x3c + 8002a38: 4b2a ldr r3, [pc, #168] @ (8002ae4 ) + 8002a3a: 492e ldr r1, [pc, #184] @ (8002af4 ) + 8002a3c: 400a ands r2, r1 + 8002a3e: 63da str r2, [r3, #60] @ 0x3c } } /*-------------------------- USART1 clock source configuration -------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) - 80029bc: 687b ldr r3, [r7, #4] - 80029be: 681b ldr r3, [r3, #0] - 80029c0: 2201 movs r2, #1 - 80029c2: 4013 ands r3, r2 - 80029c4: d009 beq.n 80029da + 8002a40: 687b ldr r3, [r7, #4] + 8002a42: 681b ldr r3, [r3, #0] + 8002a44: 2201 movs r2, #1 + 8002a46: 4013 ands r3, r2 + 8002a48: d009 beq.n 8002a5e { /* Check the parameters */ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); /* Configure the USART1 clock source */ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); - 80029c6: 4b26 ldr r3, [pc, #152] @ (8002a60 ) - 80029c8: 6d5b ldr r3, [r3, #84] @ 0x54 - 80029ca: 2203 movs r2, #3 - 80029cc: 4393 bics r3, r2 - 80029ce: 0019 movs r1, r3 - 80029d0: 687b ldr r3, [r7, #4] - 80029d2: 689a ldr r2, [r3, #8] - 80029d4: 4b22 ldr r3, [pc, #136] @ (8002a60 ) - 80029d6: 430a orrs r2, r1 - 80029d8: 655a str r2, [r3, #84] @ 0x54 + 8002a4a: 4b26 ldr r3, [pc, #152] @ (8002ae4 ) + 8002a4c: 6d5b ldr r3, [r3, #84] @ 0x54 + 8002a4e: 2203 movs r2, #3 + 8002a50: 4393 bics r3, r2 + 8002a52: 0019 movs r1, r3 + 8002a54: 687b ldr r3, [r7, #4] + 8002a56: 689a ldr r2, [r3, #8] + 8002a58: 4b22 ldr r3, [pc, #136] @ (8002ae4 ) + 8002a5a: 430a orrs r2, r1 + 8002a5c: 655a str r2, [r3, #84] @ 0x54 } /*-------------------------- I2C1 clock source configuration ---------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) - 80029da: 687b ldr r3, [r7, #4] - 80029dc: 681b ldr r3, [r3, #0] - 80029de: 2202 movs r2, #2 - 80029e0: 4013 ands r3, r2 - 80029e2: d009 beq.n 80029f8 + 8002a5e: 687b ldr r3, [r7, #4] + 8002a60: 681b ldr r3, [r3, #0] + 8002a62: 2202 movs r2, #2 + 8002a64: 4013 ands r3, r2 + 8002a66: d009 beq.n 8002a7c { /* Check the parameters */ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); /* Configure the I2C1 clock source */ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); - 80029e4: 4b1e ldr r3, [pc, #120] @ (8002a60 ) - 80029e6: 6d5b ldr r3, [r3, #84] @ 0x54 - 80029e8: 4a22 ldr r2, [pc, #136] @ (8002a74 ) - 80029ea: 4013 ands r3, r2 - 80029ec: 0019 movs r1, r3 - 80029ee: 687b ldr r3, [r7, #4] - 80029f0: 68da ldr r2, [r3, #12] - 80029f2: 4b1b ldr r3, [pc, #108] @ (8002a60 ) - 80029f4: 430a orrs r2, r1 - 80029f6: 655a str r2, [r3, #84] @ 0x54 + 8002a68: 4b1e ldr r3, [pc, #120] @ (8002ae4 ) + 8002a6a: 6d5b ldr r3, [r3, #84] @ 0x54 + 8002a6c: 4a22 ldr r2, [pc, #136] @ (8002af8 ) + 8002a6e: 4013 ands r3, r2 + 8002a70: 0019 movs r1, r3 + 8002a72: 687b ldr r3, [r7, #4] + 8002a74: 68da ldr r2, [r3, #12] + 8002a76: 4b1b ldr r3, [pc, #108] @ (8002ae4 ) + 8002a78: 430a orrs r2, r1 + 8002a7a: 655a str r2, [r3, #84] @ 0x54 } /*-------------------------- ADC clock source configuration ----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) - 80029f8: 687b ldr r3, [r7, #4] - 80029fa: 681b ldr r3, [r3, #0] - 80029fc: 2220 movs r2, #32 - 80029fe: 4013 ands r3, r2 - 8002a00: d008 beq.n 8002a14 + 8002a7c: 687b ldr r3, [r7, #4] + 8002a7e: 681b ldr r3, [r3, #0] + 8002a80: 2220 movs r2, #32 + 8002a82: 4013 ands r3, r2 + 8002a84: d008 beq.n 8002a98 { /* Check the parameters */ assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection)); /* Configure the ADC interface clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); - 8002a02: 4b17 ldr r3, [pc, #92] @ (8002a60 ) - 8002a04: 6d5b ldr r3, [r3, #84] @ 0x54 - 8002a06: 009b lsls r3, r3, #2 - 8002a08: 0899 lsrs r1, r3, #2 - 8002a0a: 687b ldr r3, [r7, #4] - 8002a0c: 695a ldr r2, [r3, #20] - 8002a0e: 4b14 ldr r3, [pc, #80] @ (8002a60 ) - 8002a10: 430a orrs r2, r1 - 8002a12: 655a str r2, [r3, #84] @ 0x54 + 8002a86: 4b17 ldr r3, [pc, #92] @ (8002ae4 ) + 8002a88: 6d5b ldr r3, [r3, #84] @ 0x54 + 8002a8a: 009b lsls r3, r3, #2 + 8002a8c: 0899 lsrs r1, r3, #2 + 8002a8e: 687b ldr r3, [r7, #4] + 8002a90: 695a ldr r2, [r3, #20] + 8002a92: 4b14 ldr r3, [pc, #80] @ (8002ae4 ) + 8002a94: 430a orrs r2, r1 + 8002a96: 655a str r2, [r3, #84] @ 0x54 __HAL_RCC_FDCAN1_CONFIG(PeriphClkInit->Fdcan1ClockSelection); } #endif /* FDCAN1 */ /*-------------------------- I2S1 clock source configuration ---------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) - 8002a14: 687b ldr r3, [r7, #4] - 8002a16: 681b ldr r3, [r3, #0] - 8002a18: 2204 movs r2, #4 - 8002a1a: 4013 ands r3, r2 - 8002a1c: d009 beq.n 8002a32 + 8002a98: 687b ldr r3, [r7, #4] + 8002a9a: 681b ldr r3, [r3, #0] + 8002a9c: 2204 movs r2, #4 + 8002a9e: 4013 ands r3, r2 + 8002aa0: d009 beq.n 8002ab6 { /* Check the parameters */ assert_param(IS_RCC_I2S1CLKSOURCE(PeriphClkInit->I2s1ClockSelection)); /* Configure the I2S1 clock source */ __HAL_RCC_I2S1_CONFIG(PeriphClkInit->I2s1ClockSelection); - 8002a1e: 4b10 ldr r3, [pc, #64] @ (8002a60 ) - 8002a20: 6d5b ldr r3, [r3, #84] @ 0x54 - 8002a22: 4a15 ldr r2, [pc, #84] @ (8002a78 ) - 8002a24: 4013 ands r3, r2 - 8002a26: 0019 movs r1, r3 - 8002a28: 687b ldr r3, [r7, #4] - 8002a2a: 691a ldr r2, [r3, #16] - 8002a2c: 4b0c ldr r3, [pc, #48] @ (8002a60 ) - 8002a2e: 430a orrs r2, r1 - 8002a30: 655a str r2, [r3, #84] @ 0x54 + 8002aa2: 4b10 ldr r3, [pc, #64] @ (8002ae4 ) + 8002aa4: 6d5b ldr r3, [r3, #84] @ 0x54 + 8002aa6: 4a15 ldr r2, [pc, #84] @ (8002afc ) + 8002aa8: 4013 ands r3, r2 + 8002aaa: 0019 movs r1, r3 + 8002aac: 687b ldr r3, [r7, #4] + 8002aae: 691a ldr r2, [r3, #16] + 8002ab0: 4b0c ldr r3, [pc, #48] @ (8002ae4 ) + 8002ab2: 430a orrs r2, r1 + 8002ab4: 655a str r2, [r3, #84] @ 0x54 } /*------------------------------------ HSI Kernel clock source configuration --------------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HSIKER) == RCC_PERIPHCLK_HSIKER) - 8002a32: 687b ldr r3, [r7, #4] - 8002a34: 681b ldr r3, [r3, #0] - 8002a36: 2280 movs r2, #128 @ 0x80 - 8002a38: 4013 ands r3, r2 - 8002a3a: d009 beq.n 8002a50 + 8002ab6: 687b ldr r3, [r7, #4] + 8002ab8: 681b ldr r3, [r3, #0] + 8002aba: 2280 movs r2, #128 @ 0x80 + 8002abc: 4013 ands r3, r2 + 8002abe: d009 beq.n 8002ad4 { /* Check the parameters */ assert_param(IS_RCC_HSIKERDIV(PeriphClkInit->HSIKerClockDivider)); /* Configure the HSI Kernel clock source Divider */ __HAL_RCC_HSIKER_CONFIG(PeriphClkInit->HSIKerClockDivider); - 8002a3c: 4b08 ldr r3, [pc, #32] @ (8002a60 ) - 8002a3e: 681b ldr r3, [r3, #0] - 8002a40: 22e0 movs r2, #224 @ 0xe0 - 8002a42: 4393 bics r3, r2 - 8002a44: 0019 movs r1, r3 - 8002a46: 687b ldr r3, [r7, #4] - 8002a48: 685a ldr r2, [r3, #4] - 8002a4a: 4b05 ldr r3, [pc, #20] @ (8002a60 ) - 8002a4c: 430a orrs r2, r1 - 8002a4e: 601a str r2, [r3, #0] + 8002ac0: 4b08 ldr r3, [pc, #32] @ (8002ae4 ) + 8002ac2: 681b ldr r3, [r3, #0] + 8002ac4: 22e0 movs r2, #224 @ 0xe0 + 8002ac6: 4393 bics r3, r2 + 8002ac8: 0019 movs r1, r3 + 8002aca: 687b ldr r3, [r7, #4] + 8002acc: 685a ldr r2, [r3, #4] + 8002ace: 4b05 ldr r3, [pc, #20] @ (8002ae4 ) + 8002ad0: 430a orrs r2, r1 + 8002ad2: 601a str r2, [r3, #0] } return status; - 8002a50: 2312 movs r3, #18 - 8002a52: 18fb adds r3, r7, r3 - 8002a54: 781b ldrb r3, [r3, #0] + 8002ad4: 2312 movs r3, #18 + 8002ad6: 18fb adds r3, r7, r3 + 8002ad8: 781b ldrb r3, [r3, #0] } - 8002a56: 0018 movs r0, r3 - 8002a58: 46bd mov sp, r7 - 8002a5a: b006 add sp, #24 - 8002a5c: bd80 pop {r7, pc} - 8002a5e: 46c0 nop @ (mov r8, r8) - 8002a60: 40021000 .word 0x40021000 - 8002a64: fffffcff .word 0xfffffcff - 8002a68: fffeffff .word 0xfffeffff - 8002a6c: 00001388 .word 0x00001388 - 8002a70: efffffff .word 0xefffffff - 8002a74: ffffcfff .word 0xffffcfff - 8002a78: ffff3fff .word 0xffff3fff + 8002ada: 0018 movs r0, r3 + 8002adc: 46bd mov sp, r7 + 8002ade: b006 add sp, #24 + 8002ae0: bd80 pop {r7, pc} + 8002ae2: 46c0 nop @ (mov r8, r8) + 8002ae4: 40021000 .word 0x40021000 + 8002ae8: fffffcff .word 0xfffffcff + 8002aec: fffeffff .word 0xfffeffff + 8002af0: 00001388 .word 0x00001388 + 8002af4: efffffff .word 0xefffffff + 8002af8: ffffcfff .word 0xffffcfff + 8002afc: ffff3fff .word 0xffff3fff -08002a7c : +08002b00 : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { - 8002a7c: b580 push {r7, lr} - 8002a7e: b082 sub sp, #8 - 8002a80: af00 add r7, sp, #0 - 8002a82: 6078 str r0, [r7, #4] + 8002b00: b580 push {r7, lr} + 8002b02: b082 sub sp, #8 + 8002b04: af00 add r7, sp, #0 + 8002b06: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) - 8002a84: 687b ldr r3, [r7, #4] - 8002a86: 2b00 cmp r3, #0 - 8002a88: d101 bne.n 8002a8e + 8002b08: 687b ldr r3, [r7, #4] + 8002b0a: 2b00 cmp r3, #0 + 8002b0c: d101 bne.n 8002b12 { return HAL_ERROR; - 8002a8a: 2301 movs r3, #1 - 8002a8c: e04a b.n 8002b24 + 8002b0e: 2301 movs r3, #1 + 8002b10: e04a b.n 8002ba8 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) - 8002a8e: 687b ldr r3, [r7, #4] - 8002a90: 223d movs r2, #61 @ 0x3d - 8002a92: 5c9b ldrb r3, [r3, r2] - 8002a94: b2db uxtb r3, r3 - 8002a96: 2b00 cmp r3, #0 - 8002a98: d107 bne.n 8002aaa + 8002b12: 687b ldr r3, [r7, #4] + 8002b14: 223d movs r2, #61 @ 0x3d + 8002b16: 5c9b ldrb r3, [r3, r2] + 8002b18: b2db uxtb r3, r3 + 8002b1a: 2b00 cmp r3, #0 + 8002b1c: d107 bne.n 8002b2e { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; - 8002a9a: 687b ldr r3, [r7, #4] - 8002a9c: 223c movs r2, #60 @ 0x3c - 8002a9e: 2100 movs r1, #0 - 8002aa0: 5499 strb r1, [r3, r2] + 8002b1e: 687b ldr r3, [r7, #4] + 8002b20: 223c movs r2, #60 @ 0x3c + 8002b22: 2100 movs r1, #0 + 8002b24: 5499 strb r1, [r3, r2] } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); - 8002aa2: 687b ldr r3, [r7, #4] - 8002aa4: 0018 movs r0, r3 - 8002aa6: f7fe fb29 bl 80010fc + 8002b26: 687b ldr r3, [r7, #4] + 8002b28: 0018 movs r0, r3 + 8002b2a: f7fe fb29 bl 8001180 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; - 8002aaa: 687b ldr r3, [r7, #4] - 8002aac: 223d movs r2, #61 @ 0x3d - 8002aae: 2102 movs r1, #2 - 8002ab0: 5499 strb r1, [r3, r2] + 8002b2e: 687b ldr r3, [r7, #4] + 8002b30: 223d movs r2, #61 @ 0x3d + 8002b32: 2102 movs r1, #2 + 8002b34: 5499 strb r1, [r3, r2] /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); - 8002ab2: 687b ldr r3, [r7, #4] - 8002ab4: 681a ldr r2, [r3, #0] - 8002ab6: 687b ldr r3, [r7, #4] - 8002ab8: 3304 adds r3, #4 - 8002aba: 0019 movs r1, r3 - 8002abc: 0010 movs r0, r2 - 8002abe: f000 fc3b bl 8003338 + 8002b36: 687b ldr r3, [r7, #4] + 8002b38: 681a ldr r2, [r3, #0] + 8002b3a: 687b ldr r3, [r7, #4] + 8002b3c: 3304 adds r3, #4 + 8002b3e: 0019 movs r1, r3 + 8002b40: 0010 movs r0, r2 + 8002b42: f000 fc3b bl 80033bc /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - 8002ac2: 687b ldr r3, [r7, #4] - 8002ac4: 2248 movs r2, #72 @ 0x48 - 8002ac6: 2101 movs r1, #1 - 8002ac8: 5499 strb r1, [r3, r2] + 8002b46: 687b ldr r3, [r7, #4] + 8002b48: 2248 movs r2, #72 @ 0x48 + 8002b4a: 2101 movs r1, #1 + 8002b4c: 5499 strb r1, [r3, r2] /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - 8002aca: 687b ldr r3, [r7, #4] - 8002acc: 223e movs r2, #62 @ 0x3e - 8002ace: 2101 movs r1, #1 - 8002ad0: 5499 strb r1, [r3, r2] - 8002ad2: 687b ldr r3, [r7, #4] - 8002ad4: 223f movs r2, #63 @ 0x3f - 8002ad6: 2101 movs r1, #1 - 8002ad8: 5499 strb r1, [r3, r2] - 8002ada: 687b ldr r3, [r7, #4] - 8002adc: 2240 movs r2, #64 @ 0x40 - 8002ade: 2101 movs r1, #1 - 8002ae0: 5499 strb r1, [r3, r2] - 8002ae2: 687b ldr r3, [r7, #4] - 8002ae4: 2241 movs r2, #65 @ 0x41 - 8002ae6: 2101 movs r1, #1 - 8002ae8: 5499 strb r1, [r3, r2] - 8002aea: 687b ldr r3, [r7, #4] - 8002aec: 2242 movs r2, #66 @ 0x42 - 8002aee: 2101 movs r1, #1 - 8002af0: 5499 strb r1, [r3, r2] - 8002af2: 687b ldr r3, [r7, #4] - 8002af4: 2243 movs r2, #67 @ 0x43 - 8002af6: 2101 movs r1, #1 - 8002af8: 5499 strb r1, [r3, r2] + 8002b4e: 687b ldr r3, [r7, #4] + 8002b50: 223e movs r2, #62 @ 0x3e + 8002b52: 2101 movs r1, #1 + 8002b54: 5499 strb r1, [r3, r2] + 8002b56: 687b ldr r3, [r7, #4] + 8002b58: 223f movs r2, #63 @ 0x3f + 8002b5a: 2101 movs r1, #1 + 8002b5c: 5499 strb r1, [r3, r2] + 8002b5e: 687b ldr r3, [r7, #4] + 8002b60: 2240 movs r2, #64 @ 0x40 + 8002b62: 2101 movs r1, #1 + 8002b64: 5499 strb r1, [r3, r2] + 8002b66: 687b ldr r3, [r7, #4] + 8002b68: 2241 movs r2, #65 @ 0x41 + 8002b6a: 2101 movs r1, #1 + 8002b6c: 5499 strb r1, [r3, r2] + 8002b6e: 687b ldr r3, [r7, #4] + 8002b70: 2242 movs r2, #66 @ 0x42 + 8002b72: 2101 movs r1, #1 + 8002b74: 5499 strb r1, [r3, r2] + 8002b76: 687b ldr r3, [r7, #4] + 8002b78: 2243 movs r2, #67 @ 0x43 + 8002b7a: 2101 movs r1, #1 + 8002b7c: 5499 strb r1, [r3, r2] TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - 8002afa: 687b ldr r3, [r7, #4] - 8002afc: 2244 movs r2, #68 @ 0x44 - 8002afe: 2101 movs r1, #1 - 8002b00: 5499 strb r1, [r3, r2] - 8002b02: 687b ldr r3, [r7, #4] - 8002b04: 2245 movs r2, #69 @ 0x45 - 8002b06: 2101 movs r1, #1 - 8002b08: 5499 strb r1, [r3, r2] - 8002b0a: 687b ldr r3, [r7, #4] - 8002b0c: 2246 movs r2, #70 @ 0x46 - 8002b0e: 2101 movs r1, #1 - 8002b10: 5499 strb r1, [r3, r2] - 8002b12: 687b ldr r3, [r7, #4] - 8002b14: 2247 movs r2, #71 @ 0x47 - 8002b16: 2101 movs r1, #1 - 8002b18: 5499 strb r1, [r3, r2] + 8002b7e: 687b ldr r3, [r7, #4] + 8002b80: 2244 movs r2, #68 @ 0x44 + 8002b82: 2101 movs r1, #1 + 8002b84: 5499 strb r1, [r3, r2] + 8002b86: 687b ldr r3, [r7, #4] + 8002b88: 2245 movs r2, #69 @ 0x45 + 8002b8a: 2101 movs r1, #1 + 8002b8c: 5499 strb r1, [r3, r2] + 8002b8e: 687b ldr r3, [r7, #4] + 8002b90: 2246 movs r2, #70 @ 0x46 + 8002b92: 2101 movs r1, #1 + 8002b94: 5499 strb r1, [r3, r2] + 8002b96: 687b ldr r3, [r7, #4] + 8002b98: 2247 movs r2, #71 @ 0x47 + 8002b9a: 2101 movs r1, #1 + 8002b9c: 5499 strb r1, [r3, r2] /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; - 8002b1a: 687b ldr r3, [r7, #4] - 8002b1c: 223d movs r2, #61 @ 0x3d - 8002b1e: 2101 movs r1, #1 - 8002b20: 5499 strb r1, [r3, r2] + 8002b9e: 687b ldr r3, [r7, #4] + 8002ba0: 223d movs r2, #61 @ 0x3d + 8002ba2: 2101 movs r1, #1 + 8002ba4: 5499 strb r1, [r3, r2] return HAL_OK; - 8002b22: 2300 movs r3, #0 + 8002ba6: 2300 movs r3, #0 } - 8002b24: 0018 movs r0, r3 - 8002b26: 46bd mov sp, r7 - 8002b28: b002 add sp, #8 - 8002b2a: bd80 pop {r7, pc} + 8002ba8: 0018 movs r0, r3 + 8002baa: 46bd mov sp, r7 + 8002bac: b002 add sp, #8 + 8002bae: bd80 pop {r7, pc} -08002b2c : +08002bb0 : * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { - 8002b2c: b580 push {r7, lr} - 8002b2e: b082 sub sp, #8 - 8002b30: af00 add r7, sp, #0 - 8002b32: 6078 str r0, [r7, #4] + 8002bb0: b580 push {r7, lr} + 8002bb2: b082 sub sp, #8 + 8002bb4: af00 add r7, sp, #0 + 8002bb6: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) - 8002b34: 687b ldr r3, [r7, #4] - 8002b36: 2b00 cmp r3, #0 - 8002b38: d101 bne.n 8002b3e + 8002bb8: 687b ldr r3, [r7, #4] + 8002bba: 2b00 cmp r3, #0 + 8002bbc: d101 bne.n 8002bc2 { return HAL_ERROR; - 8002b3a: 2301 movs r3, #1 - 8002b3c: e04a b.n 8002bd4 + 8002bbe: 2301 movs r3, #1 + 8002bc0: e04a b.n 8002c58 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) - 8002b3e: 687b ldr r3, [r7, #4] - 8002b40: 223d movs r2, #61 @ 0x3d - 8002b42: 5c9b ldrb r3, [r3, r2] - 8002b44: b2db uxtb r3, r3 - 8002b46: 2b00 cmp r3, #0 - 8002b48: d107 bne.n 8002b5a + 8002bc2: 687b ldr r3, [r7, #4] + 8002bc4: 223d movs r2, #61 @ 0x3d + 8002bc6: 5c9b ldrb r3, [r3, r2] + 8002bc8: b2db uxtb r3, r3 + 8002bca: 2b00 cmp r3, #0 + 8002bcc: d107 bne.n 8002bde { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; - 8002b4a: 687b ldr r3, [r7, #4] - 8002b4c: 223c movs r2, #60 @ 0x3c - 8002b4e: 2100 movs r1, #0 - 8002b50: 5499 strb r1, [r3, r2] + 8002bce: 687b ldr r3, [r7, #4] + 8002bd0: 223c movs r2, #60 @ 0x3c + 8002bd2: 2100 movs r1, #0 + 8002bd4: 5499 strb r1, [r3, r2] } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->PWM_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); - 8002b52: 687b ldr r3, [r7, #4] - 8002b54: 0018 movs r0, r3 - 8002b56: f000 f841 bl 8002bdc + 8002bd6: 687b ldr r3, [r7, #4] + 8002bd8: 0018 movs r0, r3 + 8002bda: f000 f841 bl 8002c60 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; - 8002b5a: 687b ldr r3, [r7, #4] - 8002b5c: 223d movs r2, #61 @ 0x3d - 8002b5e: 2102 movs r1, #2 - 8002b60: 5499 strb r1, [r3, r2] + 8002bde: 687b ldr r3, [r7, #4] + 8002be0: 223d movs r2, #61 @ 0x3d + 8002be2: 2102 movs r1, #2 + 8002be4: 5499 strb r1, [r3, r2] /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); - 8002b62: 687b ldr r3, [r7, #4] - 8002b64: 681a ldr r2, [r3, #0] - 8002b66: 687b ldr r3, [r7, #4] - 8002b68: 3304 adds r3, #4 - 8002b6a: 0019 movs r1, r3 - 8002b6c: 0010 movs r0, r2 - 8002b6e: f000 fbe3 bl 8003338 + 8002be6: 687b ldr r3, [r7, #4] + 8002be8: 681a ldr r2, [r3, #0] + 8002bea: 687b ldr r3, [r7, #4] + 8002bec: 3304 adds r3, #4 + 8002bee: 0019 movs r1, r3 + 8002bf0: 0010 movs r0, r2 + 8002bf2: f000 fbe3 bl 80033bc /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - 8002b72: 687b ldr r3, [r7, #4] - 8002b74: 2248 movs r2, #72 @ 0x48 - 8002b76: 2101 movs r1, #1 - 8002b78: 5499 strb r1, [r3, r2] + 8002bf6: 687b ldr r3, [r7, #4] + 8002bf8: 2248 movs r2, #72 @ 0x48 + 8002bfa: 2101 movs r1, #1 + 8002bfc: 5499 strb r1, [r3, r2] /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - 8002b7a: 687b ldr r3, [r7, #4] - 8002b7c: 223e movs r2, #62 @ 0x3e - 8002b7e: 2101 movs r1, #1 - 8002b80: 5499 strb r1, [r3, r2] - 8002b82: 687b ldr r3, [r7, #4] - 8002b84: 223f movs r2, #63 @ 0x3f - 8002b86: 2101 movs r1, #1 - 8002b88: 5499 strb r1, [r3, r2] - 8002b8a: 687b ldr r3, [r7, #4] - 8002b8c: 2240 movs r2, #64 @ 0x40 - 8002b8e: 2101 movs r1, #1 - 8002b90: 5499 strb r1, [r3, r2] - 8002b92: 687b ldr r3, [r7, #4] - 8002b94: 2241 movs r2, #65 @ 0x41 - 8002b96: 2101 movs r1, #1 - 8002b98: 5499 strb r1, [r3, r2] - 8002b9a: 687b ldr r3, [r7, #4] - 8002b9c: 2242 movs r2, #66 @ 0x42 - 8002b9e: 2101 movs r1, #1 - 8002ba0: 5499 strb r1, [r3, r2] - 8002ba2: 687b ldr r3, [r7, #4] - 8002ba4: 2243 movs r2, #67 @ 0x43 - 8002ba6: 2101 movs r1, #1 - 8002ba8: 5499 strb r1, [r3, r2] + 8002bfe: 687b ldr r3, [r7, #4] + 8002c00: 223e movs r2, #62 @ 0x3e + 8002c02: 2101 movs r1, #1 + 8002c04: 5499 strb r1, [r3, r2] + 8002c06: 687b ldr r3, [r7, #4] + 8002c08: 223f movs r2, #63 @ 0x3f + 8002c0a: 2101 movs r1, #1 + 8002c0c: 5499 strb r1, [r3, r2] + 8002c0e: 687b ldr r3, [r7, #4] + 8002c10: 2240 movs r2, #64 @ 0x40 + 8002c12: 2101 movs r1, #1 + 8002c14: 5499 strb r1, [r3, r2] + 8002c16: 687b ldr r3, [r7, #4] + 8002c18: 2241 movs r2, #65 @ 0x41 + 8002c1a: 2101 movs r1, #1 + 8002c1c: 5499 strb r1, [r3, r2] + 8002c1e: 687b ldr r3, [r7, #4] + 8002c20: 2242 movs r2, #66 @ 0x42 + 8002c22: 2101 movs r1, #1 + 8002c24: 5499 strb r1, [r3, r2] + 8002c26: 687b ldr r3, [r7, #4] + 8002c28: 2243 movs r2, #67 @ 0x43 + 8002c2a: 2101 movs r1, #1 + 8002c2c: 5499 strb r1, [r3, r2] TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - 8002baa: 687b ldr r3, [r7, #4] - 8002bac: 2244 movs r2, #68 @ 0x44 - 8002bae: 2101 movs r1, #1 - 8002bb0: 5499 strb r1, [r3, r2] - 8002bb2: 687b ldr r3, [r7, #4] - 8002bb4: 2245 movs r2, #69 @ 0x45 - 8002bb6: 2101 movs r1, #1 - 8002bb8: 5499 strb r1, [r3, r2] - 8002bba: 687b ldr r3, [r7, #4] - 8002bbc: 2246 movs r2, #70 @ 0x46 - 8002bbe: 2101 movs r1, #1 - 8002bc0: 5499 strb r1, [r3, r2] - 8002bc2: 687b ldr r3, [r7, #4] - 8002bc4: 2247 movs r2, #71 @ 0x47 - 8002bc6: 2101 movs r1, #1 - 8002bc8: 5499 strb r1, [r3, r2] + 8002c2e: 687b ldr r3, [r7, #4] + 8002c30: 2244 movs r2, #68 @ 0x44 + 8002c32: 2101 movs r1, #1 + 8002c34: 5499 strb r1, [r3, r2] + 8002c36: 687b ldr r3, [r7, #4] + 8002c38: 2245 movs r2, #69 @ 0x45 + 8002c3a: 2101 movs r1, #1 + 8002c3c: 5499 strb r1, [r3, r2] + 8002c3e: 687b ldr r3, [r7, #4] + 8002c40: 2246 movs r2, #70 @ 0x46 + 8002c42: 2101 movs r1, #1 + 8002c44: 5499 strb r1, [r3, r2] + 8002c46: 687b ldr r3, [r7, #4] + 8002c48: 2247 movs r2, #71 @ 0x47 + 8002c4a: 2101 movs r1, #1 + 8002c4c: 5499 strb r1, [r3, r2] /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; - 8002bca: 687b ldr r3, [r7, #4] - 8002bcc: 223d movs r2, #61 @ 0x3d - 8002bce: 2101 movs r1, #1 - 8002bd0: 5499 strb r1, [r3, r2] + 8002c4e: 687b ldr r3, [r7, #4] + 8002c50: 223d movs r2, #61 @ 0x3d + 8002c52: 2101 movs r1, #1 + 8002c54: 5499 strb r1, [r3, r2] return HAL_OK; - 8002bd2: 2300 movs r3, #0 + 8002c56: 2300 movs r3, #0 } - 8002bd4: 0018 movs r0, r3 - 8002bd6: 46bd mov sp, r7 - 8002bd8: b002 add sp, #8 - 8002bda: bd80 pop {r7, pc} + 8002c58: 0018 movs r0, r3 + 8002c5a: 46bd mov sp, r7 + 8002c5c: b002 add sp, #8 + 8002c5e: bd80 pop {r7, pc} -08002bdc : +08002c60 : * @brief Initializes the TIM PWM MSP. * @param htim TIM PWM handle * @retval None */ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) { - 8002bdc: b580 push {r7, lr} - 8002bde: b082 sub sp, #8 - 8002be0: af00 add r7, sp, #0 - 8002be2: 6078 str r0, [r7, #4] + 8002c60: b580 push {r7, lr} + 8002c62: b082 sub sp, #8 + 8002c64: af00 add r7, sp, #0 + 8002c66: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_MspInit could be implemented in the user file */ } - 8002be4: 46c0 nop @ (mov r8, r8) - 8002be6: 46bd mov sp, r7 - 8002be8: b002 add sp, #8 - 8002bea: bd80 pop {r7, pc} + 8002c68: 46c0 nop @ (mov r8, r8) + 8002c6a: 46bd mov sp, r7 + 8002c6c: b002 add sp, #8 + 8002c6e: bd80 pop {r7, pc} -08002bec : +08002c70 : * @param htim TIM Encoder Interface handle * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig) { - 8002bec: b580 push {r7, lr} - 8002bee: b086 sub sp, #24 - 8002bf0: af00 add r7, sp, #0 - 8002bf2: 6078 str r0, [r7, #4] - 8002bf4: 6039 str r1, [r7, #0] + 8002c70: b580 push {r7, lr} + 8002c72: b086 sub sp, #24 + 8002c74: af00 add r7, sp, #0 + 8002c76: 6078 str r0, [r7, #4] + 8002c78: 6039 str r1, [r7, #0] uint32_t tmpsmcr; uint32_t tmpccmr1; uint32_t tmpccer; /* Check the TIM handle allocation */ if (htim == NULL) - 8002bf6: 687b ldr r3, [r7, #4] - 8002bf8: 2b00 cmp r3, #0 - 8002bfa: d101 bne.n 8002c00 + 8002c7a: 687b ldr r3, [r7, #4] + 8002c7c: 2b00 cmp r3, #0 + 8002c7e: d101 bne.n 8002c84 { return HAL_ERROR; - 8002bfc: 2301 movs r3, #1 - 8002bfe: e090 b.n 8002d22 + 8002c80: 2301 movs r3, #1 + 8002c82: e090 b.n 8002da6 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); if (htim->State == HAL_TIM_STATE_RESET) - 8002c00: 687b ldr r3, [r7, #4] - 8002c02: 223d movs r2, #61 @ 0x3d - 8002c04: 5c9b ldrb r3, [r3, r2] - 8002c06: b2db uxtb r3, r3 - 8002c08: 2b00 cmp r3, #0 - 8002c0a: d107 bne.n 8002c1c + 8002c84: 687b ldr r3, [r7, #4] + 8002c86: 223d movs r2, #61 @ 0x3d + 8002c88: 5c9b ldrb r3, [r3, r2] + 8002c8a: b2db uxtb r3, r3 + 8002c8c: 2b00 cmp r3, #0 + 8002c8e: d107 bne.n 8002ca0 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; - 8002c0c: 687b ldr r3, [r7, #4] - 8002c0e: 223c movs r2, #60 @ 0x3c - 8002c10: 2100 movs r1, #0 - 8002c12: 5499 strb r1, [r3, r2] + 8002c90: 687b ldr r3, [r7, #4] + 8002c92: 223c movs r2, #60 @ 0x3c + 8002c94: 2100 movs r1, #0 + 8002c96: 5499 strb r1, [r3, r2] } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Encoder_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_Encoder_MspInit(htim); - 8002c14: 687b ldr r3, [r7, #4] - 8002c16: 0018 movs r0, r3 - 8002c18: f7fe faea bl 80011f0 + 8002c98: 687b ldr r3, [r7, #4] + 8002c9a: 0018 movs r0, r3 + 8002c9c: f7fe faea bl 8001274 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; - 8002c1c: 687b ldr r3, [r7, #4] - 8002c1e: 223d movs r2, #61 @ 0x3d - 8002c20: 2102 movs r1, #2 - 8002c22: 5499 strb r1, [r3, r2] + 8002ca0: 687b ldr r3, [r7, #4] + 8002ca2: 223d movs r2, #61 @ 0x3d + 8002ca4: 2102 movs r1, #2 + 8002ca6: 5499 strb r1, [r3, r2] /* Reset the SMS and ECE bits */ htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); - 8002c24: 687b ldr r3, [r7, #4] - 8002c26: 681b ldr r3, [r3, #0] - 8002c28: 689a ldr r2, [r3, #8] - 8002c2a: 687b ldr r3, [r7, #4] - 8002c2c: 681b ldr r3, [r3, #0] - 8002c2e: 493f ldr r1, [pc, #252] @ (8002d2c ) - 8002c30: 400a ands r2, r1 - 8002c32: 609a str r2, [r3, #8] + 8002ca8: 687b ldr r3, [r7, #4] + 8002caa: 681b ldr r3, [r3, #0] + 8002cac: 689a ldr r2, [r3, #8] + 8002cae: 687b ldr r3, [r7, #4] + 8002cb0: 681b ldr r3, [r3, #0] + 8002cb2: 493f ldr r1, [pc, #252] @ (8002db0 ) + 8002cb4: 400a ands r2, r1 + 8002cb6: 609a str r2, [r3, #8] /* Configure the Time base in the Encoder Mode */ TIM_Base_SetConfig(htim->Instance, &htim->Init); - 8002c34: 687b ldr r3, [r7, #4] - 8002c36: 681a ldr r2, [r3, #0] - 8002c38: 687b ldr r3, [r7, #4] - 8002c3a: 3304 adds r3, #4 - 8002c3c: 0019 movs r1, r3 - 8002c3e: 0010 movs r0, r2 - 8002c40: f000 fb7a bl 8003338 + 8002cb8: 687b ldr r3, [r7, #4] + 8002cba: 681a ldr r2, [r3, #0] + 8002cbc: 687b ldr r3, [r7, #4] + 8002cbe: 3304 adds r3, #4 + 8002cc0: 0019 movs r1, r3 + 8002cc2: 0010 movs r0, r2 + 8002cc4: f000 fb7a bl 80033bc /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; - 8002c44: 687b ldr r3, [r7, #4] - 8002c46: 681b ldr r3, [r3, #0] - 8002c48: 689b ldr r3, [r3, #8] - 8002c4a: 617b str r3, [r7, #20] + 8002cc8: 687b ldr r3, [r7, #4] + 8002cca: 681b ldr r3, [r3, #0] + 8002ccc: 689b ldr r3, [r3, #8] + 8002cce: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmr1 = htim->Instance->CCMR1; - 8002c4c: 687b ldr r3, [r7, #4] - 8002c4e: 681b ldr r3, [r3, #0] - 8002c50: 699b ldr r3, [r3, #24] - 8002c52: 613b str r3, [r7, #16] + 8002cd0: 687b ldr r3, [r7, #4] + 8002cd2: 681b ldr r3, [r3, #0] + 8002cd4: 699b ldr r3, [r3, #24] + 8002cd6: 613b str r3, [r7, #16] /* Get the TIMx CCER register value */ tmpccer = htim->Instance->CCER; - 8002c54: 687b ldr r3, [r7, #4] - 8002c56: 681b ldr r3, [r3, #0] - 8002c58: 6a1b ldr r3, [r3, #32] - 8002c5a: 60fb str r3, [r7, #12] + 8002cd8: 687b ldr r3, [r7, #4] + 8002cda: 681b ldr r3, [r3, #0] + 8002cdc: 6a1b ldr r3, [r3, #32] + 8002cde: 60fb str r3, [r7, #12] /* Set the encoder Mode */ tmpsmcr |= sConfig->EncoderMode; - 8002c5c: 683b ldr r3, [r7, #0] - 8002c5e: 681b ldr r3, [r3, #0] - 8002c60: 697a ldr r2, [r7, #20] - 8002c62: 4313 orrs r3, r2 - 8002c64: 617b str r3, [r7, #20] + 8002ce0: 683b ldr r3, [r7, #0] + 8002ce2: 681b ldr r3, [r3, #0] + 8002ce4: 697a ldr r2, [r7, #20] + 8002ce6: 4313 orrs r3, r2 + 8002ce8: 617b str r3, [r7, #20] /* Select the Capture Compare 1 and the Capture Compare 2 as input */ tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); - 8002c66: 693b ldr r3, [r7, #16] - 8002c68: 4a31 ldr r2, [pc, #196] @ (8002d30 ) - 8002c6a: 4013 ands r3, r2 - 8002c6c: 613b str r3, [r7, #16] + 8002cea: 693b ldr r3, [r7, #16] + 8002cec: 4a31 ldr r2, [pc, #196] @ (8002db4 ) + 8002cee: 4013 ands r3, r2 + 8002cf0: 613b str r3, [r7, #16] tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); - 8002c6e: 683b ldr r3, [r7, #0] - 8002c70: 689a ldr r2, [r3, #8] - 8002c72: 683b ldr r3, [r7, #0] - 8002c74: 699b ldr r3, [r3, #24] - 8002c76: 021b lsls r3, r3, #8 - 8002c78: 4313 orrs r3, r2 - 8002c7a: 693a ldr r2, [r7, #16] - 8002c7c: 4313 orrs r3, r2 - 8002c7e: 613b str r3, [r7, #16] + 8002cf2: 683b ldr r3, [r7, #0] + 8002cf4: 689a ldr r2, [r3, #8] + 8002cf6: 683b ldr r3, [r7, #0] + 8002cf8: 699b ldr r3, [r3, #24] + 8002cfa: 021b lsls r3, r3, #8 + 8002cfc: 4313 orrs r3, r2 + 8002cfe: 693a ldr r2, [r7, #16] + 8002d00: 4313 orrs r3, r2 + 8002d02: 613b str r3, [r7, #16] /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); - 8002c80: 693b ldr r3, [r7, #16] - 8002c82: 4a2c ldr r2, [pc, #176] @ (8002d34 ) - 8002c84: 4013 ands r3, r2 - 8002c86: 613b str r3, [r7, #16] + 8002d04: 693b ldr r3, [r7, #16] + 8002d06: 4a2c ldr r2, [pc, #176] @ (8002db8 ) + 8002d08: 4013 ands r3, r2 + 8002d0a: 613b str r3, [r7, #16] tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); - 8002c88: 693b ldr r3, [r7, #16] - 8002c8a: 4a2b ldr r2, [pc, #172] @ (8002d38 ) - 8002c8c: 4013 ands r3, r2 - 8002c8e: 613b str r3, [r7, #16] + 8002d0c: 693b ldr r3, [r7, #16] + 8002d0e: 4a2b ldr r2, [pc, #172] @ (8002dbc ) + 8002d10: 4013 ands r3, r2 + 8002d12: 613b str r3, [r7, #16] tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); - 8002c90: 683b ldr r3, [r7, #0] - 8002c92: 68da ldr r2, [r3, #12] - 8002c94: 683b ldr r3, [r7, #0] - 8002c96: 69db ldr r3, [r3, #28] - 8002c98: 021b lsls r3, r3, #8 - 8002c9a: 4313 orrs r3, r2 - 8002c9c: 693a ldr r2, [r7, #16] - 8002c9e: 4313 orrs r3, r2 - 8002ca0: 613b str r3, [r7, #16] + 8002d14: 683b ldr r3, [r7, #0] + 8002d16: 68da ldr r2, [r3, #12] + 8002d18: 683b ldr r3, [r7, #0] + 8002d1a: 69db ldr r3, [r3, #28] + 8002d1c: 021b lsls r3, r3, #8 + 8002d1e: 4313 orrs r3, r2 + 8002d20: 693a ldr r2, [r7, #16] + 8002d22: 4313 orrs r3, r2 + 8002d24: 613b str r3, [r7, #16] tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); - 8002ca2: 683b ldr r3, [r7, #0] - 8002ca4: 691b ldr r3, [r3, #16] - 8002ca6: 011a lsls r2, r3, #4 - 8002ca8: 683b ldr r3, [r7, #0] - 8002caa: 6a1b ldr r3, [r3, #32] - 8002cac: 031b lsls r3, r3, #12 - 8002cae: 4313 orrs r3, r2 - 8002cb0: 693a ldr r2, [r7, #16] - 8002cb2: 4313 orrs r3, r2 - 8002cb4: 613b str r3, [r7, #16] + 8002d26: 683b ldr r3, [r7, #0] + 8002d28: 691b ldr r3, [r3, #16] + 8002d2a: 011a lsls r2, r3, #4 + 8002d2c: 683b ldr r3, [r7, #0] + 8002d2e: 6a1b ldr r3, [r3, #32] + 8002d30: 031b lsls r3, r3, #12 + 8002d32: 4313 orrs r3, r2 + 8002d34: 693a ldr r2, [r7, #16] + 8002d36: 4313 orrs r3, r2 + 8002d38: 613b str r3, [r7, #16] /* Set the TI1 and the TI2 Polarities */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); - 8002cb6: 68fb ldr r3, [r7, #12] - 8002cb8: 2222 movs r2, #34 @ 0x22 - 8002cba: 4393 bics r3, r2 - 8002cbc: 60fb str r3, [r7, #12] + 8002d3a: 68fb ldr r3, [r7, #12] + 8002d3c: 2222 movs r2, #34 @ 0x22 + 8002d3e: 4393 bics r3, r2 + 8002d40: 60fb str r3, [r7, #12] tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); - 8002cbe: 68fb ldr r3, [r7, #12] - 8002cc0: 2288 movs r2, #136 @ 0x88 - 8002cc2: 4393 bics r3, r2 - 8002cc4: 60fb str r3, [r7, #12] + 8002d42: 68fb ldr r3, [r7, #12] + 8002d44: 2288 movs r2, #136 @ 0x88 + 8002d46: 4393 bics r3, r2 + 8002d48: 60fb str r3, [r7, #12] tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); - 8002cc6: 683b ldr r3, [r7, #0] - 8002cc8: 685a ldr r2, [r3, #4] - 8002cca: 683b ldr r3, [r7, #0] - 8002ccc: 695b ldr r3, [r3, #20] - 8002cce: 011b lsls r3, r3, #4 - 8002cd0: 4313 orrs r3, r2 - 8002cd2: 68fa ldr r2, [r7, #12] - 8002cd4: 4313 orrs r3, r2 - 8002cd6: 60fb str r3, [r7, #12] + 8002d4a: 683b ldr r3, [r7, #0] + 8002d4c: 685a ldr r2, [r3, #4] + 8002d4e: 683b ldr r3, [r7, #0] + 8002d50: 695b ldr r3, [r3, #20] + 8002d52: 011b lsls r3, r3, #4 + 8002d54: 4313 orrs r3, r2 + 8002d56: 68fa ldr r2, [r7, #12] + 8002d58: 4313 orrs r3, r2 + 8002d5a: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; - 8002cd8: 687b ldr r3, [r7, #4] - 8002cda: 681b ldr r3, [r3, #0] - 8002cdc: 697a ldr r2, [r7, #20] - 8002cde: 609a str r2, [r3, #8] + 8002d5c: 687b ldr r3, [r7, #4] + 8002d5e: 681b ldr r3, [r3, #0] + 8002d60: 697a ldr r2, [r7, #20] + 8002d62: 609a str r2, [r3, #8] /* Write to TIMx CCMR1 */ htim->Instance->CCMR1 = tmpccmr1; - 8002ce0: 687b ldr r3, [r7, #4] - 8002ce2: 681b ldr r3, [r3, #0] - 8002ce4: 693a ldr r2, [r7, #16] - 8002ce6: 619a str r2, [r3, #24] + 8002d64: 687b ldr r3, [r7, #4] + 8002d66: 681b ldr r3, [r3, #0] + 8002d68: 693a ldr r2, [r7, #16] + 8002d6a: 619a str r2, [r3, #24] /* Write to TIMx CCER */ htim->Instance->CCER = tmpccer; - 8002ce8: 687b ldr r3, [r7, #4] - 8002cea: 681b ldr r3, [r3, #0] - 8002cec: 68fa ldr r2, [r7, #12] - 8002cee: 621a str r2, [r3, #32] + 8002d6c: 687b ldr r3, [r7, #4] + 8002d6e: 681b ldr r3, [r3, #0] + 8002d70: 68fa ldr r2, [r7, #12] + 8002d72: 621a str r2, [r3, #32] /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - 8002cf0: 687b ldr r3, [r7, #4] - 8002cf2: 2248 movs r2, #72 @ 0x48 - 8002cf4: 2101 movs r1, #1 - 8002cf6: 5499 strb r1, [r3, r2] + 8002d74: 687b ldr r3, [r7, #4] + 8002d76: 2248 movs r2, #72 @ 0x48 + 8002d78: 2101 movs r1, #1 + 8002d7a: 5499 strb r1, [r3, r2] /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - 8002cf8: 687b ldr r3, [r7, #4] - 8002cfa: 223e movs r2, #62 @ 0x3e - 8002cfc: 2101 movs r1, #1 - 8002cfe: 5499 strb r1, [r3, r2] + 8002d7c: 687b ldr r3, [r7, #4] + 8002d7e: 223e movs r2, #62 @ 0x3e + 8002d80: 2101 movs r1, #1 + 8002d82: 5499 strb r1, [r3, r2] TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - 8002d00: 687b ldr r3, [r7, #4] - 8002d02: 223f movs r2, #63 @ 0x3f - 8002d04: 2101 movs r1, #1 - 8002d06: 5499 strb r1, [r3, r2] + 8002d84: 687b ldr r3, [r7, #4] + 8002d86: 223f movs r2, #63 @ 0x3f + 8002d88: 2101 movs r1, #1 + 8002d8a: 5499 strb r1, [r3, r2] TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - 8002d08: 687b ldr r3, [r7, #4] - 8002d0a: 2244 movs r2, #68 @ 0x44 - 8002d0c: 2101 movs r1, #1 - 8002d0e: 5499 strb r1, [r3, r2] + 8002d8c: 687b ldr r3, [r7, #4] + 8002d8e: 2244 movs r2, #68 @ 0x44 + 8002d90: 2101 movs r1, #1 + 8002d92: 5499 strb r1, [r3, r2] TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - 8002d10: 687b ldr r3, [r7, #4] - 8002d12: 2245 movs r2, #69 @ 0x45 - 8002d14: 2101 movs r1, #1 - 8002d16: 5499 strb r1, [r3, r2] + 8002d94: 687b ldr r3, [r7, #4] + 8002d96: 2245 movs r2, #69 @ 0x45 + 8002d98: 2101 movs r1, #1 + 8002d9a: 5499 strb r1, [r3, r2] /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; - 8002d18: 687b ldr r3, [r7, #4] - 8002d1a: 223d movs r2, #61 @ 0x3d - 8002d1c: 2101 movs r1, #1 - 8002d1e: 5499 strb r1, [r3, r2] + 8002d9c: 687b ldr r3, [r7, #4] + 8002d9e: 223d movs r2, #61 @ 0x3d + 8002da0: 2101 movs r1, #1 + 8002da2: 5499 strb r1, [r3, r2] return HAL_OK; - 8002d20: 2300 movs r3, #0 + 8002da4: 2300 movs r3, #0 } - 8002d22: 0018 movs r0, r3 - 8002d24: 46bd mov sp, r7 - 8002d26: b006 add sp, #24 - 8002d28: bd80 pop {r7, pc} - 8002d2a: 46c0 nop @ (mov r8, r8) - 8002d2c: fffebff8 .word 0xfffebff8 - 8002d30: fffffcfc .word 0xfffffcfc - 8002d34: fffff3f3 .word 0xfffff3f3 - 8002d38: ffff0f0f .word 0xffff0f0f + 8002da6: 0018 movs r0, r3 + 8002da8: 46bd mov sp, r7 + 8002daa: b006 add sp, #24 + 8002dac: bd80 pop {r7, pc} + 8002dae: 46c0 nop @ (mov r8, r8) + 8002db0: fffebff8 .word 0xfffebff8 + 8002db4: fffffcfc .word 0xfffffcfc + 8002db8: fffff3f3 .word 0xfffff3f3 + 8002dbc: ffff0f0f .word 0xffff0f0f -08002d3c : +08002dc0 : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { - 8002d3c: b580 push {r7, lr} - 8002d3e: b084 sub sp, #16 - 8002d40: af00 add r7, sp, #0 - 8002d42: 6078 str r0, [r7, #4] + 8002dc0: b580 push {r7, lr} + 8002dc2: b084 sub sp, #16 + 8002dc4: af00 add r7, sp, #0 + 8002dc6: 6078 str r0, [r7, #4] uint32_t itsource = htim->Instance->DIER; - 8002d44: 687b ldr r3, [r7, #4] - 8002d46: 681b ldr r3, [r3, #0] - 8002d48: 68db ldr r3, [r3, #12] - 8002d4a: 60fb str r3, [r7, #12] + 8002dc8: 687b ldr r3, [r7, #4] + 8002dca: 681b ldr r3, [r3, #0] + 8002dcc: 68db ldr r3, [r3, #12] + 8002dce: 60fb str r3, [r7, #12] uint32_t itflag = htim->Instance->SR; - 8002d4c: 687b ldr r3, [r7, #4] - 8002d4e: 681b ldr r3, [r3, #0] - 8002d50: 691b ldr r3, [r3, #16] - 8002d52: 60bb str r3, [r7, #8] + 8002dd0: 687b ldr r3, [r7, #4] + 8002dd2: 681b ldr r3, [r3, #0] + 8002dd4: 691b ldr r3, [r3, #16] + 8002dd6: 60bb str r3, [r7, #8] /* Capture compare 1 event */ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) - 8002d54: 68bb ldr r3, [r7, #8] - 8002d56: 2202 movs r2, #2 - 8002d58: 4013 ands r3, r2 - 8002d5a: d021 beq.n 8002da0 + 8002dd8: 68bb ldr r3, [r7, #8] + 8002dda: 2202 movs r2, #2 + 8002ddc: 4013 ands r3, r2 + 8002dde: d021 beq.n 8002e24 { if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) - 8002d5c: 68fb ldr r3, [r7, #12] - 8002d5e: 2202 movs r2, #2 - 8002d60: 4013 ands r3, r2 - 8002d62: d01d beq.n 8002da0 + 8002de0: 68fb ldr r3, [r7, #12] + 8002de2: 2202 movs r2, #2 + 8002de4: 4013 ands r3, r2 + 8002de6: d01d beq.n 8002e24 { { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); - 8002d64: 687b ldr r3, [r7, #4] - 8002d66: 681b ldr r3, [r3, #0] - 8002d68: 2203 movs r2, #3 - 8002d6a: 4252 negs r2, r2 - 8002d6c: 611a str r2, [r3, #16] + 8002de8: 687b ldr r3, [r7, #4] + 8002dea: 681b ldr r3, [r3, #0] + 8002dec: 2203 movs r2, #3 + 8002dee: 4252 negs r2, r2 + 8002df0: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - 8002d6e: 687b ldr r3, [r7, #4] - 8002d70: 2201 movs r2, #1 - 8002d72: 771a strb r2, [r3, #28] + 8002df2: 687b ldr r3, [r7, #4] + 8002df4: 2201 movs r2, #1 + 8002df6: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) - 8002d74: 687b ldr r3, [r7, #4] - 8002d76: 681b ldr r3, [r3, #0] - 8002d78: 699b ldr r3, [r3, #24] - 8002d7a: 2203 movs r2, #3 - 8002d7c: 4013 ands r3, r2 - 8002d7e: d004 beq.n 8002d8a + 8002df8: 687b ldr r3, [r7, #4] + 8002dfa: 681b ldr r3, [r3, #0] + 8002dfc: 699b ldr r3, [r3, #24] + 8002dfe: 2203 movs r2, #3 + 8002e00: 4013 ands r3, r2 + 8002e02: d004 beq.n 8002e0e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); - 8002d80: 687b ldr r3, [r7, #4] - 8002d82: 0018 movs r0, r3 - 8002d84: f000 fac0 bl 8003308 - 8002d88: e007 b.n 8002d9a + 8002e04: 687b ldr r3, [r7, #4] + 8002e06: 0018 movs r0, r3 + 8002e08: f000 fac0 bl 800338c + 8002e0c: e007 b.n 8002e1e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); - 8002d8a: 687b ldr r3, [r7, #4] - 8002d8c: 0018 movs r0, r3 - 8002d8e: f000 fab3 bl 80032f8 + 8002e0e: 687b ldr r3, [r7, #4] + 8002e10: 0018 movs r0, r3 + 8002e12: f000 fab3 bl 800337c HAL_TIM_PWM_PulseFinishedCallback(htim); - 8002d92: 687b ldr r3, [r7, #4] - 8002d94: 0018 movs r0, r3 - 8002d96: f000 fabf bl 8003318 + 8002e16: 687b ldr r3, [r7, #4] + 8002e18: 0018 movs r0, r3 + 8002e1a: f000 fabf bl 800339c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - 8002d9a: 687b ldr r3, [r7, #4] - 8002d9c: 2200 movs r2, #0 - 8002d9e: 771a strb r2, [r3, #28] + 8002e1e: 687b ldr r3, [r7, #4] + 8002e20: 2200 movs r2, #0 + 8002e22: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) - 8002da0: 68bb ldr r3, [r7, #8] - 8002da2: 2204 movs r2, #4 - 8002da4: 4013 ands r3, r2 - 8002da6: d022 beq.n 8002dee + 8002e24: 68bb ldr r3, [r7, #8] + 8002e26: 2204 movs r2, #4 + 8002e28: 4013 ands r3, r2 + 8002e2a: d022 beq.n 8002e72 { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) - 8002da8: 68fb ldr r3, [r7, #12] - 8002daa: 2204 movs r2, #4 - 8002dac: 4013 ands r3, r2 - 8002dae: d01e beq.n 8002dee + 8002e2c: 68fb ldr r3, [r7, #12] + 8002e2e: 2204 movs r2, #4 + 8002e30: 4013 ands r3, r2 + 8002e32: d01e beq.n 8002e72 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); - 8002db0: 687b ldr r3, [r7, #4] - 8002db2: 681b ldr r3, [r3, #0] - 8002db4: 2205 movs r2, #5 - 8002db6: 4252 negs r2, r2 - 8002db8: 611a str r2, [r3, #16] + 8002e34: 687b ldr r3, [r7, #4] + 8002e36: 681b ldr r3, [r3, #0] + 8002e38: 2205 movs r2, #5 + 8002e3a: 4252 negs r2, r2 + 8002e3c: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - 8002dba: 687b ldr r3, [r7, #4] - 8002dbc: 2202 movs r2, #2 - 8002dbe: 771a strb r2, [r3, #28] + 8002e3e: 687b ldr r3, [r7, #4] + 8002e40: 2202 movs r2, #2 + 8002e42: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) - 8002dc0: 687b ldr r3, [r7, #4] - 8002dc2: 681b ldr r3, [r3, #0] - 8002dc4: 699a ldr r2, [r3, #24] - 8002dc6: 23c0 movs r3, #192 @ 0xc0 - 8002dc8: 009b lsls r3, r3, #2 - 8002dca: 4013 ands r3, r2 - 8002dcc: d004 beq.n 8002dd8 + 8002e44: 687b ldr r3, [r7, #4] + 8002e46: 681b ldr r3, [r3, #0] + 8002e48: 699a ldr r2, [r3, #24] + 8002e4a: 23c0 movs r3, #192 @ 0xc0 + 8002e4c: 009b lsls r3, r3, #2 + 8002e4e: 4013 ands r3, r2 + 8002e50: d004 beq.n 8002e5c { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); - 8002dce: 687b ldr r3, [r7, #4] - 8002dd0: 0018 movs r0, r3 - 8002dd2: f000 fa99 bl 8003308 - 8002dd6: e007 b.n 8002de8 + 8002e52: 687b ldr r3, [r7, #4] + 8002e54: 0018 movs r0, r3 + 8002e56: f000 fa99 bl 800338c + 8002e5a: e007 b.n 8002e6c { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); - 8002dd8: 687b ldr r3, [r7, #4] - 8002dda: 0018 movs r0, r3 - 8002ddc: f000 fa8c bl 80032f8 + 8002e5c: 687b ldr r3, [r7, #4] + 8002e5e: 0018 movs r0, r3 + 8002e60: f000 fa8c bl 800337c HAL_TIM_PWM_PulseFinishedCallback(htim); - 8002de0: 687b ldr r3, [r7, #4] - 8002de2: 0018 movs r0, r3 - 8002de4: f000 fa98 bl 8003318 + 8002e64: 687b ldr r3, [r7, #4] + 8002e66: 0018 movs r0, r3 + 8002e68: f000 fa98 bl 800339c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - 8002de8: 687b ldr r3, [r7, #4] - 8002dea: 2200 movs r2, #0 - 8002dec: 771a strb r2, [r3, #28] + 8002e6c: 687b ldr r3, [r7, #4] + 8002e6e: 2200 movs r2, #0 + 8002e70: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) - 8002dee: 68bb ldr r3, [r7, #8] - 8002df0: 2208 movs r2, #8 - 8002df2: 4013 ands r3, r2 - 8002df4: d021 beq.n 8002e3a + 8002e72: 68bb ldr r3, [r7, #8] + 8002e74: 2208 movs r2, #8 + 8002e76: 4013 ands r3, r2 + 8002e78: d021 beq.n 8002ebe { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) - 8002df6: 68fb ldr r3, [r7, #12] - 8002df8: 2208 movs r2, #8 - 8002dfa: 4013 ands r3, r2 - 8002dfc: d01d beq.n 8002e3a + 8002e7a: 68fb ldr r3, [r7, #12] + 8002e7c: 2208 movs r2, #8 + 8002e7e: 4013 ands r3, r2 + 8002e80: d01d beq.n 8002ebe { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); - 8002dfe: 687b ldr r3, [r7, #4] - 8002e00: 681b ldr r3, [r3, #0] - 8002e02: 2209 movs r2, #9 - 8002e04: 4252 negs r2, r2 - 8002e06: 611a str r2, [r3, #16] + 8002e82: 687b ldr r3, [r7, #4] + 8002e84: 681b ldr r3, [r3, #0] + 8002e86: 2209 movs r2, #9 + 8002e88: 4252 negs r2, r2 + 8002e8a: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - 8002e08: 687b ldr r3, [r7, #4] - 8002e0a: 2204 movs r2, #4 - 8002e0c: 771a strb r2, [r3, #28] + 8002e8c: 687b ldr r3, [r7, #4] + 8002e8e: 2204 movs r2, #4 + 8002e90: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) - 8002e0e: 687b ldr r3, [r7, #4] - 8002e10: 681b ldr r3, [r3, #0] - 8002e12: 69db ldr r3, [r3, #28] - 8002e14: 2203 movs r2, #3 - 8002e16: 4013 ands r3, r2 - 8002e18: d004 beq.n 8002e24 + 8002e92: 687b ldr r3, [r7, #4] + 8002e94: 681b ldr r3, [r3, #0] + 8002e96: 69db ldr r3, [r3, #28] + 8002e98: 2203 movs r2, #3 + 8002e9a: 4013 ands r3, r2 + 8002e9c: d004 beq.n 8002ea8 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); - 8002e1a: 687b ldr r3, [r7, #4] - 8002e1c: 0018 movs r0, r3 - 8002e1e: f000 fa73 bl 8003308 - 8002e22: e007 b.n 8002e34 + 8002e9e: 687b ldr r3, [r7, #4] + 8002ea0: 0018 movs r0, r3 + 8002ea2: f000 fa73 bl 800338c + 8002ea6: e007 b.n 8002eb8 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); - 8002e24: 687b ldr r3, [r7, #4] - 8002e26: 0018 movs r0, r3 - 8002e28: f000 fa66 bl 80032f8 + 8002ea8: 687b ldr r3, [r7, #4] + 8002eaa: 0018 movs r0, r3 + 8002eac: f000 fa66 bl 800337c HAL_TIM_PWM_PulseFinishedCallback(htim); - 8002e2c: 687b ldr r3, [r7, #4] - 8002e2e: 0018 movs r0, r3 - 8002e30: f000 fa72 bl 8003318 + 8002eb0: 687b ldr r3, [r7, #4] + 8002eb2: 0018 movs r0, r3 + 8002eb4: f000 fa72 bl 800339c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - 8002e34: 687b ldr r3, [r7, #4] - 8002e36: 2200 movs r2, #0 - 8002e38: 771a strb r2, [r3, #28] + 8002eb8: 687b ldr r3, [r7, #4] + 8002eba: 2200 movs r2, #0 + 8002ebc: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) - 8002e3a: 68bb ldr r3, [r7, #8] - 8002e3c: 2210 movs r2, #16 - 8002e3e: 4013 ands r3, r2 - 8002e40: d022 beq.n 8002e88 + 8002ebe: 68bb ldr r3, [r7, #8] + 8002ec0: 2210 movs r2, #16 + 8002ec2: 4013 ands r3, r2 + 8002ec4: d022 beq.n 8002f0c { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) - 8002e42: 68fb ldr r3, [r7, #12] - 8002e44: 2210 movs r2, #16 - 8002e46: 4013 ands r3, r2 - 8002e48: d01e beq.n 8002e88 + 8002ec6: 68fb ldr r3, [r7, #12] + 8002ec8: 2210 movs r2, #16 + 8002eca: 4013 ands r3, r2 + 8002ecc: d01e beq.n 8002f0c { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); - 8002e4a: 687b ldr r3, [r7, #4] - 8002e4c: 681b ldr r3, [r3, #0] - 8002e4e: 2211 movs r2, #17 - 8002e50: 4252 negs r2, r2 - 8002e52: 611a str r2, [r3, #16] + 8002ece: 687b ldr r3, [r7, #4] + 8002ed0: 681b ldr r3, [r3, #0] + 8002ed2: 2211 movs r2, #17 + 8002ed4: 4252 negs r2, r2 + 8002ed6: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - 8002e54: 687b ldr r3, [r7, #4] - 8002e56: 2208 movs r2, #8 - 8002e58: 771a strb r2, [r3, #28] + 8002ed8: 687b ldr r3, [r7, #4] + 8002eda: 2208 movs r2, #8 + 8002edc: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) - 8002e5a: 687b ldr r3, [r7, #4] - 8002e5c: 681b ldr r3, [r3, #0] - 8002e5e: 69da ldr r2, [r3, #28] - 8002e60: 23c0 movs r3, #192 @ 0xc0 - 8002e62: 009b lsls r3, r3, #2 - 8002e64: 4013 ands r3, r2 - 8002e66: d004 beq.n 8002e72 + 8002ede: 687b ldr r3, [r7, #4] + 8002ee0: 681b ldr r3, [r3, #0] + 8002ee2: 69da ldr r2, [r3, #28] + 8002ee4: 23c0 movs r3, #192 @ 0xc0 + 8002ee6: 009b lsls r3, r3, #2 + 8002ee8: 4013 ands r3, r2 + 8002eea: d004 beq.n 8002ef6 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); - 8002e68: 687b ldr r3, [r7, #4] - 8002e6a: 0018 movs r0, r3 - 8002e6c: f000 fa4c bl 8003308 - 8002e70: e007 b.n 8002e82 + 8002eec: 687b ldr r3, [r7, #4] + 8002eee: 0018 movs r0, r3 + 8002ef0: f000 fa4c bl 800338c + 8002ef4: e007 b.n 8002f06 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); - 8002e72: 687b ldr r3, [r7, #4] - 8002e74: 0018 movs r0, r3 - 8002e76: f000 fa3f bl 80032f8 + 8002ef6: 687b ldr r3, [r7, #4] + 8002ef8: 0018 movs r0, r3 + 8002efa: f000 fa3f bl 800337c HAL_TIM_PWM_PulseFinishedCallback(htim); - 8002e7a: 687b ldr r3, [r7, #4] - 8002e7c: 0018 movs r0, r3 - 8002e7e: f000 fa4b bl 8003318 + 8002efe: 687b ldr r3, [r7, #4] + 8002f00: 0018 movs r0, r3 + 8002f02: f000 fa4b bl 800339c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - 8002e82: 687b ldr r3, [r7, #4] - 8002e84: 2200 movs r2, #0 - 8002e86: 771a strb r2, [r3, #28] + 8002f06: 687b ldr r3, [r7, #4] + 8002f08: 2200 movs r2, #0 + 8002f0a: 771a strb r2, [r3, #28] } } /* TIM Update event */ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) - 8002e88: 68bb ldr r3, [r7, #8] - 8002e8a: 2201 movs r2, #1 - 8002e8c: 4013 ands r3, r2 - 8002e8e: d00c beq.n 8002eaa + 8002f0c: 68bb ldr r3, [r7, #8] + 8002f0e: 2201 movs r2, #1 + 8002f10: 4013 ands r3, r2 + 8002f12: d00c beq.n 8002f2e { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) - 8002e90: 68fb ldr r3, [r7, #12] - 8002e92: 2201 movs r2, #1 - 8002e94: 4013 ands r3, r2 - 8002e96: d008 beq.n 8002eaa + 8002f14: 68fb ldr r3, [r7, #12] + 8002f16: 2201 movs r2, #1 + 8002f18: 4013 ands r3, r2 + 8002f1a: d008 beq.n 8002f2e { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); - 8002e98: 687b ldr r3, [r7, #4] - 8002e9a: 681b ldr r3, [r3, #0] - 8002e9c: 2202 movs r2, #2 - 8002e9e: 4252 negs r2, r2 - 8002ea0: 611a str r2, [r3, #16] + 8002f1c: 687b ldr r3, [r7, #4] + 8002f1e: 681b ldr r3, [r3, #0] + 8002f20: 2202 movs r2, #2 + 8002f22: 4252 negs r2, r2 + 8002f24: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); - 8002ea2: 687b ldr r3, [r7, #4] - 8002ea4: 0018 movs r0, r3 - 8002ea6: f7fe f81b bl 8000ee0 + 8002f26: 687b ldr r3, [r7, #4] + 8002f28: 0018 movs r0, r3 + 8002f2a: f7fd ffd9 bl 8000ee0 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ - 8002eaa: 68bb ldr r3, [r7, #8] - 8002eac: 2280 movs r2, #128 @ 0x80 - 8002eae: 4013 ands r3, r2 - 8002eb0: d104 bne.n 8002ebc + 8002f2e: 68bb ldr r3, [r7, #8] + 8002f30: 2280 movs r2, #128 @ 0x80 + 8002f32: 4013 ands r3, r2 + 8002f34: d104 bne.n 8002f40 ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK))) - 8002eb2: 68ba ldr r2, [r7, #8] - 8002eb4: 2380 movs r3, #128 @ 0x80 - 8002eb6: 019b lsls r3, r3, #6 - 8002eb8: 4013 ands r3, r2 + 8002f36: 68ba ldr r2, [r7, #8] + 8002f38: 2380 movs r3, #128 @ 0x80 + 8002f3a: 019b lsls r3, r3, #6 + 8002f3c: 4013 ands r3, r2 if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ - 8002eba: d00b beq.n 8002ed4 + 8002f3e: d00b beq.n 8002f58 { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) - 8002ebc: 68fb ldr r3, [r7, #12] - 8002ebe: 2280 movs r2, #128 @ 0x80 - 8002ec0: 4013 ands r3, r2 - 8002ec2: d007 beq.n 8002ed4 + 8002f40: 68fb ldr r3, [r7, #12] + 8002f42: 2280 movs r2, #128 @ 0x80 + 8002f44: 4013 ands r3, r2 + 8002f46: d007 beq.n 8002f58 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK); - 8002ec4: 687b ldr r3, [r7, #4] - 8002ec6: 681b ldr r3, [r3, #0] - 8002ec8: 4a1e ldr r2, [pc, #120] @ (8002f44 ) - 8002eca: 611a str r2, [r3, #16] + 8002f48: 687b ldr r3, [r7, #4] + 8002f4a: 681b ldr r3, [r3, #0] + 8002f4c: 4a1e ldr r2, [pc, #120] @ (8002fc8 ) + 8002f4e: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); - 8002ecc: 687b ldr r3, [r7, #4] - 8002ece: 0018 movs r0, r3 - 8002ed0: f000 fef2 bl 8003cb8 + 8002f50: 687b ldr r3, [r7, #4] + 8002f52: 0018 movs r0, r3 + 8002f54: f000 fef2 bl 8003d3c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break2 input event */ if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) - 8002ed4: 68ba ldr r2, [r7, #8] - 8002ed6: 2380 movs r3, #128 @ 0x80 - 8002ed8: 005b lsls r3, r3, #1 - 8002eda: 4013 ands r3, r2 - 8002edc: d00b beq.n 8002ef6 + 8002f58: 68ba ldr r2, [r7, #8] + 8002f5a: 2380 movs r3, #128 @ 0x80 + 8002f5c: 005b lsls r3, r3, #1 + 8002f5e: 4013 ands r3, r2 + 8002f60: d00b beq.n 8002f7a { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) - 8002ede: 68fb ldr r3, [r7, #12] - 8002ee0: 2280 movs r2, #128 @ 0x80 - 8002ee2: 4013 ands r3, r2 - 8002ee4: d007 beq.n 8002ef6 + 8002f62: 68fb ldr r3, [r7, #12] + 8002f64: 2280 movs r2, #128 @ 0x80 + 8002f66: 4013 ands r3, r2 + 8002f68: d007 beq.n 8002f7a { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); - 8002ee6: 687b ldr r3, [r7, #4] - 8002ee8: 681b ldr r3, [r3, #0] - 8002eea: 4a17 ldr r2, [pc, #92] @ (8002f48 ) - 8002eec: 611a str r2, [r3, #16] + 8002f6a: 687b ldr r3, [r7, #4] + 8002f6c: 681b ldr r3, [r3, #0] + 8002f6e: 4a17 ldr r2, [pc, #92] @ (8002fcc ) + 8002f70: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->Break2Callback(htim); #else HAL_TIMEx_Break2Callback(htim); - 8002eee: 687b ldr r3, [r7, #4] - 8002ef0: 0018 movs r0, r3 - 8002ef2: f000 fee9 bl 8003cc8 + 8002f72: 687b ldr r3, [r7, #4] + 8002f74: 0018 movs r0, r3 + 8002f76: f000 fee9 bl 8003d4c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) - 8002ef6: 68bb ldr r3, [r7, #8] - 8002ef8: 2240 movs r2, #64 @ 0x40 - 8002efa: 4013 ands r3, r2 - 8002efc: d00c beq.n 8002f18 + 8002f7a: 68bb ldr r3, [r7, #8] + 8002f7c: 2240 movs r2, #64 @ 0x40 + 8002f7e: 4013 ands r3, r2 + 8002f80: d00c beq.n 8002f9c { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) - 8002efe: 68fb ldr r3, [r7, #12] - 8002f00: 2240 movs r2, #64 @ 0x40 - 8002f02: 4013 ands r3, r2 - 8002f04: d008 beq.n 8002f18 + 8002f82: 68fb ldr r3, [r7, #12] + 8002f84: 2240 movs r2, #64 @ 0x40 + 8002f86: 4013 ands r3, r2 + 8002f88: d008 beq.n 8002f9c { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); - 8002f06: 687b ldr r3, [r7, #4] - 8002f08: 681b ldr r3, [r3, #0] - 8002f0a: 2241 movs r2, #65 @ 0x41 - 8002f0c: 4252 negs r2, r2 - 8002f0e: 611a str r2, [r3, #16] + 8002f8a: 687b ldr r3, [r7, #4] + 8002f8c: 681b ldr r3, [r3, #0] + 8002f8e: 2241 movs r2, #65 @ 0x41 + 8002f90: 4252 negs r2, r2 + 8002f92: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); - 8002f10: 687b ldr r3, [r7, #4] - 8002f12: 0018 movs r0, r3 - 8002f14: f000 fa08 bl 8003328 + 8002f94: 687b ldr r3, [r7, #4] + 8002f96: 0018 movs r0, r3 + 8002f98: f000 fa08 bl 80033ac #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) - 8002f18: 68bb ldr r3, [r7, #8] - 8002f1a: 2220 movs r2, #32 - 8002f1c: 4013 ands r3, r2 - 8002f1e: d00c beq.n 8002f3a + 8002f9c: 68bb ldr r3, [r7, #8] + 8002f9e: 2220 movs r2, #32 + 8002fa0: 4013 ands r3, r2 + 8002fa2: d00c beq.n 8002fbe { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) - 8002f20: 68fb ldr r3, [r7, #12] - 8002f22: 2220 movs r2, #32 - 8002f24: 4013 ands r3, r2 - 8002f26: d008 beq.n 8002f3a + 8002fa4: 68fb ldr r3, [r7, #12] + 8002fa6: 2220 movs r2, #32 + 8002fa8: 4013 ands r3, r2 + 8002faa: d008 beq.n 8002fbe { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); - 8002f28: 687b ldr r3, [r7, #4] - 8002f2a: 681b ldr r3, [r3, #0] - 8002f2c: 2221 movs r2, #33 @ 0x21 - 8002f2e: 4252 negs r2, r2 - 8002f30: 611a str r2, [r3, #16] + 8002fac: 687b ldr r3, [r7, #4] + 8002fae: 681b ldr r3, [r3, #0] + 8002fb0: 2221 movs r2, #33 @ 0x21 + 8002fb2: 4252 negs r2, r2 + 8002fb4: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); - 8002f32: 687b ldr r3, [r7, #4] - 8002f34: 0018 movs r0, r3 - 8002f36: f000 feb7 bl 8003ca8 + 8002fb6: 687b ldr r3, [r7, #4] + 8002fb8: 0018 movs r0, r3 + 8002fba: f000 feb7 bl 8003d2c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } - 8002f3a: 46c0 nop @ (mov r8, r8) - 8002f3c: 46bd mov sp, r7 - 8002f3e: b004 add sp, #16 - 8002f40: bd80 pop {r7, pc} - 8002f42: 46c0 nop @ (mov r8, r8) - 8002f44: ffffdf7f .word 0xffffdf7f - 8002f48: fffffeff .word 0xfffffeff + 8002fbe: 46c0 nop @ (mov r8, r8) + 8002fc0: 46bd mov sp, r7 + 8002fc2: b004 add sp, #16 + 8002fc4: bd80 pop {r7, pc} + 8002fc6: 46c0 nop @ (mov r8, r8) + 8002fc8: ffffdf7f .word 0xffffdf7f + 8002fcc: fffffeff .word 0xfffffeff -08002f4c : +08002fd0 : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { - 8002f4c: b580 push {r7, lr} - 8002f4e: b086 sub sp, #24 - 8002f50: af00 add r7, sp, #0 - 8002f52: 60f8 str r0, [r7, #12] - 8002f54: 60b9 str r1, [r7, #8] - 8002f56: 607a str r2, [r7, #4] + 8002fd0: b580 push {r7, lr} + 8002fd2: b086 sub sp, #24 + 8002fd4: af00 add r7, sp, #0 + 8002fd6: 60f8 str r0, [r7, #12] + 8002fd8: 60b9 str r1, [r7, #8] + 8002fda: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; - 8002f58: 2317 movs r3, #23 - 8002f5a: 18fb adds r3, r7, r3 - 8002f5c: 2200 movs r2, #0 - 8002f5e: 701a strb r2, [r3, #0] + 8002fdc: 2317 movs r3, #23 + 8002fde: 18fb adds r3, r7, r3 + 8002fe0: 2200 movs r2, #0 + 8002fe2: 701a strb r2, [r3, #0] assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); /* Process Locked */ __HAL_LOCK(htim); - 8002f60: 68fb ldr r3, [r7, #12] - 8002f62: 223c movs r2, #60 @ 0x3c - 8002f64: 5c9b ldrb r3, [r3, r2] - 8002f66: 2b01 cmp r3, #1 - 8002f68: d101 bne.n 8002f6e - 8002f6a: 2302 movs r3, #2 - 8002f6c: e0e5 b.n 800313a - 8002f6e: 68fb ldr r3, [r7, #12] - 8002f70: 223c movs r2, #60 @ 0x3c - 8002f72: 2101 movs r1, #1 - 8002f74: 5499 strb r1, [r3, r2] + 8002fe4: 68fb ldr r3, [r7, #12] + 8002fe6: 223c movs r2, #60 @ 0x3c + 8002fe8: 5c9b ldrb r3, [r3, r2] + 8002fea: 2b01 cmp r3, #1 + 8002fec: d101 bne.n 8002ff2 + 8002fee: 2302 movs r3, #2 + 8002ff0: e0e5 b.n 80031be + 8002ff2: 68fb ldr r3, [r7, #12] + 8002ff4: 223c movs r2, #60 @ 0x3c + 8002ff6: 2101 movs r1, #1 + 8002ff8: 5499 strb r1, [r3, r2] switch (Channel) - 8002f76: 687b ldr r3, [r7, #4] - 8002f78: 2b14 cmp r3, #20 - 8002f7a: d900 bls.n 8002f7e - 8002f7c: e0d1 b.n 8003122 - 8002f7e: 687b ldr r3, [r7, #4] - 8002f80: 009a lsls r2, r3, #2 - 8002f82: 4b70 ldr r3, [pc, #448] @ (8003144 ) - 8002f84: 18d3 adds r3, r2, r3 - 8002f86: 681b ldr r3, [r3, #0] - 8002f88: 469f mov pc, r3 + 8002ffa: 687b ldr r3, [r7, #4] + 8002ffc: 2b14 cmp r3, #20 + 8002ffe: d900 bls.n 8003002 + 8003000: e0d1 b.n 80031a6 + 8003002: 687b ldr r3, [r7, #4] + 8003004: 009a lsls r2, r3, #2 + 8003006: 4b70 ldr r3, [pc, #448] @ (80031c8 ) + 8003008: 18d3 adds r3, r2, r3 + 800300a: 681b ldr r3, [r3, #0] + 800300c: 469f mov pc, r3 { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the Channel 1 in PWM mode */ TIM_OC1_SetConfig(htim->Instance, sConfig); - 8002f8a: 68fb ldr r3, [r7, #12] - 8002f8c: 681b ldr r3, [r3, #0] - 8002f8e: 68ba ldr r2, [r7, #8] - 8002f90: 0011 movs r1, r2 - 8002f92: 0018 movs r0, r3 - 8002f94: f000 fa4c bl 8003430 + 800300e: 68fb ldr r3, [r7, #12] + 8003010: 681b ldr r3, [r3, #0] + 8003012: 68ba ldr r2, [r7, #8] + 8003014: 0011 movs r1, r2 + 8003016: 0018 movs r0, r3 + 8003018: f000 fa4c bl 80034b4 /* Set the Preload enable bit for channel1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; - 8002f98: 68fb ldr r3, [r7, #12] - 8002f9a: 681b ldr r3, [r3, #0] - 8002f9c: 699a ldr r2, [r3, #24] - 8002f9e: 68fb ldr r3, [r7, #12] - 8002fa0: 681b ldr r3, [r3, #0] - 8002fa2: 2108 movs r1, #8 - 8002fa4: 430a orrs r2, r1 - 8002fa6: 619a str r2, [r3, #24] + 800301c: 68fb ldr r3, [r7, #12] + 800301e: 681b ldr r3, [r3, #0] + 8003020: 699a ldr r2, [r3, #24] + 8003022: 68fb ldr r3, [r7, #12] + 8003024: 681b ldr r3, [r3, #0] + 8003026: 2108 movs r1, #8 + 8003028: 430a orrs r2, r1 + 800302a: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; - 8002fa8: 68fb ldr r3, [r7, #12] - 8002faa: 681b ldr r3, [r3, #0] - 8002fac: 699a ldr r2, [r3, #24] - 8002fae: 68fb ldr r3, [r7, #12] - 8002fb0: 681b ldr r3, [r3, #0] - 8002fb2: 2104 movs r1, #4 - 8002fb4: 438a bics r2, r1 - 8002fb6: 619a str r2, [r3, #24] + 800302c: 68fb ldr r3, [r7, #12] + 800302e: 681b ldr r3, [r3, #0] + 8003030: 699a ldr r2, [r3, #24] + 8003032: 68fb ldr r3, [r7, #12] + 8003034: 681b ldr r3, [r3, #0] + 8003036: 2104 movs r1, #4 + 8003038: 438a bics r2, r1 + 800303a: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode; - 8002fb8: 68fb ldr r3, [r7, #12] - 8002fba: 681b ldr r3, [r3, #0] - 8002fbc: 6999 ldr r1, [r3, #24] - 8002fbe: 68bb ldr r3, [r7, #8] - 8002fc0: 691a ldr r2, [r3, #16] - 8002fc2: 68fb ldr r3, [r7, #12] - 8002fc4: 681b ldr r3, [r3, #0] - 8002fc6: 430a orrs r2, r1 - 8002fc8: 619a str r2, [r3, #24] + 800303c: 68fb ldr r3, [r7, #12] + 800303e: 681b ldr r3, [r3, #0] + 8003040: 6999 ldr r1, [r3, #24] + 8003042: 68bb ldr r3, [r7, #8] + 8003044: 691a ldr r2, [r3, #16] + 8003046: 68fb ldr r3, [r7, #12] + 8003048: 681b ldr r3, [r3, #0] + 800304a: 430a orrs r2, r1 + 800304c: 619a str r2, [r3, #24] break; - 8002fca: e0af b.n 800312c + 800304e: e0af b.n 80031b0 { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the Channel 2 in PWM mode */ TIM_OC2_SetConfig(htim->Instance, sConfig); - 8002fcc: 68fb ldr r3, [r7, #12] - 8002fce: 681b ldr r3, [r3, #0] - 8002fd0: 68ba ldr r2, [r7, #8] - 8002fd2: 0011 movs r1, r2 - 8002fd4: 0018 movs r0, r3 - 8002fd6: f000 faab bl 8003530 + 8003050: 68fb ldr r3, [r7, #12] + 8003052: 681b ldr r3, [r3, #0] + 8003054: 68ba ldr r2, [r7, #8] + 8003056: 0011 movs r1, r2 + 8003058: 0018 movs r0, r3 + 800305a: f000 faab bl 80035b4 /* Set the Preload enable bit for channel2 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; - 8002fda: 68fb ldr r3, [r7, #12] - 8002fdc: 681b ldr r3, [r3, #0] - 8002fde: 699a ldr r2, [r3, #24] - 8002fe0: 68fb ldr r3, [r7, #12] - 8002fe2: 681b ldr r3, [r3, #0] - 8002fe4: 2180 movs r1, #128 @ 0x80 - 8002fe6: 0109 lsls r1, r1, #4 - 8002fe8: 430a orrs r2, r1 - 8002fea: 619a str r2, [r3, #24] + 800305e: 68fb ldr r3, [r7, #12] + 8003060: 681b ldr r3, [r3, #0] + 8003062: 699a ldr r2, [r3, #24] + 8003064: 68fb ldr r3, [r7, #12] + 8003066: 681b ldr r3, [r3, #0] + 8003068: 2180 movs r1, #128 @ 0x80 + 800306a: 0109 lsls r1, r1, #4 + 800306c: 430a orrs r2, r1 + 800306e: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; - 8002fec: 68fb ldr r3, [r7, #12] - 8002fee: 681b ldr r3, [r3, #0] - 8002ff0: 699a ldr r2, [r3, #24] - 8002ff2: 68fb ldr r3, [r7, #12] - 8002ff4: 681b ldr r3, [r3, #0] - 8002ff6: 4954 ldr r1, [pc, #336] @ (8003148 ) - 8002ff8: 400a ands r2, r1 - 8002ffa: 619a str r2, [r3, #24] + 8003070: 68fb ldr r3, [r7, #12] + 8003072: 681b ldr r3, [r3, #0] + 8003074: 699a ldr r2, [r3, #24] + 8003076: 68fb ldr r3, [r7, #12] + 8003078: 681b ldr r3, [r3, #0] + 800307a: 4954 ldr r1, [pc, #336] @ (80031cc ) + 800307c: 400a ands r2, r1 + 800307e: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; - 8002ffc: 68fb ldr r3, [r7, #12] - 8002ffe: 681b ldr r3, [r3, #0] - 8003000: 6999 ldr r1, [r3, #24] - 8003002: 68bb ldr r3, [r7, #8] - 8003004: 691b ldr r3, [r3, #16] - 8003006: 021a lsls r2, r3, #8 - 8003008: 68fb ldr r3, [r7, #12] - 800300a: 681b ldr r3, [r3, #0] - 800300c: 430a orrs r2, r1 - 800300e: 619a str r2, [r3, #24] + 8003080: 68fb ldr r3, [r7, #12] + 8003082: 681b ldr r3, [r3, #0] + 8003084: 6999 ldr r1, [r3, #24] + 8003086: 68bb ldr r3, [r7, #8] + 8003088: 691b ldr r3, [r3, #16] + 800308a: 021a lsls r2, r3, #8 + 800308c: 68fb ldr r3, [r7, #12] + 800308e: 681b ldr r3, [r3, #0] + 8003090: 430a orrs r2, r1 + 8003092: 619a str r2, [r3, #24] break; - 8003010: e08c b.n 800312c + 8003094: e08c b.n 80031b0 { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the Channel 3 in PWM mode */ TIM_OC3_SetConfig(htim->Instance, sConfig); - 8003012: 68fb ldr r3, [r7, #12] - 8003014: 681b ldr r3, [r3, #0] - 8003016: 68ba ldr r2, [r7, #8] - 8003018: 0011 movs r1, r2 - 800301a: 0018 movs r0, r3 - 800301c: f000 fb06 bl 800362c + 8003096: 68fb ldr r3, [r7, #12] + 8003098: 681b ldr r3, [r3, #0] + 800309a: 68ba ldr r2, [r7, #8] + 800309c: 0011 movs r1, r2 + 800309e: 0018 movs r0, r3 + 80030a0: f000 fb06 bl 80036b0 /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; - 8003020: 68fb ldr r3, [r7, #12] - 8003022: 681b ldr r3, [r3, #0] - 8003024: 69da ldr r2, [r3, #28] - 8003026: 68fb ldr r3, [r7, #12] - 8003028: 681b ldr r3, [r3, #0] - 800302a: 2108 movs r1, #8 - 800302c: 430a orrs r2, r1 - 800302e: 61da str r2, [r3, #28] + 80030a4: 68fb ldr r3, [r7, #12] + 80030a6: 681b ldr r3, [r3, #0] + 80030a8: 69da ldr r2, [r3, #28] + 80030aa: 68fb ldr r3, [r7, #12] + 80030ac: 681b ldr r3, [r3, #0] + 80030ae: 2108 movs r1, #8 + 80030b0: 430a orrs r2, r1 + 80030b2: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; - 8003030: 68fb ldr r3, [r7, #12] - 8003032: 681b ldr r3, [r3, #0] - 8003034: 69da ldr r2, [r3, #28] - 8003036: 68fb ldr r3, [r7, #12] - 8003038: 681b ldr r3, [r3, #0] - 800303a: 2104 movs r1, #4 - 800303c: 438a bics r2, r1 - 800303e: 61da str r2, [r3, #28] + 80030b4: 68fb ldr r3, [r7, #12] + 80030b6: 681b ldr r3, [r3, #0] + 80030b8: 69da ldr r2, [r3, #28] + 80030ba: 68fb ldr r3, [r7, #12] + 80030bc: 681b ldr r3, [r3, #0] + 80030be: 2104 movs r1, #4 + 80030c0: 438a bics r2, r1 + 80030c2: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode; - 8003040: 68fb ldr r3, [r7, #12] - 8003042: 681b ldr r3, [r3, #0] - 8003044: 69d9 ldr r1, [r3, #28] - 8003046: 68bb ldr r3, [r7, #8] - 8003048: 691a ldr r2, [r3, #16] - 800304a: 68fb ldr r3, [r7, #12] - 800304c: 681b ldr r3, [r3, #0] - 800304e: 430a orrs r2, r1 - 8003050: 61da str r2, [r3, #28] + 80030c4: 68fb ldr r3, [r7, #12] + 80030c6: 681b ldr r3, [r3, #0] + 80030c8: 69d9 ldr r1, [r3, #28] + 80030ca: 68bb ldr r3, [r7, #8] + 80030cc: 691a ldr r2, [r3, #16] + 80030ce: 68fb ldr r3, [r7, #12] + 80030d0: 681b ldr r3, [r3, #0] + 80030d2: 430a orrs r2, r1 + 80030d4: 61da str r2, [r3, #28] break; - 8003052: e06b b.n 800312c + 80030d6: e06b b.n 80031b0 { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the Channel 4 in PWM mode */ TIM_OC4_SetConfig(htim->Instance, sConfig); - 8003054: 68fb ldr r3, [r7, #12] - 8003056: 681b ldr r3, [r3, #0] - 8003058: 68ba ldr r2, [r7, #8] - 800305a: 0011 movs r1, r2 - 800305c: 0018 movs r0, r3 - 800305e: f000 fb67 bl 8003730 + 80030d8: 68fb ldr r3, [r7, #12] + 80030da: 681b ldr r3, [r3, #0] + 80030dc: 68ba ldr r2, [r7, #8] + 80030de: 0011 movs r1, r2 + 80030e0: 0018 movs r0, r3 + 80030e2: f000 fb67 bl 80037b4 /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; - 8003062: 68fb ldr r3, [r7, #12] - 8003064: 681b ldr r3, [r3, #0] - 8003066: 69da ldr r2, [r3, #28] - 8003068: 68fb ldr r3, [r7, #12] - 800306a: 681b ldr r3, [r3, #0] - 800306c: 2180 movs r1, #128 @ 0x80 - 800306e: 0109 lsls r1, r1, #4 - 8003070: 430a orrs r2, r1 - 8003072: 61da str r2, [r3, #28] + 80030e6: 68fb ldr r3, [r7, #12] + 80030e8: 681b ldr r3, [r3, #0] + 80030ea: 69da ldr r2, [r3, #28] + 80030ec: 68fb ldr r3, [r7, #12] + 80030ee: 681b ldr r3, [r3, #0] + 80030f0: 2180 movs r1, #128 @ 0x80 + 80030f2: 0109 lsls r1, r1, #4 + 80030f4: 430a orrs r2, r1 + 80030f6: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; - 8003074: 68fb ldr r3, [r7, #12] - 8003076: 681b ldr r3, [r3, #0] - 8003078: 69da ldr r2, [r3, #28] - 800307a: 68fb ldr r3, [r7, #12] - 800307c: 681b ldr r3, [r3, #0] - 800307e: 4932 ldr r1, [pc, #200] @ (8003148 ) - 8003080: 400a ands r2, r1 - 8003082: 61da str r2, [r3, #28] + 80030f8: 68fb ldr r3, [r7, #12] + 80030fa: 681b ldr r3, [r3, #0] + 80030fc: 69da ldr r2, [r3, #28] + 80030fe: 68fb ldr r3, [r7, #12] + 8003100: 681b ldr r3, [r3, #0] + 8003102: 4932 ldr r1, [pc, #200] @ (80031cc ) + 8003104: 400a ands r2, r1 + 8003106: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; - 8003084: 68fb ldr r3, [r7, #12] - 8003086: 681b ldr r3, [r3, #0] - 8003088: 69d9 ldr r1, [r3, #28] - 800308a: 68bb ldr r3, [r7, #8] - 800308c: 691b ldr r3, [r3, #16] - 800308e: 021a lsls r2, r3, #8 - 8003090: 68fb ldr r3, [r7, #12] - 8003092: 681b ldr r3, [r3, #0] - 8003094: 430a orrs r2, r1 - 8003096: 61da str r2, [r3, #28] + 8003108: 68fb ldr r3, [r7, #12] + 800310a: 681b ldr r3, [r3, #0] + 800310c: 69d9 ldr r1, [r3, #28] + 800310e: 68bb ldr r3, [r7, #8] + 8003110: 691b ldr r3, [r3, #16] + 8003112: 021a lsls r2, r3, #8 + 8003114: 68fb ldr r3, [r7, #12] + 8003116: 681b ldr r3, [r3, #0] + 8003118: 430a orrs r2, r1 + 800311a: 61da str r2, [r3, #28] break; - 8003098: e048 b.n 800312c + 800311c: e048 b.n 80031b0 { /* Check the parameters */ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); /* Configure the Channel 5 in PWM mode */ TIM_OC5_SetConfig(htim->Instance, sConfig); - 800309a: 68fb ldr r3, [r7, #12] - 800309c: 681b ldr r3, [r3, #0] - 800309e: 68ba ldr r2, [r7, #8] - 80030a0: 0011 movs r1, r2 - 80030a2: 0018 movs r0, r3 - 80030a4: f000 fba8 bl 80037f8 + 800311e: 68fb ldr r3, [r7, #12] + 8003120: 681b ldr r3, [r3, #0] + 8003122: 68ba ldr r2, [r7, #8] + 8003124: 0011 movs r1, r2 + 8003126: 0018 movs r0, r3 + 8003128: f000 fba8 bl 800387c /* Set the Preload enable bit for channel5*/ htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; - 80030a8: 68fb ldr r3, [r7, #12] - 80030aa: 681b ldr r3, [r3, #0] - 80030ac: 6d5a ldr r2, [r3, #84] @ 0x54 - 80030ae: 68fb ldr r3, [r7, #12] - 80030b0: 681b ldr r3, [r3, #0] - 80030b2: 2108 movs r1, #8 - 80030b4: 430a orrs r2, r1 - 80030b6: 655a str r2, [r3, #84] @ 0x54 + 800312c: 68fb ldr r3, [r7, #12] + 800312e: 681b ldr r3, [r3, #0] + 8003130: 6d5a ldr r2, [r3, #84] @ 0x54 + 8003132: 68fb ldr r3, [r7, #12] + 8003134: 681b ldr r3, [r3, #0] + 8003136: 2108 movs r1, #8 + 8003138: 430a orrs r2, r1 + 800313a: 655a str r2, [r3, #84] @ 0x54 /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; - 80030b8: 68fb ldr r3, [r7, #12] - 80030ba: 681b ldr r3, [r3, #0] - 80030bc: 6d5a ldr r2, [r3, #84] @ 0x54 - 80030be: 68fb ldr r3, [r7, #12] - 80030c0: 681b ldr r3, [r3, #0] - 80030c2: 2104 movs r1, #4 - 80030c4: 438a bics r2, r1 - 80030c6: 655a str r2, [r3, #84] @ 0x54 + 800313c: 68fb ldr r3, [r7, #12] + 800313e: 681b ldr r3, [r3, #0] + 8003140: 6d5a ldr r2, [r3, #84] @ 0x54 + 8003142: 68fb ldr r3, [r7, #12] + 8003144: 681b ldr r3, [r3, #0] + 8003146: 2104 movs r1, #4 + 8003148: 438a bics r2, r1 + 800314a: 655a str r2, [r3, #84] @ 0x54 htim->Instance->CCMR3 |= sConfig->OCFastMode; - 80030c8: 68fb ldr r3, [r7, #12] - 80030ca: 681b ldr r3, [r3, #0] - 80030cc: 6d59 ldr r1, [r3, #84] @ 0x54 - 80030ce: 68bb ldr r3, [r7, #8] - 80030d0: 691a ldr r2, [r3, #16] - 80030d2: 68fb ldr r3, [r7, #12] - 80030d4: 681b ldr r3, [r3, #0] - 80030d6: 430a orrs r2, r1 - 80030d8: 655a str r2, [r3, #84] @ 0x54 + 800314c: 68fb ldr r3, [r7, #12] + 800314e: 681b ldr r3, [r3, #0] + 8003150: 6d59 ldr r1, [r3, #84] @ 0x54 + 8003152: 68bb ldr r3, [r7, #8] + 8003154: 691a ldr r2, [r3, #16] + 8003156: 68fb ldr r3, [r7, #12] + 8003158: 681b ldr r3, [r3, #0] + 800315a: 430a orrs r2, r1 + 800315c: 655a str r2, [r3, #84] @ 0x54 break; - 80030da: e027 b.n 800312c + 800315e: e027 b.n 80031b0 { /* Check the parameters */ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); /* Configure the Channel 6 in PWM mode */ TIM_OC6_SetConfig(htim->Instance, sConfig); - 80030dc: 68fb ldr r3, [r7, #12] - 80030de: 681b ldr r3, [r3, #0] - 80030e0: 68ba ldr r2, [r7, #8] - 80030e2: 0011 movs r1, r2 - 80030e4: 0018 movs r0, r3 - 80030e6: f000 fbe1 bl 80038ac + 8003160: 68fb ldr r3, [r7, #12] + 8003162: 681b ldr r3, [r3, #0] + 8003164: 68ba ldr r2, [r7, #8] + 8003166: 0011 movs r1, r2 + 8003168: 0018 movs r0, r3 + 800316a: f000 fbe1 bl 8003930 /* Set the Preload enable bit for channel6 */ htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; - 80030ea: 68fb ldr r3, [r7, #12] - 80030ec: 681b ldr r3, [r3, #0] - 80030ee: 6d5a ldr r2, [r3, #84] @ 0x54 - 80030f0: 68fb ldr r3, [r7, #12] - 80030f2: 681b ldr r3, [r3, #0] - 80030f4: 2180 movs r1, #128 @ 0x80 - 80030f6: 0109 lsls r1, r1, #4 - 80030f8: 430a orrs r2, r1 - 80030fa: 655a str r2, [r3, #84] @ 0x54 + 800316e: 68fb ldr r3, [r7, #12] + 8003170: 681b ldr r3, [r3, #0] + 8003172: 6d5a ldr r2, [r3, #84] @ 0x54 + 8003174: 68fb ldr r3, [r7, #12] + 8003176: 681b ldr r3, [r3, #0] + 8003178: 2180 movs r1, #128 @ 0x80 + 800317a: 0109 lsls r1, r1, #4 + 800317c: 430a orrs r2, r1 + 800317e: 655a str r2, [r3, #84] @ 0x54 /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; - 80030fc: 68fb ldr r3, [r7, #12] - 80030fe: 681b ldr r3, [r3, #0] - 8003100: 6d5a ldr r2, [r3, #84] @ 0x54 - 8003102: 68fb ldr r3, [r7, #12] - 8003104: 681b ldr r3, [r3, #0] - 8003106: 4910 ldr r1, [pc, #64] @ (8003148 ) - 8003108: 400a ands r2, r1 - 800310a: 655a str r2, [r3, #84] @ 0x54 + 8003180: 68fb ldr r3, [r7, #12] + 8003182: 681b ldr r3, [r3, #0] + 8003184: 6d5a ldr r2, [r3, #84] @ 0x54 + 8003186: 68fb ldr r3, [r7, #12] + 8003188: 681b ldr r3, [r3, #0] + 800318a: 4910 ldr r1, [pc, #64] @ (80031cc ) + 800318c: 400a ands r2, r1 + 800318e: 655a str r2, [r3, #84] @ 0x54 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; - 800310c: 68fb ldr r3, [r7, #12] - 800310e: 681b ldr r3, [r3, #0] - 8003110: 6d59 ldr r1, [r3, #84] @ 0x54 - 8003112: 68bb ldr r3, [r7, #8] - 8003114: 691b ldr r3, [r3, #16] - 8003116: 021a lsls r2, r3, #8 - 8003118: 68fb ldr r3, [r7, #12] - 800311a: 681b ldr r3, [r3, #0] - 800311c: 430a orrs r2, r1 - 800311e: 655a str r2, [r3, #84] @ 0x54 + 8003190: 68fb ldr r3, [r7, #12] + 8003192: 681b ldr r3, [r3, #0] + 8003194: 6d59 ldr r1, [r3, #84] @ 0x54 + 8003196: 68bb ldr r3, [r7, #8] + 8003198: 691b ldr r3, [r3, #16] + 800319a: 021a lsls r2, r3, #8 + 800319c: 68fb ldr r3, [r7, #12] + 800319e: 681b ldr r3, [r3, #0] + 80031a0: 430a orrs r2, r1 + 80031a2: 655a str r2, [r3, #84] @ 0x54 break; - 8003120: e004 b.n 800312c + 80031a4: e004 b.n 80031b0 } default: status = HAL_ERROR; - 8003122: 2317 movs r3, #23 - 8003124: 18fb adds r3, r7, r3 - 8003126: 2201 movs r2, #1 - 8003128: 701a strb r2, [r3, #0] + 80031a6: 2317 movs r3, #23 + 80031a8: 18fb adds r3, r7, r3 + 80031aa: 2201 movs r2, #1 + 80031ac: 701a strb r2, [r3, #0] break; - 800312a: 46c0 nop @ (mov r8, r8) + 80031ae: 46c0 nop @ (mov r8, r8) } __HAL_UNLOCK(htim); - 800312c: 68fb ldr r3, [r7, #12] - 800312e: 223c movs r2, #60 @ 0x3c - 8003130: 2100 movs r1, #0 - 8003132: 5499 strb r1, [r3, r2] + 80031b0: 68fb ldr r3, [r7, #12] + 80031b2: 223c movs r2, #60 @ 0x3c + 80031b4: 2100 movs r1, #0 + 80031b6: 5499 strb r1, [r3, r2] return status; - 8003134: 2317 movs r3, #23 - 8003136: 18fb adds r3, r7, r3 - 8003138: 781b ldrb r3, [r3, #0] + 80031b8: 2317 movs r3, #23 + 80031ba: 18fb adds r3, r7, r3 + 80031bc: 781b ldrb r3, [r3, #0] } - 800313a: 0018 movs r0, r3 - 800313c: 46bd mov sp, r7 - 800313e: b006 add sp, #24 - 8003140: bd80 pop {r7, pc} - 8003142: 46c0 nop @ (mov r8, r8) - 8003144: 08004e1c .word 0x08004e1c - 8003148: fffffbff .word 0xfffffbff + 80031be: 0018 movs r0, r3 + 80031c0: 46bd mov sp, r7 + 80031c2: b006 add sp, #24 + 80031c4: bd80 pop {r7, pc} + 80031c6: 46c0 nop @ (mov r8, r8) + 80031c8: 08004ea0 .word 0x08004ea0 + 80031cc: fffffbff .word 0xfffffbff -0800314c : +080031d0 : * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) { - 800314c: b580 push {r7, lr} - 800314e: b084 sub sp, #16 - 8003150: af00 add r7, sp, #0 - 8003152: 6078 str r0, [r7, #4] - 8003154: 6039 str r1, [r7, #0] + 80031d0: b580 push {r7, lr} + 80031d2: b084 sub sp, #16 + 80031d4: af00 add r7, sp, #0 + 80031d6: 6078 str r0, [r7, #4] + 80031d8: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; - 8003156: 230f movs r3, #15 - 8003158: 18fb adds r3, r7, r3 - 800315a: 2200 movs r2, #0 - 800315c: 701a strb r2, [r3, #0] + 80031da: 230f movs r3, #15 + 80031dc: 18fb adds r3, r7, r3 + 80031de: 2200 movs r2, #0 + 80031e0: 701a strb r2, [r3, #0] uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); - 800315e: 687b ldr r3, [r7, #4] - 8003160: 223c movs r2, #60 @ 0x3c - 8003162: 5c9b ldrb r3, [r3, r2] - 8003164: 2b01 cmp r3, #1 - 8003166: d101 bne.n 800316c - 8003168: 2302 movs r3, #2 - 800316a: e0bc b.n 80032e6 - 800316c: 687b ldr r3, [r7, #4] - 800316e: 223c movs r2, #60 @ 0x3c - 8003170: 2101 movs r1, #1 - 8003172: 5499 strb r1, [r3, r2] + 80031e2: 687b ldr r3, [r7, #4] + 80031e4: 223c movs r2, #60 @ 0x3c + 80031e6: 5c9b ldrb r3, [r3, r2] + 80031e8: 2b01 cmp r3, #1 + 80031ea: d101 bne.n 80031f0 + 80031ec: 2302 movs r3, #2 + 80031ee: e0bc b.n 800336a + 80031f0: 687b ldr r3, [r7, #4] + 80031f2: 223c movs r2, #60 @ 0x3c + 80031f4: 2101 movs r1, #1 + 80031f6: 5499 strb r1, [r3, r2] htim->State = HAL_TIM_STATE_BUSY; - 8003174: 687b ldr r3, [r7, #4] - 8003176: 223d movs r2, #61 @ 0x3d - 8003178: 2102 movs r1, #2 - 800317a: 5499 strb r1, [r3, r2] + 80031f8: 687b ldr r3, [r7, #4] + 80031fa: 223d movs r2, #61 @ 0x3d + 80031fc: 2102 movs r1, #2 + 80031fe: 5499 strb r1, [r3, r2] /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; - 800317c: 687b ldr r3, [r7, #4] - 800317e: 681b ldr r3, [r3, #0] - 8003180: 689b ldr r3, [r3, #8] - 8003182: 60bb str r3, [r7, #8] + 8003200: 687b ldr r3, [r7, #4] + 8003202: 681b ldr r3, [r3, #0] + 8003204: 689b ldr r3, [r3, #8] + 8003206: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); - 8003184: 68bb ldr r3, [r7, #8] - 8003186: 4a5a ldr r2, [pc, #360] @ (80032f0 ) - 8003188: 4013 ands r3, r2 - 800318a: 60bb str r3, [r7, #8] + 8003208: 68bb ldr r3, [r7, #8] + 800320a: 4a5a ldr r2, [pc, #360] @ (8003374 ) + 800320c: 4013 ands r3, r2 + 800320e: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); - 800318c: 68bb ldr r3, [r7, #8] - 800318e: 4a59 ldr r2, [pc, #356] @ (80032f4 ) - 8003190: 4013 ands r3, r2 - 8003192: 60bb str r3, [r7, #8] + 8003210: 68bb ldr r3, [r7, #8] + 8003212: 4a59 ldr r2, [pc, #356] @ (8003378 ) + 8003214: 4013 ands r3, r2 + 8003216: 60bb str r3, [r7, #8] htim->Instance->SMCR = tmpsmcr; - 8003194: 687b ldr r3, [r7, #4] - 8003196: 681b ldr r3, [r3, #0] - 8003198: 68ba ldr r2, [r7, #8] - 800319a: 609a str r2, [r3, #8] + 8003218: 687b ldr r3, [r7, #4] + 800321a: 681b ldr r3, [r3, #0] + 800321c: 68ba ldr r2, [r7, #8] + 800321e: 609a str r2, [r3, #8] switch (sClockSourceConfig->ClockSource) - 800319c: 683b ldr r3, [r7, #0] - 800319e: 681b ldr r3, [r3, #0] - 80031a0: 2280 movs r2, #128 @ 0x80 - 80031a2: 0192 lsls r2, r2, #6 - 80031a4: 4293 cmp r3, r2 - 80031a6: d040 beq.n 800322a - 80031a8: 2280 movs r2, #128 @ 0x80 - 80031aa: 0192 lsls r2, r2, #6 - 80031ac: 4293 cmp r3, r2 - 80031ae: d900 bls.n 80031b2 - 80031b0: e088 b.n 80032c4 - 80031b2: 2280 movs r2, #128 @ 0x80 - 80031b4: 0152 lsls r2, r2, #5 - 80031b6: 4293 cmp r3, r2 - 80031b8: d100 bne.n 80031bc - 80031ba: e088 b.n 80032ce - 80031bc: 2280 movs r2, #128 @ 0x80 - 80031be: 0152 lsls r2, r2, #5 - 80031c0: 4293 cmp r3, r2 - 80031c2: d900 bls.n 80031c6 - 80031c4: e07e b.n 80032c4 - 80031c6: 2b70 cmp r3, #112 @ 0x70 - 80031c8: d018 beq.n 80031fc - 80031ca: d900 bls.n 80031ce - 80031cc: e07a b.n 80032c4 - 80031ce: 2b60 cmp r3, #96 @ 0x60 - 80031d0: d04f beq.n 8003272 - 80031d2: d900 bls.n 80031d6 - 80031d4: e076 b.n 80032c4 - 80031d6: 2b50 cmp r3, #80 @ 0x50 - 80031d8: d03b beq.n 8003252 - 80031da: d900 bls.n 80031de - 80031dc: e072 b.n 80032c4 - 80031de: 2b40 cmp r3, #64 @ 0x40 - 80031e0: d057 beq.n 8003292 - 80031e2: d900 bls.n 80031e6 - 80031e4: e06e b.n 80032c4 - 80031e6: 2b30 cmp r3, #48 @ 0x30 - 80031e8: d063 beq.n 80032b2 - 80031ea: d86b bhi.n 80032c4 - 80031ec: 2b20 cmp r3, #32 - 80031ee: d060 beq.n 80032b2 - 80031f0: d868 bhi.n 80032c4 - 80031f2: 2b00 cmp r3, #0 - 80031f4: d05d beq.n 80032b2 - 80031f6: 2b10 cmp r3, #16 - 80031f8: d05b beq.n 80032b2 - 80031fa: e063 b.n 80032c4 + 8003220: 683b ldr r3, [r7, #0] + 8003222: 681b ldr r3, [r3, #0] + 8003224: 2280 movs r2, #128 @ 0x80 + 8003226: 0192 lsls r2, r2, #6 + 8003228: 4293 cmp r3, r2 + 800322a: d040 beq.n 80032ae + 800322c: 2280 movs r2, #128 @ 0x80 + 800322e: 0192 lsls r2, r2, #6 + 8003230: 4293 cmp r3, r2 + 8003232: d900 bls.n 8003236 + 8003234: e088 b.n 8003348 + 8003236: 2280 movs r2, #128 @ 0x80 + 8003238: 0152 lsls r2, r2, #5 + 800323a: 4293 cmp r3, r2 + 800323c: d100 bne.n 8003240 + 800323e: e088 b.n 8003352 + 8003240: 2280 movs r2, #128 @ 0x80 + 8003242: 0152 lsls r2, r2, #5 + 8003244: 4293 cmp r3, r2 + 8003246: d900 bls.n 800324a + 8003248: e07e b.n 8003348 + 800324a: 2b70 cmp r3, #112 @ 0x70 + 800324c: d018 beq.n 8003280 + 800324e: d900 bls.n 8003252 + 8003250: e07a b.n 8003348 + 8003252: 2b60 cmp r3, #96 @ 0x60 + 8003254: d04f beq.n 80032f6 + 8003256: d900 bls.n 800325a + 8003258: e076 b.n 8003348 + 800325a: 2b50 cmp r3, #80 @ 0x50 + 800325c: d03b beq.n 80032d6 + 800325e: d900 bls.n 8003262 + 8003260: e072 b.n 8003348 + 8003262: 2b40 cmp r3, #64 @ 0x40 + 8003264: d057 beq.n 8003316 + 8003266: d900 bls.n 800326a + 8003268: e06e b.n 8003348 + 800326a: 2b30 cmp r3, #48 @ 0x30 + 800326c: d063 beq.n 8003336 + 800326e: d86b bhi.n 8003348 + 8003270: 2b20 cmp r3, #32 + 8003272: d060 beq.n 8003336 + 8003274: d868 bhi.n 8003348 + 8003276: 2b00 cmp r3, #0 + 8003278: d05d beq.n 8003336 + 800327a: 2b10 cmp r3, #16 + 800327c: d05b beq.n 8003336 + 800327e: e063 b.n 8003348 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, - 80031fc: 687b ldr r3, [r7, #4] - 80031fe: 6818 ldr r0, [r3, #0] + 8003280: 687b ldr r3, [r7, #4] + 8003282: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, - 8003200: 683b ldr r3, [r7, #0] - 8003202: 6899 ldr r1, [r3, #8] + 8003284: 683b ldr r3, [r7, #0] + 8003286: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, - 8003204: 683b ldr r3, [r7, #0] - 8003206: 685a ldr r2, [r3, #4] + 8003288: 683b ldr r3, [r7, #0] + 800328a: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); - 8003208: 683b ldr r3, [r7, #0] - 800320a: 68db ldr r3, [r3, #12] + 800328c: 683b ldr r3, [r7, #0] + 800328e: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, - 800320c: f000 fc28 bl 8003a60 + 8003290: f000 fc28 bl 8003ae4 /* Select the External clock mode1 and the ETRF trigger */ tmpsmcr = htim->Instance->SMCR; - 8003210: 687b ldr r3, [r7, #4] - 8003212: 681b ldr r3, [r3, #0] - 8003214: 689b ldr r3, [r3, #8] - 8003216: 60bb str r3, [r7, #8] + 8003294: 687b ldr r3, [r7, #4] + 8003296: 681b ldr r3, [r3, #0] + 8003298: 689b ldr r3, [r3, #8] + 800329a: 60bb str r3, [r7, #8] tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); - 8003218: 68bb ldr r3, [r7, #8] - 800321a: 2277 movs r2, #119 @ 0x77 - 800321c: 4313 orrs r3, r2 - 800321e: 60bb str r3, [r7, #8] + 800329c: 68bb ldr r3, [r7, #8] + 800329e: 2277 movs r2, #119 @ 0x77 + 80032a0: 4313 orrs r3, r2 + 80032a2: 60bb str r3, [r7, #8] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; - 8003220: 687b ldr r3, [r7, #4] - 8003222: 681b ldr r3, [r3, #0] - 8003224: 68ba ldr r2, [r7, #8] - 8003226: 609a str r2, [r3, #8] + 80032a4: 687b ldr r3, [r7, #4] + 80032a6: 681b ldr r3, [r3, #0] + 80032a8: 68ba ldr r2, [r7, #8] + 80032aa: 609a str r2, [r3, #8] break; - 8003228: e052 b.n 80032d0 + 80032ac: e052 b.n 8003354 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, - 800322a: 687b ldr r3, [r7, #4] - 800322c: 6818 ldr r0, [r3, #0] + 80032ae: 687b ldr r3, [r7, #4] + 80032b0: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, - 800322e: 683b ldr r3, [r7, #0] - 8003230: 6899 ldr r1, [r3, #8] + 80032b2: 683b ldr r3, [r7, #0] + 80032b4: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, - 8003232: 683b ldr r3, [r7, #0] - 8003234: 685a ldr r2, [r3, #4] + 80032b6: 683b ldr r3, [r7, #0] + 80032b8: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); - 8003236: 683b ldr r3, [r7, #0] - 8003238: 68db ldr r3, [r3, #12] + 80032ba: 683b ldr r3, [r7, #0] + 80032bc: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, - 800323a: f000 fc11 bl 8003a60 + 80032be: f000 fc11 bl 8003ae4 /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; - 800323e: 687b ldr r3, [r7, #4] - 8003240: 681b ldr r3, [r3, #0] - 8003242: 689a ldr r2, [r3, #8] - 8003244: 687b ldr r3, [r7, #4] - 8003246: 681b ldr r3, [r3, #0] - 8003248: 2180 movs r1, #128 @ 0x80 - 800324a: 01c9 lsls r1, r1, #7 - 800324c: 430a orrs r2, r1 - 800324e: 609a str r2, [r3, #8] + 80032c2: 687b ldr r3, [r7, #4] + 80032c4: 681b ldr r3, [r3, #0] + 80032c6: 689a ldr r2, [r3, #8] + 80032c8: 687b ldr r3, [r7, #4] + 80032ca: 681b ldr r3, [r3, #0] + 80032cc: 2180 movs r1, #128 @ 0x80 + 80032ce: 01c9 lsls r1, r1, #7 + 80032d0: 430a orrs r2, r1 + 80032d2: 609a str r2, [r3, #8] break; - 8003250: e03e b.n 80032d0 + 80032d4: e03e b.n 8003354 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, - 8003252: 687b ldr r3, [r7, #4] - 8003254: 6818 ldr r0, [r3, #0] + 80032d6: 687b ldr r3, [r7, #4] + 80032d8: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, - 8003256: 683b ldr r3, [r7, #0] - 8003258: 6859 ldr r1, [r3, #4] + 80032da: 683b ldr r3, [r7, #0] + 80032dc: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); - 800325a: 683b ldr r3, [r7, #0] - 800325c: 68db ldr r3, [r3, #12] + 80032de: 683b ldr r3, [r7, #0] + 80032e0: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, - 800325e: 001a movs r2, r3 - 8003260: f000 fb82 bl 8003968 + 80032e2: 001a movs r2, r3 + 80032e4: f000 fb82 bl 80039ec TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); - 8003264: 687b ldr r3, [r7, #4] - 8003266: 681b ldr r3, [r3, #0] - 8003268: 2150 movs r1, #80 @ 0x50 - 800326a: 0018 movs r0, r3 - 800326c: f000 fbdc bl 8003a28 + 80032e8: 687b ldr r3, [r7, #4] + 80032ea: 681b ldr r3, [r3, #0] + 80032ec: 2150 movs r1, #80 @ 0x50 + 80032ee: 0018 movs r0, r3 + 80032f0: f000 fbdc bl 8003aac break; - 8003270: e02e b.n 80032d0 + 80032f4: e02e b.n 8003354 /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI2_ConfigInputStage(htim->Instance, - 8003272: 687b ldr r3, [r7, #4] - 8003274: 6818 ldr r0, [r3, #0] + 80032f6: 687b ldr r3, [r7, #4] + 80032f8: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, - 8003276: 683b ldr r3, [r7, #0] - 8003278: 6859 ldr r1, [r3, #4] + 80032fa: 683b ldr r3, [r7, #0] + 80032fc: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); - 800327a: 683b ldr r3, [r7, #0] - 800327c: 68db ldr r3, [r3, #12] + 80032fe: 683b ldr r3, [r7, #0] + 8003300: 68db ldr r3, [r3, #12] TIM_TI2_ConfigInputStage(htim->Instance, - 800327e: 001a movs r2, r3 - 8003280: f000 fba0 bl 80039c4 + 8003302: 001a movs r2, r3 + 8003304: f000 fba0 bl 8003a48 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); - 8003284: 687b ldr r3, [r7, #4] - 8003286: 681b ldr r3, [r3, #0] - 8003288: 2160 movs r1, #96 @ 0x60 - 800328a: 0018 movs r0, r3 - 800328c: f000 fbcc bl 8003a28 + 8003308: 687b ldr r3, [r7, #4] + 800330a: 681b ldr r3, [r3, #0] + 800330c: 2160 movs r1, #96 @ 0x60 + 800330e: 0018 movs r0, r3 + 8003310: f000 fbcc bl 8003aac break; - 8003290: e01e b.n 80032d0 + 8003314: e01e b.n 8003354 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, - 8003292: 687b ldr r3, [r7, #4] - 8003294: 6818 ldr r0, [r3, #0] + 8003316: 687b ldr r3, [r7, #4] + 8003318: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, - 8003296: 683b ldr r3, [r7, #0] - 8003298: 6859 ldr r1, [r3, #4] + 800331a: 683b ldr r3, [r7, #0] + 800331c: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); - 800329a: 683b ldr r3, [r7, #0] - 800329c: 68db ldr r3, [r3, #12] + 800331e: 683b ldr r3, [r7, #0] + 8003320: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, - 800329e: 001a movs r2, r3 - 80032a0: f000 fb62 bl 8003968 + 8003322: 001a movs r2, r3 + 8003324: f000 fb62 bl 80039ec TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); - 80032a4: 687b ldr r3, [r7, #4] - 80032a6: 681b ldr r3, [r3, #0] - 80032a8: 2140 movs r1, #64 @ 0x40 - 80032aa: 0018 movs r0, r3 - 80032ac: f000 fbbc bl 8003a28 + 8003328: 687b ldr r3, [r7, #4] + 800332a: 681b ldr r3, [r3, #0] + 800332c: 2140 movs r1, #64 @ 0x40 + 800332e: 0018 movs r0, r3 + 8003330: f000 fbbc bl 8003aac break; - 80032b0: e00e b.n 80032d0 + 8003334: e00e b.n 8003354 case TIM_CLOCKSOURCE_ITR3: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); - 80032b2: 687b ldr r3, [r7, #4] - 80032b4: 681a ldr r2, [r3, #0] - 80032b6: 683b ldr r3, [r7, #0] - 80032b8: 681b ldr r3, [r3, #0] - 80032ba: 0019 movs r1, r3 - 80032bc: 0010 movs r0, r2 - 80032be: f000 fbb3 bl 8003a28 + 8003336: 687b ldr r3, [r7, #4] + 8003338: 681a ldr r2, [r3, #0] + 800333a: 683b ldr r3, [r7, #0] + 800333c: 681b ldr r3, [r3, #0] + 800333e: 0019 movs r1, r3 + 8003340: 0010 movs r0, r2 + 8003342: f000 fbb3 bl 8003aac break; - 80032c2: e005 b.n 80032d0 + 8003346: e005 b.n 8003354 } default: status = HAL_ERROR; - 80032c4: 230f movs r3, #15 - 80032c6: 18fb adds r3, r7, r3 - 80032c8: 2201 movs r2, #1 - 80032ca: 701a strb r2, [r3, #0] + 8003348: 230f movs r3, #15 + 800334a: 18fb adds r3, r7, r3 + 800334c: 2201 movs r2, #1 + 800334e: 701a strb r2, [r3, #0] break; - 80032cc: e000 b.n 80032d0 + 8003350: e000 b.n 8003354 break; - 80032ce: 46c0 nop @ (mov r8, r8) + 8003352: 46c0 nop @ (mov r8, r8) } htim->State = HAL_TIM_STATE_READY; - 80032d0: 687b ldr r3, [r7, #4] - 80032d2: 223d movs r2, #61 @ 0x3d - 80032d4: 2101 movs r1, #1 - 80032d6: 5499 strb r1, [r3, r2] + 8003354: 687b ldr r3, [r7, #4] + 8003356: 223d movs r2, #61 @ 0x3d + 8003358: 2101 movs r1, #1 + 800335a: 5499 strb r1, [r3, r2] __HAL_UNLOCK(htim); - 80032d8: 687b ldr r3, [r7, #4] - 80032da: 223c movs r2, #60 @ 0x3c - 80032dc: 2100 movs r1, #0 - 80032de: 5499 strb r1, [r3, r2] + 800335c: 687b ldr r3, [r7, #4] + 800335e: 223c movs r2, #60 @ 0x3c + 8003360: 2100 movs r1, #0 + 8003362: 5499 strb r1, [r3, r2] return status; - 80032e0: 230f movs r3, #15 - 80032e2: 18fb adds r3, r7, r3 - 80032e4: 781b ldrb r3, [r3, #0] + 8003364: 230f movs r3, #15 + 8003366: 18fb adds r3, r7, r3 + 8003368: 781b ldrb r3, [r3, #0] } - 80032e6: 0018 movs r0, r3 - 80032e8: 46bd mov sp, r7 - 80032ea: b004 add sp, #16 - 80032ec: bd80 pop {r7, pc} - 80032ee: 46c0 nop @ (mov r8, r8) - 80032f0: ffceff88 .word 0xffceff88 - 80032f4: ffff00ff .word 0xffff00ff + 800336a: 0018 movs r0, r3 + 800336c: 46bd mov sp, r7 + 800336e: b004 add sp, #16 + 8003370: bd80 pop {r7, pc} + 8003372: 46c0 nop @ (mov r8, r8) + 8003374: ffceff88 .word 0xffceff88 + 8003378: ffff00ff .word 0xffff00ff -080032f8 : +0800337c : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { - 80032f8: b580 push {r7, lr} - 80032fa: b082 sub sp, #8 - 80032fc: af00 add r7, sp, #0 - 80032fe: 6078 str r0, [r7, #4] + 800337c: b580 push {r7, lr} + 800337e: b082 sub sp, #8 + 8003380: af00 add r7, sp, #0 + 8003382: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } - 8003300: 46c0 nop @ (mov r8, r8) - 8003302: 46bd mov sp, r7 - 8003304: b002 add sp, #8 - 8003306: bd80 pop {r7, pc} + 8003384: 46c0 nop @ (mov r8, r8) + 8003386: 46bd mov sp, r7 + 8003388: b002 add sp, #8 + 800338a: bd80 pop {r7, pc} -08003308 : +0800338c : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { - 8003308: b580 push {r7, lr} - 800330a: b082 sub sp, #8 - 800330c: af00 add r7, sp, #0 - 800330e: 6078 str r0, [r7, #4] + 800338c: b580 push {r7, lr} + 800338e: b082 sub sp, #8 + 8003390: af00 add r7, sp, #0 + 8003392: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } - 8003310: 46c0 nop @ (mov r8, r8) - 8003312: 46bd mov sp, r7 - 8003314: b002 add sp, #8 - 8003316: bd80 pop {r7, pc} + 8003394: 46c0 nop @ (mov r8, r8) + 8003396: 46bd mov sp, r7 + 8003398: b002 add sp, #8 + 800339a: bd80 pop {r7, pc} -08003318 : +0800339c : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { - 8003318: b580 push {r7, lr} - 800331a: b082 sub sp, #8 - 800331c: af00 add r7, sp, #0 - 800331e: 6078 str r0, [r7, #4] + 800339c: b580 push {r7, lr} + 800339e: b082 sub sp, #8 + 80033a0: af00 add r7, sp, #0 + 80033a2: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } - 8003320: 46c0 nop @ (mov r8, r8) - 8003322: 46bd mov sp, r7 - 8003324: b002 add sp, #8 - 8003326: bd80 pop {r7, pc} + 80033a4: 46c0 nop @ (mov r8, r8) + 80033a6: 46bd mov sp, r7 + 80033a8: b002 add sp, #8 + 80033aa: bd80 pop {r7, pc} -08003328 : +080033ac : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { - 8003328: b580 push {r7, lr} - 800332a: b082 sub sp, #8 - 800332c: af00 add r7, sp, #0 - 800332e: 6078 str r0, [r7, #4] + 80033ac: b580 push {r7, lr} + 80033ae: b082 sub sp, #8 + 80033b0: af00 add r7, sp, #0 + 80033b2: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } - 8003330: 46c0 nop @ (mov r8, r8) - 8003332: 46bd mov sp, r7 - 8003334: b002 add sp, #8 - 8003336: bd80 pop {r7, pc} + 80033b4: 46c0 nop @ (mov r8, r8) + 80033b6: 46bd mov sp, r7 + 80033b8: b002 add sp, #8 + 80033ba: bd80 pop {r7, pc} -08003338 : +080033bc : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { - 8003338: b580 push {r7, lr} - 800333a: b084 sub sp, #16 - 800333c: af00 add r7, sp, #0 - 800333e: 6078 str r0, [r7, #4] - 8003340: 6039 str r1, [r7, #0] + 80033bc: b580 push {r7, lr} + 80033be: b084 sub sp, #16 + 80033c0: af00 add r7, sp, #0 + 80033c2: 6078 str r0, [r7, #4] + 80033c4: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; - 8003342: 687b ldr r3, [r7, #4] - 8003344: 681b ldr r3, [r3, #0] - 8003346: 60fb str r3, [r7, #12] + 80033c6: 687b ldr r3, [r7, #4] + 80033c8: 681b ldr r3, [r3, #0] + 80033ca: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) - 8003348: 687b ldr r3, [r7, #4] - 800334a: 4a33 ldr r2, [pc, #204] @ (8003418 ) - 800334c: 4293 cmp r3, r2 - 800334e: d008 beq.n 8003362 - 8003350: 687a ldr r2, [r7, #4] - 8003352: 2380 movs r3, #128 @ 0x80 - 8003354: 05db lsls r3, r3, #23 - 8003356: 429a cmp r2, r3 - 8003358: d003 beq.n 8003362 - 800335a: 687b ldr r3, [r7, #4] - 800335c: 4a2f ldr r2, [pc, #188] @ (800341c ) - 800335e: 4293 cmp r3, r2 - 8003360: d108 bne.n 8003374 + 80033cc: 687b ldr r3, [r7, #4] + 80033ce: 4a33 ldr r2, [pc, #204] @ (800349c ) + 80033d0: 4293 cmp r3, r2 + 80033d2: d008 beq.n 80033e6 + 80033d4: 687a ldr r2, [r7, #4] + 80033d6: 2380 movs r3, #128 @ 0x80 + 80033d8: 05db lsls r3, r3, #23 + 80033da: 429a cmp r2, r3 + 80033dc: d003 beq.n 80033e6 + 80033de: 687b ldr r3, [r7, #4] + 80033e0: 4a2f ldr r2, [pc, #188] @ (80034a0 ) + 80033e2: 4293 cmp r3, r2 + 80033e4: d108 bne.n 80033f8 { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); - 8003362: 68fb ldr r3, [r7, #12] - 8003364: 2270 movs r2, #112 @ 0x70 - 8003366: 4393 bics r3, r2 - 8003368: 60fb str r3, [r7, #12] + 80033e6: 68fb ldr r3, [r7, #12] + 80033e8: 2270 movs r2, #112 @ 0x70 + 80033ea: 4393 bics r3, r2 + 80033ec: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; - 800336a: 683b ldr r3, [r7, #0] - 800336c: 685b ldr r3, [r3, #4] - 800336e: 68fa ldr r2, [r7, #12] - 8003370: 4313 orrs r3, r2 - 8003372: 60fb str r3, [r7, #12] + 80033ee: 683b ldr r3, [r7, #0] + 80033f0: 685b ldr r3, [r3, #4] + 80033f2: 68fa ldr r2, [r7, #12] + 80033f4: 4313 orrs r3, r2 + 80033f6: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) - 8003374: 687b ldr r3, [r7, #4] - 8003376: 4a28 ldr r2, [pc, #160] @ (8003418 ) - 8003378: 4293 cmp r3, r2 - 800337a: d014 beq.n 80033a6 - 800337c: 687a ldr r2, [r7, #4] - 800337e: 2380 movs r3, #128 @ 0x80 - 8003380: 05db lsls r3, r3, #23 - 8003382: 429a cmp r2, r3 - 8003384: d00f beq.n 80033a6 - 8003386: 687b ldr r3, [r7, #4] - 8003388: 4a24 ldr r2, [pc, #144] @ (800341c ) - 800338a: 4293 cmp r3, r2 - 800338c: d00b beq.n 80033a6 - 800338e: 687b ldr r3, [r7, #4] - 8003390: 4a23 ldr r2, [pc, #140] @ (8003420 ) - 8003392: 4293 cmp r3, r2 - 8003394: d007 beq.n 80033a6 - 8003396: 687b ldr r3, [r7, #4] - 8003398: 4a22 ldr r2, [pc, #136] @ (8003424 ) - 800339a: 4293 cmp r3, r2 - 800339c: d003 beq.n 80033a6 - 800339e: 687b ldr r3, [r7, #4] - 80033a0: 4a21 ldr r2, [pc, #132] @ (8003428 ) - 80033a2: 4293 cmp r3, r2 - 80033a4: d108 bne.n 80033b8 + 80033f8: 687b ldr r3, [r7, #4] + 80033fa: 4a28 ldr r2, [pc, #160] @ (800349c ) + 80033fc: 4293 cmp r3, r2 + 80033fe: d014 beq.n 800342a + 8003400: 687a ldr r2, [r7, #4] + 8003402: 2380 movs r3, #128 @ 0x80 + 8003404: 05db lsls r3, r3, #23 + 8003406: 429a cmp r2, r3 + 8003408: d00f beq.n 800342a + 800340a: 687b ldr r3, [r7, #4] + 800340c: 4a24 ldr r2, [pc, #144] @ (80034a0 ) + 800340e: 4293 cmp r3, r2 + 8003410: d00b beq.n 800342a + 8003412: 687b ldr r3, [r7, #4] + 8003414: 4a23 ldr r2, [pc, #140] @ (80034a4 ) + 8003416: 4293 cmp r3, r2 + 8003418: d007 beq.n 800342a + 800341a: 687b ldr r3, [r7, #4] + 800341c: 4a22 ldr r2, [pc, #136] @ (80034a8 ) + 800341e: 4293 cmp r3, r2 + 8003420: d003 beq.n 800342a + 8003422: 687b ldr r3, [r7, #4] + 8003424: 4a21 ldr r2, [pc, #132] @ (80034ac ) + 8003426: 4293 cmp r3, r2 + 8003428: d108 bne.n 800343c { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; - 80033a6: 68fb ldr r3, [r7, #12] - 80033a8: 4a20 ldr r2, [pc, #128] @ (800342c ) - 80033aa: 4013 ands r3, r2 - 80033ac: 60fb str r3, [r7, #12] + 800342a: 68fb ldr r3, [r7, #12] + 800342c: 4a20 ldr r2, [pc, #128] @ (80034b0 ) + 800342e: 4013 ands r3, r2 + 8003430: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; - 80033ae: 683b ldr r3, [r7, #0] - 80033b0: 68db ldr r3, [r3, #12] - 80033b2: 68fa ldr r2, [r7, #12] - 80033b4: 4313 orrs r3, r2 - 80033b6: 60fb str r3, [r7, #12] + 8003432: 683b ldr r3, [r7, #0] + 8003434: 68db ldr r3, [r3, #12] + 8003436: 68fa ldr r2, [r7, #12] + 8003438: 4313 orrs r3, r2 + 800343a: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); - 80033b8: 68fb ldr r3, [r7, #12] - 80033ba: 2280 movs r2, #128 @ 0x80 - 80033bc: 4393 bics r3, r2 - 80033be: 001a movs r2, r3 - 80033c0: 683b ldr r3, [r7, #0] - 80033c2: 695b ldr r3, [r3, #20] - 80033c4: 4313 orrs r3, r2 - 80033c6: 60fb str r3, [r7, #12] + 800343c: 68fb ldr r3, [r7, #12] + 800343e: 2280 movs r2, #128 @ 0x80 + 8003440: 4393 bics r3, r2 + 8003442: 001a movs r2, r3 + 8003444: 683b ldr r3, [r7, #0] + 8003446: 695b ldr r3, [r3, #20] + 8003448: 4313 orrs r3, r2 + 800344a: 60fb str r3, [r7, #12] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; - 80033c8: 683b ldr r3, [r7, #0] - 80033ca: 689a ldr r2, [r3, #8] - 80033cc: 687b ldr r3, [r7, #4] - 80033ce: 62da str r2, [r3, #44] @ 0x2c + 800344c: 683b ldr r3, [r7, #0] + 800344e: 689a ldr r2, [r3, #8] + 8003450: 687b ldr r3, [r7, #4] + 8003452: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; - 80033d0: 683b ldr r3, [r7, #0] - 80033d2: 681a ldr r2, [r3, #0] - 80033d4: 687b ldr r3, [r7, #4] - 80033d6: 629a str r2, [r3, #40] @ 0x28 + 8003454: 683b ldr r3, [r7, #0] + 8003456: 681a ldr r2, [r3, #0] + 8003458: 687b ldr r3, [r7, #4] + 800345a: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) - 80033d8: 687b ldr r3, [r7, #4] - 80033da: 4a0f ldr r2, [pc, #60] @ (8003418 ) - 80033dc: 4293 cmp r3, r2 - 80033de: d007 beq.n 80033f0 - 80033e0: 687b ldr r3, [r7, #4] - 80033e2: 4a10 ldr r2, [pc, #64] @ (8003424 ) - 80033e4: 4293 cmp r3, r2 - 80033e6: d003 beq.n 80033f0 - 80033e8: 687b ldr r3, [r7, #4] - 80033ea: 4a0f ldr r2, [pc, #60] @ (8003428 ) - 80033ec: 4293 cmp r3, r2 - 80033ee: d103 bne.n 80033f8 + 800345c: 687b ldr r3, [r7, #4] + 800345e: 4a0f ldr r2, [pc, #60] @ (800349c ) + 8003460: 4293 cmp r3, r2 + 8003462: d007 beq.n 8003474 + 8003464: 687b ldr r3, [r7, #4] + 8003466: 4a10 ldr r2, [pc, #64] @ (80034a8 ) + 8003468: 4293 cmp r3, r2 + 800346a: d003 beq.n 8003474 + 800346c: 687b ldr r3, [r7, #4] + 800346e: 4a0f ldr r2, [pc, #60] @ (80034ac ) + 8003470: 4293 cmp r3, r2 + 8003472: d103 bne.n 800347c { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; - 80033f0: 683b ldr r3, [r7, #0] - 80033f2: 691a ldr r2, [r3, #16] - 80033f4: 687b ldr r3, [r7, #4] - 80033f6: 631a str r2, [r3, #48] @ 0x30 + 8003474: 683b ldr r3, [r7, #0] + 8003476: 691a ldr r2, [r3, #16] + 8003478: 687b ldr r3, [r7, #4] + 800347a: 631a str r2, [r3, #48] @ 0x30 } /* Disable Update Event (UEV) with Update Generation (UG) by changing Update Request Source (URS) to avoid Update flag (UIF) */ SET_BIT(TIMx->CR1, TIM_CR1_URS); - 80033f8: 687b ldr r3, [r7, #4] - 80033fa: 681b ldr r3, [r3, #0] - 80033fc: 2204 movs r2, #4 - 80033fe: 431a orrs r2, r3 - 8003400: 687b ldr r3, [r7, #4] - 8003402: 601a str r2, [r3, #0] + 800347c: 687b ldr r3, [r7, #4] + 800347e: 681b ldr r3, [r3, #0] + 8003480: 2204 movs r2, #4 + 8003482: 431a orrs r2, r3 + 8003484: 687b ldr r3, [r7, #4] + 8003486: 601a str r2, [r3, #0] /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; - 8003404: 687b ldr r3, [r7, #4] - 8003406: 2201 movs r2, #1 - 8003408: 615a str r2, [r3, #20] + 8003488: 687b ldr r3, [r7, #4] + 800348a: 2201 movs r2, #1 + 800348c: 615a str r2, [r3, #20] TIMx->CR1 = tmpcr1; - 800340a: 687b ldr r3, [r7, #4] - 800340c: 68fa ldr r2, [r7, #12] - 800340e: 601a str r2, [r3, #0] + 800348e: 687b ldr r3, [r7, #4] + 8003490: 68fa ldr r2, [r7, #12] + 8003492: 601a str r2, [r3, #0] } - 8003410: 46c0 nop @ (mov r8, r8) - 8003412: 46bd mov sp, r7 - 8003414: b004 add sp, #16 - 8003416: bd80 pop {r7, pc} - 8003418: 40012c00 .word 0x40012c00 - 800341c: 40000400 .word 0x40000400 - 8003420: 40002000 .word 0x40002000 - 8003424: 40014400 .word 0x40014400 - 8003428: 40014800 .word 0x40014800 - 800342c: fffffcff .word 0xfffffcff + 8003494: 46c0 nop @ (mov r8, r8) + 8003496: 46bd mov sp, r7 + 8003498: b004 add sp, #16 + 800349a: bd80 pop {r7, pc} + 800349c: 40012c00 .word 0x40012c00 + 80034a0: 40000400 .word 0x40000400 + 80034a4: 40002000 .word 0x40002000 + 80034a8: 40014400 .word 0x40014400 + 80034ac: 40014800 .word 0x40014800 + 80034b0: fffffcff .word 0xfffffcff -08003430 : +080034b4 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { - 8003430: b580 push {r7, lr} - 8003432: b086 sub sp, #24 - 8003434: af00 add r7, sp, #0 - 8003436: 6078 str r0, [r7, #4] - 8003438: 6039 str r1, [r7, #0] + 80034b4: b580 push {r7, lr} + 80034b6: b086 sub sp, #24 + 80034b8: af00 add r7, sp, #0 + 80034ba: 6078 str r0, [r7, #4] + 80034bc: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; - 800343a: 687b ldr r3, [r7, #4] - 800343c: 6a1b ldr r3, [r3, #32] - 800343e: 617b str r3, [r7, #20] + 80034be: 687b ldr r3, [r7, #4] + 80034c0: 6a1b ldr r3, [r3, #32] + 80034c2: 617b str r3, [r7, #20] /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; - 8003440: 687b ldr r3, [r7, #4] - 8003442: 6a1b ldr r3, [r3, #32] - 8003444: 2201 movs r2, #1 - 8003446: 4393 bics r3, r2 - 8003448: 001a movs r2, r3 - 800344a: 687b ldr r3, [r7, #4] - 800344c: 621a str r2, [r3, #32] + 80034c4: 687b ldr r3, [r7, #4] + 80034c6: 6a1b ldr r3, [r3, #32] + 80034c8: 2201 movs r2, #1 + 80034ca: 4393 bics r3, r2 + 80034cc: 001a movs r2, r3 + 80034ce: 687b ldr r3, [r7, #4] + 80034d0: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; - 800344e: 687b ldr r3, [r7, #4] - 8003450: 685b ldr r3, [r3, #4] - 8003452: 613b str r3, [r7, #16] + 80034d2: 687b ldr r3, [r7, #4] + 80034d4: 685b ldr r3, [r3, #4] + 80034d6: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; - 8003454: 687b ldr r3, [r7, #4] - 8003456: 699b ldr r3, [r3, #24] - 8003458: 60fb str r3, [r7, #12] + 80034d8: 687b ldr r3, [r7, #4] + 80034da: 699b ldr r3, [r3, #24] + 80034dc: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; - 800345a: 68fb ldr r3, [r7, #12] - 800345c: 4a2e ldr r2, [pc, #184] @ (8003518 ) - 800345e: 4013 ands r3, r2 - 8003460: 60fb str r3, [r7, #12] + 80034de: 68fb ldr r3, [r7, #12] + 80034e0: 4a2e ldr r2, [pc, #184] @ (800359c ) + 80034e2: 4013 ands r3, r2 + 80034e4: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC1S; - 8003462: 68fb ldr r3, [r7, #12] - 8003464: 2203 movs r2, #3 - 8003466: 4393 bics r3, r2 - 8003468: 60fb str r3, [r7, #12] + 80034e6: 68fb ldr r3, [r7, #12] + 80034e8: 2203 movs r2, #3 + 80034ea: 4393 bics r3, r2 + 80034ec: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; - 800346a: 683b ldr r3, [r7, #0] - 800346c: 681b ldr r3, [r3, #0] - 800346e: 68fa ldr r2, [r7, #12] - 8003470: 4313 orrs r3, r2 - 8003472: 60fb str r3, [r7, #12] + 80034ee: 683b ldr r3, [r7, #0] + 80034f0: 681b ldr r3, [r3, #0] + 80034f2: 68fa ldr r2, [r7, #12] + 80034f4: 4313 orrs r3, r2 + 80034f6: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; - 8003474: 697b ldr r3, [r7, #20] - 8003476: 2202 movs r2, #2 - 8003478: 4393 bics r3, r2 - 800347a: 617b str r3, [r7, #20] + 80034f8: 697b ldr r3, [r7, #20] + 80034fa: 2202 movs r2, #2 + 80034fc: 4393 bics r3, r2 + 80034fe: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; - 800347c: 683b ldr r3, [r7, #0] - 800347e: 689b ldr r3, [r3, #8] - 8003480: 697a ldr r2, [r7, #20] - 8003482: 4313 orrs r3, r2 - 8003484: 617b str r3, [r7, #20] + 8003500: 683b ldr r3, [r7, #0] + 8003502: 689b ldr r3, [r3, #8] + 8003504: 697a ldr r2, [r7, #20] + 8003506: 4313 orrs r3, r2 + 8003508: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) - 8003486: 687b ldr r3, [r7, #4] - 8003488: 4a24 ldr r2, [pc, #144] @ (800351c ) - 800348a: 4293 cmp r3, r2 - 800348c: d007 beq.n 800349e - 800348e: 687b ldr r3, [r7, #4] - 8003490: 4a23 ldr r2, [pc, #140] @ (8003520 ) - 8003492: 4293 cmp r3, r2 - 8003494: d003 beq.n 800349e - 8003496: 687b ldr r3, [r7, #4] - 8003498: 4a22 ldr r2, [pc, #136] @ (8003524 ) - 800349a: 4293 cmp r3, r2 - 800349c: d10c bne.n 80034b8 + 800350a: 687b ldr r3, [r7, #4] + 800350c: 4a24 ldr r2, [pc, #144] @ (80035a0 ) + 800350e: 4293 cmp r3, r2 + 8003510: d007 beq.n 8003522 + 8003512: 687b ldr r3, [r7, #4] + 8003514: 4a23 ldr r2, [pc, #140] @ (80035a4 ) + 8003516: 4293 cmp r3, r2 + 8003518: d003 beq.n 8003522 + 800351a: 687b ldr r3, [r7, #4] + 800351c: 4a22 ldr r2, [pc, #136] @ (80035a8 ) + 800351e: 4293 cmp r3, r2 + 8003520: d10c bne.n 800353c { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; - 800349e: 697b ldr r3, [r7, #20] - 80034a0: 2208 movs r2, #8 - 80034a2: 4393 bics r3, r2 - 80034a4: 617b str r3, [r7, #20] + 8003522: 697b ldr r3, [r7, #20] + 8003524: 2208 movs r2, #8 + 8003526: 4393 bics r3, r2 + 8003528: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; - 80034a6: 683b ldr r3, [r7, #0] - 80034a8: 68db ldr r3, [r3, #12] - 80034aa: 697a ldr r2, [r7, #20] - 80034ac: 4313 orrs r3, r2 - 80034ae: 617b str r3, [r7, #20] + 800352a: 683b ldr r3, [r7, #0] + 800352c: 68db ldr r3, [r3, #12] + 800352e: 697a ldr r2, [r7, #20] + 8003530: 4313 orrs r3, r2 + 8003532: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; - 80034b0: 697b ldr r3, [r7, #20] - 80034b2: 2204 movs r2, #4 - 80034b4: 4393 bics r3, r2 - 80034b6: 617b str r3, [r7, #20] + 8003534: 697b ldr r3, [r7, #20] + 8003536: 2204 movs r2, #4 + 8003538: 4393 bics r3, r2 + 800353a: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) - 80034b8: 687b ldr r3, [r7, #4] - 80034ba: 4a18 ldr r2, [pc, #96] @ (800351c ) - 80034bc: 4293 cmp r3, r2 - 80034be: d007 beq.n 80034d0 - 80034c0: 687b ldr r3, [r7, #4] - 80034c2: 4a17 ldr r2, [pc, #92] @ (8003520 ) - 80034c4: 4293 cmp r3, r2 - 80034c6: d003 beq.n 80034d0 - 80034c8: 687b ldr r3, [r7, #4] - 80034ca: 4a16 ldr r2, [pc, #88] @ (8003524 ) - 80034cc: 4293 cmp r3, r2 - 80034ce: d111 bne.n 80034f4 + 800353c: 687b ldr r3, [r7, #4] + 800353e: 4a18 ldr r2, [pc, #96] @ (80035a0 ) + 8003540: 4293 cmp r3, r2 + 8003542: d007 beq.n 8003554 + 8003544: 687b ldr r3, [r7, #4] + 8003546: 4a17 ldr r2, [pc, #92] @ (80035a4 ) + 8003548: 4293 cmp r3, r2 + 800354a: d003 beq.n 8003554 + 800354c: 687b ldr r3, [r7, #4] + 800354e: 4a16 ldr r2, [pc, #88] @ (80035a8 ) + 8003550: 4293 cmp r3, r2 + 8003552: d111 bne.n 8003578 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; - 80034d0: 693b ldr r3, [r7, #16] - 80034d2: 4a15 ldr r2, [pc, #84] @ (8003528 ) - 80034d4: 4013 ands r3, r2 - 80034d6: 613b str r3, [r7, #16] + 8003554: 693b ldr r3, [r7, #16] + 8003556: 4a15 ldr r2, [pc, #84] @ (80035ac ) + 8003558: 4013 ands r3, r2 + 800355a: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS1N; - 80034d8: 693b ldr r3, [r7, #16] - 80034da: 4a14 ldr r2, [pc, #80] @ (800352c ) - 80034dc: 4013 ands r3, r2 - 80034de: 613b str r3, [r7, #16] + 800355c: 693b ldr r3, [r7, #16] + 800355e: 4a14 ldr r2, [pc, #80] @ (80035b0 ) + 8003560: 4013 ands r3, r2 + 8003562: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; - 80034e0: 683b ldr r3, [r7, #0] - 80034e2: 695b ldr r3, [r3, #20] - 80034e4: 693a ldr r2, [r7, #16] - 80034e6: 4313 orrs r3, r2 - 80034e8: 613b str r3, [r7, #16] + 8003564: 683b ldr r3, [r7, #0] + 8003566: 695b ldr r3, [r3, #20] + 8003568: 693a ldr r2, [r7, #16] + 800356a: 4313 orrs r3, r2 + 800356c: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; - 80034ea: 683b ldr r3, [r7, #0] - 80034ec: 699b ldr r3, [r3, #24] - 80034ee: 693a ldr r2, [r7, #16] - 80034f0: 4313 orrs r3, r2 - 80034f2: 613b str r3, [r7, #16] + 800356e: 683b ldr r3, [r7, #0] + 8003570: 699b ldr r3, [r3, #24] + 8003572: 693a ldr r2, [r7, #16] + 8003574: 4313 orrs r3, r2 + 8003576: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; - 80034f4: 687b ldr r3, [r7, #4] - 80034f6: 693a ldr r2, [r7, #16] - 80034f8: 605a str r2, [r3, #4] + 8003578: 687b ldr r3, [r7, #4] + 800357a: 693a ldr r2, [r7, #16] + 800357c: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; - 80034fa: 687b ldr r3, [r7, #4] - 80034fc: 68fa ldr r2, [r7, #12] - 80034fe: 619a str r2, [r3, #24] + 800357e: 687b ldr r3, [r7, #4] + 8003580: 68fa ldr r2, [r7, #12] + 8003582: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; - 8003500: 683b ldr r3, [r7, #0] - 8003502: 685a ldr r2, [r3, #4] - 8003504: 687b ldr r3, [r7, #4] - 8003506: 635a str r2, [r3, #52] @ 0x34 + 8003584: 683b ldr r3, [r7, #0] + 8003586: 685a ldr r2, [r3, #4] + 8003588: 687b ldr r3, [r7, #4] + 800358a: 635a str r2, [r3, #52] @ 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; - 8003508: 687b ldr r3, [r7, #4] - 800350a: 697a ldr r2, [r7, #20] - 800350c: 621a str r2, [r3, #32] + 800358c: 687b ldr r3, [r7, #4] + 800358e: 697a ldr r2, [r7, #20] + 8003590: 621a str r2, [r3, #32] } - 800350e: 46c0 nop @ (mov r8, r8) - 8003510: 46bd mov sp, r7 - 8003512: b006 add sp, #24 - 8003514: bd80 pop {r7, pc} - 8003516: 46c0 nop @ (mov r8, r8) - 8003518: fffeff8f .word 0xfffeff8f - 800351c: 40012c00 .word 0x40012c00 - 8003520: 40014400 .word 0x40014400 - 8003524: 40014800 .word 0x40014800 - 8003528: fffffeff .word 0xfffffeff - 800352c: fffffdff .word 0xfffffdff + 8003592: 46c0 nop @ (mov r8, r8) + 8003594: 46bd mov sp, r7 + 8003596: b006 add sp, #24 + 8003598: bd80 pop {r7, pc} + 800359a: 46c0 nop @ (mov r8, r8) + 800359c: fffeff8f .word 0xfffeff8f + 80035a0: 40012c00 .word 0x40012c00 + 80035a4: 40014400 .word 0x40014400 + 80035a8: 40014800 .word 0x40014800 + 80035ac: fffffeff .word 0xfffffeff + 80035b0: fffffdff .word 0xfffffdff -08003530 : +080035b4 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { - 8003530: b580 push {r7, lr} - 8003532: b086 sub sp, #24 - 8003534: af00 add r7, sp, #0 - 8003536: 6078 str r0, [r7, #4] - 8003538: 6039 str r1, [r7, #0] + 80035b4: b580 push {r7, lr} + 80035b6: b086 sub sp, #24 + 80035b8: af00 add r7, sp, #0 + 80035ba: 6078 str r0, [r7, #4] + 80035bc: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; - 800353a: 687b ldr r3, [r7, #4] - 800353c: 6a1b ldr r3, [r3, #32] - 800353e: 617b str r3, [r7, #20] + 80035be: 687b ldr r3, [r7, #4] + 80035c0: 6a1b ldr r3, [r3, #32] + 80035c2: 617b str r3, [r7, #20] /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; - 8003540: 687b ldr r3, [r7, #4] - 8003542: 6a1b ldr r3, [r3, #32] - 8003544: 2210 movs r2, #16 - 8003546: 4393 bics r3, r2 - 8003548: 001a movs r2, r3 - 800354a: 687b ldr r3, [r7, #4] - 800354c: 621a str r2, [r3, #32] + 80035c4: 687b ldr r3, [r7, #4] + 80035c6: 6a1b ldr r3, [r3, #32] + 80035c8: 2210 movs r2, #16 + 80035ca: 4393 bics r3, r2 + 80035cc: 001a movs r2, r3 + 80035ce: 687b ldr r3, [r7, #4] + 80035d0: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; - 800354e: 687b ldr r3, [r7, #4] - 8003550: 685b ldr r3, [r3, #4] - 8003552: 613b str r3, [r7, #16] + 80035d2: 687b ldr r3, [r7, #4] + 80035d4: 685b ldr r3, [r3, #4] + 80035d6: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; - 8003554: 687b ldr r3, [r7, #4] - 8003556: 699b ldr r3, [r3, #24] - 8003558: 60fb str r3, [r7, #12] + 80035d8: 687b ldr r3, [r7, #4] + 80035da: 699b ldr r3, [r3, #24] + 80035dc: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; - 800355a: 68fb ldr r3, [r7, #12] - 800355c: 4a2c ldr r2, [pc, #176] @ (8003610 ) - 800355e: 4013 ands r3, r2 - 8003560: 60fb str r3, [r7, #12] + 80035de: 68fb ldr r3, [r7, #12] + 80035e0: 4a2c ldr r2, [pc, #176] @ (8003694 ) + 80035e2: 4013 ands r3, r2 + 80035e4: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC2S; - 8003562: 68fb ldr r3, [r7, #12] - 8003564: 4a2b ldr r2, [pc, #172] @ (8003614 ) - 8003566: 4013 ands r3, r2 - 8003568: 60fb str r3, [r7, #12] + 80035e6: 68fb ldr r3, [r7, #12] + 80035e8: 4a2b ldr r2, [pc, #172] @ (8003698 ) + 80035ea: 4013 ands r3, r2 + 80035ec: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); - 800356a: 683b ldr r3, [r7, #0] - 800356c: 681b ldr r3, [r3, #0] - 800356e: 021b lsls r3, r3, #8 - 8003570: 68fa ldr r2, [r7, #12] - 8003572: 4313 orrs r3, r2 - 8003574: 60fb str r3, [r7, #12] + 80035ee: 683b ldr r3, [r7, #0] + 80035f0: 681b ldr r3, [r3, #0] + 80035f2: 021b lsls r3, r3, #8 + 80035f4: 68fa ldr r2, [r7, #12] + 80035f6: 4313 orrs r3, r2 + 80035f8: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; - 8003576: 697b ldr r3, [r7, #20] - 8003578: 2220 movs r2, #32 - 800357a: 4393 bics r3, r2 - 800357c: 617b str r3, [r7, #20] + 80035fa: 697b ldr r3, [r7, #20] + 80035fc: 2220 movs r2, #32 + 80035fe: 4393 bics r3, r2 + 8003600: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); - 800357e: 683b ldr r3, [r7, #0] - 8003580: 689b ldr r3, [r3, #8] - 8003582: 011b lsls r3, r3, #4 - 8003584: 697a ldr r2, [r7, #20] - 8003586: 4313 orrs r3, r2 - 8003588: 617b str r3, [r7, #20] + 8003602: 683b ldr r3, [r7, #0] + 8003604: 689b ldr r3, [r3, #8] + 8003606: 011b lsls r3, r3, #4 + 8003608: 697a ldr r2, [r7, #20] + 800360a: 4313 orrs r3, r2 + 800360c: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) - 800358a: 687b ldr r3, [r7, #4] - 800358c: 4a22 ldr r2, [pc, #136] @ (8003618 ) - 800358e: 4293 cmp r3, r2 - 8003590: d10d bne.n 80035ae + 800360e: 687b ldr r3, [r7, #4] + 8003610: 4a22 ldr r2, [pc, #136] @ (800369c ) + 8003612: 4293 cmp r3, r2 + 8003614: d10d bne.n 8003632 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; - 8003592: 697b ldr r3, [r7, #20] - 8003594: 2280 movs r2, #128 @ 0x80 - 8003596: 4393 bics r3, r2 - 8003598: 617b str r3, [r7, #20] + 8003616: 697b ldr r3, [r7, #20] + 8003618: 2280 movs r2, #128 @ 0x80 + 800361a: 4393 bics r3, r2 + 800361c: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); - 800359a: 683b ldr r3, [r7, #0] - 800359c: 68db ldr r3, [r3, #12] - 800359e: 011b lsls r3, r3, #4 - 80035a0: 697a ldr r2, [r7, #20] - 80035a2: 4313 orrs r3, r2 - 80035a4: 617b str r3, [r7, #20] + 800361e: 683b ldr r3, [r7, #0] + 8003620: 68db ldr r3, [r3, #12] + 8003622: 011b lsls r3, r3, #4 + 8003624: 697a ldr r2, [r7, #20] + 8003626: 4313 orrs r3, r2 + 8003628: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; - 80035a6: 697b ldr r3, [r7, #20] - 80035a8: 2240 movs r2, #64 @ 0x40 - 80035aa: 4393 bics r3, r2 - 80035ac: 617b str r3, [r7, #20] + 800362a: 697b ldr r3, [r7, #20] + 800362c: 2240 movs r2, #64 @ 0x40 + 800362e: 4393 bics r3, r2 + 8003630: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) - 80035ae: 687b ldr r3, [r7, #4] - 80035b0: 4a19 ldr r2, [pc, #100] @ (8003618 ) - 80035b2: 4293 cmp r3, r2 - 80035b4: d007 beq.n 80035c6 - 80035b6: 687b ldr r3, [r7, #4] - 80035b8: 4a18 ldr r2, [pc, #96] @ (800361c ) - 80035ba: 4293 cmp r3, r2 - 80035bc: d003 beq.n 80035c6 - 80035be: 687b ldr r3, [r7, #4] - 80035c0: 4a17 ldr r2, [pc, #92] @ (8003620 ) - 80035c2: 4293 cmp r3, r2 - 80035c4: d113 bne.n 80035ee + 8003632: 687b ldr r3, [r7, #4] + 8003634: 4a19 ldr r2, [pc, #100] @ (800369c ) + 8003636: 4293 cmp r3, r2 + 8003638: d007 beq.n 800364a + 800363a: 687b ldr r3, [r7, #4] + 800363c: 4a18 ldr r2, [pc, #96] @ (80036a0 ) + 800363e: 4293 cmp r3, r2 + 8003640: d003 beq.n 800364a + 8003642: 687b ldr r3, [r7, #4] + 8003644: 4a17 ldr r2, [pc, #92] @ (80036a4 ) + 8003646: 4293 cmp r3, r2 + 8003648: d113 bne.n 8003672 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; - 80035c6: 693b ldr r3, [r7, #16] - 80035c8: 4a16 ldr r2, [pc, #88] @ (8003624 ) - 80035ca: 4013 ands r3, r2 - 80035cc: 613b str r3, [r7, #16] + 800364a: 693b ldr r3, [r7, #16] + 800364c: 4a16 ldr r2, [pc, #88] @ (80036a8 ) + 800364e: 4013 ands r3, r2 + 8003650: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS2N; - 80035ce: 693b ldr r3, [r7, #16] - 80035d0: 4a15 ldr r2, [pc, #84] @ (8003628 ) - 80035d2: 4013 ands r3, r2 - 80035d4: 613b str r3, [r7, #16] + 8003652: 693b ldr r3, [r7, #16] + 8003654: 4a15 ldr r2, [pc, #84] @ (80036ac ) + 8003656: 4013 ands r3, r2 + 8003658: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); - 80035d6: 683b ldr r3, [r7, #0] - 80035d8: 695b ldr r3, [r3, #20] - 80035da: 009b lsls r3, r3, #2 - 80035dc: 693a ldr r2, [r7, #16] - 80035de: 4313 orrs r3, r2 - 80035e0: 613b str r3, [r7, #16] + 800365a: 683b ldr r3, [r7, #0] + 800365c: 695b ldr r3, [r3, #20] + 800365e: 009b lsls r3, r3, #2 + 8003660: 693a ldr r2, [r7, #16] + 8003662: 4313 orrs r3, r2 + 8003664: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); - 80035e2: 683b ldr r3, [r7, #0] - 80035e4: 699b ldr r3, [r3, #24] - 80035e6: 009b lsls r3, r3, #2 - 80035e8: 693a ldr r2, [r7, #16] - 80035ea: 4313 orrs r3, r2 - 80035ec: 613b str r3, [r7, #16] + 8003666: 683b ldr r3, [r7, #0] + 8003668: 699b ldr r3, [r3, #24] + 800366a: 009b lsls r3, r3, #2 + 800366c: 693a ldr r2, [r7, #16] + 800366e: 4313 orrs r3, r2 + 8003670: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; - 80035ee: 687b ldr r3, [r7, #4] - 80035f0: 693a ldr r2, [r7, #16] - 80035f2: 605a str r2, [r3, #4] + 8003672: 687b ldr r3, [r7, #4] + 8003674: 693a ldr r2, [r7, #16] + 8003676: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; - 80035f4: 687b ldr r3, [r7, #4] - 80035f6: 68fa ldr r2, [r7, #12] - 80035f8: 619a str r2, [r3, #24] + 8003678: 687b ldr r3, [r7, #4] + 800367a: 68fa ldr r2, [r7, #12] + 800367c: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; - 80035fa: 683b ldr r3, [r7, #0] - 80035fc: 685a ldr r2, [r3, #4] - 80035fe: 687b ldr r3, [r7, #4] - 8003600: 639a str r2, [r3, #56] @ 0x38 + 800367e: 683b ldr r3, [r7, #0] + 8003680: 685a ldr r2, [r3, #4] + 8003682: 687b ldr r3, [r7, #4] + 8003684: 639a str r2, [r3, #56] @ 0x38 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; - 8003602: 687b ldr r3, [r7, #4] - 8003604: 697a ldr r2, [r7, #20] - 8003606: 621a str r2, [r3, #32] + 8003686: 687b ldr r3, [r7, #4] + 8003688: 697a ldr r2, [r7, #20] + 800368a: 621a str r2, [r3, #32] } - 8003608: 46c0 nop @ (mov r8, r8) - 800360a: 46bd mov sp, r7 - 800360c: b006 add sp, #24 - 800360e: bd80 pop {r7, pc} - 8003610: feff8fff .word 0xfeff8fff - 8003614: fffffcff .word 0xfffffcff - 8003618: 40012c00 .word 0x40012c00 - 800361c: 40014400 .word 0x40014400 - 8003620: 40014800 .word 0x40014800 - 8003624: fffffbff .word 0xfffffbff - 8003628: fffff7ff .word 0xfffff7ff + 800368c: 46c0 nop @ (mov r8, r8) + 800368e: 46bd mov sp, r7 + 8003690: b006 add sp, #24 + 8003692: bd80 pop {r7, pc} + 8003694: feff8fff .word 0xfeff8fff + 8003698: fffffcff .word 0xfffffcff + 800369c: 40012c00 .word 0x40012c00 + 80036a0: 40014400 .word 0x40014400 + 80036a4: 40014800 .word 0x40014800 + 80036a8: fffffbff .word 0xfffffbff + 80036ac: fffff7ff .word 0xfffff7ff -0800362c : +080036b0 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { - 800362c: b580 push {r7, lr} - 800362e: b086 sub sp, #24 - 8003630: af00 add r7, sp, #0 - 8003632: 6078 str r0, [r7, #4] - 8003634: 6039 str r1, [r7, #0] + 80036b0: b580 push {r7, lr} + 80036b2: b086 sub sp, #24 + 80036b4: af00 add r7, sp, #0 + 80036b6: 6078 str r0, [r7, #4] + 80036b8: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; - 8003636: 687b ldr r3, [r7, #4] - 8003638: 6a1b ldr r3, [r3, #32] - 800363a: 617b str r3, [r7, #20] + 80036ba: 687b ldr r3, [r7, #4] + 80036bc: 6a1b ldr r3, [r3, #32] + 80036be: 617b str r3, [r7, #20] /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; - 800363c: 687b ldr r3, [r7, #4] - 800363e: 6a1b ldr r3, [r3, #32] - 8003640: 4a31 ldr r2, [pc, #196] @ (8003708 ) - 8003642: 401a ands r2, r3 - 8003644: 687b ldr r3, [r7, #4] - 8003646: 621a str r2, [r3, #32] + 80036c0: 687b ldr r3, [r7, #4] + 80036c2: 6a1b ldr r3, [r3, #32] + 80036c4: 4a31 ldr r2, [pc, #196] @ (800378c ) + 80036c6: 401a ands r2, r3 + 80036c8: 687b ldr r3, [r7, #4] + 80036ca: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; - 8003648: 687b ldr r3, [r7, #4] - 800364a: 685b ldr r3, [r3, #4] - 800364c: 613b str r3, [r7, #16] + 80036cc: 687b ldr r3, [r7, #4] + 80036ce: 685b ldr r3, [r3, #4] + 80036d0: 613b str r3, [r7, #16] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; - 800364e: 687b ldr r3, [r7, #4] - 8003650: 69db ldr r3, [r3, #28] - 8003652: 60fb str r3, [r7, #12] + 80036d2: 687b ldr r3, [r7, #4] + 80036d4: 69db ldr r3, [r3, #28] + 80036d6: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; - 8003654: 68fb ldr r3, [r7, #12] - 8003656: 4a2d ldr r2, [pc, #180] @ (800370c ) - 8003658: 4013 ands r3, r2 - 800365a: 60fb str r3, [r7, #12] + 80036d8: 68fb ldr r3, [r7, #12] + 80036da: 4a2d ldr r2, [pc, #180] @ (8003790 ) + 80036dc: 4013 ands r3, r2 + 80036de: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC3S; - 800365c: 68fb ldr r3, [r7, #12] - 800365e: 2203 movs r2, #3 - 8003660: 4393 bics r3, r2 - 8003662: 60fb str r3, [r7, #12] + 80036e0: 68fb ldr r3, [r7, #12] + 80036e2: 2203 movs r2, #3 + 80036e4: 4393 bics r3, r2 + 80036e6: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; - 8003664: 683b ldr r3, [r7, #0] - 8003666: 681b ldr r3, [r3, #0] - 8003668: 68fa ldr r2, [r7, #12] - 800366a: 4313 orrs r3, r2 - 800366c: 60fb str r3, [r7, #12] + 80036e8: 683b ldr r3, [r7, #0] + 80036ea: 681b ldr r3, [r3, #0] + 80036ec: 68fa ldr r2, [r7, #12] + 80036ee: 4313 orrs r3, r2 + 80036f0: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; - 800366e: 697b ldr r3, [r7, #20] - 8003670: 4a27 ldr r2, [pc, #156] @ (8003710 ) - 8003672: 4013 ands r3, r2 - 8003674: 617b str r3, [r7, #20] + 80036f2: 697b ldr r3, [r7, #20] + 80036f4: 4a27 ldr r2, [pc, #156] @ (8003794 ) + 80036f6: 4013 ands r3, r2 + 80036f8: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); - 8003676: 683b ldr r3, [r7, #0] - 8003678: 689b ldr r3, [r3, #8] - 800367a: 021b lsls r3, r3, #8 - 800367c: 697a ldr r2, [r7, #20] - 800367e: 4313 orrs r3, r2 - 8003680: 617b str r3, [r7, #20] + 80036fa: 683b ldr r3, [r7, #0] + 80036fc: 689b ldr r3, [r3, #8] + 80036fe: 021b lsls r3, r3, #8 + 8003700: 697a ldr r2, [r7, #20] + 8003702: 4313 orrs r3, r2 + 8003704: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) - 8003682: 687b ldr r3, [r7, #4] - 8003684: 4a23 ldr r2, [pc, #140] @ (8003714 ) - 8003686: 4293 cmp r3, r2 - 8003688: d10d bne.n 80036a6 + 8003706: 687b ldr r3, [r7, #4] + 8003708: 4a23 ldr r2, [pc, #140] @ (8003798 ) + 800370a: 4293 cmp r3, r2 + 800370c: d10d bne.n 800372a { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; - 800368a: 697b ldr r3, [r7, #20] - 800368c: 4a22 ldr r2, [pc, #136] @ (8003718 ) - 800368e: 4013 ands r3, r2 - 8003690: 617b str r3, [r7, #20] + 800370e: 697b ldr r3, [r7, #20] + 8003710: 4a22 ldr r2, [pc, #136] @ (800379c ) + 8003712: 4013 ands r3, r2 + 8003714: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); - 8003692: 683b ldr r3, [r7, #0] - 8003694: 68db ldr r3, [r3, #12] - 8003696: 021b lsls r3, r3, #8 - 8003698: 697a ldr r2, [r7, #20] - 800369a: 4313 orrs r3, r2 - 800369c: 617b str r3, [r7, #20] + 8003716: 683b ldr r3, [r7, #0] + 8003718: 68db ldr r3, [r3, #12] + 800371a: 021b lsls r3, r3, #8 + 800371c: 697a ldr r2, [r7, #20] + 800371e: 4313 orrs r3, r2 + 8003720: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; - 800369e: 697b ldr r3, [r7, #20] - 80036a0: 4a1e ldr r2, [pc, #120] @ (800371c ) - 80036a2: 4013 ands r3, r2 - 80036a4: 617b str r3, [r7, #20] + 8003722: 697b ldr r3, [r7, #20] + 8003724: 4a1e ldr r2, [pc, #120] @ (80037a0 ) + 8003726: 4013 ands r3, r2 + 8003728: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) - 80036a6: 687b ldr r3, [r7, #4] - 80036a8: 4a1a ldr r2, [pc, #104] @ (8003714 ) - 80036aa: 4293 cmp r3, r2 - 80036ac: d007 beq.n 80036be - 80036ae: 687b ldr r3, [r7, #4] - 80036b0: 4a1b ldr r2, [pc, #108] @ (8003720 ) - 80036b2: 4293 cmp r3, r2 - 80036b4: d003 beq.n 80036be - 80036b6: 687b ldr r3, [r7, #4] - 80036b8: 4a1a ldr r2, [pc, #104] @ (8003724 ) - 80036ba: 4293 cmp r3, r2 - 80036bc: d113 bne.n 80036e6 + 800372a: 687b ldr r3, [r7, #4] + 800372c: 4a1a ldr r2, [pc, #104] @ (8003798 ) + 800372e: 4293 cmp r3, r2 + 8003730: d007 beq.n 8003742 + 8003732: 687b ldr r3, [r7, #4] + 8003734: 4a1b ldr r2, [pc, #108] @ (80037a4 ) + 8003736: 4293 cmp r3, r2 + 8003738: d003 beq.n 8003742 + 800373a: 687b ldr r3, [r7, #4] + 800373c: 4a1a ldr r2, [pc, #104] @ (80037a8 ) + 800373e: 4293 cmp r3, r2 + 8003740: d113 bne.n 800376a /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; - 80036be: 693b ldr r3, [r7, #16] - 80036c0: 4a19 ldr r2, [pc, #100] @ (8003728 ) - 80036c2: 4013 ands r3, r2 - 80036c4: 613b str r3, [r7, #16] + 8003742: 693b ldr r3, [r7, #16] + 8003744: 4a19 ldr r2, [pc, #100] @ (80037ac ) + 8003746: 4013 ands r3, r2 + 8003748: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS3N; - 80036c6: 693b ldr r3, [r7, #16] - 80036c8: 4a18 ldr r2, [pc, #96] @ (800372c ) - 80036ca: 4013 ands r3, r2 - 80036cc: 613b str r3, [r7, #16] + 800374a: 693b ldr r3, [r7, #16] + 800374c: 4a18 ldr r2, [pc, #96] @ (80037b0 ) + 800374e: 4013 ands r3, r2 + 8003750: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); - 80036ce: 683b ldr r3, [r7, #0] - 80036d0: 695b ldr r3, [r3, #20] - 80036d2: 011b lsls r3, r3, #4 - 80036d4: 693a ldr r2, [r7, #16] - 80036d6: 4313 orrs r3, r2 - 80036d8: 613b str r3, [r7, #16] + 8003752: 683b ldr r3, [r7, #0] + 8003754: 695b ldr r3, [r3, #20] + 8003756: 011b lsls r3, r3, #4 + 8003758: 693a ldr r2, [r7, #16] + 800375a: 4313 orrs r3, r2 + 800375c: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); - 80036da: 683b ldr r3, [r7, #0] - 80036dc: 699b ldr r3, [r3, #24] - 80036de: 011b lsls r3, r3, #4 - 80036e0: 693a ldr r2, [r7, #16] - 80036e2: 4313 orrs r3, r2 - 80036e4: 613b str r3, [r7, #16] + 800375e: 683b ldr r3, [r7, #0] + 8003760: 699b ldr r3, [r3, #24] + 8003762: 011b lsls r3, r3, #4 + 8003764: 693a ldr r2, [r7, #16] + 8003766: 4313 orrs r3, r2 + 8003768: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; - 80036e6: 687b ldr r3, [r7, #4] - 80036e8: 693a ldr r2, [r7, #16] - 80036ea: 605a str r2, [r3, #4] + 800376a: 687b ldr r3, [r7, #4] + 800376c: 693a ldr r2, [r7, #16] + 800376e: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; - 80036ec: 687b ldr r3, [r7, #4] - 80036ee: 68fa ldr r2, [r7, #12] - 80036f0: 61da str r2, [r3, #28] + 8003770: 687b ldr r3, [r7, #4] + 8003772: 68fa ldr r2, [r7, #12] + 8003774: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; - 80036f2: 683b ldr r3, [r7, #0] - 80036f4: 685a ldr r2, [r3, #4] - 80036f6: 687b ldr r3, [r7, #4] - 80036f8: 63da str r2, [r3, #60] @ 0x3c + 8003776: 683b ldr r3, [r7, #0] + 8003778: 685a ldr r2, [r3, #4] + 800377a: 687b ldr r3, [r7, #4] + 800377c: 63da str r2, [r3, #60] @ 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; - 80036fa: 687b ldr r3, [r7, #4] - 80036fc: 697a ldr r2, [r7, #20] - 80036fe: 621a str r2, [r3, #32] + 800377e: 687b ldr r3, [r7, #4] + 8003780: 697a ldr r2, [r7, #20] + 8003782: 621a str r2, [r3, #32] } - 8003700: 46c0 nop @ (mov r8, r8) - 8003702: 46bd mov sp, r7 - 8003704: b006 add sp, #24 - 8003706: bd80 pop {r7, pc} - 8003708: fffffeff .word 0xfffffeff - 800370c: fffeff8f .word 0xfffeff8f - 8003710: fffffdff .word 0xfffffdff - 8003714: 40012c00 .word 0x40012c00 - 8003718: fffff7ff .word 0xfffff7ff - 800371c: fffffbff .word 0xfffffbff - 8003720: 40014400 .word 0x40014400 - 8003724: 40014800 .word 0x40014800 - 8003728: ffffefff .word 0xffffefff - 800372c: ffffdfff .word 0xffffdfff + 8003784: 46c0 nop @ (mov r8, r8) + 8003786: 46bd mov sp, r7 + 8003788: b006 add sp, #24 + 800378a: bd80 pop {r7, pc} + 800378c: fffffeff .word 0xfffffeff + 8003790: fffeff8f .word 0xfffeff8f + 8003794: fffffdff .word 0xfffffdff + 8003798: 40012c00 .word 0x40012c00 + 800379c: fffff7ff .word 0xfffff7ff + 80037a0: fffffbff .word 0xfffffbff + 80037a4: 40014400 .word 0x40014400 + 80037a8: 40014800 .word 0x40014800 + 80037ac: ffffefff .word 0xffffefff + 80037b0: ffffdfff .word 0xffffdfff -08003730 : +080037b4 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { - 8003730: b580 push {r7, lr} - 8003732: b086 sub sp, #24 - 8003734: af00 add r7, sp, #0 - 8003736: 6078 str r0, [r7, #4] - 8003738: 6039 str r1, [r7, #0] + 80037b4: b580 push {r7, lr} + 80037b6: b086 sub sp, #24 + 80037b8: af00 add r7, sp, #0 + 80037ba: 6078 str r0, [r7, #4] + 80037bc: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; - 800373a: 687b ldr r3, [r7, #4] - 800373c: 6a1b ldr r3, [r3, #32] - 800373e: 613b str r3, [r7, #16] + 80037be: 687b ldr r3, [r7, #4] + 80037c0: 6a1b ldr r3, [r3, #32] + 80037c2: 613b str r3, [r7, #16] /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; - 8003740: 687b ldr r3, [r7, #4] - 8003742: 6a1b ldr r3, [r3, #32] - 8003744: 4a24 ldr r2, [pc, #144] @ (80037d8 ) - 8003746: 401a ands r2, r3 - 8003748: 687b ldr r3, [r7, #4] - 800374a: 621a str r2, [r3, #32] + 80037c4: 687b ldr r3, [r7, #4] + 80037c6: 6a1b ldr r3, [r3, #32] + 80037c8: 4a24 ldr r2, [pc, #144] @ (800385c ) + 80037ca: 401a ands r2, r3 + 80037cc: 687b ldr r3, [r7, #4] + 80037ce: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; - 800374c: 687b ldr r3, [r7, #4] - 800374e: 685b ldr r3, [r3, #4] - 8003750: 617b str r3, [r7, #20] + 80037d0: 687b ldr r3, [r7, #4] + 80037d2: 685b ldr r3, [r3, #4] + 80037d4: 617b str r3, [r7, #20] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; - 8003752: 687b ldr r3, [r7, #4] - 8003754: 69db ldr r3, [r3, #28] - 8003756: 60fb str r3, [r7, #12] + 80037d6: 687b ldr r3, [r7, #4] + 80037d8: 69db ldr r3, [r3, #28] + 80037da: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; - 8003758: 68fb ldr r3, [r7, #12] - 800375a: 4a20 ldr r2, [pc, #128] @ (80037dc ) - 800375c: 4013 ands r3, r2 - 800375e: 60fb str r3, [r7, #12] + 80037dc: 68fb ldr r3, [r7, #12] + 80037de: 4a20 ldr r2, [pc, #128] @ (8003860 ) + 80037e0: 4013 ands r3, r2 + 80037e2: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC4S; - 8003760: 68fb ldr r3, [r7, #12] - 8003762: 4a1f ldr r2, [pc, #124] @ (80037e0 ) - 8003764: 4013 ands r3, r2 - 8003766: 60fb str r3, [r7, #12] + 80037e4: 68fb ldr r3, [r7, #12] + 80037e6: 4a1f ldr r2, [pc, #124] @ (8003864 ) + 80037e8: 4013 ands r3, r2 + 80037ea: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); - 8003768: 683b ldr r3, [r7, #0] - 800376a: 681b ldr r3, [r3, #0] - 800376c: 021b lsls r3, r3, #8 - 800376e: 68fa ldr r2, [r7, #12] - 8003770: 4313 orrs r3, r2 - 8003772: 60fb str r3, [r7, #12] + 80037ec: 683b ldr r3, [r7, #0] + 80037ee: 681b ldr r3, [r3, #0] + 80037f0: 021b lsls r3, r3, #8 + 80037f2: 68fa ldr r2, [r7, #12] + 80037f4: 4313 orrs r3, r2 + 80037f6: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; - 8003774: 693b ldr r3, [r7, #16] - 8003776: 4a1b ldr r2, [pc, #108] @ (80037e4 ) - 8003778: 4013 ands r3, r2 - 800377a: 613b str r3, [r7, #16] + 80037f8: 693b ldr r3, [r7, #16] + 80037fa: 4a1b ldr r2, [pc, #108] @ (8003868 ) + 80037fc: 4013 ands r3, r2 + 80037fe: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); - 800377c: 683b ldr r3, [r7, #0] - 800377e: 689b ldr r3, [r3, #8] - 8003780: 031b lsls r3, r3, #12 - 8003782: 693a ldr r2, [r7, #16] - 8003784: 4313 orrs r3, r2 - 8003786: 613b str r3, [r7, #16] + 8003800: 683b ldr r3, [r7, #0] + 8003802: 689b ldr r3, [r3, #8] + 8003804: 031b lsls r3, r3, #12 + 8003806: 693a ldr r2, [r7, #16] + 8003808: 4313 orrs r3, r2 + 800380a: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) - 8003788: 687b ldr r3, [r7, #4] - 800378a: 4a17 ldr r2, [pc, #92] @ (80037e8 ) - 800378c: 4293 cmp r3, r2 - 800378e: d007 beq.n 80037a0 - 8003790: 687b ldr r3, [r7, #4] - 8003792: 4a16 ldr r2, [pc, #88] @ (80037ec ) - 8003794: 4293 cmp r3, r2 - 8003796: d003 beq.n 80037a0 - 8003798: 687b ldr r3, [r7, #4] - 800379a: 4a15 ldr r2, [pc, #84] @ (80037f0 ) - 800379c: 4293 cmp r3, r2 - 800379e: d109 bne.n 80037b4 + 800380c: 687b ldr r3, [r7, #4] + 800380e: 4a17 ldr r2, [pc, #92] @ (800386c ) + 8003810: 4293 cmp r3, r2 + 8003812: d007 beq.n 8003824 + 8003814: 687b ldr r3, [r7, #4] + 8003816: 4a16 ldr r2, [pc, #88] @ (8003870 ) + 8003818: 4293 cmp r3, r2 + 800381a: d003 beq.n 8003824 + 800381c: 687b ldr r3, [r7, #4] + 800381e: 4a15 ldr r2, [pc, #84] @ (8003874 ) + 8003820: 4293 cmp r3, r2 + 8003822: d109 bne.n 8003838 { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; - 80037a0: 697b ldr r3, [r7, #20] - 80037a2: 4a14 ldr r2, [pc, #80] @ (80037f4 ) - 80037a4: 4013 ands r3, r2 - 80037a6: 617b str r3, [r7, #20] + 8003824: 697b ldr r3, [r7, #20] + 8003826: 4a14 ldr r2, [pc, #80] @ (8003878 ) + 8003828: 4013 ands r3, r2 + 800382a: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); - 80037a8: 683b ldr r3, [r7, #0] - 80037aa: 695b ldr r3, [r3, #20] - 80037ac: 019b lsls r3, r3, #6 - 80037ae: 697a ldr r2, [r7, #20] - 80037b0: 4313 orrs r3, r2 - 80037b2: 617b str r3, [r7, #20] + 800382c: 683b ldr r3, [r7, #0] + 800382e: 695b ldr r3, [r3, #20] + 8003830: 019b lsls r3, r3, #6 + 8003832: 697a ldr r2, [r7, #20] + 8003834: 4313 orrs r3, r2 + 8003836: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; - 80037b4: 687b ldr r3, [r7, #4] - 80037b6: 697a ldr r2, [r7, #20] - 80037b8: 605a str r2, [r3, #4] + 8003838: 687b ldr r3, [r7, #4] + 800383a: 697a ldr r2, [r7, #20] + 800383c: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; - 80037ba: 687b ldr r3, [r7, #4] - 80037bc: 68fa ldr r2, [r7, #12] - 80037be: 61da str r2, [r3, #28] + 800383e: 687b ldr r3, [r7, #4] + 8003840: 68fa ldr r2, [r7, #12] + 8003842: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; - 80037c0: 683b ldr r3, [r7, #0] - 80037c2: 685a ldr r2, [r3, #4] - 80037c4: 687b ldr r3, [r7, #4] - 80037c6: 641a str r2, [r3, #64] @ 0x40 + 8003844: 683b ldr r3, [r7, #0] + 8003846: 685a ldr r2, [r3, #4] + 8003848: 687b ldr r3, [r7, #4] + 800384a: 641a str r2, [r3, #64] @ 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; - 80037c8: 687b ldr r3, [r7, #4] - 80037ca: 693a ldr r2, [r7, #16] - 80037cc: 621a str r2, [r3, #32] + 800384c: 687b ldr r3, [r7, #4] + 800384e: 693a ldr r2, [r7, #16] + 8003850: 621a str r2, [r3, #32] } - 80037ce: 46c0 nop @ (mov r8, r8) - 80037d0: 46bd mov sp, r7 - 80037d2: b006 add sp, #24 - 80037d4: bd80 pop {r7, pc} - 80037d6: 46c0 nop @ (mov r8, r8) - 80037d8: ffffefff .word 0xffffefff - 80037dc: feff8fff .word 0xfeff8fff - 80037e0: fffffcff .word 0xfffffcff - 80037e4: ffffdfff .word 0xffffdfff - 80037e8: 40012c00 .word 0x40012c00 - 80037ec: 40014400 .word 0x40014400 - 80037f0: 40014800 .word 0x40014800 - 80037f4: ffffbfff .word 0xffffbfff + 8003852: 46c0 nop @ (mov r8, r8) + 8003854: 46bd mov sp, r7 + 8003856: b006 add sp, #24 + 8003858: bd80 pop {r7, pc} + 800385a: 46c0 nop @ (mov r8, r8) + 800385c: ffffefff .word 0xffffefff + 8003860: feff8fff .word 0xfeff8fff + 8003864: fffffcff .word 0xfffffcff + 8003868: ffffdfff .word 0xffffdfff + 800386c: 40012c00 .word 0x40012c00 + 8003870: 40014400 .word 0x40014400 + 8003874: 40014800 .word 0x40014800 + 8003878: ffffbfff .word 0xffffbfff -080037f8 : +0800387c : * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { - 80037f8: b580 push {r7, lr} - 80037fa: b086 sub sp, #24 - 80037fc: af00 add r7, sp, #0 - 80037fe: 6078 str r0, [r7, #4] - 8003800: 6039 str r1, [r7, #0] + 800387c: b580 push {r7, lr} + 800387e: b086 sub sp, #24 + 8003880: af00 add r7, sp, #0 + 8003882: 6078 str r0, [r7, #4] + 8003884: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; - 8003802: 687b ldr r3, [r7, #4] - 8003804: 6a1b ldr r3, [r3, #32] - 8003806: 613b str r3, [r7, #16] + 8003886: 687b ldr r3, [r7, #4] + 8003888: 6a1b ldr r3, [r3, #32] + 800388a: 613b str r3, [r7, #16] /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC5E; - 8003808: 687b ldr r3, [r7, #4] - 800380a: 6a1b ldr r3, [r3, #32] - 800380c: 4a21 ldr r2, [pc, #132] @ (8003894 ) - 800380e: 401a ands r2, r3 - 8003810: 687b ldr r3, [r7, #4] - 8003812: 621a str r2, [r3, #32] + 800388c: 687b ldr r3, [r7, #4] + 800388e: 6a1b ldr r3, [r3, #32] + 8003890: 4a21 ldr r2, [pc, #132] @ (8003918 ) + 8003892: 401a ands r2, r3 + 8003894: 687b ldr r3, [r7, #4] + 8003896: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; - 8003814: 687b ldr r3, [r7, #4] - 8003816: 685b ldr r3, [r3, #4] - 8003818: 617b str r3, [r7, #20] + 8003898: 687b ldr r3, [r7, #4] + 800389a: 685b ldr r3, [r3, #4] + 800389c: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR3; - 800381a: 687b ldr r3, [r7, #4] - 800381c: 6d5b ldr r3, [r3, #84] @ 0x54 - 800381e: 60fb str r3, [r7, #12] + 800389e: 687b ldr r3, [r7, #4] + 80038a0: 6d5b ldr r3, [r3, #84] @ 0x54 + 80038a2: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC5M); - 8003820: 68fb ldr r3, [r7, #12] - 8003822: 4a1d ldr r2, [pc, #116] @ (8003898 ) - 8003824: 4013 ands r3, r2 - 8003826: 60fb str r3, [r7, #12] + 80038a4: 68fb ldr r3, [r7, #12] + 80038a6: 4a1d ldr r2, [pc, #116] @ (800391c ) + 80038a8: 4013 ands r3, r2 + 80038aa: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; - 8003828: 683b ldr r3, [r7, #0] - 800382a: 681b ldr r3, [r3, #0] - 800382c: 68fa ldr r2, [r7, #12] - 800382e: 4313 orrs r3, r2 - 8003830: 60fb str r3, [r7, #12] + 80038ac: 683b ldr r3, [r7, #0] + 80038ae: 681b ldr r3, [r3, #0] + 80038b0: 68fa ldr r2, [r7, #12] + 80038b2: 4313 orrs r3, r2 + 80038b4: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC5P; - 8003832: 693b ldr r3, [r7, #16] - 8003834: 4a19 ldr r2, [pc, #100] @ (800389c ) - 8003836: 4013 ands r3, r2 - 8003838: 613b str r3, [r7, #16] + 80038b6: 693b ldr r3, [r7, #16] + 80038b8: 4a19 ldr r2, [pc, #100] @ (8003920 ) + 80038ba: 4013 ands r3, r2 + 80038bc: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 16U); - 800383a: 683b ldr r3, [r7, #0] - 800383c: 689b ldr r3, [r3, #8] - 800383e: 041b lsls r3, r3, #16 - 8003840: 693a ldr r2, [r7, #16] - 8003842: 4313 orrs r3, r2 - 8003844: 613b str r3, [r7, #16] + 80038be: 683b ldr r3, [r7, #0] + 80038c0: 689b ldr r3, [r3, #8] + 80038c2: 041b lsls r3, r3, #16 + 80038c4: 693a ldr r2, [r7, #16] + 80038c6: 4313 orrs r3, r2 + 80038c8: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) - 8003846: 687b ldr r3, [r7, #4] - 8003848: 4a15 ldr r2, [pc, #84] @ (80038a0 ) - 800384a: 4293 cmp r3, r2 - 800384c: d007 beq.n 800385e - 800384e: 687b ldr r3, [r7, #4] - 8003850: 4a14 ldr r2, [pc, #80] @ (80038a4 ) - 8003852: 4293 cmp r3, r2 - 8003854: d003 beq.n 800385e - 8003856: 687b ldr r3, [r7, #4] - 8003858: 4a13 ldr r2, [pc, #76] @ (80038a8 ) - 800385a: 4293 cmp r3, r2 - 800385c: d109 bne.n 8003872 + 80038ca: 687b ldr r3, [r7, #4] + 80038cc: 4a15 ldr r2, [pc, #84] @ (8003924 ) + 80038ce: 4293 cmp r3, r2 + 80038d0: d007 beq.n 80038e2 + 80038d2: 687b ldr r3, [r7, #4] + 80038d4: 4a14 ldr r2, [pc, #80] @ (8003928 ) + 80038d6: 4293 cmp r3, r2 + 80038d8: d003 beq.n 80038e2 + 80038da: 687b ldr r3, [r7, #4] + 80038dc: 4a13 ldr r2, [pc, #76] @ (800392c ) + 80038de: 4293 cmp r3, r2 + 80038e0: d109 bne.n 80038f6 { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS5; - 800385e: 697b ldr r3, [r7, #20] - 8003860: 4a0c ldr r2, [pc, #48] @ (8003894 ) - 8003862: 4013 ands r3, r2 - 8003864: 617b str r3, [r7, #20] + 80038e2: 697b ldr r3, [r7, #20] + 80038e4: 4a0c ldr r2, [pc, #48] @ (8003918 ) + 80038e6: 4013 ands r3, r2 + 80038e8: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 8U); - 8003866: 683b ldr r3, [r7, #0] - 8003868: 695b ldr r3, [r3, #20] - 800386a: 021b lsls r3, r3, #8 - 800386c: 697a ldr r2, [r7, #20] - 800386e: 4313 orrs r3, r2 - 8003870: 617b str r3, [r7, #20] + 80038ea: 683b ldr r3, [r7, #0] + 80038ec: 695b ldr r3, [r3, #20] + 80038ee: 021b lsls r3, r3, #8 + 80038f0: 697a ldr r2, [r7, #20] + 80038f2: 4313 orrs r3, r2 + 80038f4: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; - 8003872: 687b ldr r3, [r7, #4] - 8003874: 697a ldr r2, [r7, #20] - 8003876: 605a str r2, [r3, #4] + 80038f6: 687b ldr r3, [r7, #4] + 80038f8: 697a ldr r2, [r7, #20] + 80038fa: 605a str r2, [r3, #4] /* Write to TIMx CCMR3 */ TIMx->CCMR3 = tmpccmrx; - 8003878: 687b ldr r3, [r7, #4] - 800387a: 68fa ldr r2, [r7, #12] - 800387c: 655a str r2, [r3, #84] @ 0x54 + 80038fc: 687b ldr r3, [r7, #4] + 80038fe: 68fa ldr r2, [r7, #12] + 8003900: 655a str r2, [r3, #84] @ 0x54 /* Set the Capture Compare Register value */ TIMx->CCR5 = OC_Config->Pulse; - 800387e: 683b ldr r3, [r7, #0] - 8003880: 685a ldr r2, [r3, #4] - 8003882: 687b ldr r3, [r7, #4] - 8003884: 659a str r2, [r3, #88] @ 0x58 + 8003902: 683b ldr r3, [r7, #0] + 8003904: 685a ldr r2, [r3, #4] + 8003906: 687b ldr r3, [r7, #4] + 8003908: 659a str r2, [r3, #88] @ 0x58 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; - 8003886: 687b ldr r3, [r7, #4] - 8003888: 693a ldr r2, [r7, #16] - 800388a: 621a str r2, [r3, #32] + 800390a: 687b ldr r3, [r7, #4] + 800390c: 693a ldr r2, [r7, #16] + 800390e: 621a str r2, [r3, #32] } - 800388c: 46c0 nop @ (mov r8, r8) - 800388e: 46bd mov sp, r7 - 8003890: b006 add sp, #24 - 8003892: bd80 pop {r7, pc} - 8003894: fffeffff .word 0xfffeffff - 8003898: fffeff8f .word 0xfffeff8f - 800389c: fffdffff .word 0xfffdffff - 80038a0: 40012c00 .word 0x40012c00 - 80038a4: 40014400 .word 0x40014400 - 80038a8: 40014800 .word 0x40014800 + 8003910: 46c0 nop @ (mov r8, r8) + 8003912: 46bd mov sp, r7 + 8003914: b006 add sp, #24 + 8003916: bd80 pop {r7, pc} + 8003918: fffeffff .word 0xfffeffff + 800391c: fffeff8f .word 0xfffeff8f + 8003920: fffdffff .word 0xfffdffff + 8003924: 40012c00 .word 0x40012c00 + 8003928: 40014400 .word 0x40014400 + 800392c: 40014800 .word 0x40014800 -080038ac : +08003930 : * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { - 80038ac: b580 push {r7, lr} - 80038ae: b086 sub sp, #24 - 80038b0: af00 add r7, sp, #0 - 80038b2: 6078 str r0, [r7, #4] - 80038b4: 6039 str r1, [r7, #0] + 8003930: b580 push {r7, lr} + 8003932: b086 sub sp, #24 + 8003934: af00 add r7, sp, #0 + 8003936: 6078 str r0, [r7, #4] + 8003938: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; - 80038b6: 687b ldr r3, [r7, #4] - 80038b8: 6a1b ldr r3, [r3, #32] - 80038ba: 613b str r3, [r7, #16] + 800393a: 687b ldr r3, [r7, #4] + 800393c: 6a1b ldr r3, [r3, #32] + 800393e: 613b str r3, [r7, #16] /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC6E; - 80038bc: 687b ldr r3, [r7, #4] - 80038be: 6a1b ldr r3, [r3, #32] - 80038c0: 4a22 ldr r2, [pc, #136] @ (800394c ) - 80038c2: 401a ands r2, r3 - 80038c4: 687b ldr r3, [r7, #4] - 80038c6: 621a str r2, [r3, #32] + 8003940: 687b ldr r3, [r7, #4] + 8003942: 6a1b ldr r3, [r3, #32] + 8003944: 4a22 ldr r2, [pc, #136] @ (80039d0 ) + 8003946: 401a ands r2, r3 + 8003948: 687b ldr r3, [r7, #4] + 800394a: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; - 80038c8: 687b ldr r3, [r7, #4] - 80038ca: 685b ldr r3, [r3, #4] - 80038cc: 617b str r3, [r7, #20] + 800394c: 687b ldr r3, [r7, #4] + 800394e: 685b ldr r3, [r3, #4] + 8003950: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR3; - 80038ce: 687b ldr r3, [r7, #4] - 80038d0: 6d5b ldr r3, [r3, #84] @ 0x54 - 80038d2: 60fb str r3, [r7, #12] + 8003952: 687b ldr r3, [r7, #4] + 8003954: 6d5b ldr r3, [r3, #84] @ 0x54 + 8003956: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC6M); - 80038d4: 68fb ldr r3, [r7, #12] - 80038d6: 4a1e ldr r2, [pc, #120] @ (8003950 ) - 80038d8: 4013 ands r3, r2 - 80038da: 60fb str r3, [r7, #12] + 8003958: 68fb ldr r3, [r7, #12] + 800395a: 4a1e ldr r2, [pc, #120] @ (80039d4 ) + 800395c: 4013 ands r3, r2 + 800395e: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); - 80038dc: 683b ldr r3, [r7, #0] - 80038de: 681b ldr r3, [r3, #0] - 80038e0: 021b lsls r3, r3, #8 - 80038e2: 68fa ldr r2, [r7, #12] - 80038e4: 4313 orrs r3, r2 - 80038e6: 60fb str r3, [r7, #12] + 8003960: 683b ldr r3, [r7, #0] + 8003962: 681b ldr r3, [r3, #0] + 8003964: 021b lsls r3, r3, #8 + 8003966: 68fa ldr r2, [r7, #12] + 8003968: 4313 orrs r3, r2 + 800396a: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= (uint32_t)~TIM_CCER_CC6P; - 80038e8: 693b ldr r3, [r7, #16] - 80038ea: 4a1a ldr r2, [pc, #104] @ (8003954 ) - 80038ec: 4013 ands r3, r2 - 80038ee: 613b str r3, [r7, #16] + 800396c: 693b ldr r3, [r7, #16] + 800396e: 4a1a ldr r2, [pc, #104] @ (80039d8 ) + 8003970: 4013 ands r3, r2 + 8003972: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 20U); - 80038f0: 683b ldr r3, [r7, #0] - 80038f2: 689b ldr r3, [r3, #8] - 80038f4: 051b lsls r3, r3, #20 - 80038f6: 693a ldr r2, [r7, #16] - 80038f8: 4313 orrs r3, r2 - 80038fa: 613b str r3, [r7, #16] + 8003974: 683b ldr r3, [r7, #0] + 8003976: 689b ldr r3, [r3, #8] + 8003978: 051b lsls r3, r3, #20 + 800397a: 693a ldr r2, [r7, #16] + 800397c: 4313 orrs r3, r2 + 800397e: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) - 80038fc: 687b ldr r3, [r7, #4] - 80038fe: 4a16 ldr r2, [pc, #88] @ (8003958 ) - 8003900: 4293 cmp r3, r2 - 8003902: d007 beq.n 8003914 - 8003904: 687b ldr r3, [r7, #4] - 8003906: 4a15 ldr r2, [pc, #84] @ (800395c ) - 8003908: 4293 cmp r3, r2 - 800390a: d003 beq.n 8003914 - 800390c: 687b ldr r3, [r7, #4] - 800390e: 4a14 ldr r2, [pc, #80] @ (8003960 ) - 8003910: 4293 cmp r3, r2 - 8003912: d109 bne.n 8003928 + 8003980: 687b ldr r3, [r7, #4] + 8003982: 4a16 ldr r2, [pc, #88] @ (80039dc ) + 8003984: 4293 cmp r3, r2 + 8003986: d007 beq.n 8003998 + 8003988: 687b ldr r3, [r7, #4] + 800398a: 4a15 ldr r2, [pc, #84] @ (80039e0 ) + 800398c: 4293 cmp r3, r2 + 800398e: d003 beq.n 8003998 + 8003990: 687b ldr r3, [r7, #4] + 8003992: 4a14 ldr r2, [pc, #80] @ (80039e4 ) + 8003994: 4293 cmp r3, r2 + 8003996: d109 bne.n 80039ac { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS6; - 8003914: 697b ldr r3, [r7, #20] - 8003916: 4a13 ldr r2, [pc, #76] @ (8003964 ) - 8003918: 4013 ands r3, r2 - 800391a: 617b str r3, [r7, #20] + 8003998: 697b ldr r3, [r7, #20] + 800399a: 4a13 ldr r2, [pc, #76] @ (80039e8 ) + 800399c: 4013 ands r3, r2 + 800399e: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 10U); - 800391c: 683b ldr r3, [r7, #0] - 800391e: 695b ldr r3, [r3, #20] - 8003920: 029b lsls r3, r3, #10 - 8003922: 697a ldr r2, [r7, #20] - 8003924: 4313 orrs r3, r2 - 8003926: 617b str r3, [r7, #20] + 80039a0: 683b ldr r3, [r7, #0] + 80039a2: 695b ldr r3, [r3, #20] + 80039a4: 029b lsls r3, r3, #10 + 80039a6: 697a ldr r2, [r7, #20] + 80039a8: 4313 orrs r3, r2 + 80039aa: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; - 8003928: 687b ldr r3, [r7, #4] - 800392a: 697a ldr r2, [r7, #20] - 800392c: 605a str r2, [r3, #4] + 80039ac: 687b ldr r3, [r7, #4] + 80039ae: 697a ldr r2, [r7, #20] + 80039b0: 605a str r2, [r3, #4] /* Write to TIMx CCMR3 */ TIMx->CCMR3 = tmpccmrx; - 800392e: 687b ldr r3, [r7, #4] - 8003930: 68fa ldr r2, [r7, #12] - 8003932: 655a str r2, [r3, #84] @ 0x54 + 80039b2: 687b ldr r3, [r7, #4] + 80039b4: 68fa ldr r2, [r7, #12] + 80039b6: 655a str r2, [r3, #84] @ 0x54 /* Set the Capture Compare Register value */ TIMx->CCR6 = OC_Config->Pulse; - 8003934: 683b ldr r3, [r7, #0] - 8003936: 685a ldr r2, [r3, #4] - 8003938: 687b ldr r3, [r7, #4] - 800393a: 65da str r2, [r3, #92] @ 0x5c + 80039b8: 683b ldr r3, [r7, #0] + 80039ba: 685a ldr r2, [r3, #4] + 80039bc: 687b ldr r3, [r7, #4] + 80039be: 65da str r2, [r3, #92] @ 0x5c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; - 800393c: 687b ldr r3, [r7, #4] - 800393e: 693a ldr r2, [r7, #16] - 8003940: 621a str r2, [r3, #32] + 80039c0: 687b ldr r3, [r7, #4] + 80039c2: 693a ldr r2, [r7, #16] + 80039c4: 621a str r2, [r3, #32] } - 8003942: 46c0 nop @ (mov r8, r8) - 8003944: 46bd mov sp, r7 - 8003946: b006 add sp, #24 - 8003948: bd80 pop {r7, pc} - 800394a: 46c0 nop @ (mov r8, r8) - 800394c: ffefffff .word 0xffefffff - 8003950: feff8fff .word 0xfeff8fff - 8003954: ffdfffff .word 0xffdfffff - 8003958: 40012c00 .word 0x40012c00 - 800395c: 40014400 .word 0x40014400 - 8003960: 40014800 .word 0x40014800 - 8003964: fffbffff .word 0xfffbffff + 80039c6: 46c0 nop @ (mov r8, r8) + 80039c8: 46bd mov sp, r7 + 80039ca: b006 add sp, #24 + 80039cc: bd80 pop {r7, pc} + 80039ce: 46c0 nop @ (mov r8, r8) + 80039d0: ffefffff .word 0xffefffff + 80039d4: feff8fff .word 0xfeff8fff + 80039d8: ffdfffff .word 0xffdfffff + 80039dc: 40012c00 .word 0x40012c00 + 80039e0: 40014400 .word 0x40014400 + 80039e4: 40014800 .word 0x40014800 + 80039e8: fffbffff .word 0xfffbffff -08003968 : +080039ec : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { - 8003968: b580 push {r7, lr} - 800396a: b086 sub sp, #24 - 800396c: af00 add r7, sp, #0 - 800396e: 60f8 str r0, [r7, #12] - 8003970: 60b9 str r1, [r7, #8] - 8003972: 607a str r2, [r7, #4] + 80039ec: b580 push {r7, lr} + 80039ee: b086 sub sp, #24 + 80039f0: af00 add r7, sp, #0 + 80039f2: 60f8 str r0, [r7, #12] + 80039f4: 60b9 str r1, [r7, #8] + 80039f6: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; - 8003974: 68fb ldr r3, [r7, #12] - 8003976: 6a1b ldr r3, [r3, #32] - 8003978: 617b str r3, [r7, #20] + 80039f8: 68fb ldr r3, [r7, #12] + 80039fa: 6a1b ldr r3, [r3, #32] + 80039fc: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC1E; - 800397a: 68fb ldr r3, [r7, #12] - 800397c: 6a1b ldr r3, [r3, #32] - 800397e: 2201 movs r2, #1 - 8003980: 4393 bics r3, r2 - 8003982: 001a movs r2, r3 - 8003984: 68fb ldr r3, [r7, #12] - 8003986: 621a str r2, [r3, #32] + 80039fe: 68fb ldr r3, [r7, #12] + 8003a00: 6a1b ldr r3, [r3, #32] + 8003a02: 2201 movs r2, #1 + 8003a04: 4393 bics r3, r2 + 8003a06: 001a movs r2, r3 + 8003a08: 68fb ldr r3, [r7, #12] + 8003a0a: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; - 8003988: 68fb ldr r3, [r7, #12] - 800398a: 699b ldr r3, [r3, #24] - 800398c: 613b str r3, [r7, #16] + 8003a0c: 68fb ldr r3, [r7, #12] + 8003a0e: 699b ldr r3, [r3, #24] + 8003a10: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; - 800398e: 693b ldr r3, [r7, #16] - 8003990: 22f0 movs r2, #240 @ 0xf0 - 8003992: 4393 bics r3, r2 - 8003994: 613b str r3, [r7, #16] + 8003a12: 693b ldr r3, [r7, #16] + 8003a14: 22f0 movs r2, #240 @ 0xf0 + 8003a16: 4393 bics r3, r2 + 8003a18: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 4U); - 8003996: 687b ldr r3, [r7, #4] - 8003998: 011b lsls r3, r3, #4 - 800399a: 693a ldr r2, [r7, #16] - 800399c: 4313 orrs r3, r2 - 800399e: 613b str r3, [r7, #16] + 8003a1a: 687b ldr r3, [r7, #4] + 8003a1c: 011b lsls r3, r3, #4 + 8003a1e: 693a ldr r2, [r7, #16] + 8003a20: 4313 orrs r3, r2 + 8003a22: 613b str r3, [r7, #16] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); - 80039a0: 697b ldr r3, [r7, #20] - 80039a2: 220a movs r2, #10 - 80039a4: 4393 bics r3, r2 - 80039a6: 617b str r3, [r7, #20] + 8003a24: 697b ldr r3, [r7, #20] + 8003a26: 220a movs r2, #10 + 8003a28: 4393 bics r3, r2 + 8003a2a: 617b str r3, [r7, #20] tmpccer |= TIM_ICPolarity; - 80039a8: 697a ldr r2, [r7, #20] - 80039aa: 68bb ldr r3, [r7, #8] - 80039ac: 4313 orrs r3, r2 - 80039ae: 617b str r3, [r7, #20] + 8003a2c: 697a ldr r2, [r7, #20] + 8003a2e: 68bb ldr r3, [r7, #8] + 8003a30: 4313 orrs r3, r2 + 8003a32: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; - 80039b0: 68fb ldr r3, [r7, #12] - 80039b2: 693a ldr r2, [r7, #16] - 80039b4: 619a str r2, [r3, #24] + 8003a34: 68fb ldr r3, [r7, #12] + 8003a36: 693a ldr r2, [r7, #16] + 8003a38: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; - 80039b6: 68fb ldr r3, [r7, #12] - 80039b8: 697a ldr r2, [r7, #20] - 80039ba: 621a str r2, [r3, #32] + 8003a3a: 68fb ldr r3, [r7, #12] + 8003a3c: 697a ldr r2, [r7, #20] + 8003a3e: 621a str r2, [r3, #32] } - 80039bc: 46c0 nop @ (mov r8, r8) - 80039be: 46bd mov sp, r7 - 80039c0: b006 add sp, #24 - 80039c2: bd80 pop {r7, pc} + 8003a40: 46c0 nop @ (mov r8, r8) + 8003a42: 46bd mov sp, r7 + 8003a44: b006 add sp, #24 + 8003a46: bd80 pop {r7, pc} -080039c4 : +08003a48 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { - 80039c4: b580 push {r7, lr} - 80039c6: b086 sub sp, #24 - 80039c8: af00 add r7, sp, #0 - 80039ca: 60f8 str r0, [r7, #12] - 80039cc: 60b9 str r1, [r7, #8] - 80039ce: 607a str r2, [r7, #4] + 8003a48: b580 push {r7, lr} + 8003a4a: b086 sub sp, #24 + 8003a4c: af00 add r7, sp, #0 + 8003a4e: 60f8 str r0, [r7, #12] + 8003a50: 60b9 str r1, [r7, #8] + 8003a52: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ tmpccer = TIMx->CCER; - 80039d0: 68fb ldr r3, [r7, #12] - 80039d2: 6a1b ldr r3, [r3, #32] - 80039d4: 617b str r3, [r7, #20] + 8003a54: 68fb ldr r3, [r7, #12] + 8003a56: 6a1b ldr r3, [r3, #32] + 8003a58: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC2E; - 80039d6: 68fb ldr r3, [r7, #12] - 80039d8: 6a1b ldr r3, [r3, #32] - 80039da: 2210 movs r2, #16 - 80039dc: 4393 bics r3, r2 - 80039de: 001a movs r2, r3 - 80039e0: 68fb ldr r3, [r7, #12] - 80039e2: 621a str r2, [r3, #32] + 8003a5a: 68fb ldr r3, [r7, #12] + 8003a5c: 6a1b ldr r3, [r3, #32] + 8003a5e: 2210 movs r2, #16 + 8003a60: 4393 bics r3, r2 + 8003a62: 001a movs r2, r3 + 8003a64: 68fb ldr r3, [r7, #12] + 8003a66: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; - 80039e4: 68fb ldr r3, [r7, #12] - 80039e6: 699b ldr r3, [r3, #24] - 80039e8: 613b str r3, [r7, #16] + 8003a68: 68fb ldr r3, [r7, #12] + 8003a6a: 699b ldr r3, [r3, #24] + 8003a6c: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; - 80039ea: 693b ldr r3, [r7, #16] - 80039ec: 4a0d ldr r2, [pc, #52] @ (8003a24 ) - 80039ee: 4013 ands r3, r2 - 80039f0: 613b str r3, [r7, #16] + 8003a6e: 693b ldr r3, [r7, #16] + 8003a70: 4a0d ldr r2, [pc, #52] @ (8003aa8 ) + 8003a72: 4013 ands r3, r2 + 8003a74: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 12U); - 80039f2: 687b ldr r3, [r7, #4] - 80039f4: 031b lsls r3, r3, #12 - 80039f6: 693a ldr r2, [r7, #16] - 80039f8: 4313 orrs r3, r2 - 80039fa: 613b str r3, [r7, #16] + 8003a76: 687b ldr r3, [r7, #4] + 8003a78: 031b lsls r3, r3, #12 + 8003a7a: 693a ldr r2, [r7, #16] + 8003a7c: 4313 orrs r3, r2 + 8003a7e: 613b str r3, [r7, #16] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - 80039fc: 697b ldr r3, [r7, #20] - 80039fe: 22a0 movs r2, #160 @ 0xa0 - 8003a00: 4393 bics r3, r2 - 8003a02: 617b str r3, [r7, #20] + 8003a80: 697b ldr r3, [r7, #20] + 8003a82: 22a0 movs r2, #160 @ 0xa0 + 8003a84: 4393 bics r3, r2 + 8003a86: 617b str r3, [r7, #20] tmpccer |= (TIM_ICPolarity << 4U); - 8003a04: 68bb ldr r3, [r7, #8] - 8003a06: 011b lsls r3, r3, #4 - 8003a08: 697a ldr r2, [r7, #20] - 8003a0a: 4313 orrs r3, r2 - 8003a0c: 617b str r3, [r7, #20] + 8003a88: 68bb ldr r3, [r7, #8] + 8003a8a: 011b lsls r3, r3, #4 + 8003a8c: 697a ldr r2, [r7, #20] + 8003a8e: 4313 orrs r3, r2 + 8003a90: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; - 8003a0e: 68fb ldr r3, [r7, #12] - 8003a10: 693a ldr r2, [r7, #16] - 8003a12: 619a str r2, [r3, #24] + 8003a92: 68fb ldr r3, [r7, #12] + 8003a94: 693a ldr r2, [r7, #16] + 8003a96: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; - 8003a14: 68fb ldr r3, [r7, #12] - 8003a16: 697a ldr r2, [r7, #20] - 8003a18: 621a str r2, [r3, #32] + 8003a98: 68fb ldr r3, [r7, #12] + 8003a9a: 697a ldr r2, [r7, #20] + 8003a9c: 621a str r2, [r3, #32] } - 8003a1a: 46c0 nop @ (mov r8, r8) - 8003a1c: 46bd mov sp, r7 - 8003a1e: b006 add sp, #24 - 8003a20: bd80 pop {r7, pc} - 8003a22: 46c0 nop @ (mov r8, r8) - 8003a24: ffff0fff .word 0xffff0fff + 8003a9e: 46c0 nop @ (mov r8, r8) + 8003aa0: 46bd mov sp, r7 + 8003aa2: b006 add sp, #24 + 8003aa4: bd80 pop {r7, pc} + 8003aa6: 46c0 nop @ (mov r8, r8) + 8003aa8: ffff0fff .word 0xffff0fff -08003a28 : +08003aac : * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 * @arg TIM_TS_ETRF: External Trigger input * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { - 8003a28: b580 push {r7, lr} - 8003a2a: b084 sub sp, #16 - 8003a2c: af00 add r7, sp, #0 - 8003a2e: 6078 str r0, [r7, #4] - 8003a30: 6039 str r1, [r7, #0] + 8003aac: b580 push {r7, lr} + 8003aae: b084 sub sp, #16 + 8003ab0: af00 add r7, sp, #0 + 8003ab2: 6078 str r0, [r7, #4] + 8003ab4: 6039 str r1, [r7, #0] uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; - 8003a32: 687b ldr r3, [r7, #4] - 8003a34: 689b ldr r3, [r3, #8] - 8003a36: 60fb str r3, [r7, #12] + 8003ab6: 687b ldr r3, [r7, #4] + 8003ab8: 689b ldr r3, [r3, #8] + 8003aba: 60fb str r3, [r7, #12] /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; - 8003a38: 68fb ldr r3, [r7, #12] - 8003a3a: 4a08 ldr r2, [pc, #32] @ (8003a5c ) - 8003a3c: 4013 ands r3, r2 - 8003a3e: 60fb str r3, [r7, #12] + 8003abc: 68fb ldr r3, [r7, #12] + 8003abe: 4a08 ldr r2, [pc, #32] @ (8003ae0 ) + 8003ac0: 4013 ands r3, r2 + 8003ac2: 60fb str r3, [r7, #12] /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); - 8003a40: 683a ldr r2, [r7, #0] - 8003a42: 68fb ldr r3, [r7, #12] - 8003a44: 4313 orrs r3, r2 - 8003a46: 2207 movs r2, #7 - 8003a48: 4313 orrs r3, r2 - 8003a4a: 60fb str r3, [r7, #12] + 8003ac4: 683a ldr r2, [r7, #0] + 8003ac6: 68fb ldr r3, [r7, #12] + 8003ac8: 4313 orrs r3, r2 + 8003aca: 2207 movs r2, #7 + 8003acc: 4313 orrs r3, r2 + 8003ace: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; - 8003a4c: 687b ldr r3, [r7, #4] - 8003a4e: 68fa ldr r2, [r7, #12] - 8003a50: 609a str r2, [r3, #8] + 8003ad0: 687b ldr r3, [r7, #4] + 8003ad2: 68fa ldr r2, [r7, #12] + 8003ad4: 609a str r2, [r3, #8] } - 8003a52: 46c0 nop @ (mov r8, r8) - 8003a54: 46bd mov sp, r7 - 8003a56: b004 add sp, #16 - 8003a58: bd80 pop {r7, pc} - 8003a5a: 46c0 nop @ (mov r8, r8) - 8003a5c: ffcfff8f .word 0xffcfff8f + 8003ad6: 46c0 nop @ (mov r8, r8) + 8003ad8: 46bd mov sp, r7 + 8003ada: b004 add sp, #16 + 8003adc: bd80 pop {r7, pc} + 8003ade: 46c0 nop @ (mov r8, r8) + 8003ae0: ffcfff8f .word 0xffcfff8f -08003a60 : +08003ae4 : * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { - 8003a60: b580 push {r7, lr} - 8003a62: b086 sub sp, #24 - 8003a64: af00 add r7, sp, #0 - 8003a66: 60f8 str r0, [r7, #12] - 8003a68: 60b9 str r1, [r7, #8] - 8003a6a: 607a str r2, [r7, #4] - 8003a6c: 603b str r3, [r7, #0] + 8003ae4: b580 push {r7, lr} + 8003ae6: b086 sub sp, #24 + 8003ae8: af00 add r7, sp, #0 + 8003aea: 60f8 str r0, [r7, #12] + 8003aec: 60b9 str r1, [r7, #8] + 8003aee: 607a str r2, [r7, #4] + 8003af0: 603b str r3, [r7, #0] uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; - 8003a6e: 68fb ldr r3, [r7, #12] - 8003a70: 689b ldr r3, [r3, #8] - 8003a72: 617b str r3, [r7, #20] + 8003af2: 68fb ldr r3, [r7, #12] + 8003af4: 689b ldr r3, [r3, #8] + 8003af6: 617b str r3, [r7, #20] /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); - 8003a74: 697b ldr r3, [r7, #20] - 8003a76: 4a09 ldr r2, [pc, #36] @ (8003a9c ) - 8003a78: 4013 ands r3, r2 - 8003a7a: 617b str r3, [r7, #20] + 8003af8: 697b ldr r3, [r7, #20] + 8003afa: 4a09 ldr r2, [pc, #36] @ (8003b20 ) + 8003afc: 4013 ands r3, r2 + 8003afe: 617b str r3, [r7, #20] /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); - 8003a7c: 683b ldr r3, [r7, #0] - 8003a7e: 021a lsls r2, r3, #8 - 8003a80: 687b ldr r3, [r7, #4] - 8003a82: 431a orrs r2, r3 - 8003a84: 68bb ldr r3, [r7, #8] - 8003a86: 4313 orrs r3, r2 - 8003a88: 697a ldr r2, [r7, #20] - 8003a8a: 4313 orrs r3, r2 - 8003a8c: 617b str r3, [r7, #20] + 8003b00: 683b ldr r3, [r7, #0] + 8003b02: 021a lsls r2, r3, #8 + 8003b04: 687b ldr r3, [r7, #4] + 8003b06: 431a orrs r2, r3 + 8003b08: 68bb ldr r3, [r7, #8] + 8003b0a: 4313 orrs r3, r2 + 8003b0c: 697a ldr r2, [r7, #20] + 8003b0e: 4313 orrs r3, r2 + 8003b10: 617b str r3, [r7, #20] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; - 8003a8e: 68fb ldr r3, [r7, #12] - 8003a90: 697a ldr r2, [r7, #20] - 8003a92: 609a str r2, [r3, #8] + 8003b12: 68fb ldr r3, [r7, #12] + 8003b14: 697a ldr r2, [r7, #20] + 8003b16: 609a str r2, [r3, #8] } - 8003a94: 46c0 nop @ (mov r8, r8) - 8003a96: 46bd mov sp, r7 - 8003a98: b006 add sp, #24 - 8003a9a: bd80 pop {r7, pc} - 8003a9c: ffff00ff .word 0xffff00ff + 8003b18: 46c0 nop @ (mov r8, r8) + 8003b1a: 46bd mov sp, r7 + 8003b1c: b006 add sp, #24 + 8003b1e: bd80 pop {r7, pc} + 8003b20: ffff00ff .word 0xffff00ff -08003aa0 : +08003b24 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { - 8003aa0: b580 push {r7, lr} - 8003aa2: b084 sub sp, #16 - 8003aa4: af00 add r7, sp, #0 - 8003aa6: 6078 str r0, [r7, #4] - 8003aa8: 6039 str r1, [r7, #0] + 8003b24: b580 push {r7, lr} + 8003b26: b084 sub sp, #16 + 8003b28: af00 add r7, sp, #0 + 8003b2a: 6078 str r0, [r7, #4] + 8003b2c: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); - 8003aaa: 687b ldr r3, [r7, #4] - 8003aac: 223c movs r2, #60 @ 0x3c - 8003aae: 5c9b ldrb r3, [r3, r2] - 8003ab0: 2b01 cmp r3, #1 - 8003ab2: d101 bne.n 8003ab8 - 8003ab4: 2302 movs r3, #2 - 8003ab6: e050 b.n 8003b5a - 8003ab8: 687b ldr r3, [r7, #4] - 8003aba: 223c movs r2, #60 @ 0x3c - 8003abc: 2101 movs r1, #1 - 8003abe: 5499 strb r1, [r3, r2] + 8003b2e: 687b ldr r3, [r7, #4] + 8003b30: 223c movs r2, #60 @ 0x3c + 8003b32: 5c9b ldrb r3, [r3, r2] + 8003b34: 2b01 cmp r3, #1 + 8003b36: d101 bne.n 8003b3c + 8003b38: 2302 movs r3, #2 + 8003b3a: e050 b.n 8003bde + 8003b3c: 687b ldr r3, [r7, #4] + 8003b3e: 223c movs r2, #60 @ 0x3c + 8003b40: 2101 movs r1, #1 + 8003b42: 5499 strb r1, [r3, r2] /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; - 8003ac0: 687b ldr r3, [r7, #4] - 8003ac2: 223d movs r2, #61 @ 0x3d - 8003ac4: 2102 movs r1, #2 - 8003ac6: 5499 strb r1, [r3, r2] + 8003b44: 687b ldr r3, [r7, #4] + 8003b46: 223d movs r2, #61 @ 0x3d + 8003b48: 2102 movs r1, #2 + 8003b4a: 5499 strb r1, [r3, r2] /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; - 8003ac8: 687b ldr r3, [r7, #4] - 8003aca: 681b ldr r3, [r3, #0] - 8003acc: 685b ldr r3, [r3, #4] - 8003ace: 60fb str r3, [r7, #12] + 8003b4c: 687b ldr r3, [r7, #4] + 8003b4e: 681b ldr r3, [r3, #0] + 8003b50: 685b ldr r3, [r3, #4] + 8003b52: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; - 8003ad0: 687b ldr r3, [r7, #4] - 8003ad2: 681b ldr r3, [r3, #0] - 8003ad4: 689b ldr r3, [r3, #8] - 8003ad6: 60bb str r3, [r7, #8] + 8003b54: 687b ldr r3, [r7, #4] + 8003b56: 681b ldr r3, [r3, #0] + 8003b58: 689b ldr r3, [r3, #8] + 8003b5a: 60bb str r3, [r7, #8] /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) - 8003ad8: 687b ldr r3, [r7, #4] - 8003ada: 681b ldr r3, [r3, #0] - 8003adc: 4a21 ldr r2, [pc, #132] @ (8003b64 ) - 8003ade: 4293 cmp r3, r2 - 8003ae0: d108 bne.n 8003af4 + 8003b5c: 687b ldr r3, [r7, #4] + 8003b5e: 681b ldr r3, [r3, #0] + 8003b60: 4a21 ldr r2, [pc, #132] @ (8003be8 ) + 8003b62: 4293 cmp r3, r2 + 8003b64: d108 bne.n 8003b78 { /* Check the parameters */ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); /* Clear the MMS2 bits */ tmpcr2 &= ~TIM_CR2_MMS2; - 8003ae2: 68fb ldr r3, [r7, #12] - 8003ae4: 4a20 ldr r2, [pc, #128] @ (8003b68 ) - 8003ae6: 4013 ands r3, r2 - 8003ae8: 60fb str r3, [r7, #12] + 8003b66: 68fb ldr r3, [r7, #12] + 8003b68: 4a20 ldr r2, [pc, #128] @ (8003bec ) + 8003b6a: 4013 ands r3, r2 + 8003b6c: 60fb str r3, [r7, #12] /* Select the TRGO2 source*/ tmpcr2 |= sMasterConfig->MasterOutputTrigger2; - 8003aea: 683b ldr r3, [r7, #0] - 8003aec: 685b ldr r3, [r3, #4] - 8003aee: 68fa ldr r2, [r7, #12] - 8003af0: 4313 orrs r3, r2 - 8003af2: 60fb str r3, [r7, #12] + 8003b6e: 683b ldr r3, [r7, #0] + 8003b70: 685b ldr r3, [r3, #4] + 8003b72: 68fa ldr r2, [r7, #12] + 8003b74: 4313 orrs r3, r2 + 8003b76: 60fb str r3, [r7, #12] } /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; - 8003af4: 68fb ldr r3, [r7, #12] - 8003af6: 2270 movs r2, #112 @ 0x70 - 8003af8: 4393 bics r3, r2 - 8003afa: 60fb str r3, [r7, #12] + 8003b78: 68fb ldr r3, [r7, #12] + 8003b7a: 2270 movs r2, #112 @ 0x70 + 8003b7c: 4393 bics r3, r2 + 8003b7e: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; - 8003afc: 683b ldr r3, [r7, #0] - 8003afe: 681b ldr r3, [r3, #0] - 8003b00: 68fa ldr r2, [r7, #12] - 8003b02: 4313 orrs r3, r2 - 8003b04: 60fb str r3, [r7, #12] + 8003b80: 683b ldr r3, [r7, #0] + 8003b82: 681b ldr r3, [r3, #0] + 8003b84: 68fa ldr r2, [r7, #12] + 8003b86: 4313 orrs r3, r2 + 8003b88: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; - 8003b06: 687b ldr r3, [r7, #4] - 8003b08: 681b ldr r3, [r3, #0] - 8003b0a: 68fa ldr r2, [r7, #12] - 8003b0c: 605a str r2, [r3, #4] + 8003b8a: 687b ldr r3, [r7, #4] + 8003b8c: 681b ldr r3, [r3, #0] + 8003b8e: 68fa ldr r2, [r7, #12] + 8003b90: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - 8003b0e: 687b ldr r3, [r7, #4] - 8003b10: 681b ldr r3, [r3, #0] - 8003b12: 4a14 ldr r2, [pc, #80] @ (8003b64 ) - 8003b14: 4293 cmp r3, r2 - 8003b16: d00a beq.n 8003b2e - 8003b18: 687b ldr r3, [r7, #4] - 8003b1a: 681a ldr r2, [r3, #0] - 8003b1c: 2380 movs r3, #128 @ 0x80 - 8003b1e: 05db lsls r3, r3, #23 - 8003b20: 429a cmp r2, r3 - 8003b22: d004 beq.n 8003b2e - 8003b24: 687b ldr r3, [r7, #4] - 8003b26: 681b ldr r3, [r3, #0] - 8003b28: 4a10 ldr r2, [pc, #64] @ (8003b6c ) - 8003b2a: 4293 cmp r3, r2 - 8003b2c: d10c bne.n 8003b48 + 8003b92: 687b ldr r3, [r7, #4] + 8003b94: 681b ldr r3, [r3, #0] + 8003b96: 4a14 ldr r2, [pc, #80] @ (8003be8 ) + 8003b98: 4293 cmp r3, r2 + 8003b9a: d00a beq.n 8003bb2 + 8003b9c: 687b ldr r3, [r7, #4] + 8003b9e: 681a ldr r2, [r3, #0] + 8003ba0: 2380 movs r3, #128 @ 0x80 + 8003ba2: 05db lsls r3, r3, #23 + 8003ba4: 429a cmp r2, r3 + 8003ba6: d004 beq.n 8003bb2 + 8003ba8: 687b ldr r3, [r7, #4] + 8003baa: 681b ldr r3, [r3, #0] + 8003bac: 4a10 ldr r2, [pc, #64] @ (8003bf0 ) + 8003bae: 4293 cmp r3, r2 + 8003bb0: d10c bne.n 8003bcc { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; - 8003b2e: 68bb ldr r3, [r7, #8] - 8003b30: 2280 movs r2, #128 @ 0x80 - 8003b32: 4393 bics r3, r2 - 8003b34: 60bb str r3, [r7, #8] + 8003bb2: 68bb ldr r3, [r7, #8] + 8003bb4: 2280 movs r2, #128 @ 0x80 + 8003bb6: 4393 bics r3, r2 + 8003bb8: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; - 8003b36: 683b ldr r3, [r7, #0] - 8003b38: 689b ldr r3, [r3, #8] - 8003b3a: 68ba ldr r2, [r7, #8] - 8003b3c: 4313 orrs r3, r2 - 8003b3e: 60bb str r3, [r7, #8] + 8003bba: 683b ldr r3, [r7, #0] + 8003bbc: 689b ldr r3, [r3, #8] + 8003bbe: 68ba ldr r2, [r7, #8] + 8003bc0: 4313 orrs r3, r2 + 8003bc2: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; - 8003b40: 687b ldr r3, [r7, #4] - 8003b42: 681b ldr r3, [r3, #0] - 8003b44: 68ba ldr r2, [r7, #8] - 8003b46: 609a str r2, [r3, #8] + 8003bc4: 687b ldr r3, [r7, #4] + 8003bc6: 681b ldr r3, [r3, #0] + 8003bc8: 68ba ldr r2, [r7, #8] + 8003bca: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; - 8003b48: 687b ldr r3, [r7, #4] - 8003b4a: 223d movs r2, #61 @ 0x3d - 8003b4c: 2101 movs r1, #1 - 8003b4e: 5499 strb r1, [r3, r2] + 8003bcc: 687b ldr r3, [r7, #4] + 8003bce: 223d movs r2, #61 @ 0x3d + 8003bd0: 2101 movs r1, #1 + 8003bd2: 5499 strb r1, [r3, r2] __HAL_UNLOCK(htim); - 8003b50: 687b ldr r3, [r7, #4] - 8003b52: 223c movs r2, #60 @ 0x3c - 8003b54: 2100 movs r1, #0 - 8003b56: 5499 strb r1, [r3, r2] + 8003bd4: 687b ldr r3, [r7, #4] + 8003bd6: 223c movs r2, #60 @ 0x3c + 8003bd8: 2100 movs r1, #0 + 8003bda: 5499 strb r1, [r3, r2] return HAL_OK; - 8003b58: 2300 movs r3, #0 + 8003bdc: 2300 movs r3, #0 } - 8003b5a: 0018 movs r0, r3 - 8003b5c: 46bd mov sp, r7 - 8003b5e: b004 add sp, #16 - 8003b60: bd80 pop {r7, pc} - 8003b62: 46c0 nop @ (mov r8, r8) - 8003b64: 40012c00 .word 0x40012c00 - 8003b68: ff0fffff .word 0xff0fffff - 8003b6c: 40000400 .word 0x40000400 + 8003bde: 0018 movs r0, r3 + 8003be0: 46bd mov sp, r7 + 8003be2: b004 add sp, #16 + 8003be4: bd80 pop {r7, pc} + 8003be6: 46c0 nop @ (mov r8, r8) + 8003be8: 40012c00 .word 0x40012c00 + 8003bec: ff0fffff .word 0xff0fffff + 8003bf0: 40000400 .word 0x40000400 -08003b70 : +08003bf4 : * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) { - 8003b70: b580 push {r7, lr} - 8003b72: b084 sub sp, #16 - 8003b74: af00 add r7, sp, #0 - 8003b76: 6078 str r0, [r7, #4] - 8003b78: 6039 str r1, [r7, #0] + 8003bf4: b580 push {r7, lr} + 8003bf6: b084 sub sp, #16 + 8003bf8: af00 add r7, sp, #0 + 8003bfa: 6078 str r0, [r7, #4] + 8003bfc: 6039 str r1, [r7, #0] /* Keep this variable initialized to 0 as it is used to configure BDTR register */ uint32_t tmpbdtr = 0U; - 8003b7a: 2300 movs r3, #0 - 8003b7c: 60fb str r3, [r7, #12] + 8003bfe: 2300 movs r3, #0 + 8003c00: 60fb str r3, [r7, #12] assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); /* Check input state */ __HAL_LOCK(htim); - 8003b7e: 687b ldr r3, [r7, #4] - 8003b80: 223c movs r2, #60 @ 0x3c - 8003b82: 5c9b ldrb r3, [r3, r2] - 8003b84: 2b01 cmp r3, #1 - 8003b86: d101 bne.n 8003b8c - 8003b88: 2302 movs r3, #2 - 8003b8a: e06f b.n 8003c6c - 8003b8c: 687b ldr r3, [r7, #4] - 8003b8e: 223c movs r2, #60 @ 0x3c - 8003b90: 2101 movs r1, #1 - 8003b92: 5499 strb r1, [r3, r2] + 8003c02: 687b ldr r3, [r7, #4] + 8003c04: 223c movs r2, #60 @ 0x3c + 8003c06: 5c9b ldrb r3, [r3, r2] + 8003c08: 2b01 cmp r3, #1 + 8003c0a: d101 bne.n 8003c10 + 8003c0c: 2302 movs r3, #2 + 8003c0e: e06f b.n 8003cf0 + 8003c10: 687b ldr r3, [r7, #4] + 8003c12: 223c movs r2, #60 @ 0x3c + 8003c14: 2101 movs r1, #1 + 8003c16: 5499 strb r1, [r3, r2] /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ /* Set the BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); - 8003b94: 68fb ldr r3, [r7, #12] - 8003b96: 22ff movs r2, #255 @ 0xff - 8003b98: 4393 bics r3, r2 - 8003b9a: 001a movs r2, r3 - 8003b9c: 683b ldr r3, [r7, #0] - 8003b9e: 68db ldr r3, [r3, #12] - 8003ba0: 4313 orrs r3, r2 - 8003ba2: 60fb str r3, [r7, #12] + 8003c18: 68fb ldr r3, [r7, #12] + 8003c1a: 22ff movs r2, #255 @ 0xff + 8003c1c: 4393 bics r3, r2 + 8003c1e: 001a movs r2, r3 + 8003c20: 683b ldr r3, [r7, #0] + 8003c22: 68db ldr r3, [r3, #12] + 8003c24: 4313 orrs r3, r2 + 8003c26: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); - 8003ba4: 68fb ldr r3, [r7, #12] - 8003ba6: 4a33 ldr r2, [pc, #204] @ (8003c74 ) - 8003ba8: 401a ands r2, r3 - 8003baa: 683b ldr r3, [r7, #0] - 8003bac: 689b ldr r3, [r3, #8] - 8003bae: 4313 orrs r3, r2 - 8003bb0: 60fb str r3, [r7, #12] + 8003c28: 68fb ldr r3, [r7, #12] + 8003c2a: 4a33 ldr r2, [pc, #204] @ (8003cf8 ) + 8003c2c: 401a ands r2, r3 + 8003c2e: 683b ldr r3, [r7, #0] + 8003c30: 689b ldr r3, [r3, #8] + 8003c32: 4313 orrs r3, r2 + 8003c34: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); - 8003bb2: 68fb ldr r3, [r7, #12] - 8003bb4: 4a30 ldr r2, [pc, #192] @ (8003c78 ) - 8003bb6: 401a ands r2, r3 - 8003bb8: 683b ldr r3, [r7, #0] - 8003bba: 685b ldr r3, [r3, #4] - 8003bbc: 4313 orrs r3, r2 - 8003bbe: 60fb str r3, [r7, #12] + 8003c36: 68fb ldr r3, [r7, #12] + 8003c38: 4a30 ldr r2, [pc, #192] @ (8003cfc ) + 8003c3a: 401a ands r2, r3 + 8003c3c: 683b ldr r3, [r7, #0] + 8003c3e: 685b ldr r3, [r3, #4] + 8003c40: 4313 orrs r3, r2 + 8003c42: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); - 8003bc0: 68fb ldr r3, [r7, #12] - 8003bc2: 4a2e ldr r2, [pc, #184] @ (8003c7c ) - 8003bc4: 401a ands r2, r3 - 8003bc6: 683b ldr r3, [r7, #0] - 8003bc8: 681b ldr r3, [r3, #0] - 8003bca: 4313 orrs r3, r2 - 8003bcc: 60fb str r3, [r7, #12] + 8003c44: 68fb ldr r3, [r7, #12] + 8003c46: 4a2e ldr r2, [pc, #184] @ (8003d00 ) + 8003c48: 401a ands r2, r3 + 8003c4a: 683b ldr r3, [r7, #0] + 8003c4c: 681b ldr r3, [r3, #0] + 8003c4e: 4313 orrs r3, r2 + 8003c50: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); - 8003bce: 68fb ldr r3, [r7, #12] - 8003bd0: 4a2b ldr r2, [pc, #172] @ (8003c80 ) - 8003bd2: 401a ands r2, r3 - 8003bd4: 683b ldr r3, [r7, #0] - 8003bd6: 691b ldr r3, [r3, #16] - 8003bd8: 4313 orrs r3, r2 - 8003bda: 60fb str r3, [r7, #12] + 8003c52: 68fb ldr r3, [r7, #12] + 8003c54: 4a2b ldr r2, [pc, #172] @ (8003d04 ) + 8003c56: 401a ands r2, r3 + 8003c58: 683b ldr r3, [r7, #0] + 8003c5a: 691b ldr r3, [r3, #16] + 8003c5c: 4313 orrs r3, r2 + 8003c5e: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); - 8003bdc: 68fb ldr r3, [r7, #12] - 8003bde: 4a29 ldr r2, [pc, #164] @ (8003c84 ) - 8003be0: 401a ands r2, r3 - 8003be2: 683b ldr r3, [r7, #0] - 8003be4: 695b ldr r3, [r3, #20] - 8003be6: 4313 orrs r3, r2 - 8003be8: 60fb str r3, [r7, #12] + 8003c60: 68fb ldr r3, [r7, #12] + 8003c62: 4a29 ldr r2, [pc, #164] @ (8003d08 ) + 8003c64: 401a ands r2, r3 + 8003c66: 683b ldr r3, [r7, #0] + 8003c68: 695b ldr r3, [r3, #20] + 8003c6a: 4313 orrs r3, r2 + 8003c6c: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); - 8003bea: 68fb ldr r3, [r7, #12] - 8003bec: 4a26 ldr r2, [pc, #152] @ (8003c88 ) - 8003bee: 401a ands r2, r3 - 8003bf0: 683b ldr r3, [r7, #0] - 8003bf2: 6b1b ldr r3, [r3, #48] @ 0x30 - 8003bf4: 4313 orrs r3, r2 - 8003bf6: 60fb str r3, [r7, #12] + 8003c6e: 68fb ldr r3, [r7, #12] + 8003c70: 4a26 ldr r2, [pc, #152] @ (8003d0c ) + 8003c72: 401a ands r2, r3 + 8003c74: 683b ldr r3, [r7, #0] + 8003c76: 6b1b ldr r3, [r3, #48] @ 0x30 + 8003c78: 4313 orrs r3, r2 + 8003c7a: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); - 8003bf8: 68fb ldr r3, [r7, #12] - 8003bfa: 4a24 ldr r2, [pc, #144] @ (8003c8c ) - 8003bfc: 401a ands r2, r3 - 8003bfe: 683b ldr r3, [r7, #0] - 8003c00: 699b ldr r3, [r3, #24] - 8003c02: 041b lsls r3, r3, #16 - 8003c04: 4313 orrs r3, r2 - 8003c06: 60fb str r3, [r7, #12] + 8003c7c: 68fb ldr r3, [r7, #12] + 8003c7e: 4a24 ldr r2, [pc, #144] @ (8003d10 ) + 8003c80: 401a ands r2, r3 + 8003c82: 683b ldr r3, [r7, #0] + 8003c84: 699b ldr r3, [r3, #24] + 8003c86: 041b lsls r3, r3, #16 + 8003c88: 4313 orrs r3, r2 + 8003c8a: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); - 8003c08: 68fb ldr r3, [r7, #12] - 8003c0a: 4a21 ldr r2, [pc, #132] @ (8003c90 ) - 8003c0c: 401a ands r2, r3 - 8003c0e: 683b ldr r3, [r7, #0] - 8003c10: 69db ldr r3, [r3, #28] - 8003c12: 4313 orrs r3, r2 - 8003c14: 60fb str r3, [r7, #12] + 8003c8c: 68fb ldr r3, [r7, #12] + 8003c8e: 4a21 ldr r2, [pc, #132] @ (8003d14 ) + 8003c90: 401a ands r2, r3 + 8003c92: 683b ldr r3, [r7, #0] + 8003c94: 69db ldr r3, [r3, #28] + 8003c96: 4313 orrs r3, r2 + 8003c98: 60fb str r3, [r7, #12] if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) - 8003c16: 687b ldr r3, [r7, #4] - 8003c18: 681b ldr r3, [r3, #0] - 8003c1a: 4a1e ldr r2, [pc, #120] @ (8003c94 ) - 8003c1c: 4293 cmp r3, r2 - 8003c1e: d11c bne.n 8003c5a + 8003c9a: 687b ldr r3, [r7, #4] + 8003c9c: 681b ldr r3, [r3, #0] + 8003c9e: 4a1e ldr r2, [pc, #120] @ (8003d18 ) + 8003ca0: 4293 cmp r3, r2 + 8003ca2: d11c bne.n 8003cde assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); /* Set the BREAK2 input related BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); - 8003c20: 68fb ldr r3, [r7, #12] - 8003c22: 4a1d ldr r2, [pc, #116] @ (8003c98 ) - 8003c24: 401a ands r2, r3 - 8003c26: 683b ldr r3, [r7, #0] - 8003c28: 6a9b ldr r3, [r3, #40] @ 0x28 - 8003c2a: 051b lsls r3, r3, #20 - 8003c2c: 4313 orrs r3, r2 - 8003c2e: 60fb str r3, [r7, #12] + 8003ca4: 68fb ldr r3, [r7, #12] + 8003ca6: 4a1d ldr r2, [pc, #116] @ (8003d1c ) + 8003ca8: 401a ands r2, r3 + 8003caa: 683b ldr r3, [r7, #0] + 8003cac: 6a9b ldr r3, [r3, #40] @ 0x28 + 8003cae: 051b lsls r3, r3, #20 + 8003cb0: 4313 orrs r3, r2 + 8003cb2: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); - 8003c30: 68fb ldr r3, [r7, #12] - 8003c32: 4a1a ldr r2, [pc, #104] @ (8003c9c ) - 8003c34: 401a ands r2, r3 - 8003c36: 683b ldr r3, [r7, #0] - 8003c38: 6a1b ldr r3, [r3, #32] - 8003c3a: 4313 orrs r3, r2 - 8003c3c: 60fb str r3, [r7, #12] + 8003cb4: 68fb ldr r3, [r7, #12] + 8003cb6: 4a1a ldr r2, [pc, #104] @ (8003d20 ) + 8003cb8: 401a ands r2, r3 + 8003cba: 683b ldr r3, [r7, #0] + 8003cbc: 6a1b ldr r3, [r3, #32] + 8003cbe: 4313 orrs r3, r2 + 8003cc0: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); - 8003c3e: 68fb ldr r3, [r7, #12] - 8003c40: 4a17 ldr r2, [pc, #92] @ (8003ca0 ) - 8003c42: 401a ands r2, r3 - 8003c44: 683b ldr r3, [r7, #0] - 8003c46: 6a5b ldr r3, [r3, #36] @ 0x24 - 8003c48: 4313 orrs r3, r2 - 8003c4a: 60fb str r3, [r7, #12] + 8003cc2: 68fb ldr r3, [r7, #12] + 8003cc4: 4a17 ldr r2, [pc, #92] @ (8003d24 ) + 8003cc6: 401a ands r2, r3 + 8003cc8: 683b ldr r3, [r7, #0] + 8003cca: 6a5b ldr r3, [r3, #36] @ 0x24 + 8003ccc: 4313 orrs r3, r2 + 8003cce: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); - 8003c4c: 68fb ldr r3, [r7, #12] - 8003c4e: 4a15 ldr r2, [pc, #84] @ (8003ca4 ) - 8003c50: 401a ands r2, r3 - 8003c52: 683b ldr r3, [r7, #0] - 8003c54: 6adb ldr r3, [r3, #44] @ 0x2c - 8003c56: 4313 orrs r3, r2 - 8003c58: 60fb str r3, [r7, #12] + 8003cd0: 68fb ldr r3, [r7, #12] + 8003cd2: 4a15 ldr r2, [pc, #84] @ (8003d28 ) + 8003cd4: 401a ands r2, r3 + 8003cd6: 683b ldr r3, [r7, #0] + 8003cd8: 6adb ldr r3, [r3, #44] @ 0x2c + 8003cda: 4313 orrs r3, r2 + 8003cdc: 60fb str r3, [r7, #12] } /* Set TIMx_BDTR */ htim->Instance->BDTR = tmpbdtr; - 8003c5a: 687b ldr r3, [r7, #4] - 8003c5c: 681b ldr r3, [r3, #0] - 8003c5e: 68fa ldr r2, [r7, #12] - 8003c60: 645a str r2, [r3, #68] @ 0x44 + 8003cde: 687b ldr r3, [r7, #4] + 8003ce0: 681b ldr r3, [r3, #0] + 8003ce2: 68fa ldr r2, [r7, #12] + 8003ce4: 645a str r2, [r3, #68] @ 0x44 __HAL_UNLOCK(htim); - 8003c62: 687b ldr r3, [r7, #4] - 8003c64: 223c movs r2, #60 @ 0x3c - 8003c66: 2100 movs r1, #0 - 8003c68: 5499 strb r1, [r3, r2] + 8003ce6: 687b ldr r3, [r7, #4] + 8003ce8: 223c movs r2, #60 @ 0x3c + 8003cea: 2100 movs r1, #0 + 8003cec: 5499 strb r1, [r3, r2] return HAL_OK; - 8003c6a: 2300 movs r3, #0 + 8003cee: 2300 movs r3, #0 } - 8003c6c: 0018 movs r0, r3 - 8003c6e: 46bd mov sp, r7 - 8003c70: b004 add sp, #16 - 8003c72: bd80 pop {r7, pc} - 8003c74: fffffcff .word 0xfffffcff - 8003c78: fffffbff .word 0xfffffbff - 8003c7c: fffff7ff .word 0xfffff7ff - 8003c80: ffffefff .word 0xffffefff - 8003c84: ffffdfff .word 0xffffdfff - 8003c88: ffffbfff .word 0xffffbfff - 8003c8c: fff0ffff .word 0xfff0ffff - 8003c90: efffffff .word 0xefffffff - 8003c94: 40012c00 .word 0x40012c00 - 8003c98: ff0fffff .word 0xff0fffff - 8003c9c: feffffff .word 0xfeffffff - 8003ca0: fdffffff .word 0xfdffffff - 8003ca4: dfffffff .word 0xdfffffff + 8003cf0: 0018 movs r0, r3 + 8003cf2: 46bd mov sp, r7 + 8003cf4: b004 add sp, #16 + 8003cf6: bd80 pop {r7, pc} + 8003cf8: fffffcff .word 0xfffffcff + 8003cfc: fffffbff .word 0xfffffbff + 8003d00: fffff7ff .word 0xfffff7ff + 8003d04: ffffefff .word 0xffffefff + 8003d08: ffffdfff .word 0xffffdfff + 8003d0c: ffffbfff .word 0xffffbfff + 8003d10: fff0ffff .word 0xfff0ffff + 8003d14: efffffff .word 0xefffffff + 8003d18: 40012c00 .word 0x40012c00 + 8003d1c: ff0fffff .word 0xff0fffff + 8003d20: feffffff .word 0xfeffffff + 8003d24: fdffffff .word 0xfdffffff + 8003d28: dfffffff .word 0xdfffffff -08003ca8 : +08003d2c : * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { - 8003ca8: b580 push {r7, lr} - 8003caa: b082 sub sp, #8 - 8003cac: af00 add r7, sp, #0 - 8003cae: 6078 str r0, [r7, #4] + 8003d2c: b580 push {r7, lr} + 8003d2e: b082 sub sp, #8 + 8003d30: af00 add r7, sp, #0 + 8003d32: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } - 8003cb0: 46c0 nop @ (mov r8, r8) - 8003cb2: 46bd mov sp, r7 - 8003cb4: b002 add sp, #8 - 8003cb6: bd80 pop {r7, pc} + 8003d34: 46c0 nop @ (mov r8, r8) + 8003d36: 46bd mov sp, r7 + 8003d38: b002 add sp, #8 + 8003d3a: bd80 pop {r7, pc} -08003cb8 : +08003d3c : * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { - 8003cb8: b580 push {r7, lr} - 8003cba: b082 sub sp, #8 - 8003cbc: af00 add r7, sp, #0 - 8003cbe: 6078 str r0, [r7, #4] + 8003d3c: b580 push {r7, lr} + 8003d3e: b082 sub sp, #8 + 8003d40: af00 add r7, sp, #0 + 8003d42: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } - 8003cc0: 46c0 nop @ (mov r8, r8) - 8003cc2: 46bd mov sp, r7 - 8003cc4: b002 add sp, #8 - 8003cc6: bd80 pop {r7, pc} + 8003d44: 46c0 nop @ (mov r8, r8) + 8003d46: 46bd mov sp, r7 + 8003d48: b002 add sp, #8 + 8003d4a: bd80 pop {r7, pc} -08003cc8 : +08003d4c : * @brief Break2 detection callback in non blocking mode * @param htim: TIM handle * @retval None */ __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) { - 8003cc8: b580 push {r7, lr} - 8003cca: b082 sub sp, #8 - 8003ccc: af00 add r7, sp, #0 - 8003cce: 6078 str r0, [r7, #4] + 8003d4c: b580 push {r7, lr} + 8003d4e: b082 sub sp, #8 + 8003d50: af00 add r7, sp, #0 + 8003d52: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIMEx_Break2Callback could be implemented in the user file */ } - 8003cd0: 46c0 nop @ (mov r8, r8) - 8003cd2: 46bd mov sp, r7 - 8003cd4: b002 add sp, #8 - 8003cd6: bd80 pop {r7, pc} + 8003d54: 46c0 nop @ (mov r8, r8) + 8003d56: 46bd mov sp, r7 + 8003d58: b002 add sp, #8 + 8003d5a: bd80 pop {r7, pc} -08003cd8 : +08003d5c : * parameters in the UART_InitTypeDef and initialize the associated handle. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { - 8003cd8: b580 push {r7, lr} - 8003cda: b082 sub sp, #8 - 8003cdc: af00 add r7, sp, #0 - 8003cde: 6078 str r0, [r7, #4] + 8003d5c: b580 push {r7, lr} + 8003d5e: b082 sub sp, #8 + 8003d60: af00 add r7, sp, #0 + 8003d62: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) - 8003ce0: 687b ldr r3, [r7, #4] - 8003ce2: 2b00 cmp r3, #0 - 8003ce4: d101 bne.n 8003cea + 8003d64: 687b ldr r3, [r7, #4] + 8003d66: 2b00 cmp r3, #0 + 8003d68: d101 bne.n 8003d6e { return HAL_ERROR; - 8003ce6: 2301 movs r3, #1 - 8003ce8: e046 b.n 8003d78 + 8003d6a: 2301 movs r3, #1 + 8003d6c: e046 b.n 8003dfc { /* Check the parameters */ assert_param(IS_UART_INSTANCE(huart->Instance)); } if (huart->gState == HAL_UART_STATE_RESET) - 8003cea: 687b ldr r3, [r7, #4] - 8003cec: 2288 movs r2, #136 @ 0x88 - 8003cee: 589b ldr r3, [r3, r2] - 8003cf0: 2b00 cmp r3, #0 - 8003cf2: d107 bne.n 8003d04 + 8003d6e: 687b ldr r3, [r7, #4] + 8003d70: 2288 movs r2, #136 @ 0x88 + 8003d72: 589b ldr r3, [r3, r2] + 8003d74: 2b00 cmp r3, #0 + 8003d76: d107 bne.n 8003d88 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; - 8003cf4: 687b ldr r3, [r7, #4] - 8003cf6: 2284 movs r2, #132 @ 0x84 - 8003cf8: 2100 movs r1, #0 - 8003cfa: 5499 strb r1, [r3, r2] + 8003d78: 687b ldr r3, [r7, #4] + 8003d7a: 2284 movs r2, #132 @ 0x84 + 8003d7c: 2100 movs r1, #0 + 8003d7e: 5499 strb r1, [r3, r2] /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); - 8003cfc: 687b ldr r3, [r7, #4] - 8003cfe: 0018 movs r0, r3 - 8003d00: f7fd fb14 bl 800132c + 8003d80: 687b ldr r3, [r7, #4] + 8003d82: 0018 movs r0, r3 + 8003d84: f7fd fb14 bl 80013b0 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; - 8003d04: 687b ldr r3, [r7, #4] - 8003d06: 2288 movs r2, #136 @ 0x88 - 8003d08: 2124 movs r1, #36 @ 0x24 - 8003d0a: 5099 str r1, [r3, r2] + 8003d88: 687b ldr r3, [r7, #4] + 8003d8a: 2288 movs r2, #136 @ 0x88 + 8003d8c: 2124 movs r1, #36 @ 0x24 + 8003d8e: 5099 str r1, [r3, r2] __HAL_UART_DISABLE(huart); - 8003d0c: 687b ldr r3, [r7, #4] - 8003d0e: 681b ldr r3, [r3, #0] - 8003d10: 681a ldr r2, [r3, #0] - 8003d12: 687b ldr r3, [r7, #4] - 8003d14: 681b ldr r3, [r3, #0] - 8003d16: 2101 movs r1, #1 - 8003d18: 438a bics r2, r1 - 8003d1a: 601a str r2, [r3, #0] + 8003d90: 687b ldr r3, [r7, #4] + 8003d92: 681b ldr r3, [r3, #0] + 8003d94: 681a ldr r2, [r3, #0] + 8003d96: 687b ldr r3, [r7, #4] + 8003d98: 681b ldr r3, [r3, #0] + 8003d9a: 2101 movs r1, #1 + 8003d9c: 438a bics r2, r1 + 8003d9e: 601a str r2, [r3, #0] /* Perform advanced settings configuration */ /* For some items, configuration requires to be done prior TE and RE bits are set */ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - 8003d1c: 687b ldr r3, [r7, #4] - 8003d1e: 6a9b ldr r3, [r3, #40] @ 0x28 - 8003d20: 2b00 cmp r3, #0 - 8003d22: d003 beq.n 8003d2c + 8003da0: 687b ldr r3, [r7, #4] + 8003da2: 6a9b ldr r3, [r3, #40] @ 0x28 + 8003da4: 2b00 cmp r3, #0 + 8003da6: d003 beq.n 8003db0 { UART_AdvFeatureConfig(huart); - 8003d24: 687b ldr r3, [r7, #4] - 8003d26: 0018 movs r0, r3 - 8003d28: f000 f9c2 bl 80040b0 + 8003da8: 687b ldr r3, [r7, #4] + 8003daa: 0018 movs r0, r3 + 8003dac: f000 f9c2 bl 8004134 } /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) - 8003d2c: 687b ldr r3, [r7, #4] - 8003d2e: 0018 movs r0, r3 - 8003d30: f000 f840 bl 8003db4 - 8003d34: 0003 movs r3, r0 - 8003d36: 2b01 cmp r3, #1 - 8003d38: d101 bne.n 8003d3e + 8003db0: 687b ldr r3, [r7, #4] + 8003db2: 0018 movs r0, r3 + 8003db4: f000 f840 bl 8003e38 + 8003db8: 0003 movs r3, r0 + 8003dba: 2b01 cmp r3, #1 + 8003dbc: d101 bne.n 8003dc2 { return HAL_ERROR; - 8003d3a: 2301 movs r3, #1 - 8003d3c: e01c b.n 8003d78 + 8003dbe: 2301 movs r3, #1 + 8003dc0: e01c b.n 8003dfc } /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - 8003d3e: 687b ldr r3, [r7, #4] - 8003d40: 681b ldr r3, [r3, #0] - 8003d42: 685a ldr r2, [r3, #4] - 8003d44: 687b ldr r3, [r7, #4] - 8003d46: 681b ldr r3, [r3, #0] - 8003d48: 490d ldr r1, [pc, #52] @ (8003d80 ) - 8003d4a: 400a ands r2, r1 - 8003d4c: 605a str r2, [r3, #4] + 8003dc2: 687b ldr r3, [r7, #4] + 8003dc4: 681b ldr r3, [r3, #0] + 8003dc6: 685a ldr r2, [r3, #4] + 8003dc8: 687b ldr r3, [r7, #4] + 8003dca: 681b ldr r3, [r3, #0] + 8003dcc: 490d ldr r1, [pc, #52] @ (8003e04 ) + 8003dce: 400a ands r2, r1 + 8003dd0: 605a str r2, [r3, #4] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - 8003d4e: 687b ldr r3, [r7, #4] - 8003d50: 681b ldr r3, [r3, #0] - 8003d52: 689a ldr r2, [r3, #8] - 8003d54: 687b ldr r3, [r7, #4] - 8003d56: 681b ldr r3, [r3, #0] - 8003d58: 212a movs r1, #42 @ 0x2a - 8003d5a: 438a bics r2, r1 - 8003d5c: 609a str r2, [r3, #8] + 8003dd2: 687b ldr r3, [r7, #4] + 8003dd4: 681b ldr r3, [r3, #0] + 8003dd6: 689a ldr r2, [r3, #8] + 8003dd8: 687b ldr r3, [r7, #4] + 8003dda: 681b ldr r3, [r3, #0] + 8003ddc: 212a movs r1, #42 @ 0x2a + 8003dde: 438a bics r2, r1 + 8003de0: 609a str r2, [r3, #8] __HAL_UART_ENABLE(huart); - 8003d5e: 687b ldr r3, [r7, #4] - 8003d60: 681b ldr r3, [r3, #0] - 8003d62: 681a ldr r2, [r3, #0] - 8003d64: 687b ldr r3, [r7, #4] - 8003d66: 681b ldr r3, [r3, #0] - 8003d68: 2101 movs r1, #1 - 8003d6a: 430a orrs r2, r1 - 8003d6c: 601a str r2, [r3, #0] + 8003de2: 687b ldr r3, [r7, #4] + 8003de4: 681b ldr r3, [r3, #0] + 8003de6: 681a ldr r2, [r3, #0] + 8003de8: 687b ldr r3, [r7, #4] + 8003dea: 681b ldr r3, [r3, #0] + 8003dec: 2101 movs r1, #1 + 8003dee: 430a orrs r2, r1 + 8003df0: 601a str r2, [r3, #0] /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); - 8003d6e: 687b ldr r3, [r7, #4] - 8003d70: 0018 movs r0, r3 - 8003d72: f000 fa51 bl 8004218 - 8003d76: 0003 movs r3, r0 + 8003df2: 687b ldr r3, [r7, #4] + 8003df4: 0018 movs r0, r3 + 8003df6: f000 fa51 bl 800429c + 8003dfa: 0003 movs r3, r0 } - 8003d78: 0018 movs r0, r3 - 8003d7a: 46bd mov sp, r7 - 8003d7c: b002 add sp, #8 - 8003d7e: bd80 pop {r7, pc} - 8003d80: ffffb7ff .word 0xffffb7ff + 8003dfc: 0018 movs r0, r3 + 8003dfe: 46bd mov sp, r7 + 8003e00: b002 add sp, #8 + 8003e02: bd80 pop {r7, pc} + 8003e04: ffffb7ff .word 0xffffb7ff -08003d84 : +08003e08 : * @brief Rx Transfer completed callback. * @param huart UART handle. * @retval None */ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { - 8003d84: b580 push {r7, lr} - 8003d86: b082 sub sp, #8 - 8003d88: af00 add r7, sp, #0 - 8003d8a: 6078 str r0, [r7, #4] + 8003e08: b580 push {r7, lr} + 8003e0a: b082 sub sp, #8 + 8003e0c: af00 add r7, sp, #0 + 8003e0e: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_RxCpltCallback can be implemented in the user file. */ } - 8003d8c: 46c0 nop @ (mov r8, r8) - 8003d8e: 46bd mov sp, r7 - 8003d90: b002 add sp, #8 - 8003d92: bd80 pop {r7, pc} + 8003e10: 46c0 nop @ (mov r8, r8) + 8003e12: 46bd mov sp, r7 + 8003e14: b002 add sp, #8 + 8003e16: bd80 pop {r7, pc} -08003d94 : +08003e18 : * @brief Rx Half Transfer completed callback. * @param huart UART handle. * @retval None */ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) { - 8003d94: b580 push {r7, lr} - 8003d96: b082 sub sp, #8 - 8003d98: af00 add r7, sp, #0 - 8003d9a: 6078 str r0, [r7, #4] + 8003e18: b580 push {r7, lr} + 8003e1a: b082 sub sp, #8 + 8003e1c: af00 add r7, sp, #0 + 8003e1e: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_RxHalfCpltCallback can be implemented in the user file. */ } - 8003d9c: 46c0 nop @ (mov r8, r8) - 8003d9e: 46bd mov sp, r7 - 8003da0: b002 add sp, #8 - 8003da2: bd80 pop {r7, pc} + 8003e20: 46c0 nop @ (mov r8, r8) + 8003e22: 46bd mov sp, r7 + 8003e24: b002 add sp, #8 + 8003e26: bd80 pop {r7, pc} -08003da4 : +08003e28 : * @brief UART error callback. * @param huart UART handle. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { - 8003da4: b580 push {r7, lr} - 8003da6: b082 sub sp, #8 - 8003da8: af00 add r7, sp, #0 - 8003daa: 6078 str r0, [r7, #4] + 8003e28: b580 push {r7, lr} + 8003e2a: b082 sub sp, #8 + 8003e2c: af00 add r7, sp, #0 + 8003e2e: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_ErrorCallback can be implemented in the user file. */ } - 8003dac: 46c0 nop @ (mov r8, r8) - 8003dae: 46bd mov sp, r7 - 8003db0: b002 add sp, #8 - 8003db2: bd80 pop {r7, pc} + 8003e30: 46c0 nop @ (mov r8, r8) + 8003e32: 46bd mov sp, r7 + 8003e34: b002 add sp, #8 + 8003e36: bd80 pop {r7, pc} -08003db4 : +08003e38 : * @brief Configure the UART peripheral. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { - 8003db4: b580 push {r7, lr} - 8003db6: b088 sub sp, #32 - 8003db8: af00 add r7, sp, #0 - 8003dba: 6078 str r0, [r7, #4] + 8003e38: b580 push {r7, lr} + 8003e3a: b088 sub sp, #32 + 8003e3c: af00 add r7, sp, #0 + 8003e3e: 6078 str r0, [r7, #4] uint32_t tmpreg; uint16_t brrtemp; UART_ClockSourceTypeDef clocksource; uint32_t usartdiv; HAL_StatusTypeDef ret = HAL_OK; - 8003dbc: 231e movs r3, #30 - 8003dbe: 18fb adds r3, r7, r3 - 8003dc0: 2200 movs r2, #0 - 8003dc2: 701a strb r2, [r3, #0] + 8003e40: 231e movs r3, #30 + 8003e42: 18fb adds r3, r7, r3 + 8003e44: 2200 movs r2, #0 + 8003e46: 701a strb r2, [r3, #0] * the UART Word Length, Parity, Mode and oversampling: * set the M bits according to huart->Init.WordLength value * set PCE and PS bits according to huart->Init.Parity value * set TE and RE bits according to huart->Init.Mode value * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; - 8003dc4: 687b ldr r3, [r7, #4] - 8003dc6: 689a ldr r2, [r3, #8] - 8003dc8: 687b ldr r3, [r7, #4] - 8003dca: 691b ldr r3, [r3, #16] - 8003dcc: 431a orrs r2, r3 - 8003dce: 687b ldr r3, [r7, #4] - 8003dd0: 695b ldr r3, [r3, #20] - 8003dd2: 431a orrs r2, r3 - 8003dd4: 687b ldr r3, [r7, #4] - 8003dd6: 69db ldr r3, [r3, #28] - 8003dd8: 4313 orrs r3, r2 - 8003dda: 617b str r3, [r7, #20] + 8003e48: 687b ldr r3, [r7, #4] + 8003e4a: 689a ldr r2, [r3, #8] + 8003e4c: 687b ldr r3, [r7, #4] + 8003e4e: 691b ldr r3, [r3, #16] + 8003e50: 431a orrs r2, r3 + 8003e52: 687b ldr r3, [r7, #4] + 8003e54: 695b ldr r3, [r3, #20] + 8003e56: 431a orrs r2, r3 + 8003e58: 687b ldr r3, [r7, #4] + 8003e5a: 69db ldr r3, [r3, #28] + 8003e5c: 4313 orrs r3, r2 + 8003e5e: 617b str r3, [r7, #20] MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); - 8003ddc: 687b ldr r3, [r7, #4] - 8003dde: 681b ldr r3, [r3, #0] - 8003de0: 681b ldr r3, [r3, #0] - 8003de2: 4aab ldr r2, [pc, #684] @ (8004090 ) - 8003de4: 4013 ands r3, r2 - 8003de6: 0019 movs r1, r3 - 8003de8: 687b ldr r3, [r7, #4] - 8003dea: 681b ldr r3, [r3, #0] - 8003dec: 697a ldr r2, [r7, #20] - 8003dee: 430a orrs r2, r1 - 8003df0: 601a str r2, [r3, #0] + 8003e60: 687b ldr r3, [r7, #4] + 8003e62: 681b ldr r3, [r3, #0] + 8003e64: 681b ldr r3, [r3, #0] + 8003e66: 4aab ldr r2, [pc, #684] @ (8004114 ) + 8003e68: 4013 ands r3, r2 + 8003e6a: 0019 movs r1, r3 + 8003e6c: 687b ldr r3, [r7, #4] + 8003e6e: 681b ldr r3, [r3, #0] + 8003e70: 697a ldr r2, [r7, #20] + 8003e72: 430a orrs r2, r1 + 8003e74: 601a str r2, [r3, #0] /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); - 8003df2: 687b ldr r3, [r7, #4] - 8003df4: 681b ldr r3, [r3, #0] - 8003df6: 685b ldr r3, [r3, #4] - 8003df8: 4aa6 ldr r2, [pc, #664] @ (8004094 ) - 8003dfa: 4013 ands r3, r2 - 8003dfc: 0019 movs r1, r3 - 8003dfe: 687b ldr r3, [r7, #4] - 8003e00: 68da ldr r2, [r3, #12] - 8003e02: 687b ldr r3, [r7, #4] - 8003e04: 681b ldr r3, [r3, #0] - 8003e06: 430a orrs r2, r1 - 8003e08: 605a str r2, [r3, #4] + 8003e76: 687b ldr r3, [r7, #4] + 8003e78: 681b ldr r3, [r3, #0] + 8003e7a: 685b ldr r3, [r3, #4] + 8003e7c: 4aa6 ldr r2, [pc, #664] @ (8004118 ) + 8003e7e: 4013 ands r3, r2 + 8003e80: 0019 movs r1, r3 + 8003e82: 687b ldr r3, [r7, #4] + 8003e84: 68da ldr r2, [r3, #12] + 8003e86: 687b ldr r3, [r7, #4] + 8003e88: 681b ldr r3, [r3, #0] + 8003e8a: 430a orrs r2, r1 + 8003e8c: 605a str r2, [r3, #4] /* Configure * - UART HardWare Flow Control: set CTSE and RTSE bits according * to huart->Init.HwFlowCtl value * - one-bit sampling method versus three samples' majority rule according * to huart->Init.OneBitSampling (not applicable to LPUART) */ tmpreg = (uint32_t)huart->Init.HwFlowCtl; - 8003e0a: 687b ldr r3, [r7, #4] - 8003e0c: 699b ldr r3, [r3, #24] - 8003e0e: 617b str r3, [r7, #20] + 8003e8e: 687b ldr r3, [r7, #4] + 8003e90: 699b ldr r3, [r3, #24] + 8003e92: 617b str r3, [r7, #20] tmpreg |= huart->Init.OneBitSampling; - 8003e10: 687b ldr r3, [r7, #4] - 8003e12: 6a1b ldr r3, [r3, #32] - 8003e14: 697a ldr r2, [r7, #20] - 8003e16: 4313 orrs r3, r2 - 8003e18: 617b str r3, [r7, #20] + 8003e94: 687b ldr r3, [r7, #4] + 8003e96: 6a1b ldr r3, [r3, #32] + 8003e98: 697a ldr r2, [r7, #20] + 8003e9a: 4313 orrs r3, r2 + 8003e9c: 617b str r3, [r7, #20] MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); - 8003e1a: 687b ldr r3, [r7, #4] - 8003e1c: 681b ldr r3, [r3, #0] - 8003e1e: 689b ldr r3, [r3, #8] - 8003e20: 4a9d ldr r2, [pc, #628] @ (8004098 ) - 8003e22: 4013 ands r3, r2 - 8003e24: 0019 movs r1, r3 - 8003e26: 687b ldr r3, [r7, #4] - 8003e28: 681b ldr r3, [r3, #0] - 8003e2a: 697a ldr r2, [r7, #20] - 8003e2c: 430a orrs r2, r1 - 8003e2e: 609a str r2, [r3, #8] + 8003e9e: 687b ldr r3, [r7, #4] + 8003ea0: 681b ldr r3, [r3, #0] + 8003ea2: 689b ldr r3, [r3, #8] + 8003ea4: 4a9d ldr r2, [pc, #628] @ (800411c ) + 8003ea6: 4013 ands r3, r2 + 8003ea8: 0019 movs r1, r3 + 8003eaa: 687b ldr r3, [r7, #4] + 8003eac: 681b ldr r3, [r3, #0] + 8003eae: 697a ldr r2, [r7, #20] + 8003eb0: 430a orrs r2, r1 + 8003eb2: 609a str r2, [r3, #8] /*-------------------------- USART PRESC Configuration -----------------------*/ /* Configure * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); - 8003e30: 687b ldr r3, [r7, #4] - 8003e32: 681b ldr r3, [r3, #0] - 8003e34: 6adb ldr r3, [r3, #44] @ 0x2c - 8003e36: 220f movs r2, #15 - 8003e38: 4393 bics r3, r2 - 8003e3a: 0019 movs r1, r3 - 8003e3c: 687b ldr r3, [r7, #4] - 8003e3e: 6a5a ldr r2, [r3, #36] @ 0x24 - 8003e40: 687b ldr r3, [r7, #4] - 8003e42: 681b ldr r3, [r3, #0] - 8003e44: 430a orrs r2, r1 - 8003e46: 62da str r2, [r3, #44] @ 0x2c + 8003eb4: 687b ldr r3, [r7, #4] + 8003eb6: 681b ldr r3, [r3, #0] + 8003eb8: 6adb ldr r3, [r3, #44] @ 0x2c + 8003eba: 220f movs r2, #15 + 8003ebc: 4393 bics r3, r2 + 8003ebe: 0019 movs r1, r3 + 8003ec0: 687b ldr r3, [r7, #4] + 8003ec2: 6a5a ldr r2, [r3, #36] @ 0x24 + 8003ec4: 687b ldr r3, [r7, #4] + 8003ec6: 681b ldr r3, [r3, #0] + 8003ec8: 430a orrs r2, r1 + 8003eca: 62da str r2, [r3, #44] @ 0x2c /*-------------------------- USART BRR Configuration -----------------------*/ UART_GETCLOCKSOURCE(huart, clocksource); - 8003e48: 687b ldr r3, [r7, #4] - 8003e4a: 681b ldr r3, [r3, #0] - 8003e4c: 4a93 ldr r2, [pc, #588] @ (800409c ) - 8003e4e: 4293 cmp r3, r2 - 8003e50: d127 bne.n 8003ea2 - 8003e52: 4b93 ldr r3, [pc, #588] @ (80040a0 ) - 8003e54: 6d5b ldr r3, [r3, #84] @ 0x54 - 8003e56: 2203 movs r2, #3 - 8003e58: 4013 ands r3, r2 - 8003e5a: 2b03 cmp r3, #3 - 8003e5c: d017 beq.n 8003e8e - 8003e5e: d81b bhi.n 8003e98 - 8003e60: 2b02 cmp r3, #2 - 8003e62: d00a beq.n 8003e7a - 8003e64: d818 bhi.n 8003e98 - 8003e66: 2b00 cmp r3, #0 - 8003e68: d002 beq.n 8003e70 - 8003e6a: 2b01 cmp r3, #1 - 8003e6c: d00a beq.n 8003e84 - 8003e6e: e013 b.n 8003e98 - 8003e70: 231f movs r3, #31 - 8003e72: 18fb adds r3, r7, r3 - 8003e74: 2200 movs r2, #0 - 8003e76: 701a strb r2, [r3, #0] - 8003e78: e021 b.n 8003ebe - 8003e7a: 231f movs r3, #31 - 8003e7c: 18fb adds r3, r7, r3 - 8003e7e: 2202 movs r2, #2 - 8003e80: 701a strb r2, [r3, #0] - 8003e82: e01c b.n 8003ebe - 8003e84: 231f movs r3, #31 - 8003e86: 18fb adds r3, r7, r3 - 8003e88: 2204 movs r2, #4 - 8003e8a: 701a strb r2, [r3, #0] - 8003e8c: e017 b.n 8003ebe - 8003e8e: 231f movs r3, #31 - 8003e90: 18fb adds r3, r7, r3 - 8003e92: 2208 movs r2, #8 - 8003e94: 701a strb r2, [r3, #0] - 8003e96: e012 b.n 8003ebe - 8003e98: 231f movs r3, #31 - 8003e9a: 18fb adds r3, r7, r3 - 8003e9c: 2210 movs r2, #16 - 8003e9e: 701a strb r2, [r3, #0] - 8003ea0: e00d b.n 8003ebe - 8003ea2: 687b ldr r3, [r7, #4] - 8003ea4: 681b ldr r3, [r3, #0] - 8003ea6: 4a7f ldr r2, [pc, #508] @ (80040a4 ) - 8003ea8: 4293 cmp r3, r2 - 8003eaa: d104 bne.n 8003eb6 - 8003eac: 231f movs r3, #31 - 8003eae: 18fb adds r3, r7, r3 - 8003eb0: 2200 movs r2, #0 - 8003eb2: 701a strb r2, [r3, #0] - 8003eb4: e003 b.n 8003ebe - 8003eb6: 231f movs r3, #31 - 8003eb8: 18fb adds r3, r7, r3 - 8003eba: 2210 movs r2, #16 - 8003ebc: 701a strb r2, [r3, #0] + 8003ecc: 687b ldr r3, [r7, #4] + 8003ece: 681b ldr r3, [r3, #0] + 8003ed0: 4a93 ldr r2, [pc, #588] @ (8004120 ) + 8003ed2: 4293 cmp r3, r2 + 8003ed4: d127 bne.n 8003f26 + 8003ed6: 4b93 ldr r3, [pc, #588] @ (8004124 ) + 8003ed8: 6d5b ldr r3, [r3, #84] @ 0x54 + 8003eda: 2203 movs r2, #3 + 8003edc: 4013 ands r3, r2 + 8003ede: 2b03 cmp r3, #3 + 8003ee0: d017 beq.n 8003f12 + 8003ee2: d81b bhi.n 8003f1c + 8003ee4: 2b02 cmp r3, #2 + 8003ee6: d00a beq.n 8003efe + 8003ee8: d818 bhi.n 8003f1c + 8003eea: 2b00 cmp r3, #0 + 8003eec: d002 beq.n 8003ef4 + 8003eee: 2b01 cmp r3, #1 + 8003ef0: d00a beq.n 8003f08 + 8003ef2: e013 b.n 8003f1c + 8003ef4: 231f movs r3, #31 + 8003ef6: 18fb adds r3, r7, r3 + 8003ef8: 2200 movs r2, #0 + 8003efa: 701a strb r2, [r3, #0] + 8003efc: e021 b.n 8003f42 + 8003efe: 231f movs r3, #31 + 8003f00: 18fb adds r3, r7, r3 + 8003f02: 2202 movs r2, #2 + 8003f04: 701a strb r2, [r3, #0] + 8003f06: e01c b.n 8003f42 + 8003f08: 231f movs r3, #31 + 8003f0a: 18fb adds r3, r7, r3 + 8003f0c: 2204 movs r2, #4 + 8003f0e: 701a strb r2, [r3, #0] + 8003f10: e017 b.n 8003f42 + 8003f12: 231f movs r3, #31 + 8003f14: 18fb adds r3, r7, r3 + 8003f16: 2208 movs r2, #8 + 8003f18: 701a strb r2, [r3, #0] + 8003f1a: e012 b.n 8003f42 + 8003f1c: 231f movs r3, #31 + 8003f1e: 18fb adds r3, r7, r3 + 8003f20: 2210 movs r2, #16 + 8003f22: 701a strb r2, [r3, #0] + 8003f24: e00d b.n 8003f42 + 8003f26: 687b ldr r3, [r7, #4] + 8003f28: 681b ldr r3, [r3, #0] + 8003f2a: 4a7f ldr r2, [pc, #508] @ (8004128 ) + 8003f2c: 4293 cmp r3, r2 + 8003f2e: d104 bne.n 8003f3a + 8003f30: 231f movs r3, #31 + 8003f32: 18fb adds r3, r7, r3 + 8003f34: 2200 movs r2, #0 + 8003f36: 701a strb r2, [r3, #0] + 8003f38: e003 b.n 8003f42 + 8003f3a: 231f movs r3, #31 + 8003f3c: 18fb adds r3, r7, r3 + 8003f3e: 2210 movs r2, #16 + 8003f40: 701a strb r2, [r3, #0] if (huart->Init.OverSampling == UART_OVERSAMPLING_8) - 8003ebe: 687b ldr r3, [r7, #4] - 8003ec0: 69da ldr r2, [r3, #28] - 8003ec2: 2380 movs r3, #128 @ 0x80 - 8003ec4: 021b lsls r3, r3, #8 - 8003ec6: 429a cmp r2, r3 - 8003ec8: d000 beq.n 8003ecc - 8003eca: e06f b.n 8003fac + 8003f42: 687b ldr r3, [r7, #4] + 8003f44: 69da ldr r2, [r3, #28] + 8003f46: 2380 movs r3, #128 @ 0x80 + 8003f48: 021b lsls r3, r3, #8 + 8003f4a: 429a cmp r2, r3 + 8003f4c: d000 beq.n 8003f50 + 8003f4e: e06f b.n 8004030 { switch (clocksource) - 8003ecc: 231f movs r3, #31 - 8003ece: 18fb adds r3, r7, r3 - 8003ed0: 781b ldrb r3, [r3, #0] - 8003ed2: 2b08 cmp r3, #8 - 8003ed4: d01f beq.n 8003f16 - 8003ed6: dc22 bgt.n 8003f1e - 8003ed8: 2b04 cmp r3, #4 - 8003eda: d017 beq.n 8003f0c - 8003edc: dc1f bgt.n 8003f1e - 8003ede: 2b00 cmp r3, #0 - 8003ee0: d002 beq.n 8003ee8 - 8003ee2: 2b02 cmp r3, #2 - 8003ee4: d005 beq.n 8003ef2 - 8003ee6: e01a b.n 8003f1e + 8003f50: 231f movs r3, #31 + 8003f52: 18fb adds r3, r7, r3 + 8003f54: 781b ldrb r3, [r3, #0] + 8003f56: 2b08 cmp r3, #8 + 8003f58: d01f beq.n 8003f9a + 8003f5a: dc22 bgt.n 8003fa2 + 8003f5c: 2b04 cmp r3, #4 + 8003f5e: d017 beq.n 8003f90 + 8003f60: dc1f bgt.n 8003fa2 + 8003f62: 2b00 cmp r3, #0 + 8003f64: d002 beq.n 8003f6c + 8003f66: 2b02 cmp r3, #2 + 8003f68: d005 beq.n 8003f76 + 8003f6a: e01a b.n 8003fa2 { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); - 8003ee8: f7fe fcc4 bl 8002874 - 8003eec: 0003 movs r3, r0 - 8003eee: 61bb str r3, [r7, #24] + 8003f6c: f7fe fcc4 bl 80028f8 + 8003f70: 0003 movs r3, r0 + 8003f72: 61bb str r3, [r7, #24] break; - 8003ef0: e01c b.n 8003f2c + 8003f74: e01c b.n 8003fb0 case UART_CLOCKSOURCE_HSI: pclk = (HSI_VALUE / ((__HAL_RCC_GET_HSIKER_DIVIDER() >> RCC_CR_HSIKERDIV_Pos) + 1U)); - 8003ef2: 4b6b ldr r3, [pc, #428] @ (80040a0 ) - 8003ef4: 681b ldr r3, [r3, #0] - 8003ef6: 095b lsrs r3, r3, #5 - 8003ef8: 2207 movs r2, #7 - 8003efa: 4013 ands r3, r2 - 8003efc: 3301 adds r3, #1 - 8003efe: 0019 movs r1, r3 - 8003f00: 4869 ldr r0, [pc, #420] @ (80040a8 ) - 8003f02: f7fc f901 bl 8000108 <__udivsi3> - 8003f06: 0003 movs r3, r0 - 8003f08: 61bb str r3, [r7, #24] + 8003f76: 4b6b ldr r3, [pc, #428] @ (8004124 ) + 8003f78: 681b ldr r3, [r3, #0] + 8003f7a: 095b lsrs r3, r3, #5 + 8003f7c: 2207 movs r2, #7 + 8003f7e: 4013 ands r3, r2 + 8003f80: 3301 adds r3, #1 + 8003f82: 0019 movs r1, r3 + 8003f84: 4869 ldr r0, [pc, #420] @ (800412c ) + 8003f86: f7fc f8bf bl 8000108 <__udivsi3> + 8003f8a: 0003 movs r3, r0 + 8003f8c: 61bb str r3, [r7, #24] break; - 8003f0a: e00f b.n 8003f2c + 8003f8e: e00f b.n 8003fb0 case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); - 8003f0c: f7fe fc44 bl 8002798 - 8003f10: 0003 movs r3, r0 - 8003f12: 61bb str r3, [r7, #24] + 8003f90: f7fe fc44 bl 800281c + 8003f94: 0003 movs r3, r0 + 8003f96: 61bb str r3, [r7, #24] break; - 8003f14: e00a b.n 8003f2c + 8003f98: e00a b.n 8003fb0 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; - 8003f16: 2380 movs r3, #128 @ 0x80 - 8003f18: 021b lsls r3, r3, #8 - 8003f1a: 61bb str r3, [r7, #24] + 8003f9a: 2380 movs r3, #128 @ 0x80 + 8003f9c: 021b lsls r3, r3, #8 + 8003f9e: 61bb str r3, [r7, #24] break; - 8003f1c: e006 b.n 8003f2c + 8003fa0: e006 b.n 8003fb0 default: pclk = 0U; - 8003f1e: 2300 movs r3, #0 - 8003f20: 61bb str r3, [r7, #24] + 8003fa2: 2300 movs r3, #0 + 8003fa4: 61bb str r3, [r7, #24] ret = HAL_ERROR; - 8003f22: 231e movs r3, #30 - 8003f24: 18fb adds r3, r7, r3 - 8003f26: 2201 movs r2, #1 - 8003f28: 701a strb r2, [r3, #0] + 8003fa6: 231e movs r3, #30 + 8003fa8: 18fb adds r3, r7, r3 + 8003faa: 2201 movs r2, #1 + 8003fac: 701a strb r2, [r3, #0] break; - 8003f2a: 46c0 nop @ (mov r8, r8) + 8003fae: 46c0 nop @ (mov r8, r8) } /* USARTDIV must be greater than or equal to 0d16 */ if (pclk != 0U) - 8003f2c: 69bb ldr r3, [r7, #24] - 8003f2e: 2b00 cmp r3, #0 - 8003f30: d100 bne.n 8003f34 - 8003f32: e097 b.n 8004064 + 8003fb0: 69bb ldr r3, [r7, #24] + 8003fb2: 2b00 cmp r3, #0 + 8003fb4: d100 bne.n 8003fb8 + 8003fb6: e097 b.n 80040e8 { usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); - 8003f34: 687b ldr r3, [r7, #4] - 8003f36: 6a5a ldr r2, [r3, #36] @ 0x24 - 8003f38: 4b5c ldr r3, [pc, #368] @ (80040ac ) - 8003f3a: 0052 lsls r2, r2, #1 - 8003f3c: 5ad3 ldrh r3, [r2, r3] - 8003f3e: 0019 movs r1, r3 - 8003f40: 69b8 ldr r0, [r7, #24] - 8003f42: f7fc f8e1 bl 8000108 <__udivsi3> - 8003f46: 0003 movs r3, r0 - 8003f48: 005a lsls r2, r3, #1 - 8003f4a: 687b ldr r3, [r7, #4] - 8003f4c: 685b ldr r3, [r3, #4] - 8003f4e: 085b lsrs r3, r3, #1 - 8003f50: 18d2 adds r2, r2, r3 - 8003f52: 687b ldr r3, [r7, #4] - 8003f54: 685b ldr r3, [r3, #4] - 8003f56: 0019 movs r1, r3 - 8003f58: 0010 movs r0, r2 - 8003f5a: f7fc f8d5 bl 8000108 <__udivsi3> - 8003f5e: 0003 movs r3, r0 - 8003f60: 613b str r3, [r7, #16] + 8003fb8: 687b ldr r3, [r7, #4] + 8003fba: 6a5a ldr r2, [r3, #36] @ 0x24 + 8003fbc: 4b5c ldr r3, [pc, #368] @ (8004130 ) + 8003fbe: 0052 lsls r2, r2, #1 + 8003fc0: 5ad3 ldrh r3, [r2, r3] + 8003fc2: 0019 movs r1, r3 + 8003fc4: 69b8 ldr r0, [r7, #24] + 8003fc6: f7fc f89f bl 8000108 <__udivsi3> + 8003fca: 0003 movs r3, r0 + 8003fcc: 005a lsls r2, r3, #1 + 8003fce: 687b ldr r3, [r7, #4] + 8003fd0: 685b ldr r3, [r3, #4] + 8003fd2: 085b lsrs r3, r3, #1 + 8003fd4: 18d2 adds r2, r2, r3 + 8003fd6: 687b ldr r3, [r7, #4] + 8003fd8: 685b ldr r3, [r3, #4] + 8003fda: 0019 movs r1, r3 + 8003fdc: 0010 movs r0, r2 + 8003fde: f7fc f893 bl 8000108 <__udivsi3> + 8003fe2: 0003 movs r3, r0 + 8003fe4: 613b str r3, [r7, #16] if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) - 8003f62: 693b ldr r3, [r7, #16] - 8003f64: 2b0f cmp r3, #15 - 8003f66: d91c bls.n 8003fa2 - 8003f68: 693a ldr r2, [r7, #16] - 8003f6a: 2380 movs r3, #128 @ 0x80 - 8003f6c: 025b lsls r3, r3, #9 - 8003f6e: 429a cmp r2, r3 - 8003f70: d217 bcs.n 8003fa2 + 8003fe6: 693b ldr r3, [r7, #16] + 8003fe8: 2b0f cmp r3, #15 + 8003fea: d91c bls.n 8004026 + 8003fec: 693a ldr r2, [r7, #16] + 8003fee: 2380 movs r3, #128 @ 0x80 + 8003ff0: 025b lsls r3, r3, #9 + 8003ff2: 429a cmp r2, r3 + 8003ff4: d217 bcs.n 8004026 { brrtemp = (uint16_t)(usartdiv & 0xFFF0U); - 8003f72: 693b ldr r3, [r7, #16] - 8003f74: b29a uxth r2, r3 - 8003f76: 200e movs r0, #14 - 8003f78: 183b adds r3, r7, r0 - 8003f7a: 210f movs r1, #15 - 8003f7c: 438a bics r2, r1 - 8003f7e: 801a strh r2, [r3, #0] + 8003ff6: 693b ldr r3, [r7, #16] + 8003ff8: b29a uxth r2, r3 + 8003ffa: 200e movs r0, #14 + 8003ffc: 183b adds r3, r7, r0 + 8003ffe: 210f movs r1, #15 + 8004000: 438a bics r2, r1 + 8004002: 801a strh r2, [r3, #0] brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); - 8003f80: 693b ldr r3, [r7, #16] - 8003f82: 085b lsrs r3, r3, #1 - 8003f84: b29b uxth r3, r3 - 8003f86: 2207 movs r2, #7 - 8003f88: 4013 ands r3, r2 - 8003f8a: b299 uxth r1, r3 - 8003f8c: 183b adds r3, r7, r0 - 8003f8e: 183a adds r2, r7, r0 - 8003f90: 8812 ldrh r2, [r2, #0] - 8003f92: 430a orrs r2, r1 - 8003f94: 801a strh r2, [r3, #0] + 8004004: 693b ldr r3, [r7, #16] + 8004006: 085b lsrs r3, r3, #1 + 8004008: b29b uxth r3, r3 + 800400a: 2207 movs r2, #7 + 800400c: 4013 ands r3, r2 + 800400e: b299 uxth r1, r3 + 8004010: 183b adds r3, r7, r0 + 8004012: 183a adds r2, r7, r0 + 8004014: 8812 ldrh r2, [r2, #0] + 8004016: 430a orrs r2, r1 + 8004018: 801a strh r2, [r3, #0] huart->Instance->BRR = brrtemp; - 8003f96: 687b ldr r3, [r7, #4] - 8003f98: 681b ldr r3, [r3, #0] - 8003f9a: 183a adds r2, r7, r0 - 8003f9c: 8812 ldrh r2, [r2, #0] - 8003f9e: 60da str r2, [r3, #12] - 8003fa0: e060 b.n 8004064 + 800401a: 687b ldr r3, [r7, #4] + 800401c: 681b ldr r3, [r3, #0] + 800401e: 183a adds r2, r7, r0 + 8004020: 8812 ldrh r2, [r2, #0] + 8004022: 60da str r2, [r3, #12] + 8004024: e060 b.n 80040e8 } else { ret = HAL_ERROR; - 8003fa2: 231e movs r3, #30 - 8003fa4: 18fb adds r3, r7, r3 - 8003fa6: 2201 movs r2, #1 - 8003fa8: 701a strb r2, [r3, #0] - 8003faa: e05b b.n 8004064 + 8004026: 231e movs r3, #30 + 8004028: 18fb adds r3, r7, r3 + 800402a: 2201 movs r2, #1 + 800402c: 701a strb r2, [r3, #0] + 800402e: e05b b.n 80040e8 } } } else { switch (clocksource) - 8003fac: 231f movs r3, #31 - 8003fae: 18fb adds r3, r7, r3 - 8003fb0: 781b ldrb r3, [r3, #0] - 8003fb2: 2b08 cmp r3, #8 - 8003fb4: d01f beq.n 8003ff6 - 8003fb6: dc22 bgt.n 8003ffe - 8003fb8: 2b04 cmp r3, #4 - 8003fba: d017 beq.n 8003fec - 8003fbc: dc1f bgt.n 8003ffe - 8003fbe: 2b00 cmp r3, #0 - 8003fc0: d002 beq.n 8003fc8 - 8003fc2: 2b02 cmp r3, #2 - 8003fc4: d005 beq.n 8003fd2 - 8003fc6: e01a b.n 8003ffe + 8004030: 231f movs r3, #31 + 8004032: 18fb adds r3, r7, r3 + 8004034: 781b ldrb r3, [r3, #0] + 8004036: 2b08 cmp r3, #8 + 8004038: d01f beq.n 800407a + 800403a: dc22 bgt.n 8004082 + 800403c: 2b04 cmp r3, #4 + 800403e: d017 beq.n 8004070 + 8004040: dc1f bgt.n 8004082 + 8004042: 2b00 cmp r3, #0 + 8004044: d002 beq.n 800404c + 8004046: 2b02 cmp r3, #2 + 8004048: d005 beq.n 8004056 + 800404a: e01a b.n 8004082 { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); - 8003fc8: f7fe fc54 bl 8002874 - 8003fcc: 0003 movs r3, r0 - 8003fce: 61bb str r3, [r7, #24] + 800404c: f7fe fc54 bl 80028f8 + 8004050: 0003 movs r3, r0 + 8004052: 61bb str r3, [r7, #24] break; - 8003fd0: e01c b.n 800400c + 8004054: e01c b.n 8004090 case UART_CLOCKSOURCE_HSI: pclk = (HSI_VALUE / ((__HAL_RCC_GET_HSIKER_DIVIDER() >> RCC_CR_HSIKERDIV_Pos) + 1U)); - 8003fd2: 4b33 ldr r3, [pc, #204] @ (80040a0 ) - 8003fd4: 681b ldr r3, [r3, #0] - 8003fd6: 095b lsrs r3, r3, #5 - 8003fd8: 2207 movs r2, #7 - 8003fda: 4013 ands r3, r2 - 8003fdc: 3301 adds r3, #1 - 8003fde: 0019 movs r1, r3 - 8003fe0: 4831 ldr r0, [pc, #196] @ (80040a8 ) - 8003fe2: f7fc f891 bl 8000108 <__udivsi3> - 8003fe6: 0003 movs r3, r0 - 8003fe8: 61bb str r3, [r7, #24] + 8004056: 4b33 ldr r3, [pc, #204] @ (8004124 ) + 8004058: 681b ldr r3, [r3, #0] + 800405a: 095b lsrs r3, r3, #5 + 800405c: 2207 movs r2, #7 + 800405e: 4013 ands r3, r2 + 8004060: 3301 adds r3, #1 + 8004062: 0019 movs r1, r3 + 8004064: 4831 ldr r0, [pc, #196] @ (800412c ) + 8004066: f7fc f84f bl 8000108 <__udivsi3> + 800406a: 0003 movs r3, r0 + 800406c: 61bb str r3, [r7, #24] break; - 8003fea: e00f b.n 800400c + 800406e: e00f b.n 8004090 case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); - 8003fec: f7fe fbd4 bl 8002798 - 8003ff0: 0003 movs r3, r0 - 8003ff2: 61bb str r3, [r7, #24] + 8004070: f7fe fbd4 bl 800281c + 8004074: 0003 movs r3, r0 + 8004076: 61bb str r3, [r7, #24] break; - 8003ff4: e00a b.n 800400c + 8004078: e00a b.n 8004090 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; - 8003ff6: 2380 movs r3, #128 @ 0x80 - 8003ff8: 021b lsls r3, r3, #8 - 8003ffa: 61bb str r3, [r7, #24] + 800407a: 2380 movs r3, #128 @ 0x80 + 800407c: 021b lsls r3, r3, #8 + 800407e: 61bb str r3, [r7, #24] break; - 8003ffc: e006 b.n 800400c + 8004080: e006 b.n 8004090 default: pclk = 0U; - 8003ffe: 2300 movs r3, #0 - 8004000: 61bb str r3, [r7, #24] + 8004082: 2300 movs r3, #0 + 8004084: 61bb str r3, [r7, #24] ret = HAL_ERROR; - 8004002: 231e movs r3, #30 - 8004004: 18fb adds r3, r7, r3 - 8004006: 2201 movs r2, #1 - 8004008: 701a strb r2, [r3, #0] + 8004086: 231e movs r3, #30 + 8004088: 18fb adds r3, r7, r3 + 800408a: 2201 movs r2, #1 + 800408c: 701a strb r2, [r3, #0] break; - 800400a: 46c0 nop @ (mov r8, r8) + 800408e: 46c0 nop @ (mov r8, r8) } if (pclk != 0U) - 800400c: 69bb ldr r3, [r7, #24] - 800400e: 2b00 cmp r3, #0 - 8004010: d028 beq.n 8004064 + 8004090: 69bb ldr r3, [r7, #24] + 8004092: 2b00 cmp r3, #0 + 8004094: d028 beq.n 80040e8 { /* USARTDIV must be greater than or equal to 0d16 */ usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); - 8004012: 687b ldr r3, [r7, #4] - 8004014: 6a5a ldr r2, [r3, #36] @ 0x24 - 8004016: 4b25 ldr r3, [pc, #148] @ (80040ac ) - 8004018: 0052 lsls r2, r2, #1 - 800401a: 5ad3 ldrh r3, [r2, r3] - 800401c: 0019 movs r1, r3 - 800401e: 69b8 ldr r0, [r7, #24] - 8004020: f7fc f872 bl 8000108 <__udivsi3> - 8004024: 0003 movs r3, r0 - 8004026: 001a movs r2, r3 - 8004028: 687b ldr r3, [r7, #4] - 800402a: 685b ldr r3, [r3, #4] - 800402c: 085b lsrs r3, r3, #1 - 800402e: 18d2 adds r2, r2, r3 - 8004030: 687b ldr r3, [r7, #4] - 8004032: 685b ldr r3, [r3, #4] - 8004034: 0019 movs r1, r3 - 8004036: 0010 movs r0, r2 - 8004038: f7fc f866 bl 8000108 <__udivsi3> - 800403c: 0003 movs r3, r0 - 800403e: 613b str r3, [r7, #16] + 8004096: 687b ldr r3, [r7, #4] + 8004098: 6a5a ldr r2, [r3, #36] @ 0x24 + 800409a: 4b25 ldr r3, [pc, #148] @ (8004130 ) + 800409c: 0052 lsls r2, r2, #1 + 800409e: 5ad3 ldrh r3, [r2, r3] + 80040a0: 0019 movs r1, r3 + 80040a2: 69b8 ldr r0, [r7, #24] + 80040a4: f7fc f830 bl 8000108 <__udivsi3> + 80040a8: 0003 movs r3, r0 + 80040aa: 001a movs r2, r3 + 80040ac: 687b ldr r3, [r7, #4] + 80040ae: 685b ldr r3, [r3, #4] + 80040b0: 085b lsrs r3, r3, #1 + 80040b2: 18d2 adds r2, r2, r3 + 80040b4: 687b ldr r3, [r7, #4] + 80040b6: 685b ldr r3, [r3, #4] + 80040b8: 0019 movs r1, r3 + 80040ba: 0010 movs r0, r2 + 80040bc: f7fc f824 bl 8000108 <__udivsi3> + 80040c0: 0003 movs r3, r0 + 80040c2: 613b str r3, [r7, #16] if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) - 8004040: 693b ldr r3, [r7, #16] - 8004042: 2b0f cmp r3, #15 - 8004044: d90a bls.n 800405c - 8004046: 693a ldr r2, [r7, #16] - 8004048: 2380 movs r3, #128 @ 0x80 - 800404a: 025b lsls r3, r3, #9 - 800404c: 429a cmp r2, r3 - 800404e: d205 bcs.n 800405c + 80040c4: 693b ldr r3, [r7, #16] + 80040c6: 2b0f cmp r3, #15 + 80040c8: d90a bls.n 80040e0 + 80040ca: 693a ldr r2, [r7, #16] + 80040cc: 2380 movs r3, #128 @ 0x80 + 80040ce: 025b lsls r3, r3, #9 + 80040d0: 429a cmp r2, r3 + 80040d2: d205 bcs.n 80040e0 { huart->Instance->BRR = (uint16_t)usartdiv; - 8004050: 693b ldr r3, [r7, #16] - 8004052: b29a uxth r2, r3 - 8004054: 687b ldr r3, [r7, #4] - 8004056: 681b ldr r3, [r3, #0] - 8004058: 60da str r2, [r3, #12] - 800405a: e003 b.n 8004064 + 80040d4: 693b ldr r3, [r7, #16] + 80040d6: b29a uxth r2, r3 + 80040d8: 687b ldr r3, [r7, #4] + 80040da: 681b ldr r3, [r3, #0] + 80040dc: 60da str r2, [r3, #12] + 80040de: e003 b.n 80040e8 } else { ret = HAL_ERROR; - 800405c: 231e movs r3, #30 - 800405e: 18fb adds r3, r7, r3 - 8004060: 2201 movs r2, #1 - 8004062: 701a strb r2, [r3, #0] + 80040e0: 231e movs r3, #30 + 80040e2: 18fb adds r3, r7, r3 + 80040e4: 2201 movs r2, #1 + 80040e6: 701a strb r2, [r3, #0] } } } /* Initialize the number of data to process during RX/TX ISR execution */ huart->NbTxDataToProcess = 1; - 8004064: 687b ldr r3, [r7, #4] - 8004066: 226a movs r2, #106 @ 0x6a - 8004068: 2101 movs r1, #1 - 800406a: 5299 strh r1, [r3, r2] + 80040e8: 687b ldr r3, [r7, #4] + 80040ea: 226a movs r2, #106 @ 0x6a + 80040ec: 2101 movs r1, #1 + 80040ee: 5299 strh r1, [r3, r2] huart->NbRxDataToProcess = 1; - 800406c: 687b ldr r3, [r7, #4] - 800406e: 2268 movs r2, #104 @ 0x68 - 8004070: 2101 movs r1, #1 - 8004072: 5299 strh r1, [r3, r2] + 80040f0: 687b ldr r3, [r7, #4] + 80040f2: 2268 movs r2, #104 @ 0x68 + 80040f4: 2101 movs r1, #1 + 80040f6: 5299 strh r1, [r3, r2] /* Clear ISR function pointers */ huart->RxISR = NULL; - 8004074: 687b ldr r3, [r7, #4] - 8004076: 2200 movs r2, #0 - 8004078: 675a str r2, [r3, #116] @ 0x74 + 80040f8: 687b ldr r3, [r7, #4] + 80040fa: 2200 movs r2, #0 + 80040fc: 675a str r2, [r3, #116] @ 0x74 huart->TxISR = NULL; - 800407a: 687b ldr r3, [r7, #4] - 800407c: 2200 movs r2, #0 - 800407e: 679a str r2, [r3, #120] @ 0x78 + 80040fe: 687b ldr r3, [r7, #4] + 8004100: 2200 movs r2, #0 + 8004102: 679a str r2, [r3, #120] @ 0x78 return ret; - 8004080: 231e movs r3, #30 - 8004082: 18fb adds r3, r7, r3 - 8004084: 781b ldrb r3, [r3, #0] + 8004104: 231e movs r3, #30 + 8004106: 18fb adds r3, r7, r3 + 8004108: 781b ldrb r3, [r3, #0] } - 8004086: 0018 movs r0, r3 - 8004088: 46bd mov sp, r7 - 800408a: b008 add sp, #32 - 800408c: bd80 pop {r7, pc} - 800408e: 46c0 nop @ (mov r8, r8) - 8004090: cfff69f3 .word 0xcfff69f3 - 8004094: ffffcfff .word 0xffffcfff - 8004098: 11fff4ff .word 0x11fff4ff - 800409c: 40013800 .word 0x40013800 - 80040a0: 40021000 .word 0x40021000 - 80040a4: 40004400 .word 0x40004400 - 80040a8: 02dc6c00 .word 0x02dc6c00 - 80040ac: 08004e70 .word 0x08004e70 + 800410a: 0018 movs r0, r3 + 800410c: 46bd mov sp, r7 + 800410e: b008 add sp, #32 + 8004110: bd80 pop {r7, pc} + 8004112: 46c0 nop @ (mov r8, r8) + 8004114: cfff69f3 .word 0xcfff69f3 + 8004118: ffffcfff .word 0xffffcfff + 800411c: 11fff4ff .word 0x11fff4ff + 8004120: 40013800 .word 0x40013800 + 8004124: 40021000 .word 0x40021000 + 8004128: 40004400 .word 0x40004400 + 800412c: 02dc6c00 .word 0x02dc6c00 + 8004130: 08004ef4 .word 0x08004ef4 -080040b0 : +08004134 : * @brief Configure the UART peripheral advanced features. * @param huart UART handle. * @retval None */ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) { - 80040b0: b580 push {r7, lr} - 80040b2: b082 sub sp, #8 - 80040b4: af00 add r7, sp, #0 - 80040b6: 6078 str r0, [r7, #4] + 8004134: b580 push {r7, lr} + 8004136: b082 sub sp, #8 + 8004138: af00 add r7, sp, #0 + 800413a: 6078 str r0, [r7, #4] /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); /* if required, configure RX/TX pins swap */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) - 80040b8: 687b ldr r3, [r7, #4] - 80040ba: 6a9b ldr r3, [r3, #40] @ 0x28 - 80040bc: 2208 movs r2, #8 - 80040be: 4013 ands r3, r2 - 80040c0: d00b beq.n 80040da + 800413c: 687b ldr r3, [r7, #4] + 800413e: 6a9b ldr r3, [r3, #40] @ 0x28 + 8004140: 2208 movs r2, #8 + 8004142: 4013 ands r3, r2 + 8004144: d00b beq.n 800415e { assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); - 80040c2: 687b ldr r3, [r7, #4] - 80040c4: 681b ldr r3, [r3, #0] - 80040c6: 685b ldr r3, [r3, #4] - 80040c8: 4a4a ldr r2, [pc, #296] @ (80041f4 ) - 80040ca: 4013 ands r3, r2 - 80040cc: 0019 movs r1, r3 - 80040ce: 687b ldr r3, [r7, #4] - 80040d0: 6b9a ldr r2, [r3, #56] @ 0x38 - 80040d2: 687b ldr r3, [r7, #4] - 80040d4: 681b ldr r3, [r3, #0] - 80040d6: 430a orrs r2, r1 - 80040d8: 605a str r2, [r3, #4] + 8004146: 687b ldr r3, [r7, #4] + 8004148: 681b ldr r3, [r3, #0] + 800414a: 685b ldr r3, [r3, #4] + 800414c: 4a4a ldr r2, [pc, #296] @ (8004278 ) + 800414e: 4013 ands r3, r2 + 8004150: 0019 movs r1, r3 + 8004152: 687b ldr r3, [r7, #4] + 8004154: 6b9a ldr r2, [r3, #56] @ 0x38 + 8004156: 687b ldr r3, [r7, #4] + 8004158: 681b ldr r3, [r3, #0] + 800415a: 430a orrs r2, r1 + 800415c: 605a str r2, [r3, #4] } /* if required, configure TX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) - 80040da: 687b ldr r3, [r7, #4] - 80040dc: 6a9b ldr r3, [r3, #40] @ 0x28 - 80040de: 2201 movs r2, #1 - 80040e0: 4013 ands r3, r2 - 80040e2: d00b beq.n 80040fc + 800415e: 687b ldr r3, [r7, #4] + 8004160: 6a9b ldr r3, [r3, #40] @ 0x28 + 8004162: 2201 movs r2, #1 + 8004164: 4013 ands r3, r2 + 8004166: d00b beq.n 8004180 { assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); - 80040e4: 687b ldr r3, [r7, #4] - 80040e6: 681b ldr r3, [r3, #0] - 80040e8: 685b ldr r3, [r3, #4] - 80040ea: 4a43 ldr r2, [pc, #268] @ (80041f8 ) - 80040ec: 4013 ands r3, r2 - 80040ee: 0019 movs r1, r3 - 80040f0: 687b ldr r3, [r7, #4] - 80040f2: 6ada ldr r2, [r3, #44] @ 0x2c - 80040f4: 687b ldr r3, [r7, #4] - 80040f6: 681b ldr r3, [r3, #0] - 80040f8: 430a orrs r2, r1 - 80040fa: 605a str r2, [r3, #4] + 8004168: 687b ldr r3, [r7, #4] + 800416a: 681b ldr r3, [r3, #0] + 800416c: 685b ldr r3, [r3, #4] + 800416e: 4a43 ldr r2, [pc, #268] @ (800427c ) + 8004170: 4013 ands r3, r2 + 8004172: 0019 movs r1, r3 + 8004174: 687b ldr r3, [r7, #4] + 8004176: 6ada ldr r2, [r3, #44] @ 0x2c + 8004178: 687b ldr r3, [r7, #4] + 800417a: 681b ldr r3, [r3, #0] + 800417c: 430a orrs r2, r1 + 800417e: 605a str r2, [r3, #4] } /* if required, configure RX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) - 80040fc: 687b ldr r3, [r7, #4] - 80040fe: 6a9b ldr r3, [r3, #40] @ 0x28 - 8004100: 2202 movs r2, #2 - 8004102: 4013 ands r3, r2 - 8004104: d00b beq.n 800411e + 8004180: 687b ldr r3, [r7, #4] + 8004182: 6a9b ldr r3, [r3, #40] @ 0x28 + 8004184: 2202 movs r2, #2 + 8004186: 4013 ands r3, r2 + 8004188: d00b beq.n 80041a2 { assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); - 8004106: 687b ldr r3, [r7, #4] - 8004108: 681b ldr r3, [r3, #0] - 800410a: 685b ldr r3, [r3, #4] - 800410c: 4a3b ldr r2, [pc, #236] @ (80041fc ) - 800410e: 4013 ands r3, r2 - 8004110: 0019 movs r1, r3 - 8004112: 687b ldr r3, [r7, #4] - 8004114: 6b1a ldr r2, [r3, #48] @ 0x30 - 8004116: 687b ldr r3, [r7, #4] - 8004118: 681b ldr r3, [r3, #0] - 800411a: 430a orrs r2, r1 - 800411c: 605a str r2, [r3, #4] + 800418a: 687b ldr r3, [r7, #4] + 800418c: 681b ldr r3, [r3, #0] + 800418e: 685b ldr r3, [r3, #4] + 8004190: 4a3b ldr r2, [pc, #236] @ (8004280 ) + 8004192: 4013 ands r3, r2 + 8004194: 0019 movs r1, r3 + 8004196: 687b ldr r3, [r7, #4] + 8004198: 6b1a ldr r2, [r3, #48] @ 0x30 + 800419a: 687b ldr r3, [r7, #4] + 800419c: 681b ldr r3, [r3, #0] + 800419e: 430a orrs r2, r1 + 80041a0: 605a str r2, [r3, #4] } /* if required, configure data inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) - 800411e: 687b ldr r3, [r7, #4] - 8004120: 6a9b ldr r3, [r3, #40] @ 0x28 - 8004122: 2204 movs r2, #4 - 8004124: 4013 ands r3, r2 - 8004126: d00b beq.n 8004140 + 80041a2: 687b ldr r3, [r7, #4] + 80041a4: 6a9b ldr r3, [r3, #40] @ 0x28 + 80041a6: 2204 movs r2, #4 + 80041a8: 4013 ands r3, r2 + 80041aa: d00b beq.n 80041c4 { assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); - 8004128: 687b ldr r3, [r7, #4] - 800412a: 681b ldr r3, [r3, #0] - 800412c: 685b ldr r3, [r3, #4] - 800412e: 4a34 ldr r2, [pc, #208] @ (8004200 ) - 8004130: 4013 ands r3, r2 - 8004132: 0019 movs r1, r3 - 8004134: 687b ldr r3, [r7, #4] - 8004136: 6b5a ldr r2, [r3, #52] @ 0x34 - 8004138: 687b ldr r3, [r7, #4] - 800413a: 681b ldr r3, [r3, #0] - 800413c: 430a orrs r2, r1 - 800413e: 605a str r2, [r3, #4] + 80041ac: 687b ldr r3, [r7, #4] + 80041ae: 681b ldr r3, [r3, #0] + 80041b0: 685b ldr r3, [r3, #4] + 80041b2: 4a34 ldr r2, [pc, #208] @ (8004284 ) + 80041b4: 4013 ands r3, r2 + 80041b6: 0019 movs r1, r3 + 80041b8: 687b ldr r3, [r7, #4] + 80041ba: 6b5a ldr r2, [r3, #52] @ 0x34 + 80041bc: 687b ldr r3, [r7, #4] + 80041be: 681b ldr r3, [r3, #0] + 80041c0: 430a orrs r2, r1 + 80041c2: 605a str r2, [r3, #4] } /* if required, configure RX overrun detection disabling */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) - 8004140: 687b ldr r3, [r7, #4] - 8004142: 6a9b ldr r3, [r3, #40] @ 0x28 - 8004144: 2210 movs r2, #16 - 8004146: 4013 ands r3, r2 - 8004148: d00b beq.n 8004162 + 80041c4: 687b ldr r3, [r7, #4] + 80041c6: 6a9b ldr r3, [r3, #40] @ 0x28 + 80041c8: 2210 movs r2, #16 + 80041ca: 4013 ands r3, r2 + 80041cc: d00b beq.n 80041e6 { assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); - 800414a: 687b ldr r3, [r7, #4] - 800414c: 681b ldr r3, [r3, #0] - 800414e: 689b ldr r3, [r3, #8] - 8004150: 4a2c ldr r2, [pc, #176] @ (8004204 ) - 8004152: 4013 ands r3, r2 - 8004154: 0019 movs r1, r3 - 8004156: 687b ldr r3, [r7, #4] - 8004158: 6bda ldr r2, [r3, #60] @ 0x3c - 800415a: 687b ldr r3, [r7, #4] - 800415c: 681b ldr r3, [r3, #0] - 800415e: 430a orrs r2, r1 - 8004160: 609a str r2, [r3, #8] + 80041ce: 687b ldr r3, [r7, #4] + 80041d0: 681b ldr r3, [r3, #0] + 80041d2: 689b ldr r3, [r3, #8] + 80041d4: 4a2c ldr r2, [pc, #176] @ (8004288 ) + 80041d6: 4013 ands r3, r2 + 80041d8: 0019 movs r1, r3 + 80041da: 687b ldr r3, [r7, #4] + 80041dc: 6bda ldr r2, [r3, #60] @ 0x3c + 80041de: 687b ldr r3, [r7, #4] + 80041e0: 681b ldr r3, [r3, #0] + 80041e2: 430a orrs r2, r1 + 80041e4: 609a str r2, [r3, #8] } #if defined(HAL_DMA_MODULE_ENABLED) /* if required, configure DMA disabling on reception error */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) - 8004162: 687b ldr r3, [r7, #4] - 8004164: 6a9b ldr r3, [r3, #40] @ 0x28 - 8004166: 2220 movs r2, #32 - 8004168: 4013 ands r3, r2 - 800416a: d00b beq.n 8004184 + 80041e6: 687b ldr r3, [r7, #4] + 80041e8: 6a9b ldr r3, [r3, #40] @ 0x28 + 80041ea: 2220 movs r2, #32 + 80041ec: 4013 ands r3, r2 + 80041ee: d00b beq.n 8004208 { assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); - 800416c: 687b ldr r3, [r7, #4] - 800416e: 681b ldr r3, [r3, #0] - 8004170: 689b ldr r3, [r3, #8] - 8004172: 4a25 ldr r2, [pc, #148] @ (8004208 ) - 8004174: 4013 ands r3, r2 - 8004176: 0019 movs r1, r3 - 8004178: 687b ldr r3, [r7, #4] - 800417a: 6c1a ldr r2, [r3, #64] @ 0x40 - 800417c: 687b ldr r3, [r7, #4] - 800417e: 681b ldr r3, [r3, #0] - 8004180: 430a orrs r2, r1 - 8004182: 609a str r2, [r3, #8] + 80041f0: 687b ldr r3, [r7, #4] + 80041f2: 681b ldr r3, [r3, #0] + 80041f4: 689b ldr r3, [r3, #8] + 80041f6: 4a25 ldr r2, [pc, #148] @ (800428c ) + 80041f8: 4013 ands r3, r2 + 80041fa: 0019 movs r1, r3 + 80041fc: 687b ldr r3, [r7, #4] + 80041fe: 6c1a ldr r2, [r3, #64] @ 0x40 + 8004200: 687b ldr r3, [r7, #4] + 8004202: 681b ldr r3, [r3, #0] + 8004204: 430a orrs r2, r1 + 8004206: 609a str r2, [r3, #8] } #endif /* HAL_DMA_MODULE_ENABLED */ /* if required, configure auto Baud rate detection scheme */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) - 8004184: 687b ldr r3, [r7, #4] - 8004186: 6a9b ldr r3, [r3, #40] @ 0x28 - 8004188: 2240 movs r2, #64 @ 0x40 - 800418a: 4013 ands r3, r2 - 800418c: d01d beq.n 80041ca + 8004208: 687b ldr r3, [r7, #4] + 800420a: 6a9b ldr r3, [r3, #40] @ 0x28 + 800420c: 2240 movs r2, #64 @ 0x40 + 800420e: 4013 ands r3, r2 + 8004210: d01d beq.n 800424e { assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); - 800418e: 687b ldr r3, [r7, #4] - 8004190: 681b ldr r3, [r3, #0] - 8004192: 685b ldr r3, [r3, #4] - 8004194: 4a1d ldr r2, [pc, #116] @ (800420c ) - 8004196: 4013 ands r3, r2 - 8004198: 0019 movs r1, r3 - 800419a: 687b ldr r3, [r7, #4] - 800419c: 6c5a ldr r2, [r3, #68] @ 0x44 - 800419e: 687b ldr r3, [r7, #4] - 80041a0: 681b ldr r3, [r3, #0] - 80041a2: 430a orrs r2, r1 - 80041a4: 605a str r2, [r3, #4] + 8004212: 687b ldr r3, [r7, #4] + 8004214: 681b ldr r3, [r3, #0] + 8004216: 685b ldr r3, [r3, #4] + 8004218: 4a1d ldr r2, [pc, #116] @ (8004290 ) + 800421a: 4013 ands r3, r2 + 800421c: 0019 movs r1, r3 + 800421e: 687b ldr r3, [r7, #4] + 8004220: 6c5a ldr r2, [r3, #68] @ 0x44 + 8004222: 687b ldr r3, [r7, #4] + 8004224: 681b ldr r3, [r3, #0] + 8004226: 430a orrs r2, r1 + 8004228: 605a str r2, [r3, #4] /* set auto Baudrate detection parameters if detection is enabled */ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) - 80041a6: 687b ldr r3, [r7, #4] - 80041a8: 6c5a ldr r2, [r3, #68] @ 0x44 - 80041aa: 2380 movs r3, #128 @ 0x80 - 80041ac: 035b lsls r3, r3, #13 - 80041ae: 429a cmp r2, r3 - 80041b0: d10b bne.n 80041ca + 800422a: 687b ldr r3, [r7, #4] + 800422c: 6c5a ldr r2, [r3, #68] @ 0x44 + 800422e: 2380 movs r3, #128 @ 0x80 + 8004230: 035b lsls r3, r3, #13 + 8004232: 429a cmp r2, r3 + 8004234: d10b bne.n 800424e { assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); - 80041b2: 687b ldr r3, [r7, #4] - 80041b4: 681b ldr r3, [r3, #0] - 80041b6: 685b ldr r3, [r3, #4] - 80041b8: 4a15 ldr r2, [pc, #84] @ (8004210 ) - 80041ba: 4013 ands r3, r2 - 80041bc: 0019 movs r1, r3 - 80041be: 687b ldr r3, [r7, #4] - 80041c0: 6c9a ldr r2, [r3, #72] @ 0x48 - 80041c2: 687b ldr r3, [r7, #4] - 80041c4: 681b ldr r3, [r3, #0] - 80041c6: 430a orrs r2, r1 - 80041c8: 605a str r2, [r3, #4] + 8004236: 687b ldr r3, [r7, #4] + 8004238: 681b ldr r3, [r3, #0] + 800423a: 685b ldr r3, [r3, #4] + 800423c: 4a15 ldr r2, [pc, #84] @ (8004294 ) + 800423e: 4013 ands r3, r2 + 8004240: 0019 movs r1, r3 + 8004242: 687b ldr r3, [r7, #4] + 8004244: 6c9a ldr r2, [r3, #72] @ 0x48 + 8004246: 687b ldr r3, [r7, #4] + 8004248: 681b ldr r3, [r3, #0] + 800424a: 430a orrs r2, r1 + 800424c: 605a str r2, [r3, #4] } } /* if required, configure MSB first on communication line */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) - 80041ca: 687b ldr r3, [r7, #4] - 80041cc: 6a9b ldr r3, [r3, #40] @ 0x28 - 80041ce: 2280 movs r2, #128 @ 0x80 - 80041d0: 4013 ands r3, r2 - 80041d2: d00b beq.n 80041ec + 800424e: 687b ldr r3, [r7, #4] + 8004250: 6a9b ldr r3, [r3, #40] @ 0x28 + 8004252: 2280 movs r2, #128 @ 0x80 + 8004254: 4013 ands r3, r2 + 8004256: d00b beq.n 8004270 { assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); - 80041d4: 687b ldr r3, [r7, #4] - 80041d6: 681b ldr r3, [r3, #0] - 80041d8: 685b ldr r3, [r3, #4] - 80041da: 4a0e ldr r2, [pc, #56] @ (8004214 ) - 80041dc: 4013 ands r3, r2 - 80041de: 0019 movs r1, r3 - 80041e0: 687b ldr r3, [r7, #4] - 80041e2: 6cda ldr r2, [r3, #76] @ 0x4c - 80041e4: 687b ldr r3, [r7, #4] - 80041e6: 681b ldr r3, [r3, #0] - 80041e8: 430a orrs r2, r1 - 80041ea: 605a str r2, [r3, #4] + 8004258: 687b ldr r3, [r7, #4] + 800425a: 681b ldr r3, [r3, #0] + 800425c: 685b ldr r3, [r3, #4] + 800425e: 4a0e ldr r2, [pc, #56] @ (8004298 ) + 8004260: 4013 ands r3, r2 + 8004262: 0019 movs r1, r3 + 8004264: 687b ldr r3, [r7, #4] + 8004266: 6cda ldr r2, [r3, #76] @ 0x4c + 8004268: 687b ldr r3, [r7, #4] + 800426a: 681b ldr r3, [r3, #0] + 800426c: 430a orrs r2, r1 + 800426e: 605a str r2, [r3, #4] } } - 80041ec: 46c0 nop @ (mov r8, r8) - 80041ee: 46bd mov sp, r7 - 80041f0: b002 add sp, #8 - 80041f2: bd80 pop {r7, pc} - 80041f4: ffff7fff .word 0xffff7fff - 80041f8: fffdffff .word 0xfffdffff - 80041fc: fffeffff .word 0xfffeffff - 8004200: fffbffff .word 0xfffbffff - 8004204: ffffefff .word 0xffffefff - 8004208: ffffdfff .word 0xffffdfff - 800420c: ffefffff .word 0xffefffff - 8004210: ff9fffff .word 0xff9fffff - 8004214: fff7ffff .word 0xfff7ffff + 8004270: 46c0 nop @ (mov r8, r8) + 8004272: 46bd mov sp, r7 + 8004274: b002 add sp, #8 + 8004276: bd80 pop {r7, pc} + 8004278: ffff7fff .word 0xffff7fff + 800427c: fffdffff .word 0xfffdffff + 8004280: fffeffff .word 0xfffeffff + 8004284: fffbffff .word 0xfffbffff + 8004288: ffffefff .word 0xffffefff + 800428c: ffffdfff .word 0xffffdfff + 8004290: ffefffff .word 0xffefffff + 8004294: ff9fffff .word 0xff9fffff + 8004298: fff7ffff .word 0xfff7ffff -08004218 : +0800429c : * @brief Check the UART Idle State. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { - 8004218: b580 push {r7, lr} - 800421a: b092 sub sp, #72 @ 0x48 - 800421c: af02 add r7, sp, #8 - 800421e: 6078 str r0, [r7, #4] + 800429c: b580 push {r7, lr} + 800429e: b092 sub sp, #72 @ 0x48 + 80042a0: af02 add r7, sp, #8 + 80042a2: 6078 str r0, [r7, #4] uint32_t tickstart; /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; - 8004220: 687b ldr r3, [r7, #4] - 8004222: 2290 movs r2, #144 @ 0x90 - 8004224: 2100 movs r1, #0 - 8004226: 5099 str r1, [r3, r2] + 80042a4: 687b ldr r3, [r7, #4] + 80042a6: 2290 movs r2, #144 @ 0x90 + 80042a8: 2100 movs r1, #0 + 80042aa: 5099 str r1, [r3, r2] /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); - 8004228: f7fd fa84 bl 8001734 - 800422c: 0003 movs r3, r0 - 800422e: 63fb str r3, [r7, #60] @ 0x3c + 80042ac: f7fd fa84 bl 80017b8 + 80042b0: 0003 movs r3, r0 + 80042b2: 63fb str r3, [r7, #60] @ 0x3c /* Check if the Transmitter is enabled */ if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) - 8004230: 687b ldr r3, [r7, #4] - 8004232: 681b ldr r3, [r3, #0] - 8004234: 681b ldr r3, [r3, #0] - 8004236: 2208 movs r2, #8 - 8004238: 4013 ands r3, r2 - 800423a: 2b08 cmp r3, #8 - 800423c: d12d bne.n 800429a + 80042b4: 687b ldr r3, [r7, #4] + 80042b6: 681b ldr r3, [r3, #0] + 80042b8: 681b ldr r3, [r3, #0] + 80042ba: 2208 movs r2, #8 + 80042bc: 4013 ands r3, r2 + 80042be: 2b08 cmp r3, #8 + 80042c0: d12d bne.n 800431e { /* Wait until TEACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - 800423e: 6bfb ldr r3, [r7, #60] @ 0x3c - 8004240: 2280 movs r2, #128 @ 0x80 - 8004242: 0391 lsls r1, r2, #14 - 8004244: 6878 ldr r0, [r7, #4] - 8004246: 4a47 ldr r2, [pc, #284] @ (8004364 ) - 8004248: 9200 str r2, [sp, #0] - 800424a: 2200 movs r2, #0 - 800424c: f000 f88e bl 800436c - 8004250: 1e03 subs r3, r0, #0 - 8004252: d022 beq.n 800429a + 80042c2: 6bfb ldr r3, [r7, #60] @ 0x3c + 80042c4: 2280 movs r2, #128 @ 0x80 + 80042c6: 0391 lsls r1, r2, #14 + 80042c8: 6878 ldr r0, [r7, #4] + 80042ca: 4a47 ldr r2, [pc, #284] @ (80043e8 ) + 80042cc: 9200 str r2, [sp, #0] + 80042ce: 2200 movs r2, #0 + 80042d0: f000 f88e bl 80043f0 + 80042d4: 1e03 subs r3, r0, #0 + 80042d6: d022 beq.n 800431e */ __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) { uint32_t result; __ASM volatile ("MRS %0, primask" : "=r" (result) ); - 8004254: f3ef 8310 mrs r3, PRIMASK - 8004258: 627b str r3, [r7, #36] @ 0x24 + 80042d8: f3ef 8310 mrs r3, PRIMASK + 80042dc: 627b str r3, [r7, #36] @ 0x24 return(result); - 800425a: 6a7b ldr r3, [r7, #36] @ 0x24 + 80042de: 6a7b ldr r3, [r7, #36] @ 0x24 { /* Disable TXE interrupt for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); - 800425c: 63bb str r3, [r7, #56] @ 0x38 - 800425e: 2301 movs r3, #1 - 8004260: 62bb str r3, [r7, #40] @ 0x28 + 80042e0: 63bb str r3, [r7, #56] @ 0x38 + 80042e2: 2301 movs r3, #1 + 80042e4: 62bb str r3, [r7, #40] @ 0x28 \details Assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) { __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 8004262: 6abb ldr r3, [r7, #40] @ 0x28 - 8004264: f383 8810 msr PRIMASK, r3 + 80042e6: 6abb ldr r3, [r7, #40] @ 0x28 + 80042e8: f383 8810 msr PRIMASK, r3 } - 8004268: 46c0 nop @ (mov r8, r8) - 800426a: 687b ldr r3, [r7, #4] - 800426c: 681b ldr r3, [r3, #0] - 800426e: 681a ldr r2, [r3, #0] - 8004270: 687b ldr r3, [r7, #4] - 8004272: 681b ldr r3, [r3, #0] - 8004274: 2180 movs r1, #128 @ 0x80 - 8004276: 438a bics r2, r1 - 8004278: 601a str r2, [r3, #0] - 800427a: 6bbb ldr r3, [r7, #56] @ 0x38 - 800427c: 62fb str r3, [r7, #44] @ 0x2c + 80042ec: 46c0 nop @ (mov r8, r8) + 80042ee: 687b ldr r3, [r7, #4] + 80042f0: 681b ldr r3, [r3, #0] + 80042f2: 681a ldr r2, [r3, #0] + 80042f4: 687b ldr r3, [r7, #4] + 80042f6: 681b ldr r3, [r3, #0] + 80042f8: 2180 movs r1, #128 @ 0x80 + 80042fa: 438a bics r2, r1 + 80042fc: 601a str r2, [r3, #0] + 80042fe: 6bbb ldr r3, [r7, #56] @ 0x38 + 8004300: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 800427e: 6afb ldr r3, [r7, #44] @ 0x2c - 8004280: f383 8810 msr PRIMASK, r3 + 8004302: 6afb ldr r3, [r7, #44] @ 0x2c + 8004304: f383 8810 msr PRIMASK, r3 } - 8004284: 46c0 nop @ (mov r8, r8) + 8004308: 46c0 nop @ (mov r8, r8) huart->gState = HAL_UART_STATE_READY; - 8004286: 687b ldr r3, [r7, #4] - 8004288: 2288 movs r2, #136 @ 0x88 - 800428a: 2120 movs r1, #32 - 800428c: 5099 str r1, [r3, r2] + 800430a: 687b ldr r3, [r7, #4] + 800430c: 2288 movs r2, #136 @ 0x88 + 800430e: 2120 movs r1, #32 + 8004310: 5099 str r1, [r3, r2] __HAL_UNLOCK(huart); - 800428e: 687b ldr r3, [r7, #4] - 8004290: 2284 movs r2, #132 @ 0x84 - 8004292: 2100 movs r1, #0 - 8004294: 5499 strb r1, [r3, r2] + 8004312: 687b ldr r3, [r7, #4] + 8004314: 2284 movs r2, #132 @ 0x84 + 8004316: 2100 movs r1, #0 + 8004318: 5499 strb r1, [r3, r2] /* Timeout occurred */ return HAL_TIMEOUT; - 8004296: 2303 movs r3, #3 - 8004298: e060 b.n 800435c + 800431a: 2303 movs r3, #3 + 800431c: e060 b.n 80043e0 } } /* Check if the Receiver is enabled */ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) - 800429a: 687b ldr r3, [r7, #4] - 800429c: 681b ldr r3, [r3, #0] - 800429e: 681b ldr r3, [r3, #0] - 80042a0: 2204 movs r2, #4 - 80042a2: 4013 ands r3, r2 - 80042a4: 2b04 cmp r3, #4 - 80042a6: d146 bne.n 8004336 + 800431e: 687b ldr r3, [r7, #4] + 8004320: 681b ldr r3, [r3, #0] + 8004322: 681b ldr r3, [r3, #0] + 8004324: 2204 movs r2, #4 + 8004326: 4013 ands r3, r2 + 8004328: 2b04 cmp r3, #4 + 800432a: d146 bne.n 80043ba { /* Wait until REACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - 80042a8: 6bfb ldr r3, [r7, #60] @ 0x3c - 80042aa: 2280 movs r2, #128 @ 0x80 - 80042ac: 03d1 lsls r1, r2, #15 - 80042ae: 6878 ldr r0, [r7, #4] - 80042b0: 4a2c ldr r2, [pc, #176] @ (8004364 ) - 80042b2: 9200 str r2, [sp, #0] - 80042b4: 2200 movs r2, #0 - 80042b6: f000 f859 bl 800436c - 80042ba: 1e03 subs r3, r0, #0 - 80042bc: d03b beq.n 8004336 + 800432c: 6bfb ldr r3, [r7, #60] @ 0x3c + 800432e: 2280 movs r2, #128 @ 0x80 + 8004330: 03d1 lsls r1, r2, #15 + 8004332: 6878 ldr r0, [r7, #4] + 8004334: 4a2c ldr r2, [pc, #176] @ (80043e8 ) + 8004336: 9200 str r2, [sp, #0] + 8004338: 2200 movs r2, #0 + 800433a: f000 f859 bl 80043f0 + 800433e: 1e03 subs r3, r0, #0 + 8004340: d03b beq.n 80043ba __ASM volatile ("MRS %0, primask" : "=r" (result) ); - 80042be: f3ef 8310 mrs r3, PRIMASK - 80042c2: 60fb str r3, [r7, #12] + 8004342: f3ef 8310 mrs r3, PRIMASK + 8004346: 60fb str r3, [r7, #12] return(result); - 80042c4: 68fb ldr r3, [r7, #12] + 8004348: 68fb ldr r3, [r7, #12] { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); - 80042c6: 637b str r3, [r7, #52] @ 0x34 - 80042c8: 2301 movs r3, #1 - 80042ca: 613b str r3, [r7, #16] + 800434a: 637b str r3, [r7, #52] @ 0x34 + 800434c: 2301 movs r3, #1 + 800434e: 613b str r3, [r7, #16] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 80042cc: 693b ldr r3, [r7, #16] - 80042ce: f383 8810 msr PRIMASK, r3 + 8004350: 693b ldr r3, [r7, #16] + 8004352: f383 8810 msr PRIMASK, r3 } - 80042d2: 46c0 nop @ (mov r8, r8) - 80042d4: 687b ldr r3, [r7, #4] - 80042d6: 681b ldr r3, [r3, #0] - 80042d8: 681a ldr r2, [r3, #0] - 80042da: 687b ldr r3, [r7, #4] - 80042dc: 681b ldr r3, [r3, #0] - 80042de: 4922 ldr r1, [pc, #136] @ (8004368 ) - 80042e0: 400a ands r2, r1 - 80042e2: 601a str r2, [r3, #0] - 80042e4: 6b7b ldr r3, [r7, #52] @ 0x34 - 80042e6: 617b str r3, [r7, #20] + 8004356: 46c0 nop @ (mov r8, r8) + 8004358: 687b ldr r3, [r7, #4] + 800435a: 681b ldr r3, [r3, #0] + 800435c: 681a ldr r2, [r3, #0] + 800435e: 687b ldr r3, [r7, #4] + 8004360: 681b ldr r3, [r3, #0] + 8004362: 4922 ldr r1, [pc, #136] @ (80043ec ) + 8004364: 400a ands r2, r1 + 8004366: 601a str r2, [r3, #0] + 8004368: 6b7b ldr r3, [r7, #52] @ 0x34 + 800436a: 617b str r3, [r7, #20] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 80042e8: 697b ldr r3, [r7, #20] - 80042ea: f383 8810 msr PRIMASK, r3 + 800436c: 697b ldr r3, [r7, #20] + 800436e: f383 8810 msr PRIMASK, r3 } - 80042ee: 46c0 nop @ (mov r8, r8) + 8004372: 46c0 nop @ (mov r8, r8) __ASM volatile ("MRS %0, primask" : "=r" (result) ); - 80042f0: f3ef 8310 mrs r3, PRIMASK - 80042f4: 61bb str r3, [r7, #24] + 8004374: f3ef 8310 mrs r3, PRIMASK + 8004378: 61bb str r3, [r7, #24] return(result); - 80042f6: 69bb ldr r3, [r7, #24] + 800437a: 69bb ldr r3, [r7, #24] ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - 80042f8: 633b str r3, [r7, #48] @ 0x30 - 80042fa: 2301 movs r3, #1 - 80042fc: 61fb str r3, [r7, #28] + 800437c: 633b str r3, [r7, #48] @ 0x30 + 800437e: 2301 movs r3, #1 + 8004380: 61fb str r3, [r7, #28] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 80042fe: 69fb ldr r3, [r7, #28] - 8004300: f383 8810 msr PRIMASK, r3 + 8004382: 69fb ldr r3, [r7, #28] + 8004384: f383 8810 msr PRIMASK, r3 } - 8004304: 46c0 nop @ (mov r8, r8) - 8004306: 687b ldr r3, [r7, #4] - 8004308: 681b ldr r3, [r3, #0] - 800430a: 689a ldr r2, [r3, #8] - 800430c: 687b ldr r3, [r7, #4] - 800430e: 681b ldr r3, [r3, #0] - 8004310: 2101 movs r1, #1 - 8004312: 438a bics r2, r1 - 8004314: 609a str r2, [r3, #8] - 8004316: 6b3b ldr r3, [r7, #48] @ 0x30 - 8004318: 623b str r3, [r7, #32] + 8004388: 46c0 nop @ (mov r8, r8) + 800438a: 687b ldr r3, [r7, #4] + 800438c: 681b ldr r3, [r3, #0] + 800438e: 689a ldr r2, [r3, #8] + 8004390: 687b ldr r3, [r7, #4] + 8004392: 681b ldr r3, [r3, #0] + 8004394: 2101 movs r1, #1 + 8004396: 438a bics r2, r1 + 8004398: 609a str r2, [r3, #8] + 800439a: 6b3b ldr r3, [r7, #48] @ 0x30 + 800439c: 623b str r3, [r7, #32] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 800431a: 6a3b ldr r3, [r7, #32] - 800431c: f383 8810 msr PRIMASK, r3 + 800439e: 6a3b ldr r3, [r7, #32] + 80043a0: f383 8810 msr PRIMASK, r3 } - 8004320: 46c0 nop @ (mov r8, r8) + 80043a4: 46c0 nop @ (mov r8, r8) huart->RxState = HAL_UART_STATE_READY; - 8004322: 687b ldr r3, [r7, #4] - 8004324: 228c movs r2, #140 @ 0x8c - 8004326: 2120 movs r1, #32 - 8004328: 5099 str r1, [r3, r2] + 80043a6: 687b ldr r3, [r7, #4] + 80043a8: 228c movs r2, #140 @ 0x8c + 80043aa: 2120 movs r1, #32 + 80043ac: 5099 str r1, [r3, r2] __HAL_UNLOCK(huart); - 800432a: 687b ldr r3, [r7, #4] - 800432c: 2284 movs r2, #132 @ 0x84 - 800432e: 2100 movs r1, #0 - 8004330: 5499 strb r1, [r3, r2] + 80043ae: 687b ldr r3, [r7, #4] + 80043b0: 2284 movs r2, #132 @ 0x84 + 80043b2: 2100 movs r1, #0 + 80043b4: 5499 strb r1, [r3, r2] /* Timeout occurred */ return HAL_TIMEOUT; - 8004332: 2303 movs r3, #3 - 8004334: e012 b.n 800435c + 80043b6: 2303 movs r3, #3 + 80043b8: e012 b.n 80043e0 } } /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; - 8004336: 687b ldr r3, [r7, #4] - 8004338: 2288 movs r2, #136 @ 0x88 - 800433a: 2120 movs r1, #32 - 800433c: 5099 str r1, [r3, r2] + 80043ba: 687b ldr r3, [r7, #4] + 80043bc: 2288 movs r2, #136 @ 0x88 + 80043be: 2120 movs r1, #32 + 80043c0: 5099 str r1, [r3, r2] huart->RxState = HAL_UART_STATE_READY; - 800433e: 687b ldr r3, [r7, #4] - 8004340: 228c movs r2, #140 @ 0x8c - 8004342: 2120 movs r1, #32 - 8004344: 5099 str r1, [r3, r2] + 80043c2: 687b ldr r3, [r7, #4] + 80043c4: 228c movs r2, #140 @ 0x8c + 80043c6: 2120 movs r1, #32 + 80043c8: 5099 str r1, [r3, r2] huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - 8004346: 687b ldr r3, [r7, #4] - 8004348: 2200 movs r2, #0 - 800434a: 66da str r2, [r3, #108] @ 0x6c + 80043ca: 687b ldr r3, [r7, #4] + 80043cc: 2200 movs r2, #0 + 80043ce: 66da str r2, [r3, #108] @ 0x6c huart->RxEventType = HAL_UART_RXEVENT_TC; - 800434c: 687b ldr r3, [r7, #4] - 800434e: 2200 movs r2, #0 - 8004350: 671a str r2, [r3, #112] @ 0x70 + 80043d0: 687b ldr r3, [r7, #4] + 80043d2: 2200 movs r2, #0 + 80043d4: 671a str r2, [r3, #112] @ 0x70 __HAL_UNLOCK(huart); - 8004352: 687b ldr r3, [r7, #4] - 8004354: 2284 movs r2, #132 @ 0x84 - 8004356: 2100 movs r1, #0 - 8004358: 5499 strb r1, [r3, r2] + 80043d6: 687b ldr r3, [r7, #4] + 80043d8: 2284 movs r2, #132 @ 0x84 + 80043da: 2100 movs r1, #0 + 80043dc: 5499 strb r1, [r3, r2] return HAL_OK; - 800435a: 2300 movs r3, #0 + 80043de: 2300 movs r3, #0 } - 800435c: 0018 movs r0, r3 - 800435e: 46bd mov sp, r7 - 8004360: b010 add sp, #64 @ 0x40 - 8004362: bd80 pop {r7, pc} - 8004364: 01ffffff .word 0x01ffffff - 8004368: fffffedf .word 0xfffffedf + 80043e0: 0018 movs r0, r3 + 80043e2: 46bd mov sp, r7 + 80043e4: b010 add sp, #64 @ 0x40 + 80043e6: bd80 pop {r7, pc} + 80043e8: 01ffffff .word 0x01ffffff + 80043ec: fffffedf .word 0xfffffedf -0800436c : +080043f0 : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { - 800436c: b580 push {r7, lr} - 800436e: b084 sub sp, #16 - 8004370: af00 add r7, sp, #0 - 8004372: 60f8 str r0, [r7, #12] - 8004374: 60b9 str r1, [r7, #8] - 8004376: 603b str r3, [r7, #0] - 8004378: 1dfb adds r3, r7, #7 - 800437a: 701a strb r2, [r3, #0] + 80043f0: b580 push {r7, lr} + 80043f2: b084 sub sp, #16 + 80043f4: af00 add r7, sp, #0 + 80043f6: 60f8 str r0, [r7, #12] + 80043f8: 60b9 str r1, [r7, #8] + 80043fa: 603b str r3, [r7, #0] + 80043fc: 1dfb adds r3, r7, #7 + 80043fe: 701a strb r2, [r3, #0] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) - 800437c: e051 b.n 8004422 + 8004400: e051 b.n 80044a6 { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) - 800437e: 69bb ldr r3, [r7, #24] - 8004380: 3301 adds r3, #1 - 8004382: d04e beq.n 8004422 + 8004402: 69bb ldr r3, [r7, #24] + 8004404: 3301 adds r3, #1 + 8004406: d04e beq.n 80044a6 { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) - 8004384: f7fd f9d6 bl 8001734 - 8004388: 0002 movs r2, r0 - 800438a: 683b ldr r3, [r7, #0] - 800438c: 1ad3 subs r3, r2, r3 - 800438e: 69ba ldr r2, [r7, #24] - 8004390: 429a cmp r2, r3 - 8004392: d302 bcc.n 800439a - 8004394: 69bb ldr r3, [r7, #24] - 8004396: 2b00 cmp r3, #0 - 8004398: d101 bne.n 800439e + 8004408: f7fd f9d6 bl 80017b8 + 800440c: 0002 movs r2, r0 + 800440e: 683b ldr r3, [r7, #0] + 8004410: 1ad3 subs r3, r2, r3 + 8004412: 69ba ldr r2, [r7, #24] + 8004414: 429a cmp r2, r3 + 8004416: d302 bcc.n 800441e + 8004418: 69bb ldr r3, [r7, #24] + 800441a: 2b00 cmp r3, #0 + 800441c: d101 bne.n 8004422 { return HAL_TIMEOUT; - 800439a: 2303 movs r3, #3 - 800439c: e051 b.n 8004442 + 800441e: 2303 movs r3, #3 + 8004420: e051 b.n 80044c6 } if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) - 800439e: 68fb ldr r3, [r7, #12] - 80043a0: 681b ldr r3, [r3, #0] - 80043a2: 681b ldr r3, [r3, #0] - 80043a4: 2204 movs r2, #4 - 80043a6: 4013 ands r3, r2 - 80043a8: d03b beq.n 8004422 - 80043aa: 68bb ldr r3, [r7, #8] - 80043ac: 2b80 cmp r3, #128 @ 0x80 - 80043ae: d038 beq.n 8004422 - 80043b0: 68bb ldr r3, [r7, #8] - 80043b2: 2b40 cmp r3, #64 @ 0x40 - 80043b4: d035 beq.n 8004422 + 8004422: 68fb ldr r3, [r7, #12] + 8004424: 681b ldr r3, [r3, #0] + 8004426: 681b ldr r3, [r3, #0] + 8004428: 2204 movs r2, #4 + 800442a: 4013 ands r3, r2 + 800442c: d03b beq.n 80044a6 + 800442e: 68bb ldr r3, [r7, #8] + 8004430: 2b80 cmp r3, #128 @ 0x80 + 8004432: d038 beq.n 80044a6 + 8004434: 68bb ldr r3, [r7, #8] + 8004436: 2b40 cmp r3, #64 @ 0x40 + 8004438: d035 beq.n 80044a6 { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) - 80043b6: 68fb ldr r3, [r7, #12] - 80043b8: 681b ldr r3, [r3, #0] - 80043ba: 69db ldr r3, [r3, #28] - 80043bc: 2208 movs r2, #8 - 80043be: 4013 ands r3, r2 - 80043c0: 2b08 cmp r3, #8 - 80043c2: d111 bne.n 80043e8 + 800443a: 68fb ldr r3, [r7, #12] + 800443c: 681b ldr r3, [r3, #0] + 800443e: 69db ldr r3, [r3, #28] + 8004440: 2208 movs r2, #8 + 8004442: 4013 ands r3, r2 + 8004444: 2b08 cmp r3, #8 + 8004446: d111 bne.n 800446c { /* Clear Overrun Error flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); - 80043c4: 68fb ldr r3, [r7, #12] - 80043c6: 681b ldr r3, [r3, #0] - 80043c8: 2208 movs r2, #8 - 80043ca: 621a str r2, [r3, #32] + 8004448: 68fb ldr r3, [r7, #12] + 800444a: 681b ldr r3, [r3, #0] + 800444c: 2208 movs r2, #8 + 800444e: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); - 80043cc: 68fb ldr r3, [r7, #12] - 80043ce: 0018 movs r0, r3 - 80043d0: f000 f922 bl 8004618 + 8004450: 68fb ldr r3, [r7, #12] + 8004452: 0018 movs r0, r3 + 8004454: f000 f922 bl 800469c huart->ErrorCode = HAL_UART_ERROR_ORE; - 80043d4: 68fb ldr r3, [r7, #12] - 80043d6: 2290 movs r2, #144 @ 0x90 - 80043d8: 2108 movs r1, #8 - 80043da: 5099 str r1, [r3, r2] + 8004458: 68fb ldr r3, [r7, #12] + 800445a: 2290 movs r2, #144 @ 0x90 + 800445c: 2108 movs r1, #8 + 800445e: 5099 str r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(huart); - 80043dc: 68fb ldr r3, [r7, #12] - 80043de: 2284 movs r2, #132 @ 0x84 - 80043e0: 2100 movs r1, #0 - 80043e2: 5499 strb r1, [r3, r2] + 8004460: 68fb ldr r3, [r7, #12] + 8004462: 2284 movs r2, #132 @ 0x84 + 8004464: 2100 movs r1, #0 + 8004466: 5499 strb r1, [r3, r2] return HAL_ERROR; - 80043e4: 2301 movs r3, #1 - 80043e6: e02c b.n 8004442 + 8004468: 2301 movs r3, #1 + 800446a: e02c b.n 80044c6 } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) - 80043e8: 68fb ldr r3, [r7, #12] - 80043ea: 681b ldr r3, [r3, #0] - 80043ec: 69da ldr r2, [r3, #28] - 80043ee: 2380 movs r3, #128 @ 0x80 - 80043f0: 011b lsls r3, r3, #4 - 80043f2: 401a ands r2, r3 - 80043f4: 2380 movs r3, #128 @ 0x80 - 80043f6: 011b lsls r3, r3, #4 - 80043f8: 429a cmp r2, r3 - 80043fa: d112 bne.n 8004422 + 800446c: 68fb ldr r3, [r7, #12] + 800446e: 681b ldr r3, [r3, #0] + 8004470: 69da ldr r2, [r3, #28] + 8004472: 2380 movs r3, #128 @ 0x80 + 8004474: 011b lsls r3, r3, #4 + 8004476: 401a ands r2, r3 + 8004478: 2380 movs r3, #128 @ 0x80 + 800447a: 011b lsls r3, r3, #4 + 800447c: 429a cmp r2, r3 + 800447e: d112 bne.n 80044a6 { /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); - 80043fc: 68fb ldr r3, [r7, #12] - 80043fe: 681b ldr r3, [r3, #0] - 8004400: 2280 movs r2, #128 @ 0x80 - 8004402: 0112 lsls r2, r2, #4 - 8004404: 621a str r2, [r3, #32] + 8004480: 68fb ldr r3, [r7, #12] + 8004482: 681b ldr r3, [r3, #0] + 8004484: 2280 movs r2, #128 @ 0x80 + 8004486: 0112 lsls r2, r2, #4 + 8004488: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); - 8004406: 68fb ldr r3, [r7, #12] - 8004408: 0018 movs r0, r3 - 800440a: f000 f905 bl 8004618 + 800448a: 68fb ldr r3, [r7, #12] + 800448c: 0018 movs r0, r3 + 800448e: f000 f905 bl 800469c huart->ErrorCode = HAL_UART_ERROR_RTO; - 800440e: 68fb ldr r3, [r7, #12] - 8004410: 2290 movs r2, #144 @ 0x90 - 8004412: 2120 movs r1, #32 - 8004414: 5099 str r1, [r3, r2] + 8004492: 68fb ldr r3, [r7, #12] + 8004494: 2290 movs r2, #144 @ 0x90 + 8004496: 2120 movs r1, #32 + 8004498: 5099 str r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(huart); - 8004416: 68fb ldr r3, [r7, #12] - 8004418: 2284 movs r2, #132 @ 0x84 - 800441a: 2100 movs r1, #0 - 800441c: 5499 strb r1, [r3, r2] + 800449a: 68fb ldr r3, [r7, #12] + 800449c: 2284 movs r2, #132 @ 0x84 + 800449e: 2100 movs r1, #0 + 80044a0: 5499 strb r1, [r3, r2] return HAL_TIMEOUT; - 800441e: 2303 movs r3, #3 - 8004420: e00f b.n 8004442 + 80044a2: 2303 movs r3, #3 + 80044a4: e00f b.n 80044c6 while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) - 8004422: 68fb ldr r3, [r7, #12] - 8004424: 681b ldr r3, [r3, #0] - 8004426: 69db ldr r3, [r3, #28] - 8004428: 68ba ldr r2, [r7, #8] - 800442a: 4013 ands r3, r2 - 800442c: 68ba ldr r2, [r7, #8] - 800442e: 1ad3 subs r3, r2, r3 - 8004430: 425a negs r2, r3 - 8004432: 4153 adcs r3, r2 - 8004434: b2db uxtb r3, r3 - 8004436: 001a movs r2, r3 - 8004438: 1dfb adds r3, r7, #7 - 800443a: 781b ldrb r3, [r3, #0] - 800443c: 429a cmp r2, r3 - 800443e: d09e beq.n 800437e + 80044a6: 68fb ldr r3, [r7, #12] + 80044a8: 681b ldr r3, [r3, #0] + 80044aa: 69db ldr r3, [r3, #28] + 80044ac: 68ba ldr r2, [r7, #8] + 80044ae: 4013 ands r3, r2 + 80044b0: 68ba ldr r2, [r7, #8] + 80044b2: 1ad3 subs r3, r2, r3 + 80044b4: 425a negs r2, r3 + 80044b6: 4153 adcs r3, r2 + 80044b8: b2db uxtb r3, r3 + 80044ba: 001a movs r2, r3 + 80044bc: 1dfb adds r3, r7, #7 + 80044be: 781b ldrb r3, [r3, #0] + 80044c0: 429a cmp r2, r3 + 80044c2: d09e beq.n 8004402 } } } } return HAL_OK; - 8004440: 2300 movs r3, #0 + 80044c4: 2300 movs r3, #0 } - 8004442: 0018 movs r0, r3 - 8004444: 46bd mov sp, r7 - 8004446: b004 add sp, #16 - 8004448: bd80 pop {r7, pc} + 80044c6: 0018 movs r0, r3 + 80044c8: 46bd mov sp, r7 + 80044ca: b004 add sp, #16 + 80044cc: bd80 pop {r7, pc} ... -0800444c : +080044d0 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { - 800444c: b580 push {r7, lr} - 800444e: b090 sub sp, #64 @ 0x40 - 8004450: af00 add r7, sp, #0 - 8004452: 60f8 str r0, [r7, #12] - 8004454: 60b9 str r1, [r7, #8] - 8004456: 1dbb adds r3, r7, #6 - 8004458: 801a strh r2, [r3, #0] + 80044d0: b580 push {r7, lr} + 80044d2: b090 sub sp, #64 @ 0x40 + 80044d4: af00 add r7, sp, #0 + 80044d6: 60f8 str r0, [r7, #12] + 80044d8: 60b9 str r1, [r7, #8] + 80044da: 1dbb adds r3, r7, #6 + 80044dc: 801a strh r2, [r3, #0] huart->pRxBuffPtr = pData; - 800445a: 68fb ldr r3, [r7, #12] - 800445c: 68ba ldr r2, [r7, #8] - 800445e: 659a str r2, [r3, #88] @ 0x58 + 80044de: 68fb ldr r3, [r7, #12] + 80044e0: 68ba ldr r2, [r7, #8] + 80044e2: 659a str r2, [r3, #88] @ 0x58 huart->RxXferSize = Size; - 8004460: 68fb ldr r3, [r7, #12] - 8004462: 1dba adds r2, r7, #6 - 8004464: 215c movs r1, #92 @ 0x5c - 8004466: 8812 ldrh r2, [r2, #0] - 8004468: 525a strh r2, [r3, r1] + 80044e4: 68fb ldr r3, [r7, #12] + 80044e6: 1dba adds r2, r7, #6 + 80044e8: 215c movs r1, #92 @ 0x5c + 80044ea: 8812 ldrh r2, [r2, #0] + 80044ec: 525a strh r2, [r3, r1] huart->ErrorCode = HAL_UART_ERROR_NONE; - 800446a: 68fb ldr r3, [r7, #12] - 800446c: 2290 movs r2, #144 @ 0x90 - 800446e: 2100 movs r1, #0 - 8004470: 5099 str r1, [r3, r2] + 80044ee: 68fb ldr r3, [r7, #12] + 80044f0: 2290 movs r2, #144 @ 0x90 + 80044f2: 2100 movs r1, #0 + 80044f4: 5099 str r1, [r3, r2] huart->RxState = HAL_UART_STATE_BUSY_RX; - 8004472: 68fb ldr r3, [r7, #12] - 8004474: 228c movs r2, #140 @ 0x8c - 8004476: 2122 movs r1, #34 @ 0x22 - 8004478: 5099 str r1, [r3, r2] + 80044f6: 68fb ldr r3, [r7, #12] + 80044f8: 228c movs r2, #140 @ 0x8c + 80044fa: 2122 movs r1, #34 @ 0x22 + 80044fc: 5099 str r1, [r3, r2] if (huart->hdmarx != NULL) - 800447a: 68fb ldr r3, [r7, #12] - 800447c: 2280 movs r2, #128 @ 0x80 - 800447e: 589b ldr r3, [r3, r2] - 8004480: 2b00 cmp r3, #0 - 8004482: d02d beq.n 80044e0 + 80044fe: 68fb ldr r3, [r7, #12] + 8004500: 2280 movs r2, #128 @ 0x80 + 8004502: 589b ldr r3, [r3, r2] + 8004504: 2b00 cmp r3, #0 + 8004506: d02d beq.n 8004564 { /* Set the UART DMA transfer complete callback */ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; - 8004484: 68fb ldr r3, [r7, #12] - 8004486: 2280 movs r2, #128 @ 0x80 - 8004488: 589b ldr r3, [r3, r2] - 800448a: 4a40 ldr r2, [pc, #256] @ (800458c ) - 800448c: 62da str r2, [r3, #44] @ 0x2c + 8004508: 68fb ldr r3, [r7, #12] + 800450a: 2280 movs r2, #128 @ 0x80 + 800450c: 589b ldr r3, [r3, r2] + 800450e: 4a40 ldr r2, [pc, #256] @ (8004610 ) + 8004510: 62da str r2, [r3, #44] @ 0x2c /* Set the UART DMA Half transfer complete callback */ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; - 800448e: 68fb ldr r3, [r7, #12] - 8004490: 2280 movs r2, #128 @ 0x80 - 8004492: 589b ldr r3, [r3, r2] - 8004494: 4a3e ldr r2, [pc, #248] @ (8004590 ) - 8004496: 631a str r2, [r3, #48] @ 0x30 + 8004512: 68fb ldr r3, [r7, #12] + 8004514: 2280 movs r2, #128 @ 0x80 + 8004516: 589b ldr r3, [r3, r2] + 8004518: 4a3e ldr r2, [pc, #248] @ (8004614 ) + 800451a: 631a str r2, [r3, #48] @ 0x30 /* Set the DMA error callback */ huart->hdmarx->XferErrorCallback = UART_DMAError; - 8004498: 68fb ldr r3, [r7, #12] - 800449a: 2280 movs r2, #128 @ 0x80 - 800449c: 589b ldr r3, [r3, r2] - 800449e: 4a3d ldr r2, [pc, #244] @ (8004594 ) - 80044a0: 635a str r2, [r3, #52] @ 0x34 + 800451c: 68fb ldr r3, [r7, #12] + 800451e: 2280 movs r2, #128 @ 0x80 + 8004520: 589b ldr r3, [r3, r2] + 8004522: 4a3d ldr r2, [pc, #244] @ (8004618 ) + 8004524: 635a str r2, [r3, #52] @ 0x34 /* Set the DMA abort callback */ huart->hdmarx->XferAbortCallback = NULL; - 80044a2: 68fb ldr r3, [r7, #12] - 80044a4: 2280 movs r2, #128 @ 0x80 - 80044a6: 589b ldr r3, [r3, r2] - 80044a8: 2200 movs r2, #0 - 80044aa: 639a str r2, [r3, #56] @ 0x38 + 8004526: 68fb ldr r3, [r7, #12] + 8004528: 2280 movs r2, #128 @ 0x80 + 800452a: 589b ldr r3, [r3, r2] + 800452c: 2200 movs r2, #0 + 800452e: 639a str r2, [r3, #56] @ 0x38 /* Enable the DMA channel */ if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK) - 80044ac: 68fb ldr r3, [r7, #12] - 80044ae: 2280 movs r2, #128 @ 0x80 - 80044b0: 5898 ldr r0, [r3, r2] - 80044b2: 68fb ldr r3, [r7, #12] - 80044b4: 681b ldr r3, [r3, #0] - 80044b6: 3324 adds r3, #36 @ 0x24 - 80044b8: 0019 movs r1, r3 - 80044ba: 68fb ldr r3, [r7, #12] - 80044bc: 6d9b ldr r3, [r3, #88] @ 0x58 - 80044be: 001a movs r2, r3 - 80044c0: 1dbb adds r3, r7, #6 - 80044c2: 881b ldrh r3, [r3, #0] - 80044c4: f7fd fac6 bl 8001a54 - 80044c8: 1e03 subs r3, r0, #0 - 80044ca: d009 beq.n 80044e0 + 8004530: 68fb ldr r3, [r7, #12] + 8004532: 2280 movs r2, #128 @ 0x80 + 8004534: 5898 ldr r0, [r3, r2] + 8004536: 68fb ldr r3, [r7, #12] + 8004538: 681b ldr r3, [r3, #0] + 800453a: 3324 adds r3, #36 @ 0x24 + 800453c: 0019 movs r1, r3 + 800453e: 68fb ldr r3, [r7, #12] + 8004540: 6d9b ldr r3, [r3, #88] @ 0x58 + 8004542: 001a movs r2, r3 + 8004544: 1dbb adds r3, r7, #6 + 8004546: 881b ldrh r3, [r3, #0] + 8004548: f7fd fac6 bl 8001ad8 + 800454c: 1e03 subs r3, r0, #0 + 800454e: d009 beq.n 8004564 { /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; - 80044cc: 68fb ldr r3, [r7, #12] - 80044ce: 2290 movs r2, #144 @ 0x90 - 80044d0: 2110 movs r1, #16 - 80044d2: 5099 str r1, [r3, r2] + 8004550: 68fb ldr r3, [r7, #12] + 8004552: 2290 movs r2, #144 @ 0x90 + 8004554: 2110 movs r1, #16 + 8004556: 5099 str r1, [r3, r2] /* Restore huart->RxState to ready */ huart->RxState = HAL_UART_STATE_READY; - 80044d4: 68fb ldr r3, [r7, #12] - 80044d6: 228c movs r2, #140 @ 0x8c - 80044d8: 2120 movs r1, #32 - 80044da: 5099 str r1, [r3, r2] + 8004558: 68fb ldr r3, [r7, #12] + 800455a: 228c movs r2, #140 @ 0x8c + 800455c: 2120 movs r1, #32 + 800455e: 5099 str r1, [r3, r2] return HAL_ERROR; - 80044dc: 2301 movs r3, #1 - 80044de: e050 b.n 8004582 + 8004560: 2301 movs r3, #1 + 8004562: e050 b.n 8004606 } } /* Enable the UART Parity Error Interrupt */ if (huart->Init.Parity != UART_PARITY_NONE) - 80044e0: 68fb ldr r3, [r7, #12] - 80044e2: 691b ldr r3, [r3, #16] - 80044e4: 2b00 cmp r3, #0 - 80044e6: d019 beq.n 800451c + 8004564: 68fb ldr r3, [r7, #12] + 8004566: 691b ldr r3, [r3, #16] + 8004568: 2b00 cmp r3, #0 + 800456a: d019 beq.n 80045a0 __ASM volatile ("MRS %0, primask" : "=r" (result) ); - 80044e8: f3ef 8310 mrs r3, PRIMASK - 80044ec: 62bb str r3, [r7, #40] @ 0x28 + 800456c: f3ef 8310 mrs r3, PRIMASK + 8004570: 62bb str r3, [r7, #40] @ 0x28 return(result); - 80044ee: 6abb ldr r3, [r7, #40] @ 0x28 + 8004572: 6abb ldr r3, [r7, #40] @ 0x28 { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - 80044f0: 63fb str r3, [r7, #60] @ 0x3c - 80044f2: 2301 movs r3, #1 - 80044f4: 62fb str r3, [r7, #44] @ 0x2c + 8004574: 63fb str r3, [r7, #60] @ 0x3c + 8004576: 2301 movs r3, #1 + 8004578: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 80044f6: 6afb ldr r3, [r7, #44] @ 0x2c - 80044f8: f383 8810 msr PRIMASK, r3 + 800457a: 6afb ldr r3, [r7, #44] @ 0x2c + 800457c: f383 8810 msr PRIMASK, r3 } - 80044fc: 46c0 nop @ (mov r8, r8) - 80044fe: 68fb ldr r3, [r7, #12] - 8004500: 681b ldr r3, [r3, #0] - 8004502: 681a ldr r2, [r3, #0] - 8004504: 68fb ldr r3, [r7, #12] - 8004506: 681b ldr r3, [r3, #0] - 8004508: 2180 movs r1, #128 @ 0x80 - 800450a: 0049 lsls r1, r1, #1 - 800450c: 430a orrs r2, r1 - 800450e: 601a str r2, [r3, #0] - 8004510: 6bfb ldr r3, [r7, #60] @ 0x3c - 8004512: 633b str r3, [r7, #48] @ 0x30 + 8004580: 46c0 nop @ (mov r8, r8) + 8004582: 68fb ldr r3, [r7, #12] + 8004584: 681b ldr r3, [r3, #0] + 8004586: 681a ldr r2, [r3, #0] + 8004588: 68fb ldr r3, [r7, #12] + 800458a: 681b ldr r3, [r3, #0] + 800458c: 2180 movs r1, #128 @ 0x80 + 800458e: 0049 lsls r1, r1, #1 + 8004590: 430a orrs r2, r1 + 8004592: 601a str r2, [r3, #0] + 8004594: 6bfb ldr r3, [r7, #60] @ 0x3c + 8004596: 633b str r3, [r7, #48] @ 0x30 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 8004514: 6b3b ldr r3, [r7, #48] @ 0x30 - 8004516: f383 8810 msr PRIMASK, r3 + 8004598: 6b3b ldr r3, [r7, #48] @ 0x30 + 800459a: f383 8810 msr PRIMASK, r3 } - 800451a: 46c0 nop @ (mov r8, r8) + 800459e: 46c0 nop @ (mov r8, r8) __ASM volatile ("MRS %0, primask" : "=r" (result) ); - 800451c: f3ef 8310 mrs r3, PRIMASK - 8004520: 613b str r3, [r7, #16] + 80045a0: f3ef 8310 mrs r3, PRIMASK + 80045a4: 613b str r3, [r7, #16] return(result); - 8004522: 693b ldr r3, [r7, #16] + 80045a6: 693b ldr r3, [r7, #16] } /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - 8004524: 63bb str r3, [r7, #56] @ 0x38 - 8004526: 2301 movs r3, #1 - 8004528: 617b str r3, [r7, #20] + 80045a8: 63bb str r3, [r7, #56] @ 0x38 + 80045aa: 2301 movs r3, #1 + 80045ac: 617b str r3, [r7, #20] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 800452a: 697b ldr r3, [r7, #20] - 800452c: f383 8810 msr PRIMASK, r3 + 80045ae: 697b ldr r3, [r7, #20] + 80045b0: f383 8810 msr PRIMASK, r3 } - 8004530: 46c0 nop @ (mov r8, r8) - 8004532: 68fb ldr r3, [r7, #12] - 8004534: 681b ldr r3, [r3, #0] - 8004536: 689a ldr r2, [r3, #8] - 8004538: 68fb ldr r3, [r7, #12] - 800453a: 681b ldr r3, [r3, #0] - 800453c: 2101 movs r1, #1 - 800453e: 430a orrs r2, r1 - 8004540: 609a str r2, [r3, #8] - 8004542: 6bbb ldr r3, [r7, #56] @ 0x38 - 8004544: 61bb str r3, [r7, #24] + 80045b4: 46c0 nop @ (mov r8, r8) + 80045b6: 68fb ldr r3, [r7, #12] + 80045b8: 681b ldr r3, [r3, #0] + 80045ba: 689a ldr r2, [r3, #8] + 80045bc: 68fb ldr r3, [r7, #12] + 80045be: 681b ldr r3, [r3, #0] + 80045c0: 2101 movs r1, #1 + 80045c2: 430a orrs r2, r1 + 80045c4: 609a str r2, [r3, #8] + 80045c6: 6bbb ldr r3, [r7, #56] @ 0x38 + 80045c8: 61bb str r3, [r7, #24] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 8004546: 69bb ldr r3, [r7, #24] - 8004548: f383 8810 msr PRIMASK, r3 + 80045ca: 69bb ldr r3, [r7, #24] + 80045cc: f383 8810 msr PRIMASK, r3 } - 800454c: 46c0 nop @ (mov r8, r8) + 80045d0: 46c0 nop @ (mov r8, r8) __ASM volatile ("MRS %0, primask" : "=r" (result) ); - 800454e: f3ef 8310 mrs r3, PRIMASK - 8004552: 61fb str r3, [r7, #28] + 80045d2: f3ef 8310 mrs r3, PRIMASK + 80045d6: 61fb str r3, [r7, #28] return(result); - 8004554: 69fb ldr r3, [r7, #28] + 80045d8: 69fb ldr r3, [r7, #28] /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); - 8004556: 637b str r3, [r7, #52] @ 0x34 - 8004558: 2301 movs r3, #1 - 800455a: 623b str r3, [r7, #32] + 80045da: 637b str r3, [r7, #52] @ 0x34 + 80045dc: 2301 movs r3, #1 + 80045de: 623b str r3, [r7, #32] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 800455c: 6a3b ldr r3, [r7, #32] - 800455e: f383 8810 msr PRIMASK, r3 + 80045e0: 6a3b ldr r3, [r7, #32] + 80045e2: f383 8810 msr PRIMASK, r3 } - 8004562: 46c0 nop @ (mov r8, r8) - 8004564: 68fb ldr r3, [r7, #12] - 8004566: 681b ldr r3, [r3, #0] - 8004568: 689a ldr r2, [r3, #8] - 800456a: 68fb ldr r3, [r7, #12] - 800456c: 681b ldr r3, [r3, #0] - 800456e: 2140 movs r1, #64 @ 0x40 - 8004570: 430a orrs r2, r1 - 8004572: 609a str r2, [r3, #8] - 8004574: 6b7b ldr r3, [r7, #52] @ 0x34 - 8004576: 627b str r3, [r7, #36] @ 0x24 + 80045e6: 46c0 nop @ (mov r8, r8) + 80045e8: 68fb ldr r3, [r7, #12] + 80045ea: 681b ldr r3, [r3, #0] + 80045ec: 689a ldr r2, [r3, #8] + 80045ee: 68fb ldr r3, [r7, #12] + 80045f0: 681b ldr r3, [r3, #0] + 80045f2: 2140 movs r1, #64 @ 0x40 + 80045f4: 430a orrs r2, r1 + 80045f6: 609a str r2, [r3, #8] + 80045f8: 6b7b ldr r3, [r7, #52] @ 0x34 + 80045fa: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 8004578: 6a7b ldr r3, [r7, #36] @ 0x24 - 800457a: f383 8810 msr PRIMASK, r3 + 80045fc: 6a7b ldr r3, [r7, #36] @ 0x24 + 80045fe: f383 8810 msr PRIMASK, r3 } - 800457e: 46c0 nop @ (mov r8, r8) + 8004602: 46c0 nop @ (mov r8, r8) return HAL_OK; - 8004580: 2300 movs r3, #0 + 8004604: 2300 movs r3, #0 } - 8004582: 0018 movs r0, r3 - 8004584: 46bd mov sp, r7 - 8004586: b010 add sp, #64 @ 0x40 - 8004588: bd80 pop {r7, pc} - 800458a: 46c0 nop @ (mov r8, r8) - 800458c: 080046e5 .word 0x080046e5 - 8004590: 0800484d .word 0x0800484d - 8004594: 080048cb .word 0x080048cb + 8004606: 0018 movs r0, r3 + 8004608: 46bd mov sp, r7 + 800460a: b010 add sp, #64 @ 0x40 + 800460c: bd80 pop {r7, pc} + 800460e: 46c0 nop @ (mov r8, r8) + 8004610: 08004769 .word 0x08004769 + 8004614: 080048d1 .word 0x080048d1 + 8004618: 0800494f .word 0x0800494f -08004598 : +0800461c : * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). * @param huart UART handle. * @retval None */ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) { - 8004598: b580 push {r7, lr} - 800459a: b08a sub sp, #40 @ 0x28 - 800459c: af00 add r7, sp, #0 - 800459e: 6078 str r0, [r7, #4] + 800461c: b580 push {r7, lr} + 800461e: b08a sub sp, #40 @ 0x28 + 8004620: af00 add r7, sp, #0 + 8004622: 6078 str r0, [r7, #4] __ASM volatile ("MRS %0, primask" : "=r" (result) ); - 80045a0: f3ef 8310 mrs r3, PRIMASK - 80045a4: 60bb str r3, [r7, #8] + 8004624: f3ef 8310 mrs r3, PRIMASK + 8004628: 60bb str r3, [r7, #8] return(result); - 80045a6: 68bb ldr r3, [r7, #8] + 800462a: 68bb ldr r3, [r7, #8] /* Disable TXEIE, TCIE, TXFT interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); - 80045a8: 627b str r3, [r7, #36] @ 0x24 - 80045aa: 2301 movs r3, #1 - 80045ac: 60fb str r3, [r7, #12] + 800462c: 627b str r3, [r7, #36] @ 0x24 + 800462e: 2301 movs r3, #1 + 8004630: 60fb str r3, [r7, #12] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 80045ae: 68fb ldr r3, [r7, #12] - 80045b0: f383 8810 msr PRIMASK, r3 + 8004632: 68fb ldr r3, [r7, #12] + 8004634: f383 8810 msr PRIMASK, r3 } - 80045b4: 46c0 nop @ (mov r8, r8) - 80045b6: 687b ldr r3, [r7, #4] - 80045b8: 681b ldr r3, [r3, #0] - 80045ba: 681a ldr r2, [r3, #0] - 80045bc: 687b ldr r3, [r7, #4] - 80045be: 681b ldr r3, [r3, #0] - 80045c0: 21c0 movs r1, #192 @ 0xc0 - 80045c2: 438a bics r2, r1 - 80045c4: 601a str r2, [r3, #0] - 80045c6: 6a7b ldr r3, [r7, #36] @ 0x24 - 80045c8: 613b str r3, [r7, #16] + 8004638: 46c0 nop @ (mov r8, r8) + 800463a: 687b ldr r3, [r7, #4] + 800463c: 681b ldr r3, [r3, #0] + 800463e: 681a ldr r2, [r3, #0] + 8004640: 687b ldr r3, [r7, #4] + 8004642: 681b ldr r3, [r3, #0] + 8004644: 21c0 movs r1, #192 @ 0xc0 + 8004646: 438a bics r2, r1 + 8004648: 601a str r2, [r3, #0] + 800464a: 6a7b ldr r3, [r7, #36] @ 0x24 + 800464c: 613b str r3, [r7, #16] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 80045ca: 693b ldr r3, [r7, #16] - 80045cc: f383 8810 msr PRIMASK, r3 + 800464e: 693b ldr r3, [r7, #16] + 8004650: f383 8810 msr PRIMASK, r3 } - 80045d0: 46c0 nop @ (mov r8, r8) + 8004654: 46c0 nop @ (mov r8, r8) __ASM volatile ("MRS %0, primask" : "=r" (result) ); - 80045d2: f3ef 8310 mrs r3, PRIMASK - 80045d6: 617b str r3, [r7, #20] + 8004656: f3ef 8310 mrs r3, PRIMASK + 800465a: 617b str r3, [r7, #20] return(result); - 80045d8: 697b ldr r3, [r7, #20] + 800465c: 697b ldr r3, [r7, #20] ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE)); - 80045da: 623b str r3, [r7, #32] - 80045dc: 2301 movs r3, #1 - 80045de: 61bb str r3, [r7, #24] + 800465e: 623b str r3, [r7, #32] + 8004660: 2301 movs r3, #1 + 8004662: 61bb str r3, [r7, #24] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 80045e0: 69bb ldr r3, [r7, #24] - 80045e2: f383 8810 msr PRIMASK, r3 + 8004664: 69bb ldr r3, [r7, #24] + 8004666: f383 8810 msr PRIMASK, r3 } - 80045e6: 46c0 nop @ (mov r8, r8) - 80045e8: 687b ldr r3, [r7, #4] - 80045ea: 681b ldr r3, [r3, #0] - 80045ec: 689a ldr r2, [r3, #8] - 80045ee: 687b ldr r3, [r7, #4] - 80045f0: 681b ldr r3, [r3, #0] - 80045f2: 4908 ldr r1, [pc, #32] @ (8004614 ) - 80045f4: 400a ands r2, r1 - 80045f6: 609a str r2, [r3, #8] - 80045f8: 6a3b ldr r3, [r7, #32] - 80045fa: 61fb str r3, [r7, #28] + 800466a: 46c0 nop @ (mov r8, r8) + 800466c: 687b ldr r3, [r7, #4] + 800466e: 681b ldr r3, [r3, #0] + 8004670: 689a ldr r2, [r3, #8] + 8004672: 687b ldr r3, [r7, #4] + 8004674: 681b ldr r3, [r3, #0] + 8004676: 4908 ldr r1, [pc, #32] @ (8004698 ) + 8004678: 400a ands r2, r1 + 800467a: 609a str r2, [r3, #8] + 800467c: 6a3b ldr r3, [r7, #32] + 800467e: 61fb str r3, [r7, #28] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 80045fc: 69fb ldr r3, [r7, #28] - 80045fe: f383 8810 msr PRIMASK, r3 + 8004680: 69fb ldr r3, [r7, #28] + 8004682: f383 8810 msr PRIMASK, r3 } - 8004602: 46c0 nop @ (mov r8, r8) + 8004686: 46c0 nop @ (mov r8, r8) /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - 8004604: 687b ldr r3, [r7, #4] - 8004606: 2288 movs r2, #136 @ 0x88 - 8004608: 2120 movs r1, #32 - 800460a: 5099 str r1, [r3, r2] + 8004688: 687b ldr r3, [r7, #4] + 800468a: 2288 movs r2, #136 @ 0x88 + 800468c: 2120 movs r1, #32 + 800468e: 5099 str r1, [r3, r2] } - 800460c: 46c0 nop @ (mov r8, r8) - 800460e: 46bd mov sp, r7 - 8004610: b00a add sp, #40 @ 0x28 - 8004612: bd80 pop {r7, pc} - 8004614: ff7fffff .word 0xff7fffff + 8004690: 46c0 nop @ (mov r8, r8) + 8004692: 46bd mov sp, r7 + 8004694: b00a add sp, #40 @ 0x28 + 8004696: bd80 pop {r7, pc} + 8004698: ff7fffff .word 0xff7fffff -08004618 : +0800469c : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { - 8004618: b580 push {r7, lr} - 800461a: b08e sub sp, #56 @ 0x38 - 800461c: af00 add r7, sp, #0 - 800461e: 6078 str r0, [r7, #4] + 800469c: b580 push {r7, lr} + 800469e: b08e sub sp, #56 @ 0x38 + 80046a0: af00 add r7, sp, #0 + 80046a2: 6078 str r0, [r7, #4] __ASM volatile ("MRS %0, primask" : "=r" (result) ); - 8004620: f3ef 8310 mrs r3, PRIMASK - 8004624: 617b str r3, [r7, #20] + 80046a4: f3ef 8310 mrs r3, PRIMASK + 80046a8: 617b str r3, [r7, #20] return(result); - 8004626: 697b ldr r3, [r7, #20] + 80046aa: 697b ldr r3, [r7, #20] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); - 8004628: 637b str r3, [r7, #52] @ 0x34 - 800462a: 2301 movs r3, #1 - 800462c: 61bb str r3, [r7, #24] + 80046ac: 637b str r3, [r7, #52] @ 0x34 + 80046ae: 2301 movs r3, #1 + 80046b0: 61bb str r3, [r7, #24] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 800462e: 69bb ldr r3, [r7, #24] - 8004630: f383 8810 msr PRIMASK, r3 + 80046b2: 69bb ldr r3, [r7, #24] + 80046b4: f383 8810 msr PRIMASK, r3 } - 8004634: 46c0 nop @ (mov r8, r8) - 8004636: 687b ldr r3, [r7, #4] - 8004638: 681b ldr r3, [r3, #0] - 800463a: 681a ldr r2, [r3, #0] - 800463c: 687b ldr r3, [r7, #4] - 800463e: 681b ldr r3, [r3, #0] - 8004640: 4926 ldr r1, [pc, #152] @ (80046dc ) - 8004642: 400a ands r2, r1 - 8004644: 601a str r2, [r3, #0] - 8004646: 6b7b ldr r3, [r7, #52] @ 0x34 - 8004648: 61fb str r3, [r7, #28] + 80046b8: 46c0 nop @ (mov r8, r8) + 80046ba: 687b ldr r3, [r7, #4] + 80046bc: 681b ldr r3, [r3, #0] + 80046be: 681a ldr r2, [r3, #0] + 80046c0: 687b ldr r3, [r7, #4] + 80046c2: 681b ldr r3, [r3, #0] + 80046c4: 4926 ldr r1, [pc, #152] @ (8004760 ) + 80046c6: 400a ands r2, r1 + 80046c8: 601a str r2, [r3, #0] + 80046ca: 6b7b ldr r3, [r7, #52] @ 0x34 + 80046cc: 61fb str r3, [r7, #28] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 800464a: 69fb ldr r3, [r7, #28] - 800464c: f383 8810 msr PRIMASK, r3 + 80046ce: 69fb ldr r3, [r7, #28] + 80046d0: f383 8810 msr PRIMASK, r3 } - 8004650: 46c0 nop @ (mov r8, r8) + 80046d4: 46c0 nop @ (mov r8, r8) __ASM volatile ("MRS %0, primask" : "=r" (result) ); - 8004652: f3ef 8310 mrs r3, PRIMASK - 8004656: 623b str r3, [r7, #32] + 80046d6: f3ef 8310 mrs r3, PRIMASK + 80046da: 623b str r3, [r7, #32] return(result); - 8004658: 6a3b ldr r3, [r7, #32] + 80046dc: 6a3b ldr r3, [r7, #32] ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); - 800465a: 633b str r3, [r7, #48] @ 0x30 - 800465c: 2301 movs r3, #1 - 800465e: 627b str r3, [r7, #36] @ 0x24 + 80046de: 633b str r3, [r7, #48] @ 0x30 + 80046e0: 2301 movs r3, #1 + 80046e2: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 8004660: 6a7b ldr r3, [r7, #36] @ 0x24 - 8004662: f383 8810 msr PRIMASK, r3 + 80046e4: 6a7b ldr r3, [r7, #36] @ 0x24 + 80046e6: f383 8810 msr PRIMASK, r3 } - 8004666: 46c0 nop @ (mov r8, r8) - 8004668: 687b ldr r3, [r7, #4] - 800466a: 681b ldr r3, [r3, #0] - 800466c: 689a ldr r2, [r3, #8] - 800466e: 687b ldr r3, [r7, #4] - 8004670: 681b ldr r3, [r3, #0] - 8004672: 491b ldr r1, [pc, #108] @ (80046e0 ) - 8004674: 400a ands r2, r1 - 8004676: 609a str r2, [r3, #8] - 8004678: 6b3b ldr r3, [r7, #48] @ 0x30 - 800467a: 62bb str r3, [r7, #40] @ 0x28 + 80046ea: 46c0 nop @ (mov r8, r8) + 80046ec: 687b ldr r3, [r7, #4] + 80046ee: 681b ldr r3, [r3, #0] + 80046f0: 689a ldr r2, [r3, #8] + 80046f2: 687b ldr r3, [r7, #4] + 80046f4: 681b ldr r3, [r3, #0] + 80046f6: 491b ldr r1, [pc, #108] @ (8004764 ) + 80046f8: 400a ands r2, r1 + 80046fa: 609a str r2, [r3, #8] + 80046fc: 6b3b ldr r3, [r7, #48] @ 0x30 + 80046fe: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 800467c: 6abb ldr r3, [r7, #40] @ 0x28 - 800467e: f383 8810 msr PRIMASK, r3 + 8004700: 6abb ldr r3, [r7, #40] @ 0x28 + 8004702: f383 8810 msr PRIMASK, r3 } - 8004682: 46c0 nop @ (mov r8, r8) + 8004706: 46c0 nop @ (mov r8, r8) /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - 8004684: 687b ldr r3, [r7, #4] - 8004686: 6edb ldr r3, [r3, #108] @ 0x6c - 8004688: 2b01 cmp r3, #1 - 800468a: d118 bne.n 80046be + 8004708: 687b ldr r3, [r7, #4] + 800470a: 6edb ldr r3, [r3, #108] @ 0x6c + 800470c: 2b01 cmp r3, #1 + 800470e: d118 bne.n 8004742 __ASM volatile ("MRS %0, primask" : "=r" (result) ); - 800468c: f3ef 8310 mrs r3, PRIMASK - 8004690: 60bb str r3, [r7, #8] + 8004710: f3ef 8310 mrs r3, PRIMASK + 8004714: 60bb str r3, [r7, #8] return(result); - 8004692: 68bb ldr r3, [r7, #8] + 8004716: 68bb ldr r3, [r7, #8] { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - 8004694: 62fb str r3, [r7, #44] @ 0x2c - 8004696: 2301 movs r3, #1 - 8004698: 60fb str r3, [r7, #12] + 8004718: 62fb str r3, [r7, #44] @ 0x2c + 800471a: 2301 movs r3, #1 + 800471c: 60fb str r3, [r7, #12] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 800469a: 68fb ldr r3, [r7, #12] - 800469c: f383 8810 msr PRIMASK, r3 + 800471e: 68fb ldr r3, [r7, #12] + 8004720: f383 8810 msr PRIMASK, r3 } - 80046a0: 46c0 nop @ (mov r8, r8) - 80046a2: 687b ldr r3, [r7, #4] - 80046a4: 681b ldr r3, [r3, #0] - 80046a6: 681a ldr r2, [r3, #0] - 80046a8: 687b ldr r3, [r7, #4] - 80046aa: 681b ldr r3, [r3, #0] - 80046ac: 2110 movs r1, #16 - 80046ae: 438a bics r2, r1 - 80046b0: 601a str r2, [r3, #0] - 80046b2: 6afb ldr r3, [r7, #44] @ 0x2c - 80046b4: 613b str r3, [r7, #16] + 8004724: 46c0 nop @ (mov r8, r8) + 8004726: 687b ldr r3, [r7, #4] + 8004728: 681b ldr r3, [r3, #0] + 800472a: 681a ldr r2, [r3, #0] + 800472c: 687b ldr r3, [r7, #4] + 800472e: 681b ldr r3, [r3, #0] + 8004730: 2110 movs r1, #16 + 8004732: 438a bics r2, r1 + 8004734: 601a str r2, [r3, #0] + 8004736: 6afb ldr r3, [r7, #44] @ 0x2c + 8004738: 613b str r3, [r7, #16] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 80046b6: 693b ldr r3, [r7, #16] - 80046b8: f383 8810 msr PRIMASK, r3 + 800473a: 693b ldr r3, [r7, #16] + 800473c: f383 8810 msr PRIMASK, r3 } - 80046bc: 46c0 nop @ (mov r8, r8) + 8004740: 46c0 nop @ (mov r8, r8) } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - 80046be: 687b ldr r3, [r7, #4] - 80046c0: 228c movs r2, #140 @ 0x8c - 80046c2: 2120 movs r1, #32 - 80046c4: 5099 str r1, [r3, r2] + 8004742: 687b ldr r3, [r7, #4] + 8004744: 228c movs r2, #140 @ 0x8c + 8004746: 2120 movs r1, #32 + 8004748: 5099 str r1, [r3, r2] huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - 80046c6: 687b ldr r3, [r7, #4] - 80046c8: 2200 movs r2, #0 - 80046ca: 66da str r2, [r3, #108] @ 0x6c + 800474a: 687b ldr r3, [r7, #4] + 800474c: 2200 movs r2, #0 + 800474e: 66da str r2, [r3, #108] @ 0x6c /* Reset RxIsr function pointer */ huart->RxISR = NULL; - 80046cc: 687b ldr r3, [r7, #4] - 80046ce: 2200 movs r2, #0 - 80046d0: 675a str r2, [r3, #116] @ 0x74 + 8004750: 687b ldr r3, [r7, #4] + 8004752: 2200 movs r2, #0 + 8004754: 675a str r2, [r3, #116] @ 0x74 } - 80046d2: 46c0 nop @ (mov r8, r8) - 80046d4: 46bd mov sp, r7 - 80046d6: b00e add sp, #56 @ 0x38 - 80046d8: bd80 pop {r7, pc} - 80046da: 46c0 nop @ (mov r8, r8) - 80046dc: fffffedf .word 0xfffffedf - 80046e0: effffffe .word 0xeffffffe + 8004756: 46c0 nop @ (mov r8, r8) + 8004758: 46bd mov sp, r7 + 800475a: b00e add sp, #56 @ 0x38 + 800475c: bd80 pop {r7, pc} + 800475e: 46c0 nop @ (mov r8, r8) + 8004760: fffffedf .word 0xfffffedf + 8004764: effffffe .word 0xeffffffe -080046e4 : +08004768 : * @brief DMA UART receive process complete callback. * @param hdma DMA handle. * @retval None */ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { - 80046e4: b580 push {r7, lr} - 80046e6: b094 sub sp, #80 @ 0x50 - 80046e8: af00 add r7, sp, #0 - 80046ea: 6078 str r0, [r7, #4] + 8004768: b580 push {r7, lr} + 800476a: b094 sub sp, #80 @ 0x50 + 800476c: af00 add r7, sp, #0 + 800476e: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - 80046ec: 687b ldr r3, [r7, #4] - 80046ee: 6a9b ldr r3, [r3, #40] @ 0x28 - 80046f0: 64fb str r3, [r7, #76] @ 0x4c + 8004770: 687b ldr r3, [r7, #4] + 8004772: 6a9b ldr r3, [r3, #40] @ 0x28 + 8004774: 64fb str r3, [r7, #76] @ 0x4c /* DMA Normal mode */ if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) - 80046f2: 687b ldr r3, [r7, #4] - 80046f4: 681b ldr r3, [r3, #0] - 80046f6: 681b ldr r3, [r3, #0] - 80046f8: 2220 movs r2, #32 - 80046fa: 4013 ands r3, r2 - 80046fc: d16f bne.n 80047de + 8004776: 687b ldr r3, [r7, #4] + 8004778: 681b ldr r3, [r3, #0] + 800477a: 681b ldr r3, [r3, #0] + 800477c: 2220 movs r2, #32 + 800477e: 4013 ands r3, r2 + 8004780: d16f bne.n 8004862 { huart->RxXferCount = 0U; - 80046fe: 6cfb ldr r3, [r7, #76] @ 0x4c - 8004700: 225e movs r2, #94 @ 0x5e - 8004702: 2100 movs r1, #0 - 8004704: 5299 strh r1, [r3, r2] + 8004782: 6cfb ldr r3, [r7, #76] @ 0x4c + 8004784: 225e movs r2, #94 @ 0x5e + 8004786: 2100 movs r1, #0 + 8004788: 5299 strh r1, [r3, r2] __ASM volatile ("MRS %0, primask" : "=r" (result) ); - 8004706: f3ef 8310 mrs r3, PRIMASK - 800470a: 617b str r3, [r7, #20] + 800478a: f3ef 8310 mrs r3, PRIMASK + 800478e: 617b str r3, [r7, #20] return(result); - 800470c: 697b ldr r3, [r7, #20] + 8004790: 697b ldr r3, [r7, #20] /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - 800470e: 64bb str r3, [r7, #72] @ 0x48 - 8004710: 2301 movs r3, #1 - 8004712: 61bb str r3, [r7, #24] + 8004792: 64bb str r3, [r7, #72] @ 0x48 + 8004794: 2301 movs r3, #1 + 8004796: 61bb str r3, [r7, #24] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 8004714: 69bb ldr r3, [r7, #24] - 8004716: f383 8810 msr PRIMASK, r3 + 8004798: 69bb ldr r3, [r7, #24] + 800479a: f383 8810 msr PRIMASK, r3 } - 800471a: 46c0 nop @ (mov r8, r8) - 800471c: 6cfb ldr r3, [r7, #76] @ 0x4c - 800471e: 681b ldr r3, [r3, #0] - 8004720: 681a ldr r2, [r3, #0] - 8004722: 6cfb ldr r3, [r7, #76] @ 0x4c - 8004724: 681b ldr r3, [r3, #0] - 8004726: 4948 ldr r1, [pc, #288] @ (8004848 ) - 8004728: 400a ands r2, r1 - 800472a: 601a str r2, [r3, #0] - 800472c: 6cbb ldr r3, [r7, #72] @ 0x48 - 800472e: 61fb str r3, [r7, #28] + 800479e: 46c0 nop @ (mov r8, r8) + 80047a0: 6cfb ldr r3, [r7, #76] @ 0x4c + 80047a2: 681b ldr r3, [r3, #0] + 80047a4: 681a ldr r2, [r3, #0] + 80047a6: 6cfb ldr r3, [r7, #76] @ 0x4c + 80047a8: 681b ldr r3, [r3, #0] + 80047aa: 4948 ldr r1, [pc, #288] @ (80048cc ) + 80047ac: 400a ands r2, r1 + 80047ae: 601a str r2, [r3, #0] + 80047b0: 6cbb ldr r3, [r7, #72] @ 0x48 + 80047b2: 61fb str r3, [r7, #28] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 8004730: 69fb ldr r3, [r7, #28] - 8004732: f383 8810 msr PRIMASK, r3 + 80047b4: 69fb ldr r3, [r7, #28] + 80047b6: f383 8810 msr PRIMASK, r3 } - 8004736: 46c0 nop @ (mov r8, r8) + 80047ba: 46c0 nop @ (mov r8, r8) __ASM volatile ("MRS %0, primask" : "=r" (result) ); - 8004738: f3ef 8310 mrs r3, PRIMASK - 800473c: 623b str r3, [r7, #32] + 80047bc: f3ef 8310 mrs r3, PRIMASK + 80047c0: 623b str r3, [r7, #32] return(result); - 800473e: 6a3b ldr r3, [r7, #32] + 80047c2: 6a3b ldr r3, [r7, #32] ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - 8004740: 647b str r3, [r7, #68] @ 0x44 - 8004742: 2301 movs r3, #1 - 8004744: 627b str r3, [r7, #36] @ 0x24 + 80047c4: 647b str r3, [r7, #68] @ 0x44 + 80047c6: 2301 movs r3, #1 + 80047c8: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 8004746: 6a7b ldr r3, [r7, #36] @ 0x24 - 8004748: f383 8810 msr PRIMASK, r3 + 80047ca: 6a7b ldr r3, [r7, #36] @ 0x24 + 80047cc: f383 8810 msr PRIMASK, r3 } - 800474c: 46c0 nop @ (mov r8, r8) - 800474e: 6cfb ldr r3, [r7, #76] @ 0x4c - 8004750: 681b ldr r3, [r3, #0] - 8004752: 689a ldr r2, [r3, #8] - 8004754: 6cfb ldr r3, [r7, #76] @ 0x4c - 8004756: 681b ldr r3, [r3, #0] - 8004758: 2101 movs r1, #1 - 800475a: 438a bics r2, r1 - 800475c: 609a str r2, [r3, #8] - 800475e: 6c7b ldr r3, [r7, #68] @ 0x44 - 8004760: 62bb str r3, [r7, #40] @ 0x28 + 80047d0: 46c0 nop @ (mov r8, r8) + 80047d2: 6cfb ldr r3, [r7, #76] @ 0x4c + 80047d4: 681b ldr r3, [r3, #0] + 80047d6: 689a ldr r2, [r3, #8] + 80047d8: 6cfb ldr r3, [r7, #76] @ 0x4c + 80047da: 681b ldr r3, [r3, #0] + 80047dc: 2101 movs r1, #1 + 80047de: 438a bics r2, r1 + 80047e0: 609a str r2, [r3, #8] + 80047e2: 6c7b ldr r3, [r7, #68] @ 0x44 + 80047e4: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 8004762: 6abb ldr r3, [r7, #40] @ 0x28 - 8004764: f383 8810 msr PRIMASK, r3 + 80047e6: 6abb ldr r3, [r7, #40] @ 0x28 + 80047e8: f383 8810 msr PRIMASK, r3 } - 8004768: 46c0 nop @ (mov r8, r8) + 80047ec: 46c0 nop @ (mov r8, r8) __ASM volatile ("MRS %0, primask" : "=r" (result) ); - 800476a: f3ef 8310 mrs r3, PRIMASK - 800476e: 62fb str r3, [r7, #44] @ 0x2c + 80047ee: f3ef 8310 mrs r3, PRIMASK + 80047f2: 62fb str r3, [r7, #44] @ 0x2c return(result); - 8004770: 6afb ldr r3, [r7, #44] @ 0x2c + 80047f4: 6afb ldr r3, [r7, #44] @ 0x2c /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - 8004772: 643b str r3, [r7, #64] @ 0x40 - 8004774: 2301 movs r3, #1 - 8004776: 633b str r3, [r7, #48] @ 0x30 + 80047f6: 643b str r3, [r7, #64] @ 0x40 + 80047f8: 2301 movs r3, #1 + 80047fa: 633b str r3, [r7, #48] @ 0x30 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 8004778: 6b3b ldr r3, [r7, #48] @ 0x30 - 800477a: f383 8810 msr PRIMASK, r3 + 80047fc: 6b3b ldr r3, [r7, #48] @ 0x30 + 80047fe: f383 8810 msr PRIMASK, r3 } - 800477e: 46c0 nop @ (mov r8, r8) - 8004780: 6cfb ldr r3, [r7, #76] @ 0x4c - 8004782: 681b ldr r3, [r3, #0] - 8004784: 689a ldr r2, [r3, #8] - 8004786: 6cfb ldr r3, [r7, #76] @ 0x4c - 8004788: 681b ldr r3, [r3, #0] - 800478a: 2140 movs r1, #64 @ 0x40 - 800478c: 438a bics r2, r1 - 800478e: 609a str r2, [r3, #8] - 8004790: 6c3b ldr r3, [r7, #64] @ 0x40 - 8004792: 637b str r3, [r7, #52] @ 0x34 + 8004802: 46c0 nop @ (mov r8, r8) + 8004804: 6cfb ldr r3, [r7, #76] @ 0x4c + 8004806: 681b ldr r3, [r3, #0] + 8004808: 689a ldr r2, [r3, #8] + 800480a: 6cfb ldr r3, [r7, #76] @ 0x4c + 800480c: 681b ldr r3, [r3, #0] + 800480e: 2140 movs r1, #64 @ 0x40 + 8004810: 438a bics r2, r1 + 8004812: 609a str r2, [r3, #8] + 8004814: 6c3b ldr r3, [r7, #64] @ 0x40 + 8004816: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 8004794: 6b7b ldr r3, [r7, #52] @ 0x34 - 8004796: f383 8810 msr PRIMASK, r3 + 8004818: 6b7b ldr r3, [r7, #52] @ 0x34 + 800481a: f383 8810 msr PRIMASK, r3 } - 800479a: 46c0 nop @ (mov r8, r8) + 800481e: 46c0 nop @ (mov r8, r8) /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - 800479c: 6cfb ldr r3, [r7, #76] @ 0x4c - 800479e: 228c movs r2, #140 @ 0x8c - 80047a0: 2120 movs r1, #32 - 80047a2: 5099 str r1, [r3, r2] + 8004820: 6cfb ldr r3, [r7, #76] @ 0x4c + 8004822: 228c movs r2, #140 @ 0x8c + 8004824: 2120 movs r1, #32 + 8004826: 5099 str r1, [r3, r2] /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - 80047a4: 6cfb ldr r3, [r7, #76] @ 0x4c - 80047a6: 6edb ldr r3, [r3, #108] @ 0x6c - 80047a8: 2b01 cmp r3, #1 - 80047aa: d118 bne.n 80047de + 8004828: 6cfb ldr r3, [r7, #76] @ 0x4c + 800482a: 6edb ldr r3, [r3, #108] @ 0x6c + 800482c: 2b01 cmp r3, #1 + 800482e: d118 bne.n 8004862 __ASM volatile ("MRS %0, primask" : "=r" (result) ); - 80047ac: f3ef 8310 mrs r3, PRIMASK - 80047b0: 60bb str r3, [r7, #8] + 8004830: f3ef 8310 mrs r3, PRIMASK + 8004834: 60bb str r3, [r7, #8] return(result); - 80047b2: 68bb ldr r3, [r7, #8] + 8004836: 68bb ldr r3, [r7, #8] { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - 80047b4: 63fb str r3, [r7, #60] @ 0x3c - 80047b6: 2301 movs r3, #1 - 80047b8: 60fb str r3, [r7, #12] + 8004838: 63fb str r3, [r7, #60] @ 0x3c + 800483a: 2301 movs r3, #1 + 800483c: 60fb str r3, [r7, #12] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 80047ba: 68fb ldr r3, [r7, #12] - 80047bc: f383 8810 msr PRIMASK, r3 + 800483e: 68fb ldr r3, [r7, #12] + 8004840: f383 8810 msr PRIMASK, r3 } - 80047c0: 46c0 nop @ (mov r8, r8) - 80047c2: 6cfb ldr r3, [r7, #76] @ 0x4c - 80047c4: 681b ldr r3, [r3, #0] - 80047c6: 681a ldr r2, [r3, #0] - 80047c8: 6cfb ldr r3, [r7, #76] @ 0x4c - 80047ca: 681b ldr r3, [r3, #0] - 80047cc: 2110 movs r1, #16 - 80047ce: 438a bics r2, r1 - 80047d0: 601a str r2, [r3, #0] - 80047d2: 6bfb ldr r3, [r7, #60] @ 0x3c - 80047d4: 613b str r3, [r7, #16] + 8004844: 46c0 nop @ (mov r8, r8) + 8004846: 6cfb ldr r3, [r7, #76] @ 0x4c + 8004848: 681b ldr r3, [r3, #0] + 800484a: 681a ldr r2, [r3, #0] + 800484c: 6cfb ldr r3, [r7, #76] @ 0x4c + 800484e: 681b ldr r3, [r3, #0] + 8004850: 2110 movs r1, #16 + 8004852: 438a bics r2, r1 + 8004854: 601a str r2, [r3, #0] + 8004856: 6bfb ldr r3, [r7, #60] @ 0x3c + 8004858: 613b str r3, [r7, #16] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 80047d6: 693b ldr r3, [r7, #16] - 80047d8: f383 8810 msr PRIMASK, r3 + 800485a: 693b ldr r3, [r7, #16] + 800485c: f383 8810 msr PRIMASK, r3 } - 80047dc: 46c0 nop @ (mov r8, r8) + 8004860: 46c0 nop @ (mov r8, r8) } } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; - 80047de: 6cfb ldr r3, [r7, #76] @ 0x4c - 80047e0: 2200 movs r2, #0 - 80047e2: 671a str r2, [r3, #112] @ 0x70 + 8004862: 6cfb ldr r3, [r7, #76] @ 0x4c + 8004864: 2200 movs r2, #0 + 8004866: 671a str r2, [r3, #112] @ 0x70 /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - 80047e4: 6cfb ldr r3, [r7, #76] @ 0x4c - 80047e6: 6edb ldr r3, [r3, #108] @ 0x6c - 80047e8: 2b01 cmp r3, #1 - 80047ea: d124 bne.n 8004836 + 8004868: 6cfb ldr r3, [r7, #76] @ 0x4c + 800486a: 6edb ldr r3, [r3, #108] @ 0x6c + 800486c: 2b01 cmp r3, #1 + 800486e: d124 bne.n 80048ba { huart->RxXferCount = 0; - 80047ec: 6cfb ldr r3, [r7, #76] @ 0x4c - 80047ee: 225e movs r2, #94 @ 0x5e - 80047f0: 2100 movs r1, #0 - 80047f2: 5299 strh r1, [r3, r2] + 8004870: 6cfb ldr r3, [r7, #76] @ 0x4c + 8004872: 225e movs r2, #94 @ 0x5e + 8004874: 2100 movs r1, #0 + 8004876: 5299 strh r1, [r3, r2] /* Check current nb of data still to be received on DMA side. DMA Normal mode, remaining nb of data will be 0 DMA Circular mode, remaining nb of data is reset to RxXferSize */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma); - 80047f4: 687b ldr r3, [r7, #4] - 80047f6: 681b ldr r3, [r3, #0] - 80047f8: 685a ldr r2, [r3, #4] - 80047fa: 213a movs r1, #58 @ 0x3a - 80047fc: 187b adds r3, r7, r1 - 80047fe: 801a strh r2, [r3, #0] - if (nb_remaining_rx_data < huart->RxXferSize) - 8004800: 6cfb ldr r3, [r7, #76] @ 0x4c - 8004802: 225c movs r2, #92 @ 0x5c - 8004804: 5a9b ldrh r3, [r3, r2] - 8004806: 187a adds r2, r7, r1 - 8004808: 8812 ldrh r2, [r2, #0] - 800480a: 429a cmp r2, r3 - 800480c: d204 bcs.n 8004818 - { - /* Update nb of remaining data */ - huart->RxXferCount = nb_remaining_rx_data; - 800480e: 6cfb ldr r3, [r7, #76] @ 0x4c - 8004810: 187a adds r2, r7, r1 - 8004812: 215e movs r1, #94 @ 0x5e - 8004814: 8812 ldrh r2, [r2, #0] - 8004816: 525a strh r2, [r3, r1] -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); -#else - /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); - 8004818: 6cfb ldr r3, [r7, #76] @ 0x4c - 800481a: 225c movs r2, #92 @ 0x5c - 800481c: 5a9a ldrh r2, [r3, r2] - 800481e: 6cfb ldr r3, [r7, #76] @ 0x4c - 8004820: 215e movs r1, #94 @ 0x5e - 8004822: 5a5b ldrh r3, [r3, r1] - 8004824: b29b uxth r3, r3 - 8004826: 1ad3 subs r3, r2, r3 - 8004828: b29a uxth r2, r3 - 800482a: 6cfb ldr r3, [r7, #76] @ 0x4c - 800482c: 0011 movs r1, r2 - 800482e: 0018 movs r0, r3 - 8004830: f7fc fbf8 bl 8001024 -#else - /*Call legacy weak Rx complete callback*/ - HAL_UART_RxCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } -} - 8004834: e003 b.n 800483e - HAL_UART_RxCpltCallback(huart); - 8004836: 6cfb ldr r3, [r7, #76] @ 0x4c - 8004838: 0018 movs r0, r3 - 800483a: f7ff faa3 bl 8003d84 -} - 800483e: 46c0 nop @ (mov r8, r8) - 8004840: 46bd mov sp, r7 - 8004842: b014 add sp, #80 @ 0x50 - 8004844: bd80 pop {r7, pc} - 8004846: 46c0 nop @ (mov r8, r8) - 8004848: fffffeff .word 0xfffffeff - -0800484c : - * @brief DMA UART receive process half complete callback. - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) -{ - 800484c: b580 push {r7, lr} - 800484e: b084 sub sp, #16 - 8004850: af00 add r7, sp, #0 - 8004852: 6078 str r0, [r7, #4] - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - 8004854: 687b ldr r3, [r7, #4] - 8004856: 6a9b ldr r3, [r3, #40] @ 0x28 - 8004858: 60fb str r3, [r7, #12] - - /* Initialize type of RxEvent that correspond to RxEvent callback execution; - In this case, Rx Event type is Half Transfer */ - huart->RxEventType = HAL_UART_RXEVENT_HT; - 800485a: 68fb ldr r3, [r7, #12] - 800485c: 2201 movs r2, #1 - 800485e: 671a str r2, [r3, #112] @ 0x70 - - /* Check current reception Mode : - If Reception till IDLE event has been selected : use Rx Event callback */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - 8004860: 68fb ldr r3, [r7, #12] - 8004862: 6edb ldr r3, [r3, #108] @ 0x6c - 8004864: 2b01 cmp r3, #1 - 8004866: d128 bne.n 80048ba - { - huart->RxXferCount = huart->RxXferSize / 2U; - 8004868: 68fb ldr r3, [r7, #12] - 800486a: 225c movs r2, #92 @ 0x5c - 800486c: 5a9b ldrh r3, [r3, r2] - 800486e: 085b lsrs r3, r3, #1 - 8004870: b299 uxth r1, r3 - 8004872: 68fb ldr r3, [r7, #12] - 8004874: 225e movs r2, #94 @ 0x5e - 8004876: 5299 strh r1, [r3, r2] - - /* Check current nb of data still to be received on DMA side. */ - uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma); 8004878: 687b ldr r3, [r7, #4] 800487a: 681b ldr r3, [r3, #0] 800487c: 685a ldr r2, [r3, #4] - 800487e: 210a movs r1, #10 + 800487e: 213a movs r1, #58 @ 0x3a 8004880: 187b adds r3, r7, r1 8004882: 801a strh r2, [r3, #0] - if (nb_remaining_rx_data <= huart->RxXferSize) - 8004884: 68fb ldr r3, [r7, #12] + if (nb_remaining_rx_data < huart->RxXferSize) + 8004884: 6cfb ldr r3, [r7, #76] @ 0x4c 8004886: 225c movs r2, #92 @ 0x5c 8004888: 5a9b ldrh r3, [r3, r2] 800488a: 187a adds r2, r7, r1 800488c: 8812 ldrh r2, [r2, #0] 800488e: 429a cmp r2, r3 - 8004890: d804 bhi.n 800489c + 8004890: d204 bcs.n 800489c { /* Update nb of remaining data */ huart->RxXferCount = nb_remaining_rx_data; - 8004892: 68fb ldr r3, [r7, #12] + 8004892: 6cfb ldr r3, [r7, #76] @ 0x4c 8004894: 187a adds r2, r7, r1 8004896: 215e movs r1, #94 @ 0x5e 8004898: 8812 ldrh r2, [r2, #0] @@ -13355,479 +13349,479 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); - 800489c: 68fb ldr r3, [r7, #12] + 800489c: 6cfb ldr r3, [r7, #76] @ 0x4c 800489e: 225c movs r2, #92 @ 0x5c 80048a0: 5a9a ldrh r2, [r3, r2] - 80048a2: 68fb ldr r3, [r7, #12] + 80048a2: 6cfb ldr r3, [r7, #76] @ 0x4c 80048a4: 215e movs r1, #94 @ 0x5e 80048a6: 5a5b ldrh r3, [r3, r1] 80048a8: b29b uxth r3, r3 80048aa: 1ad3 subs r3, r2, r3 80048ac: b29a uxth r2, r3 - 80048ae: 68fb ldr r3, [r7, #12] + 80048ae: 6cfb ldr r3, [r7, #76] @ 0x4c 80048b0: 0011 movs r1, r2 80048b2: 0018 movs r0, r3 - 80048b4: f7fc fbb6 bl 8001024 + 80048b4: f7fc fbd2 bl 800105c +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + 80048b8: e003 b.n 80048c2 + HAL_UART_RxCpltCallback(huart); + 80048ba: 6cfb ldr r3, [r7, #76] @ 0x4c + 80048bc: 0018 movs r0, r3 + 80048be: f7ff faa3 bl 8003e08 +} + 80048c2: 46c0 nop @ (mov r8, r8) + 80048c4: 46bd mov sp, r7 + 80048c6: b014 add sp, #80 @ 0x50 + 80048c8: bd80 pop {r7, pc} + 80048ca: 46c0 nop @ (mov r8, r8) + 80048cc: fffffeff .word 0xfffffeff + +080048d0 : + * @brief DMA UART receive process half complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +{ + 80048d0: b580 push {r7, lr} + 80048d2: b084 sub sp, #16 + 80048d4: af00 add r7, sp, #0 + 80048d6: 6078 str r0, [r7, #4] + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 80048d8: 687b ldr r3, [r7, #4] + 80048da: 6a9b ldr r3, [r3, #40] @ 0x28 + 80048dc: 60fb str r3, [r7, #12] + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Half Transfer */ + huart->RxEventType = HAL_UART_RXEVENT_HT; + 80048de: 68fb ldr r3, [r7, #12] + 80048e0: 2201 movs r2, #1 + 80048e2: 671a str r2, [r3, #112] @ 0x70 + + /* Check current reception Mode : + If Reception till IDLE event has been selected : use Rx Event callback */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + 80048e4: 68fb ldr r3, [r7, #12] + 80048e6: 6edb ldr r3, [r3, #108] @ 0x6c + 80048e8: 2b01 cmp r3, #1 + 80048ea: d128 bne.n 800493e + { + huart->RxXferCount = huart->RxXferSize / 2U; + 80048ec: 68fb ldr r3, [r7, #12] + 80048ee: 225c movs r2, #92 @ 0x5c + 80048f0: 5a9b ldrh r3, [r3, r2] + 80048f2: 085b lsrs r3, r3, #1 + 80048f4: b299 uxth r1, r3 + 80048f6: 68fb ldr r3, [r7, #12] + 80048f8: 225e movs r2, #94 @ 0x5e + 80048fa: 5299 strh r1, [r3, r2] + + /* Check current nb of data still to be received on DMA side. */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma); + 80048fc: 687b ldr r3, [r7, #4] + 80048fe: 681b ldr r3, [r3, #0] + 8004900: 685a ldr r2, [r3, #4] + 8004902: 210a movs r1, #10 + 8004904: 187b adds r3, r7, r1 + 8004906: 801a strh r2, [r3, #0] + if (nb_remaining_rx_data <= huart->RxXferSize) + 8004908: 68fb ldr r3, [r7, #12] + 800490a: 225c movs r2, #92 @ 0x5c + 800490c: 5a9b ldrh r3, [r3, r2] + 800490e: 187a adds r2, r7, r1 + 8004910: 8812 ldrh r2, [r2, #0] + 8004912: 429a cmp r2, r3 + 8004914: d804 bhi.n 8004920 + { + /* Update nb of remaining data */ + huart->RxXferCount = nb_remaining_rx_data; + 8004916: 68fb ldr r3, [r7, #12] + 8004918: 187a adds r2, r7, r1 + 800491a: 215e movs r1, #94 @ 0x5e + 800491c: 8812 ldrh r2, [r2, #0] + 800491e: 525a strh r2, [r3, r1] +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); + 8004920: 68fb ldr r3, [r7, #12] + 8004922: 225c movs r2, #92 @ 0x5c + 8004924: 5a9a ldrh r2, [r3, r2] + 8004926: 68fb ldr r3, [r7, #12] + 8004928: 215e movs r1, #94 @ 0x5e + 800492a: 5a5b ldrh r3, [r3, r1] + 800492c: b29b uxth r3, r3 + 800492e: 1ad3 subs r3, r2, r3 + 8004930: b29a uxth r2, r3 + 8004932: 68fb ldr r3, [r7, #12] + 8004934: 0011 movs r1, r2 + 8004936: 0018 movs r0, r3 + 8004938: f7fc fb90 bl 800105c #else /*Call legacy weak Rx Half complete callback*/ HAL_UART_RxHalfCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } - 80048b8: e003 b.n 80048c2 + 800493c: e003 b.n 8004946 HAL_UART_RxHalfCpltCallback(huart); - 80048ba: 68fb ldr r3, [r7, #12] - 80048bc: 0018 movs r0, r3 - 80048be: f7ff fa69 bl 8003d94 + 800493e: 68fb ldr r3, [r7, #12] + 8004940: 0018 movs r0, r3 + 8004942: f7ff fa69 bl 8003e18 } - 80048c2: 46c0 nop @ (mov r8, r8) - 80048c4: 46bd mov sp, r7 - 80048c6: b004 add sp, #16 - 80048c8: bd80 pop {r7, pc} + 8004946: 46c0 nop @ (mov r8, r8) + 8004948: 46bd mov sp, r7 + 800494a: b004 add sp, #16 + 800494c: bd80 pop {r7, pc} -080048ca : +0800494e : * @brief DMA UART communication error callback. * @param hdma DMA handle. * @retval None */ static void UART_DMAError(DMA_HandleTypeDef *hdma) { - 80048ca: b580 push {r7, lr} - 80048cc: b086 sub sp, #24 - 80048ce: af00 add r7, sp, #0 - 80048d0: 6078 str r0, [r7, #4] + 800494e: b580 push {r7, lr} + 8004950: b086 sub sp, #24 + 8004952: af00 add r7, sp, #0 + 8004954: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - 80048d2: 687b ldr r3, [r7, #4] - 80048d4: 6a9b ldr r3, [r3, #40] @ 0x28 - 80048d6: 617b str r3, [r7, #20] + 8004956: 687b ldr r3, [r7, #4] + 8004958: 6a9b ldr r3, [r3, #40] @ 0x28 + 800495a: 617b str r3, [r7, #20] const HAL_UART_StateTypeDef gstate = huart->gState; - 80048d8: 697b ldr r3, [r7, #20] - 80048da: 2288 movs r2, #136 @ 0x88 - 80048dc: 589b ldr r3, [r3, r2] - 80048de: 613b str r3, [r7, #16] + 800495c: 697b ldr r3, [r7, #20] + 800495e: 2288 movs r2, #136 @ 0x88 + 8004960: 589b ldr r3, [r3, r2] + 8004962: 613b str r3, [r7, #16] const HAL_UART_StateTypeDef rxstate = huart->RxState; - 80048e0: 697b ldr r3, [r7, #20] - 80048e2: 228c movs r2, #140 @ 0x8c - 80048e4: 589b ldr r3, [r3, r2] - 80048e6: 60fb str r3, [r7, #12] + 8004964: 697b ldr r3, [r7, #20] + 8004966: 228c movs r2, #140 @ 0x8c + 8004968: 589b ldr r3, [r3, r2] + 800496a: 60fb str r3, [r7, #12] /* Stop UART DMA Tx request if ongoing */ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && - 80048e8: 697b ldr r3, [r7, #20] - 80048ea: 681b ldr r3, [r3, #0] - 80048ec: 689b ldr r3, [r3, #8] - 80048ee: 2280 movs r2, #128 @ 0x80 - 80048f0: 4013 ands r3, r2 - 80048f2: 2b80 cmp r3, #128 @ 0x80 - 80048f4: d10a bne.n 800490c - 80048f6: 693b ldr r3, [r7, #16] - 80048f8: 2b21 cmp r3, #33 @ 0x21 - 80048fa: d107 bne.n 800490c + 800496c: 697b ldr r3, [r7, #20] + 800496e: 681b ldr r3, [r3, #0] + 8004970: 689b ldr r3, [r3, #8] + 8004972: 2280 movs r2, #128 @ 0x80 + 8004974: 4013 ands r3, r2 + 8004976: 2b80 cmp r3, #128 @ 0x80 + 8004978: d10a bne.n 8004990 + 800497a: 693b ldr r3, [r7, #16] + 800497c: 2b21 cmp r3, #33 @ 0x21 + 800497e: d107 bne.n 8004990 (gstate == HAL_UART_STATE_BUSY_TX)) { huart->TxXferCount = 0U; - 80048fc: 697b ldr r3, [r7, #20] - 80048fe: 2256 movs r2, #86 @ 0x56 - 8004900: 2100 movs r1, #0 - 8004902: 5299 strh r1, [r3, r2] + 8004980: 697b ldr r3, [r7, #20] + 8004982: 2256 movs r2, #86 @ 0x56 + 8004984: 2100 movs r1, #0 + 8004986: 5299 strh r1, [r3, r2] UART_EndTxTransfer(huart); - 8004904: 697b ldr r3, [r7, #20] - 8004906: 0018 movs r0, r3 - 8004908: f7ff fe46 bl 8004598 + 8004988: 697b ldr r3, [r7, #20] + 800498a: 0018 movs r0, r3 + 800498c: f7ff fe46 bl 800461c } /* Stop UART DMA Rx request if ongoing */ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && - 800490c: 697b ldr r3, [r7, #20] - 800490e: 681b ldr r3, [r3, #0] - 8004910: 689b ldr r3, [r3, #8] - 8004912: 2240 movs r2, #64 @ 0x40 - 8004914: 4013 ands r3, r2 - 8004916: 2b40 cmp r3, #64 @ 0x40 - 8004918: d10a bne.n 8004930 - 800491a: 68fb ldr r3, [r7, #12] - 800491c: 2b22 cmp r3, #34 @ 0x22 - 800491e: d107 bne.n 8004930 + 8004990: 697b ldr r3, [r7, #20] + 8004992: 681b ldr r3, [r3, #0] + 8004994: 689b ldr r3, [r3, #8] + 8004996: 2240 movs r2, #64 @ 0x40 + 8004998: 4013 ands r3, r2 + 800499a: 2b40 cmp r3, #64 @ 0x40 + 800499c: d10a bne.n 80049b4 + 800499e: 68fb ldr r3, [r7, #12] + 80049a0: 2b22 cmp r3, #34 @ 0x22 + 80049a2: d107 bne.n 80049b4 (rxstate == HAL_UART_STATE_BUSY_RX)) { huart->RxXferCount = 0U; - 8004920: 697b ldr r3, [r7, #20] - 8004922: 225e movs r2, #94 @ 0x5e - 8004924: 2100 movs r1, #0 - 8004926: 5299 strh r1, [r3, r2] + 80049a4: 697b ldr r3, [r7, #20] + 80049a6: 225e movs r2, #94 @ 0x5e + 80049a8: 2100 movs r1, #0 + 80049aa: 5299 strh r1, [r3, r2] UART_EndRxTransfer(huart); - 8004928: 697b ldr r3, [r7, #20] - 800492a: 0018 movs r0, r3 - 800492c: f7ff fe74 bl 8004618 + 80049ac: 697b ldr r3, [r7, #20] + 80049ae: 0018 movs r0, r3 + 80049b0: f7ff fe74 bl 800469c } huart->ErrorCode |= HAL_UART_ERROR_DMA; - 8004930: 697b ldr r3, [r7, #20] - 8004932: 2290 movs r2, #144 @ 0x90 - 8004934: 589b ldr r3, [r3, r2] - 8004936: 2210 movs r2, #16 - 8004938: 431a orrs r2, r3 - 800493a: 697b ldr r3, [r7, #20] - 800493c: 2190 movs r1, #144 @ 0x90 - 800493e: 505a str r2, [r3, r1] + 80049b4: 697b ldr r3, [r7, #20] + 80049b6: 2290 movs r2, #144 @ 0x90 + 80049b8: 589b ldr r3, [r3, r2] + 80049ba: 2210 movs r2, #16 + 80049bc: 431a orrs r2, r3 + 80049be: 697b ldr r3, [r7, #20] + 80049c0: 2190 movs r1, #144 @ 0x90 + 80049c2: 505a str r2, [r3, r1] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); - 8004940: 697b ldr r3, [r7, #20] - 8004942: 0018 movs r0, r3 - 8004944: f7ff fa2e bl 8003da4 + 80049c4: 697b ldr r3, [r7, #20] + 80049c6: 0018 movs r0, r3 + 80049c8: f7ff fa2e bl 8003e28 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } - 8004948: 46c0 nop @ (mov r8, r8) - 800494a: 46bd mov sp, r7 - 800494c: b006 add sp, #24 - 800494e: bd80 pop {r7, pc} + 80049cc: 46c0 nop @ (mov r8, r8) + 80049ce: 46bd mov sp, r7 + 80049d0: b006 add sp, #24 + 80049d2: bd80 pop {r7, pc} -08004950 : +080049d4 : * oversampling rate). * @retval HAL status */ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime) { - 8004950: b580 push {r7, lr} - 8004952: b086 sub sp, #24 - 8004954: af00 add r7, sp, #0 - 8004956: 60f8 str r0, [r7, #12] - 8004958: 60b9 str r1, [r7, #8] - 800495a: 607a str r2, [r7, #4] - 800495c: 603b str r3, [r7, #0] + 80049d4: b580 push {r7, lr} + 80049d6: b086 sub sp, #24 + 80049d8: af00 add r7, sp, #0 + 80049da: 60f8 str r0, [r7, #12] + 80049dc: 60b9 str r1, [r7, #8] + 80049de: 607a str r2, [r7, #4] + 80049e0: 603b str r3, [r7, #0] uint32_t temp; /* Check the UART handle allocation */ if (huart == NULL) - 800495e: 68fb ldr r3, [r7, #12] - 8004960: 2b00 cmp r3, #0 - 8004962: d101 bne.n 8004968 + 80049e2: 68fb ldr r3, [r7, #12] + 80049e4: 2b00 cmp r3, #0 + 80049e6: d101 bne.n 80049ec { return HAL_ERROR; - 8004964: 2301 movs r3, #1 - 8004966: e05d b.n 8004a24 + 80049e8: 2301 movs r3, #1 + 80049ea: e05d b.n 8004aa8 assert_param(IS_UART_ASSERTIONTIME(AssertionTime)); /* Check the Driver Enable deassertion time */ assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime)); if (huart->gState == HAL_UART_STATE_RESET) - 8004968: 68fb ldr r3, [r7, #12] - 800496a: 2288 movs r2, #136 @ 0x88 - 800496c: 589b ldr r3, [r3, r2] - 800496e: 2b00 cmp r3, #0 - 8004970: d107 bne.n 8004982 + 80049ec: 68fb ldr r3, [r7, #12] + 80049ee: 2288 movs r2, #136 @ 0x88 + 80049f0: 589b ldr r3, [r3, r2] + 80049f2: 2b00 cmp r3, #0 + 80049f4: d107 bne.n 8004a06 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; - 8004972: 68fb ldr r3, [r7, #12] - 8004974: 2284 movs r2, #132 @ 0x84 - 8004976: 2100 movs r1, #0 - 8004978: 5499 strb r1, [r3, r2] + 80049f6: 68fb ldr r3, [r7, #12] + 80049f8: 2284 movs r2, #132 @ 0x84 + 80049fa: 2100 movs r1, #0 + 80049fc: 5499 strb r1, [r3, r2] /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK, CORTEX */ HAL_UART_MspInit(huart); - 800497a: 68fb ldr r3, [r7, #12] - 800497c: 0018 movs r0, r3 - 800497e: f7fc fcd5 bl 800132c + 80049fe: 68fb ldr r3, [r7, #12] + 8004a00: 0018 movs r0, r3 + 8004a02: f7fc fcd5 bl 80013b0 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; - 8004982: 68fb ldr r3, [r7, #12] - 8004984: 2288 movs r2, #136 @ 0x88 - 8004986: 2124 movs r1, #36 @ 0x24 - 8004988: 5099 str r1, [r3, r2] + 8004a06: 68fb ldr r3, [r7, #12] + 8004a08: 2288 movs r2, #136 @ 0x88 + 8004a0a: 2124 movs r1, #36 @ 0x24 + 8004a0c: 5099 str r1, [r3, r2] /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - 800498a: 68fb ldr r3, [r7, #12] - 800498c: 681b ldr r3, [r3, #0] - 800498e: 681a ldr r2, [r3, #0] - 8004990: 68fb ldr r3, [r7, #12] - 8004992: 681b ldr r3, [r3, #0] - 8004994: 2101 movs r1, #1 - 8004996: 438a bics r2, r1 - 8004998: 601a str r2, [r3, #0] + 8004a0e: 68fb ldr r3, [r7, #12] + 8004a10: 681b ldr r3, [r3, #0] + 8004a12: 681a ldr r2, [r3, #0] + 8004a14: 68fb ldr r3, [r7, #12] + 8004a16: 681b ldr r3, [r3, #0] + 8004a18: 2101 movs r1, #1 + 8004a1a: 438a bics r2, r1 + 8004a1c: 601a str r2, [r3, #0] /* Perform advanced settings configuration */ /* For some items, configuration requires to be done prior TE and RE bits are set */ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - 800499a: 68fb ldr r3, [r7, #12] - 800499c: 6a9b ldr r3, [r3, #40] @ 0x28 - 800499e: 2b00 cmp r3, #0 - 80049a0: d003 beq.n 80049aa + 8004a1e: 68fb ldr r3, [r7, #12] + 8004a20: 6a9b ldr r3, [r3, #40] @ 0x28 + 8004a22: 2b00 cmp r3, #0 + 8004a24: d003 beq.n 8004a2e { UART_AdvFeatureConfig(huart); - 80049a2: 68fb ldr r3, [r7, #12] - 80049a4: 0018 movs r0, r3 - 80049a6: f7ff fb83 bl 80040b0 + 8004a26: 68fb ldr r3, [r7, #12] + 8004a28: 0018 movs r0, r3 + 8004a2a: f7ff fb83 bl 8004134 } /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) - 80049aa: 68fb ldr r3, [r7, #12] - 80049ac: 0018 movs r0, r3 - 80049ae: f7ff fa01 bl 8003db4 - 80049b2: 0003 movs r3, r0 - 80049b4: 2b01 cmp r3, #1 - 80049b6: d101 bne.n 80049bc + 8004a2e: 68fb ldr r3, [r7, #12] + 8004a30: 0018 movs r0, r3 + 8004a32: f7ff fa01 bl 8003e38 + 8004a36: 0003 movs r3, r0 + 8004a38: 2b01 cmp r3, #1 + 8004a3a: d101 bne.n 8004a40 { return HAL_ERROR; - 80049b8: 2301 movs r3, #1 - 80049ba: e033 b.n 8004a24 + 8004a3c: 2301 movs r3, #1 + 8004a3e: e033 b.n 8004aa8 } /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ SET_BIT(huart->Instance->CR3, USART_CR3_DEM); - 80049bc: 68fb ldr r3, [r7, #12] - 80049be: 681b ldr r3, [r3, #0] - 80049c0: 689a ldr r2, [r3, #8] - 80049c2: 68fb ldr r3, [r7, #12] - 80049c4: 681b ldr r3, [r3, #0] - 80049c6: 2180 movs r1, #128 @ 0x80 - 80049c8: 01c9 lsls r1, r1, #7 - 80049ca: 430a orrs r2, r1 - 80049cc: 609a str r2, [r3, #8] + 8004a40: 68fb ldr r3, [r7, #12] + 8004a42: 681b ldr r3, [r3, #0] + 8004a44: 689a ldr r2, [r3, #8] + 8004a46: 68fb ldr r3, [r7, #12] + 8004a48: 681b ldr r3, [r3, #0] + 8004a4a: 2180 movs r1, #128 @ 0x80 + 8004a4c: 01c9 lsls r1, r1, #7 + 8004a4e: 430a orrs r2, r1 + 8004a50: 609a str r2, [r3, #8] /* Set the Driver Enable polarity */ MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity); - 80049ce: 68fb ldr r3, [r7, #12] - 80049d0: 681b ldr r3, [r3, #0] - 80049d2: 689b ldr r3, [r3, #8] - 80049d4: 4a15 ldr r2, [pc, #84] @ (8004a2c ) - 80049d6: 4013 ands r3, r2 - 80049d8: 0019 movs r1, r3 - 80049da: 68fb ldr r3, [r7, #12] - 80049dc: 681b ldr r3, [r3, #0] - 80049de: 68ba ldr r2, [r7, #8] - 80049e0: 430a orrs r2, r1 - 80049e2: 609a str r2, [r3, #8] + 8004a52: 68fb ldr r3, [r7, #12] + 8004a54: 681b ldr r3, [r3, #0] + 8004a56: 689b ldr r3, [r3, #8] + 8004a58: 4a15 ldr r2, [pc, #84] @ (8004ab0 ) + 8004a5a: 4013 ands r3, r2 + 8004a5c: 0019 movs r1, r3 + 8004a5e: 68fb ldr r3, [r7, #12] + 8004a60: 681b ldr r3, [r3, #0] + 8004a62: 68ba ldr r2, [r7, #8] + 8004a64: 430a orrs r2, r1 + 8004a66: 609a str r2, [r3, #8] /* Set the Driver Enable assertion and deassertion times */ temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS); - 80049e4: 687b ldr r3, [r7, #4] - 80049e6: 055b lsls r3, r3, #21 - 80049e8: 617b str r3, [r7, #20] + 8004a68: 687b ldr r3, [r7, #4] + 8004a6a: 055b lsls r3, r3, #21 + 8004a6c: 617b str r3, [r7, #20] temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS); - 80049ea: 683b ldr r3, [r7, #0] - 80049ec: 041b lsls r3, r3, #16 - 80049ee: 697a ldr r2, [r7, #20] - 80049f0: 4313 orrs r3, r2 - 80049f2: 617b str r3, [r7, #20] + 8004a6e: 683b ldr r3, [r7, #0] + 8004a70: 041b lsls r3, r3, #16 + 8004a72: 697a ldr r2, [r7, #20] + 8004a74: 4313 orrs r3, r2 + 8004a76: 617b str r3, [r7, #20] MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp); - 80049f4: 68fb ldr r3, [r7, #12] - 80049f6: 681b ldr r3, [r3, #0] - 80049f8: 681b ldr r3, [r3, #0] - 80049fa: 4a0d ldr r2, [pc, #52] @ (8004a30 ) - 80049fc: 4013 ands r3, r2 - 80049fe: 0019 movs r1, r3 - 8004a00: 68fb ldr r3, [r7, #12] - 8004a02: 681b ldr r3, [r3, #0] - 8004a04: 697a ldr r2, [r7, #20] - 8004a06: 430a orrs r2, r1 - 8004a08: 601a str r2, [r3, #0] + 8004a78: 68fb ldr r3, [r7, #12] + 8004a7a: 681b ldr r3, [r3, #0] + 8004a7c: 681b ldr r3, [r3, #0] + 8004a7e: 4a0d ldr r2, [pc, #52] @ (8004ab4 ) + 8004a80: 4013 ands r3, r2 + 8004a82: 0019 movs r1, r3 + 8004a84: 68fb ldr r3, [r7, #12] + 8004a86: 681b ldr r3, [r3, #0] + 8004a88: 697a ldr r2, [r7, #20] + 8004a8a: 430a orrs r2, r1 + 8004a8c: 601a str r2, [r3, #0] /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - 8004a0a: 68fb ldr r3, [r7, #12] - 8004a0c: 681b ldr r3, [r3, #0] - 8004a0e: 681a ldr r2, [r3, #0] - 8004a10: 68fb ldr r3, [r7, #12] - 8004a12: 681b ldr r3, [r3, #0] - 8004a14: 2101 movs r1, #1 - 8004a16: 430a orrs r2, r1 - 8004a18: 601a str r2, [r3, #0] + 8004a8e: 68fb ldr r3, [r7, #12] + 8004a90: 681b ldr r3, [r3, #0] + 8004a92: 681a ldr r2, [r3, #0] + 8004a94: 68fb ldr r3, [r7, #12] + 8004a96: 681b ldr r3, [r3, #0] + 8004a98: 2101 movs r1, #1 + 8004a9a: 430a orrs r2, r1 + 8004a9c: 601a str r2, [r3, #0] /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); - 8004a1a: 68fb ldr r3, [r7, #12] - 8004a1c: 0018 movs r0, r3 - 8004a1e: f7ff fbfb bl 8004218 - 8004a22: 0003 movs r3, r0 + 8004a9e: 68fb ldr r3, [r7, #12] + 8004aa0: 0018 movs r0, r3 + 8004aa2: f7ff fbfb bl 800429c + 8004aa6: 0003 movs r3, r0 } - 8004a24: 0018 movs r0, r3 - 8004a26: 46bd mov sp, r7 - 8004a28: b006 add sp, #24 - 8004a2a: bd80 pop {r7, pc} - 8004a2c: ffff7fff .word 0xffff7fff - 8004a30: fc00ffff .word 0xfc00ffff + 8004aa8: 0018 movs r0, r3 + 8004aaa: 46bd mov sp, r7 + 8004aac: b006 add sp, #24 + 8004aae: bd80 pop {r7, pc} + 8004ab0: ffff7fff .word 0xffff7fff + 8004ab4: fc00ffff .word 0xfc00ffff -08004a34 : +08004ab8 : * @brief Disable the FIFO mode. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) { - 8004a34: b580 push {r7, lr} - 8004a36: b084 sub sp, #16 - 8004a38: af00 add r7, sp, #0 - 8004a3a: 6078 str r0, [r7, #4] + 8004ab8: b580 push {r7, lr} + 8004aba: b084 sub sp, #16 + 8004abc: af00 add r7, sp, #0 + 8004abe: 6078 str r0, [r7, #4] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); /* Process Locked */ __HAL_LOCK(huart); - 8004a3c: 687b ldr r3, [r7, #4] - 8004a3e: 2284 movs r2, #132 @ 0x84 - 8004a40: 5c9b ldrb r3, [r3, r2] - 8004a42: 2b01 cmp r3, #1 - 8004a44: d101 bne.n 8004a4a - 8004a46: 2302 movs r3, #2 - 8004a48: e027 b.n 8004a9a - 8004a4a: 687b ldr r3, [r7, #4] - 8004a4c: 2284 movs r2, #132 @ 0x84 - 8004a4e: 2101 movs r1, #1 - 8004a50: 5499 strb r1, [r3, r2] + 8004ac0: 687b ldr r3, [r7, #4] + 8004ac2: 2284 movs r2, #132 @ 0x84 + 8004ac4: 5c9b ldrb r3, [r3, r2] + 8004ac6: 2b01 cmp r3, #1 + 8004ac8: d101 bne.n 8004ace + 8004aca: 2302 movs r3, #2 + 8004acc: e027 b.n 8004b1e + 8004ace: 687b ldr r3, [r7, #4] + 8004ad0: 2284 movs r2, #132 @ 0x84 + 8004ad2: 2101 movs r1, #1 + 8004ad4: 5499 strb r1, [r3, r2] huart->gState = HAL_UART_STATE_BUSY; - 8004a52: 687b ldr r3, [r7, #4] - 8004a54: 2288 movs r2, #136 @ 0x88 - 8004a56: 2124 movs r1, #36 @ 0x24 - 8004a58: 5099 str r1, [r3, r2] + 8004ad6: 687b ldr r3, [r7, #4] + 8004ad8: 2288 movs r2, #136 @ 0x88 + 8004ada: 2124 movs r1, #36 @ 0x24 + 8004adc: 5099 str r1, [r3, r2] /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); - 8004a5a: 687b ldr r3, [r7, #4] - 8004a5c: 681b ldr r3, [r3, #0] - 8004a5e: 681b ldr r3, [r3, #0] - 8004a60: 60fb str r3, [r7, #12] + 8004ade: 687b ldr r3, [r7, #4] + 8004ae0: 681b ldr r3, [r3, #0] + 8004ae2: 681b ldr r3, [r3, #0] + 8004ae4: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); - 8004a62: 687b ldr r3, [r7, #4] - 8004a64: 681b ldr r3, [r3, #0] - 8004a66: 681a ldr r2, [r3, #0] - 8004a68: 687b ldr r3, [r7, #4] - 8004a6a: 681b ldr r3, [r3, #0] - 8004a6c: 2101 movs r1, #1 - 8004a6e: 438a bics r2, r1 - 8004a70: 601a str r2, [r3, #0] + 8004ae6: 687b ldr r3, [r7, #4] + 8004ae8: 681b ldr r3, [r3, #0] + 8004aea: 681a ldr r2, [r3, #0] + 8004aec: 687b ldr r3, [r7, #4] + 8004aee: 681b ldr r3, [r3, #0] + 8004af0: 2101 movs r1, #1 + 8004af2: 438a bics r2, r1 + 8004af4: 601a str r2, [r3, #0] /* Disable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); - 8004a72: 68fb ldr r3, [r7, #12] - 8004a74: 4a0b ldr r2, [pc, #44] @ (8004aa4 ) - 8004a76: 4013 ands r3, r2 - 8004a78: 60fb str r3, [r7, #12] + 8004af6: 68fb ldr r3, [r7, #12] + 8004af8: 4a0b ldr r2, [pc, #44] @ (8004b28 ) + 8004afa: 4013 ands r3, r2 + 8004afc: 60fb str r3, [r7, #12] huart->FifoMode = UART_FIFOMODE_DISABLE; - 8004a7a: 687b ldr r3, [r7, #4] - 8004a7c: 2200 movs r2, #0 - 8004a7e: 665a str r2, [r3, #100] @ 0x64 - - /* Restore UART configuration */ - WRITE_REG(huart->Instance->CR1, tmpcr1); - 8004a80: 687b ldr r3, [r7, #4] - 8004a82: 681b ldr r3, [r3, #0] - 8004a84: 68fa ldr r2, [r7, #12] - 8004a86: 601a str r2, [r3, #0] - - huart->gState = HAL_UART_STATE_READY; - 8004a88: 687b ldr r3, [r7, #4] - 8004a8a: 2288 movs r2, #136 @ 0x88 - 8004a8c: 2120 movs r1, #32 - 8004a8e: 5099 str r1, [r3, r2] - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - 8004a90: 687b ldr r3, [r7, #4] - 8004a92: 2284 movs r2, #132 @ 0x84 - 8004a94: 2100 movs r1, #0 - 8004a96: 5499 strb r1, [r3, r2] - - return HAL_OK; - 8004a98: 2300 movs r3, #0 -} - 8004a9a: 0018 movs r0, r3 - 8004a9c: 46bd mov sp, r7 - 8004a9e: b004 add sp, #16 - 8004aa0: bd80 pop {r7, pc} - 8004aa2: 46c0 nop @ (mov r8, r8) - 8004aa4: dfffffff .word 0xdfffffff - -08004aa8 : - * @arg @ref UART_TXFIFO_THRESHOLD_7_8 - * @arg @ref UART_TXFIFO_THRESHOLD_8_8 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) -{ - 8004aa8: b580 push {r7, lr} - 8004aaa: b084 sub sp, #16 - 8004aac: af00 add r7, sp, #0 - 8004aae: 6078 str r0, [r7, #4] - 8004ab0: 6039 str r1, [r7, #0] - /* Check parameters */ - assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); - assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); - - /* Process Locked */ - __HAL_LOCK(huart); - 8004ab2: 687b ldr r3, [r7, #4] - 8004ab4: 2284 movs r2, #132 @ 0x84 - 8004ab6: 5c9b ldrb r3, [r3, r2] - 8004ab8: 2b01 cmp r3, #1 - 8004aba: d101 bne.n 8004ac0 - 8004abc: 2302 movs r3, #2 - 8004abe: e02e b.n 8004b1e - 8004ac0: 687b ldr r3, [r7, #4] - 8004ac2: 2284 movs r2, #132 @ 0x84 - 8004ac4: 2101 movs r1, #1 - 8004ac6: 5499 strb r1, [r3, r2] - - huart->gState = HAL_UART_STATE_BUSY; - 8004ac8: 687b ldr r3, [r7, #4] - 8004aca: 2288 movs r2, #136 @ 0x88 - 8004acc: 2124 movs r1, #36 @ 0x24 - 8004ace: 5099 str r1, [r3, r2] - - /* Save actual UART configuration */ - tmpcr1 = READ_REG(huart->Instance->CR1); - 8004ad0: 687b ldr r3, [r7, #4] - 8004ad2: 681b ldr r3, [r3, #0] - 8004ad4: 681b ldr r3, [r3, #0] - 8004ad6: 60fb str r3, [r7, #12] - - /* Disable UART */ - __HAL_UART_DISABLE(huart); - 8004ad8: 687b ldr r3, [r7, #4] - 8004ada: 681b ldr r3, [r3, #0] - 8004adc: 681a ldr r2, [r3, #0] - 8004ade: 687b ldr r3, [r7, #4] - 8004ae0: 681b ldr r3, [r3, #0] - 8004ae2: 2101 movs r1, #1 - 8004ae4: 438a bics r2, r1 - 8004ae6: 601a str r2, [r3, #0] - - /* Update TX threshold configuration */ - MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); - 8004ae8: 687b ldr r3, [r7, #4] - 8004aea: 681b ldr r3, [r3, #0] - 8004aec: 689b ldr r3, [r3, #8] - 8004aee: 00db lsls r3, r3, #3 - 8004af0: 08d9 lsrs r1, r3, #3 - 8004af2: 687b ldr r3, [r7, #4] - 8004af4: 681b ldr r3, [r3, #0] - 8004af6: 683a ldr r2, [r7, #0] - 8004af8: 430a orrs r2, r1 - 8004afa: 609a str r2, [r3, #8] - - /* Determine the number of data to process during RX/TX ISR execution */ - UARTEx_SetNbDataToProcess(huart); - 8004afc: 687b ldr r3, [r7, #4] - 8004afe: 0018 movs r0, r3 - 8004b00: f000 f8bc bl 8004c7c + 8004afe: 687b ldr r3, [r7, #4] + 8004b00: 2200 movs r2, #0 + 8004b02: 665a str r2, [r3, #100] @ 0x64 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); @@ -13856,466 +13850,569 @@ HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint3 8004b20: 46bd mov sp, r7 8004b22: b004 add sp, #16 8004b24: bd80 pop {r7, pc} + 8004b26: 46c0 nop @ (mov r8, r8) + 8004b28: dfffffff .word 0xdfffffff + +08004b2c : + * @arg @ref UART_TXFIFO_THRESHOLD_7_8 + * @arg @ref UART_TXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) +{ + 8004b2c: b580 push {r7, lr} + 8004b2e: b084 sub sp, #16 + 8004b30: af00 add r7, sp, #0 + 8004b32: 6078 str r0, [r7, #4] + 8004b34: 6039 str r1, [r7, #0] + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(huart); + 8004b36: 687b ldr r3, [r7, #4] + 8004b38: 2284 movs r2, #132 @ 0x84 + 8004b3a: 5c9b ldrb r3, [r3, r2] + 8004b3c: 2b01 cmp r3, #1 + 8004b3e: d101 bne.n 8004b44 + 8004b40: 2302 movs r3, #2 + 8004b42: e02e b.n 8004ba2 + 8004b44: 687b ldr r3, [r7, #4] + 8004b46: 2284 movs r2, #132 @ 0x84 + 8004b48: 2101 movs r1, #1 + 8004b4a: 5499 strb r1, [r3, r2] + + huart->gState = HAL_UART_STATE_BUSY; + 8004b4c: 687b ldr r3, [r7, #4] + 8004b4e: 2288 movs r2, #136 @ 0x88 + 8004b50: 2124 movs r1, #36 @ 0x24 + 8004b52: 5099 str r1, [r3, r2] + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + 8004b54: 687b ldr r3, [r7, #4] + 8004b56: 681b ldr r3, [r3, #0] + 8004b58: 681b ldr r3, [r3, #0] + 8004b5a: 60fb str r3, [r7, #12] + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + 8004b5c: 687b ldr r3, [r7, #4] + 8004b5e: 681b ldr r3, [r3, #0] + 8004b60: 681a ldr r2, [r3, #0] + 8004b62: 687b ldr r3, [r7, #4] + 8004b64: 681b ldr r3, [r3, #0] + 8004b66: 2101 movs r1, #1 + 8004b68: 438a bics r2, r1 + 8004b6a: 601a str r2, [r3, #0] + + /* Update TX threshold configuration */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); + 8004b6c: 687b ldr r3, [r7, #4] + 8004b6e: 681b ldr r3, [r3, #0] + 8004b70: 689b ldr r3, [r3, #8] + 8004b72: 00db lsls r3, r3, #3 + 8004b74: 08d9 lsrs r1, r3, #3 + 8004b76: 687b ldr r3, [r7, #4] + 8004b78: 681b ldr r3, [r3, #0] + 8004b7a: 683a ldr r2, [r7, #0] + 8004b7c: 430a orrs r2, r1 + 8004b7e: 609a str r2, [r3, #8] + + /* Determine the number of data to process during RX/TX ISR execution */ + UARTEx_SetNbDataToProcess(huart); + 8004b80: 687b ldr r3, [r7, #4] + 8004b82: 0018 movs r0, r3 + 8004b84: f000 f8bc bl 8004d00 + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + 8004b88: 687b ldr r3, [r7, #4] + 8004b8a: 681b ldr r3, [r3, #0] + 8004b8c: 68fa ldr r2, [r7, #12] + 8004b8e: 601a str r2, [r3, #0] + + huart->gState = HAL_UART_STATE_READY; + 8004b90: 687b ldr r3, [r7, #4] + 8004b92: 2288 movs r2, #136 @ 0x88 + 8004b94: 2120 movs r1, #32 + 8004b96: 5099 str r1, [r3, r2] + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 8004b98: 687b ldr r3, [r7, #4] + 8004b9a: 2284 movs r2, #132 @ 0x84 + 8004b9c: 2100 movs r1, #0 + 8004b9e: 5499 strb r1, [r3, r2] + + return HAL_OK; + 8004ba0: 2300 movs r3, #0 +} + 8004ba2: 0018 movs r0, r3 + 8004ba4: 46bd mov sp, r7 + 8004ba6: b004 add sp, #16 + 8004ba8: bd80 pop {r7, pc} ... -08004b28 : +08004bac : * @arg @ref UART_RXFIFO_THRESHOLD_7_8 * @arg @ref UART_RXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { - 8004b28: b580 push {r7, lr} - 8004b2a: b084 sub sp, #16 - 8004b2c: af00 add r7, sp, #0 - 8004b2e: 6078 str r0, [r7, #4] - 8004b30: 6039 str r1, [r7, #0] + 8004bac: b580 push {r7, lr} + 8004bae: b084 sub sp, #16 + 8004bb0: af00 add r7, sp, #0 + 8004bb2: 6078 str r0, [r7, #4] + 8004bb4: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); - 8004b32: 687b ldr r3, [r7, #4] - 8004b34: 2284 movs r2, #132 @ 0x84 - 8004b36: 5c9b ldrb r3, [r3, r2] - 8004b38: 2b01 cmp r3, #1 - 8004b3a: d101 bne.n 8004b40 - 8004b3c: 2302 movs r3, #2 - 8004b3e: e02f b.n 8004ba0 - 8004b40: 687b ldr r3, [r7, #4] - 8004b42: 2284 movs r2, #132 @ 0x84 - 8004b44: 2101 movs r1, #1 - 8004b46: 5499 strb r1, [r3, r2] + 8004bb6: 687b ldr r3, [r7, #4] + 8004bb8: 2284 movs r2, #132 @ 0x84 + 8004bba: 5c9b ldrb r3, [r3, r2] + 8004bbc: 2b01 cmp r3, #1 + 8004bbe: d101 bne.n 8004bc4 + 8004bc0: 2302 movs r3, #2 + 8004bc2: e02f b.n 8004c24 + 8004bc4: 687b ldr r3, [r7, #4] + 8004bc6: 2284 movs r2, #132 @ 0x84 + 8004bc8: 2101 movs r1, #1 + 8004bca: 5499 strb r1, [r3, r2] huart->gState = HAL_UART_STATE_BUSY; - 8004b48: 687b ldr r3, [r7, #4] - 8004b4a: 2288 movs r2, #136 @ 0x88 - 8004b4c: 2124 movs r1, #36 @ 0x24 - 8004b4e: 5099 str r1, [r3, r2] + 8004bcc: 687b ldr r3, [r7, #4] + 8004bce: 2288 movs r2, #136 @ 0x88 + 8004bd0: 2124 movs r1, #36 @ 0x24 + 8004bd2: 5099 str r1, [r3, r2] /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); - 8004b50: 687b ldr r3, [r7, #4] - 8004b52: 681b ldr r3, [r3, #0] - 8004b54: 681b ldr r3, [r3, #0] - 8004b56: 60fb str r3, [r7, #12] + 8004bd4: 687b ldr r3, [r7, #4] + 8004bd6: 681b ldr r3, [r3, #0] + 8004bd8: 681b ldr r3, [r3, #0] + 8004bda: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); - 8004b58: 687b ldr r3, [r7, #4] - 8004b5a: 681b ldr r3, [r3, #0] - 8004b5c: 681a ldr r2, [r3, #0] - 8004b5e: 687b ldr r3, [r7, #4] - 8004b60: 681b ldr r3, [r3, #0] - 8004b62: 2101 movs r1, #1 - 8004b64: 438a bics r2, r1 - 8004b66: 601a str r2, [r3, #0] + 8004bdc: 687b ldr r3, [r7, #4] + 8004bde: 681b ldr r3, [r3, #0] + 8004be0: 681a ldr r2, [r3, #0] + 8004be2: 687b ldr r3, [r7, #4] + 8004be4: 681b ldr r3, [r3, #0] + 8004be6: 2101 movs r1, #1 + 8004be8: 438a bics r2, r1 + 8004bea: 601a str r2, [r3, #0] /* Update RX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); - 8004b68: 687b ldr r3, [r7, #4] - 8004b6a: 681b ldr r3, [r3, #0] - 8004b6c: 689b ldr r3, [r3, #8] - 8004b6e: 4a0e ldr r2, [pc, #56] @ (8004ba8 ) - 8004b70: 4013 ands r3, r2 - 8004b72: 0019 movs r1, r3 - 8004b74: 687b ldr r3, [r7, #4] - 8004b76: 681b ldr r3, [r3, #0] - 8004b78: 683a ldr r2, [r7, #0] - 8004b7a: 430a orrs r2, r1 - 8004b7c: 609a str r2, [r3, #8] + 8004bec: 687b ldr r3, [r7, #4] + 8004bee: 681b ldr r3, [r3, #0] + 8004bf0: 689b ldr r3, [r3, #8] + 8004bf2: 4a0e ldr r2, [pc, #56] @ (8004c2c ) + 8004bf4: 4013 ands r3, r2 + 8004bf6: 0019 movs r1, r3 + 8004bf8: 687b ldr r3, [r7, #4] + 8004bfa: 681b ldr r3, [r3, #0] + 8004bfc: 683a ldr r2, [r7, #0] + 8004bfe: 430a orrs r2, r1 + 8004c00: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); - 8004b7e: 687b ldr r3, [r7, #4] - 8004b80: 0018 movs r0, r3 - 8004b82: f000 f87b bl 8004c7c + 8004c02: 687b ldr r3, [r7, #4] + 8004c04: 0018 movs r0, r3 + 8004c06: f000 f87b bl 8004d00 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); - 8004b86: 687b ldr r3, [r7, #4] - 8004b88: 681b ldr r3, [r3, #0] - 8004b8a: 68fa ldr r2, [r7, #12] - 8004b8c: 601a str r2, [r3, #0] + 8004c0a: 687b ldr r3, [r7, #4] + 8004c0c: 681b ldr r3, [r3, #0] + 8004c0e: 68fa ldr r2, [r7, #12] + 8004c10: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; - 8004b8e: 687b ldr r3, [r7, #4] - 8004b90: 2288 movs r2, #136 @ 0x88 - 8004b92: 2120 movs r1, #32 - 8004b94: 5099 str r1, [r3, r2] + 8004c12: 687b ldr r3, [r7, #4] + 8004c14: 2288 movs r2, #136 @ 0x88 + 8004c16: 2120 movs r1, #32 + 8004c18: 5099 str r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(huart); - 8004b96: 687b ldr r3, [r7, #4] - 8004b98: 2284 movs r2, #132 @ 0x84 - 8004b9a: 2100 movs r1, #0 - 8004b9c: 5499 strb r1, [r3, r2] + 8004c1a: 687b ldr r3, [r7, #4] + 8004c1c: 2284 movs r2, #132 @ 0x84 + 8004c1e: 2100 movs r1, #0 + 8004c20: 5499 strb r1, [r3, r2] return HAL_OK; - 8004b9e: 2300 movs r3, #0 + 8004c22: 2300 movs r3, #0 } - 8004ba0: 0018 movs r0, r3 - 8004ba2: 46bd mov sp, r7 - 8004ba4: b004 add sp, #16 - 8004ba6: bd80 pop {r7, pc} - 8004ba8: f1ffffff .word 0xf1ffffff + 8004c24: 0018 movs r0, r3 + 8004c26: 46bd mov sp, r7 + 8004c28: b004 add sp, #16 + 8004c2a: bd80 pop {r7, pc} + 8004c2c: f1ffffff .word 0xf1ffffff -08004bac : +08004c30 : * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). * @param Size Amount of data elements (uint8_t or uint16_t) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { - 8004bac: b5b0 push {r4, r5, r7, lr} - 8004bae: b08a sub sp, #40 @ 0x28 - 8004bb0: af00 add r7, sp, #0 - 8004bb2: 60f8 str r0, [r7, #12] - 8004bb4: 60b9 str r1, [r7, #8] - 8004bb6: 1dbb adds r3, r7, #6 - 8004bb8: 801a strh r2, [r3, #0] + 8004c30: b5b0 push {r4, r5, r7, lr} + 8004c32: b08a sub sp, #40 @ 0x28 + 8004c34: af00 add r7, sp, #0 + 8004c36: 60f8 str r0, [r7, #12] + 8004c38: 60b9 str r1, [r7, #8] + 8004c3a: 1dbb adds r3, r7, #6 + 8004c3c: 801a strh r2, [r3, #0] HAL_StatusTypeDef status; /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) - 8004bba: 68fb ldr r3, [r7, #12] - 8004bbc: 228c movs r2, #140 @ 0x8c - 8004bbe: 589b ldr r3, [r3, r2] - 8004bc0: 2b20 cmp r3, #32 - 8004bc2: d156 bne.n 8004c72 + 8004c3e: 68fb ldr r3, [r7, #12] + 8004c40: 228c movs r2, #140 @ 0x8c + 8004c42: 589b ldr r3, [r3, r2] + 8004c44: 2b20 cmp r3, #32 + 8004c46: d156 bne.n 8004cf6 { if ((pData == NULL) || (Size == 0U)) - 8004bc4: 68bb ldr r3, [r7, #8] - 8004bc6: 2b00 cmp r3, #0 - 8004bc8: d003 beq.n 8004bd2 - 8004bca: 1dbb adds r3, r7, #6 - 8004bcc: 881b ldrh r3, [r3, #0] - 8004bce: 2b00 cmp r3, #0 - 8004bd0: d101 bne.n 8004bd6 + 8004c48: 68bb ldr r3, [r7, #8] + 8004c4a: 2b00 cmp r3, #0 + 8004c4c: d003 beq.n 8004c56 + 8004c4e: 1dbb adds r3, r7, #6 + 8004c50: 881b ldrh r3, [r3, #0] + 8004c52: 2b00 cmp r3, #0 + 8004c54: d101 bne.n 8004c5a { return HAL_ERROR; - 8004bd2: 2301 movs r3, #1 - 8004bd4: e04e b.n 8004c74 + 8004c56: 2301 movs r3, #1 + 8004c58: e04e b.n 8004cf8 } /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter should be aligned on a uint16_t frontier, as data copy from RDR will be handled by DMA from a uint16_t frontier. */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - 8004bd6: 68fb ldr r3, [r7, #12] - 8004bd8: 689a ldr r2, [r3, #8] - 8004bda: 2380 movs r3, #128 @ 0x80 - 8004bdc: 015b lsls r3, r3, #5 - 8004bde: 429a cmp r2, r3 - 8004be0: d109 bne.n 8004bf6 - 8004be2: 68fb ldr r3, [r7, #12] - 8004be4: 691b ldr r3, [r3, #16] - 8004be6: 2b00 cmp r3, #0 - 8004be8: d105 bne.n 8004bf6 + 8004c5a: 68fb ldr r3, [r7, #12] + 8004c5c: 689a ldr r2, [r3, #8] + 8004c5e: 2380 movs r3, #128 @ 0x80 + 8004c60: 015b lsls r3, r3, #5 + 8004c62: 429a cmp r2, r3 + 8004c64: d109 bne.n 8004c7a + 8004c66: 68fb ldr r3, [r7, #12] + 8004c68: 691b ldr r3, [r3, #16] + 8004c6a: 2b00 cmp r3, #0 + 8004c6c: d105 bne.n 8004c7a { if ((((uint32_t)pData) & 1U) != 0U) - 8004bea: 68bb ldr r3, [r7, #8] - 8004bec: 2201 movs r2, #1 - 8004bee: 4013 ands r3, r2 - 8004bf0: d001 beq.n 8004bf6 + 8004c6e: 68bb ldr r3, [r7, #8] + 8004c70: 2201 movs r2, #1 + 8004c72: 4013 ands r3, r2 + 8004c74: d001 beq.n 8004c7a { return HAL_ERROR; - 8004bf2: 2301 movs r3, #1 - 8004bf4: e03e b.n 8004c74 + 8004c76: 2301 movs r3, #1 + 8004c78: e03e b.n 8004cf8 } } /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; - 8004bf6: 68fb ldr r3, [r7, #12] - 8004bf8: 2201 movs r2, #1 - 8004bfa: 66da str r2, [r3, #108] @ 0x6c + 8004c7a: 68fb ldr r3, [r7, #12] + 8004c7c: 2201 movs r2, #1 + 8004c7e: 66da str r2, [r3, #108] @ 0x6c huart->RxEventType = HAL_UART_RXEVENT_TC; - 8004bfc: 68fb ldr r3, [r7, #12] - 8004bfe: 2200 movs r2, #0 - 8004c00: 671a str r2, [r3, #112] @ 0x70 + 8004c80: 68fb ldr r3, [r7, #12] + 8004c82: 2200 movs r2, #0 + 8004c84: 671a str r2, [r3, #112] @ 0x70 status = UART_Start_Receive_DMA(huart, pData, Size); - 8004c02: 2527 movs r5, #39 @ 0x27 - 8004c04: 197c adds r4, r7, r5 - 8004c06: 1dbb adds r3, r7, #6 - 8004c08: 881a ldrh r2, [r3, #0] - 8004c0a: 68b9 ldr r1, [r7, #8] - 8004c0c: 68fb ldr r3, [r7, #12] - 8004c0e: 0018 movs r0, r3 - 8004c10: f7ff fc1c bl 800444c - 8004c14: 0003 movs r3, r0 - 8004c16: 7023 strb r3, [r4, #0] + 8004c86: 2527 movs r5, #39 @ 0x27 + 8004c88: 197c adds r4, r7, r5 + 8004c8a: 1dbb adds r3, r7, #6 + 8004c8c: 881a ldrh r2, [r3, #0] + 8004c8e: 68b9 ldr r1, [r7, #8] + 8004c90: 68fb ldr r3, [r7, #12] + 8004c92: 0018 movs r0, r3 + 8004c94: f7ff fc1c bl 80044d0 + 8004c98: 0003 movs r3, r0 + 8004c9a: 7023 strb r3, [r4, #0] /* Check Rx process has been successfully started */ if (status == HAL_OK) - 8004c18: 197b adds r3, r7, r5 - 8004c1a: 781b ldrb r3, [r3, #0] - 8004c1c: 2b00 cmp r3, #0 - 8004c1e: d124 bne.n 8004c6a + 8004c9c: 197b adds r3, r7, r5 + 8004c9e: 781b ldrb r3, [r3, #0] + 8004ca0: 2b00 cmp r3, #0 + 8004ca2: d124 bne.n 8004cee { if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - 8004c20: 68fb ldr r3, [r7, #12] - 8004c22: 6edb ldr r3, [r3, #108] @ 0x6c - 8004c24: 2b01 cmp r3, #1 - 8004c26: d11c bne.n 8004c62 + 8004ca4: 68fb ldr r3, [r7, #12] + 8004ca6: 6edb ldr r3, [r3, #108] @ 0x6c + 8004ca8: 2b01 cmp r3, #1 + 8004caa: d11c bne.n 8004ce6 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); - 8004c28: 68fb ldr r3, [r7, #12] - 8004c2a: 681b ldr r3, [r3, #0] - 8004c2c: 2210 movs r2, #16 - 8004c2e: 621a str r2, [r3, #32] + 8004cac: 68fb ldr r3, [r7, #12] + 8004cae: 681b ldr r3, [r3, #0] + 8004cb0: 2210 movs r2, #16 + 8004cb2: 621a str r2, [r3, #32] __ASM volatile ("MRS %0, primask" : "=r" (result) ); - 8004c30: f3ef 8310 mrs r3, PRIMASK - 8004c34: 617b str r3, [r7, #20] + 8004cb4: f3ef 8310 mrs r3, PRIMASK + 8004cb8: 617b str r3, [r7, #20] return(result); - 8004c36: 697b ldr r3, [r7, #20] + 8004cba: 697b ldr r3, [r7, #20] ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - 8004c38: 623b str r3, [r7, #32] - 8004c3a: 2301 movs r3, #1 - 8004c3c: 61bb str r3, [r7, #24] + 8004cbc: 623b str r3, [r7, #32] + 8004cbe: 2301 movs r3, #1 + 8004cc0: 61bb str r3, [r7, #24] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 8004c3e: 69bb ldr r3, [r7, #24] - 8004c40: f383 8810 msr PRIMASK, r3 + 8004cc2: 69bb ldr r3, [r7, #24] + 8004cc4: f383 8810 msr PRIMASK, r3 } - 8004c44: 46c0 nop @ (mov r8, r8) - 8004c46: 68fb ldr r3, [r7, #12] - 8004c48: 681b ldr r3, [r3, #0] - 8004c4a: 681a ldr r2, [r3, #0] - 8004c4c: 68fb ldr r3, [r7, #12] - 8004c4e: 681b ldr r3, [r3, #0] - 8004c50: 2110 movs r1, #16 - 8004c52: 430a orrs r2, r1 - 8004c54: 601a str r2, [r3, #0] - 8004c56: 6a3b ldr r3, [r7, #32] - 8004c58: 61fb str r3, [r7, #28] + 8004cc8: 46c0 nop @ (mov r8, r8) + 8004cca: 68fb ldr r3, [r7, #12] + 8004ccc: 681b ldr r3, [r3, #0] + 8004cce: 681a ldr r2, [r3, #0] + 8004cd0: 68fb ldr r3, [r7, #12] + 8004cd2: 681b ldr r3, [r3, #0] + 8004cd4: 2110 movs r1, #16 + 8004cd6: 430a orrs r2, r1 + 8004cd8: 601a str r2, [r3, #0] + 8004cda: 6a3b ldr r3, [r7, #32] + 8004cdc: 61fb str r3, [r7, #28] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 8004c5a: 69fb ldr r3, [r7, #28] - 8004c5c: f383 8810 msr PRIMASK, r3 + 8004cde: 69fb ldr r3, [r7, #28] + 8004ce0: f383 8810 msr PRIMASK, r3 } - 8004c60: e003 b.n 8004c6a + 8004ce4: e003 b.n 8004cee { /* In case of errors already pending when reception is started, Interrupts may have already been raised and lead to reception abortion. (Overrun error for instance). In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ status = HAL_ERROR; - 8004c62: 2327 movs r3, #39 @ 0x27 - 8004c64: 18fb adds r3, r7, r3 - 8004c66: 2201 movs r2, #1 - 8004c68: 701a strb r2, [r3, #0] + 8004ce6: 2327 movs r3, #39 @ 0x27 + 8004ce8: 18fb adds r3, r7, r3 + 8004cea: 2201 movs r2, #1 + 8004cec: 701a strb r2, [r3, #0] } } return status; - 8004c6a: 2327 movs r3, #39 @ 0x27 - 8004c6c: 18fb adds r3, r7, r3 - 8004c6e: 781b ldrb r3, [r3, #0] - 8004c70: e000 b.n 8004c74 + 8004cee: 2327 movs r3, #39 @ 0x27 + 8004cf0: 18fb adds r3, r7, r3 + 8004cf2: 781b ldrb r3, [r3, #0] + 8004cf4: e000 b.n 8004cf8 } else { return HAL_BUSY; - 8004c72: 2302 movs r3, #2 + 8004cf6: 2302 movs r3, #2 } } - 8004c74: 0018 movs r0, r3 - 8004c76: 46bd mov sp, r7 - 8004c78: b00a add sp, #40 @ 0x28 - 8004c7a: bdb0 pop {r4, r5, r7, pc} + 8004cf8: 0018 movs r0, r3 + 8004cfa: 46bd mov sp, r7 + 8004cfc: b00a add sp, #40 @ 0x28 + 8004cfe: bdb0 pop {r4, r5, r7, pc} -08004c7c : +08004d00 : * the UART configuration registers. * @param huart UART handle. * @retval None */ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) { - 8004c7c: b5f0 push {r4, r5, r6, r7, lr} - 8004c7e: b085 sub sp, #20 - 8004c80: af00 add r7, sp, #0 - 8004c82: 6078 str r0, [r7, #4] + 8004d00: b5f0 push {r4, r5, r6, r7, lr} + 8004d02: b085 sub sp, #20 + 8004d04: af00 add r7, sp, #0 + 8004d06: 6078 str r0, [r7, #4] uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (huart->FifoMode == UART_FIFOMODE_DISABLE) - 8004c84: 687b ldr r3, [r7, #4] - 8004c86: 6e5b ldr r3, [r3, #100] @ 0x64 - 8004c88: 2b00 cmp r3, #0 - 8004c8a: d108 bne.n 8004c9e + 8004d08: 687b ldr r3, [r7, #4] + 8004d0a: 6e5b ldr r3, [r3, #100] @ 0x64 + 8004d0c: 2b00 cmp r3, #0 + 8004d0e: d108 bne.n 8004d22 { huart->NbTxDataToProcess = 1U; - 8004c8c: 687b ldr r3, [r7, #4] - 8004c8e: 226a movs r2, #106 @ 0x6a - 8004c90: 2101 movs r1, #1 - 8004c92: 5299 strh r1, [r3, r2] + 8004d10: 687b ldr r3, [r7, #4] + 8004d12: 226a movs r2, #106 @ 0x6a + 8004d14: 2101 movs r1, #1 + 8004d16: 5299 strh r1, [r3, r2] huart->NbRxDataToProcess = 1U; - 8004c94: 687b ldr r3, [r7, #4] - 8004c96: 2268 movs r2, #104 @ 0x68 - 8004c98: 2101 movs r1, #1 - 8004c9a: 5299 strh r1, [r3, r2] + 8004d18: 687b ldr r3, [r7, #4] + 8004d1a: 2268 movs r2, #104 @ 0x68 + 8004d1c: 2101 movs r1, #1 + 8004d1e: 5299 strh r1, [r3, r2] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; } } - 8004c9c: e043 b.n 8004d26 + 8004d20: e043 b.n 8004daa rx_fifo_depth = RX_FIFO_DEPTH; - 8004c9e: 260f movs r6, #15 - 8004ca0: 19bb adds r3, r7, r6 - 8004ca2: 2208 movs r2, #8 - 8004ca4: 701a strb r2, [r3, #0] + 8004d22: 260f movs r6, #15 + 8004d24: 19bb adds r3, r7, r6 + 8004d26: 2208 movs r2, #8 + 8004d28: 701a strb r2, [r3, #0] tx_fifo_depth = TX_FIFO_DEPTH; - 8004ca6: 200e movs r0, #14 - 8004ca8: 183b adds r3, r7, r0 - 8004caa: 2208 movs r2, #8 - 8004cac: 701a strb r2, [r3, #0] + 8004d2a: 200e movs r0, #14 + 8004d2c: 183b adds r3, r7, r0 + 8004d2e: 2208 movs r2, #8 + 8004d30: 701a strb r2, [r3, #0] rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); - 8004cae: 687b ldr r3, [r7, #4] - 8004cb0: 681b ldr r3, [r3, #0] - 8004cb2: 689b ldr r3, [r3, #8] - 8004cb4: 0e5b lsrs r3, r3, #25 - 8004cb6: b2da uxtb r2, r3 - 8004cb8: 240d movs r4, #13 - 8004cba: 193b adds r3, r7, r4 - 8004cbc: 2107 movs r1, #7 - 8004cbe: 400a ands r2, r1 - 8004cc0: 701a strb r2, [r3, #0] + 8004d32: 687b ldr r3, [r7, #4] + 8004d34: 681b ldr r3, [r3, #0] + 8004d36: 689b ldr r3, [r3, #8] + 8004d38: 0e5b lsrs r3, r3, #25 + 8004d3a: b2da uxtb r2, r3 + 8004d3c: 240d movs r4, #13 + 8004d3e: 193b adds r3, r7, r4 + 8004d40: 2107 movs r1, #7 + 8004d42: 400a ands r2, r1 + 8004d44: 701a strb r2, [r3, #0] tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); - 8004cc2: 687b ldr r3, [r7, #4] - 8004cc4: 681b ldr r3, [r3, #0] - 8004cc6: 689b ldr r3, [r3, #8] - 8004cc8: 0f5b lsrs r3, r3, #29 - 8004cca: b2da uxtb r2, r3 - 8004ccc: 250c movs r5, #12 - 8004cce: 197b adds r3, r7, r5 - 8004cd0: 2107 movs r1, #7 - 8004cd2: 400a ands r2, r1 - 8004cd4: 701a strb r2, [r3, #0] + 8004d46: 687b ldr r3, [r7, #4] + 8004d48: 681b ldr r3, [r3, #0] + 8004d4a: 689b ldr r3, [r3, #8] + 8004d4c: 0f5b lsrs r3, r3, #29 + 8004d4e: b2da uxtb r2, r3 + 8004d50: 250c movs r5, #12 + 8004d52: 197b adds r3, r7, r5 + 8004d54: 2107 movs r1, #7 + 8004d56: 400a ands r2, r1 + 8004d58: 701a strb r2, [r3, #0] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / - 8004cd6: 183b adds r3, r7, r0 - 8004cd8: 781b ldrb r3, [r3, #0] - 8004cda: 197a adds r2, r7, r5 - 8004cdc: 7812 ldrb r2, [r2, #0] - 8004cde: 4914 ldr r1, [pc, #80] @ (8004d30 ) - 8004ce0: 5c8a ldrb r2, [r1, r2] - 8004ce2: 435a muls r2, r3 - 8004ce4: 0010 movs r0, r2 + 8004d5a: 183b adds r3, r7, r0 + 8004d5c: 781b ldrb r3, [r3, #0] + 8004d5e: 197a adds r2, r7, r5 + 8004d60: 7812 ldrb r2, [r2, #0] + 8004d62: 4914 ldr r1, [pc, #80] @ (8004db4 ) + 8004d64: 5c8a ldrb r2, [r1, r2] + 8004d66: 435a muls r2, r3 + 8004d68: 0010 movs r0, r2 (uint16_t)denominator[tx_fifo_threshold]; - 8004ce6: 197b adds r3, r7, r5 - 8004ce8: 781b ldrb r3, [r3, #0] - 8004cea: 4a12 ldr r2, [pc, #72] @ (8004d34 ) - 8004cec: 5cd3 ldrb r3, [r2, r3] + 8004d6a: 197b adds r3, r7, r5 + 8004d6c: 781b ldrb r3, [r3, #0] + 8004d6e: 4a12 ldr r2, [pc, #72] @ (8004db8 ) + 8004d70: 5cd3 ldrb r3, [r2, r3] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / - 8004cee: 0019 movs r1, r3 - 8004cf0: f7fb fa94 bl 800021c <__divsi3> - 8004cf4: 0003 movs r3, r0 - 8004cf6: b299 uxth r1, r3 - 8004cf8: 687b ldr r3, [r7, #4] - 8004cfa: 226a movs r2, #106 @ 0x6a - 8004cfc: 5299 strh r1, [r3, r2] + 8004d72: 0019 movs r1, r3 + 8004d74: f7fb fa52 bl 800021c <__divsi3> + 8004d78: 0003 movs r3, r0 + 8004d7a: b299 uxth r1, r3 + 8004d7c: 687b ldr r3, [r7, #4] + 8004d7e: 226a movs r2, #106 @ 0x6a + 8004d80: 5299 strh r1, [r3, r2] huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / - 8004cfe: 19bb adds r3, r7, r6 - 8004d00: 781b ldrb r3, [r3, #0] - 8004d02: 193a adds r2, r7, r4 - 8004d04: 7812 ldrb r2, [r2, #0] - 8004d06: 490a ldr r1, [pc, #40] @ (8004d30 ) - 8004d08: 5c8a ldrb r2, [r1, r2] - 8004d0a: 435a muls r2, r3 - 8004d0c: 0010 movs r0, r2 + 8004d82: 19bb adds r3, r7, r6 + 8004d84: 781b ldrb r3, [r3, #0] + 8004d86: 193a adds r2, r7, r4 + 8004d88: 7812 ldrb r2, [r2, #0] + 8004d8a: 490a ldr r1, [pc, #40] @ (8004db4 ) + 8004d8c: 5c8a ldrb r2, [r1, r2] + 8004d8e: 435a muls r2, r3 + 8004d90: 0010 movs r0, r2 (uint16_t)denominator[rx_fifo_threshold]; - 8004d0e: 193b adds r3, r7, r4 - 8004d10: 781b ldrb r3, [r3, #0] - 8004d12: 4a08 ldr r2, [pc, #32] @ (8004d34 ) - 8004d14: 5cd3 ldrb r3, [r2, r3] + 8004d92: 193b adds r3, r7, r4 + 8004d94: 781b ldrb r3, [r3, #0] + 8004d96: 4a08 ldr r2, [pc, #32] @ (8004db8 ) + 8004d98: 5cd3 ldrb r3, [r2, r3] huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / - 8004d16: 0019 movs r1, r3 - 8004d18: f7fb fa80 bl 800021c <__divsi3> - 8004d1c: 0003 movs r3, r0 - 8004d1e: b299 uxth r1, r3 - 8004d20: 687b ldr r3, [r7, #4] - 8004d22: 2268 movs r2, #104 @ 0x68 - 8004d24: 5299 strh r1, [r3, r2] + 8004d9a: 0019 movs r1, r3 + 8004d9c: f7fb fa3e bl 800021c <__divsi3> + 8004da0: 0003 movs r3, r0 + 8004da2: b299 uxth r1, r3 + 8004da4: 687b ldr r3, [r7, #4] + 8004da6: 2268 movs r2, #104 @ 0x68 + 8004da8: 5299 strh r1, [r3, r2] } - 8004d26: 46c0 nop @ (mov r8, r8) - 8004d28: 46bd mov sp, r7 - 8004d2a: b005 add sp, #20 - 8004d2c: bdf0 pop {r4, r5, r6, r7, pc} - 8004d2e: 46c0 nop @ (mov r8, r8) - 8004d30: 08004e88 .word 0x08004e88 - 8004d34: 08004e90 .word 0x08004e90 + 8004daa: 46c0 nop @ (mov r8, r8) + 8004dac: 46bd mov sp, r7 + 8004dae: b005 add sp, #20 + 8004db0: bdf0 pop {r4, r5, r6, r7, pc} + 8004db2: 46c0 nop @ (mov r8, r8) + 8004db4: 08004f0c .word 0x08004f0c + 8004db8: 08004f14 .word 0x08004f14 -08004d38 : - 8004d38: 0003 movs r3, r0 - 8004d3a: 1882 adds r2, r0, r2 - 8004d3c: 4293 cmp r3, r2 - 8004d3e: d100 bne.n 8004d42 - 8004d40: 4770 bx lr - 8004d42: 7019 strb r1, [r3, #0] - 8004d44: 3301 adds r3, #1 - 8004d46: e7f9 b.n 8004d3c +08004dbc : + 8004dbc: 0003 movs r3, r0 + 8004dbe: 1882 adds r2, r0, r2 + 8004dc0: 4293 cmp r3, r2 + 8004dc2: d100 bne.n 8004dc6 + 8004dc4: 4770 bx lr + 8004dc6: 7019 strb r1, [r3, #0] + 8004dc8: 3301 adds r3, #1 + 8004dca: e7f9 b.n 8004dc0 -08004d48 <__libc_init_array>: - 8004d48: b570 push {r4, r5, r6, lr} - 8004d4a: 2600 movs r6, #0 - 8004d4c: 4c0c ldr r4, [pc, #48] @ (8004d80 <__libc_init_array+0x38>) - 8004d4e: 4d0d ldr r5, [pc, #52] @ (8004d84 <__libc_init_array+0x3c>) - 8004d50: 1b64 subs r4, r4, r5 - 8004d52: 10a4 asrs r4, r4, #2 - 8004d54: 42a6 cmp r6, r4 - 8004d56: d109 bne.n 8004d6c <__libc_init_array+0x24> - 8004d58: 2600 movs r6, #0 - 8004d5a: f000 f823 bl 8004da4 <_init> - 8004d5e: 4c0a ldr r4, [pc, #40] @ (8004d88 <__libc_init_array+0x40>) - 8004d60: 4d0a ldr r5, [pc, #40] @ (8004d8c <__libc_init_array+0x44>) - 8004d62: 1b64 subs r4, r4, r5 - 8004d64: 10a4 asrs r4, r4, #2 - 8004d66: 42a6 cmp r6, r4 - 8004d68: d105 bne.n 8004d76 <__libc_init_array+0x2e> - 8004d6a: bd70 pop {r4, r5, r6, pc} - 8004d6c: 00b3 lsls r3, r6, #2 - 8004d6e: 58eb ldr r3, [r5, r3] - 8004d70: 4798 blx r3 - 8004d72: 3601 adds r6, #1 - 8004d74: e7ee b.n 8004d54 <__libc_init_array+0xc> - 8004d76: 00b3 lsls r3, r6, #2 - 8004d78: 58eb ldr r3, [r5, r3] - 8004d7a: 4798 blx r3 - 8004d7c: 3601 adds r6, #1 - 8004d7e: e7f2 b.n 8004d66 <__libc_init_array+0x1e> - 8004d80: 08004e98 .word 0x08004e98 - 8004d84: 08004e98 .word 0x08004e98 - 8004d88: 08004e9c .word 0x08004e9c - 8004d8c: 08004e98 .word 0x08004e98 +08004dcc <__libc_init_array>: + 8004dcc: b570 push {r4, r5, r6, lr} + 8004dce: 2600 movs r6, #0 + 8004dd0: 4c0c ldr r4, [pc, #48] @ (8004e04 <__libc_init_array+0x38>) + 8004dd2: 4d0d ldr r5, [pc, #52] @ (8004e08 <__libc_init_array+0x3c>) + 8004dd4: 1b64 subs r4, r4, r5 + 8004dd6: 10a4 asrs r4, r4, #2 + 8004dd8: 42a6 cmp r6, r4 + 8004dda: d109 bne.n 8004df0 <__libc_init_array+0x24> + 8004ddc: 2600 movs r6, #0 + 8004dde: f000 f823 bl 8004e28 <_init> + 8004de2: 4c0a ldr r4, [pc, #40] @ (8004e0c <__libc_init_array+0x40>) + 8004de4: 4d0a ldr r5, [pc, #40] @ (8004e10 <__libc_init_array+0x44>) + 8004de6: 1b64 subs r4, r4, r5 + 8004de8: 10a4 asrs r4, r4, #2 + 8004dea: 42a6 cmp r6, r4 + 8004dec: d105 bne.n 8004dfa <__libc_init_array+0x2e> + 8004dee: bd70 pop {r4, r5, r6, pc} + 8004df0: 00b3 lsls r3, r6, #2 + 8004df2: 58eb ldr r3, [r5, r3] + 8004df4: 4798 blx r3 + 8004df6: 3601 adds r6, #1 + 8004df8: e7ee b.n 8004dd8 <__libc_init_array+0xc> + 8004dfa: 00b3 lsls r3, r6, #2 + 8004dfc: 58eb ldr r3, [r5, r3] + 8004dfe: 4798 blx r3 + 8004e00: 3601 adds r6, #1 + 8004e02: e7f2 b.n 8004dea <__libc_init_array+0x1e> + 8004e04: 08004f1c .word 0x08004f1c + 8004e08: 08004f1c .word 0x08004f1c + 8004e0c: 08004f20 .word 0x08004f20 + 8004e10: 08004f1c .word 0x08004f1c -08004d90 : - 8004d90: 2300 movs r3, #0 - 8004d92: b510 push {r4, lr} - 8004d94: 429a cmp r2, r3 - 8004d96: d100 bne.n 8004d9a - 8004d98: bd10 pop {r4, pc} - 8004d9a: 5ccc ldrb r4, [r1, r3] - 8004d9c: 54c4 strb r4, [r0, r3] - 8004d9e: 3301 adds r3, #1 - 8004da0: e7f8 b.n 8004d94 +08004e14 : + 8004e14: 2300 movs r3, #0 + 8004e16: b510 push {r4, lr} + 8004e18: 429a cmp r2, r3 + 8004e1a: d100 bne.n 8004e1e + 8004e1c: bd10 pop {r4, pc} + 8004e1e: 5ccc ldrb r4, [r1, r3] + 8004e20: 54c4 strb r4, [r0, r3] + 8004e22: 3301 adds r3, #1 + 8004e24: e7f8 b.n 8004e18 ... -08004da4 <_init>: - 8004da4: b5f8 push {r3, r4, r5, r6, r7, lr} - 8004da6: 46c0 nop @ (mov r8, r8) - 8004da8: bcf8 pop {r3, r4, r5, r6, r7} - 8004daa: bc08 pop {r3} - 8004dac: 469e mov lr, r3 - 8004dae: 4770 bx lr +08004e28 <_init>: + 8004e28: b5f8 push {r3, r4, r5, r6, r7, lr} + 8004e2a: 46c0 nop @ (mov r8, r8) + 8004e2c: bcf8 pop {r3, r4, r5, r6, r7} + 8004e2e: bc08 pop {r3} + 8004e30: 469e mov lr, r3 + 8004e32: 4770 bx lr -08004db0 <_fini>: - 8004db0: b5f8 push {r3, r4, r5, r6, r7, lr} - 8004db2: 46c0 nop @ (mov r8, r8) - 8004db4: bcf8 pop {r3, r4, r5, r6, r7} - 8004db6: bc08 pop {r3} - 8004db8: 469e mov lr, r3 - 8004dba: 4770 bx lr +08004e34 <_fini>: + 8004e34: b5f8 push {r3, r4, r5, r6, r7, lr} + 8004e36: 46c0 nop @ (mov r8, r8) + 8004e38: bcf8 pop {r3, r4, r5, r6, r7} + 8004e3a: bc08 pop {r3} + 8004e3c: 469e mov lr, r3 + 8004e3e: 4770 bx lr diff --git a/code/Debug/feeder_mk2.map b/code/Debug/feeder_mk2.map index 8f1f9af..cc6d65d 100644 --- a/code/Debug/feeder_mk2.map +++ b/code/Debug/feeder_mk2.map @@ -8,6 +8,8 @@ C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.external C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-findfp.o) (_fwalk_sglue) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-stdio.o) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-findfp.o) (__sread) +C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memcmp.o) + ./Core/Src/main.o (memcmp) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memset.o) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o (memset) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-closer.o) @@ -43,7 +45,7 @@ C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.external C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a(_udivsi3.o) ./Core/Src/system_stm32c0xx.o (__aeabi_uidiv) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a(_divsi3.o) - ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o (__aeabi_idiv) + ./Core/Src/main.o (__aeabi_idiv) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a(_dvmd_tls.o) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a(_udivsi3.o) (__aeabi_idiv0) @@ -61,6 +63,42 @@ Discarded input sections .ARM.exidx 0x00000000 0x10 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o .ARM.attributes 0x00000000 0x1b C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o + .group 0x00000000 0xc ./Core/Src/crc.o + .group 0x00000000 0xc ./Core/Src/crc.o + .group 0x00000000 0xc ./Core/Src/crc.o + .group 0x00000000 0xc ./Core/Src/crc.o + .group 0x00000000 0xc ./Core/Src/crc.o + .group 0x00000000 0xc ./Core/Src/crc.o + .group 0x00000000 0xc ./Core/Src/crc.o + .group 0x00000000 0xc ./Core/Src/crc.o + .text 0x00000000 0x0 ./Core/Src/crc.o + .data 0x00000000 0x0 ./Core/Src/crc.o + .bss 0x00000000 0x0 ./Core/Src/crc.o + .text.CRC8_107_add + 0x00000000 0x60 ./Core/Src/crc.o + .text.CRC8_107_getChecksum + 0x00000000 0x18 ./Core/Src/crc.o + .debug_info 0x00000000 0x15c ./Core/Src/crc.o + .debug_abbrev 0x00000000 0xe1 ./Core/Src/crc.o + .debug_aranges + 0x00000000 0x28 ./Core/Src/crc.o + .debug_rnglists + 0x00000000 0x19 ./Core/Src/crc.o + .debug_macro 0x00000000 0x76 ./Core/Src/crc.o + .debug_macro 0x00000000 0xaae ./Core/Src/crc.o + .debug_macro 0x00000000 0x22 ./Core/Src/crc.o + .debug_macro 0x00000000 0x8e ./Core/Src/crc.o + .debug_macro 0x00000000 0x51 ./Core/Src/crc.o + .debug_macro 0x00000000 0x103 ./Core/Src/crc.o + .debug_macro 0x00000000 0x6a ./Core/Src/crc.o + .debug_macro 0x00000000 0x1df ./Core/Src/crc.o + .debug_macro 0x00000000 0x190 ./Core/Src/crc.o + .debug_line 0x00000000 0x480 ./Core/Src/crc.o + .debug_str 0x00000000 0x4050 ./Core/Src/crc.o + .comment 0x00000000 0x44 ./Core/Src/crc.o + .debug_frame 0x00000000 0x50 ./Core/Src/crc.o + .ARM.attributes + 0x00000000 0x2c ./Core/Src/crc.o .group 0x00000000 0xc ./Core/Src/main.o .group 0x00000000 0xc ./Core/Src/main.o .group 0x00000000 0xc ./Core/Src/main.o @@ -128,19 +166,37 @@ Discarded input sections .text 0x00000000 0x0 ./Core/Src/main.o .data 0x00000000 0x0 ./Core/Src/main.o .bss 0x00000000 0x0 ./Core/Src/main.o + .text.CRC8_107_init + 0x00000000 0x16 ./Core/Src/main.o .bss.is_initialized 0x00000000 0x1 ./Core/Src/main.o .bss.network_buffer_RX 0x00000000 0x40 ./Core/Src/main.o .data.my_address 0x00000000 0x1 ./Core/Src/main.o + .bss.vendor_options + 0x00000000 0x10 ./Core/Src/main.o + .data.feed_distance + 0x00000000 0x1 ./Core/Src/main.o .text.HAL_GPIO_EXTI_Callback 0x00000000 0x6c ./Core/Src/main.o .text.set_LED 0x00000000 0x80 ./Core/Src/main.o + .text.comp_crc_header + 0x00000000 0x4a ./Core/Src/main.o .text.handleRS485Message - 0x00000000 0x18 ./Core/Src/main.o - .text.set_Feeder_PWM - 0x00000000 0x4c ./Core/Src/main.o + 0x00000000 0x4a8 ./Core/Src/main.o + .rodata.handleRS485Message + 0x00000000 0x30 ./Core/Src/main.o + .text.update_Feeder_Target + 0x00000000 0x38 ./Core/Src/main.o + .debug_macro 0x00000000 0xaae ./Core/Src/main.o + .debug_macro 0x00000000 0x22 ./Core/Src/main.o + .debug_macro 0x00000000 0x8e ./Core/Src/main.o + .debug_macro 0x00000000 0x51 ./Core/Src/main.o + .debug_macro 0x00000000 0x103 ./Core/Src/main.o + .debug_macro 0x00000000 0x6a ./Core/Src/main.o + .debug_macro 0x00000000 0x1df ./Core/Src/main.o + .debug_macro 0x00000000 0x190 ./Core/Src/main.o .group 0x00000000 0xc ./Core/Src/stm32c0xx_hal_msp.o .group 0x00000000 0xc ./Core/Src/stm32c0xx_hal_msp.o .group 0x00000000 0xc ./Core/Src/stm32c0xx_hal_msp.o @@ -2833,6 +2889,13 @@ Discarded input sections .debug_frame 0x00000000 0x90 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-stdio.o) .ARM.attributes 0x00000000 0x2c C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-stdio.o) + .text 0x00000000 0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memcmp.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memcmp.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memcmp.o) + .text.memcmp 0x00000000 0x1c C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memcmp.o) + .debug_frame 0x00000000 0x2c C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memcmp.o) + .ARM.attributes + 0x00000000 0x2c C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memcmp.o) .text 0x00000000 0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memset.o) .data 0x00000000 0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memset.o) .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memset.o) @@ -3018,6 +3081,7 @@ Linker script and memory map LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crti.o LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o +LOAD ./Core/Src/crc.o LOAD ./Core/Src/main.o LOAD ./Core/Src/stm32c0xx_hal_msp.o LOAD ./Core/Src/stm32c0xx_it.o @@ -3072,7 +3136,7 @@ LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext 0x08000000 g_pfnVectors 0x080000c0 . = ALIGN (0x4) -.text 0x080000c0 0x4cfc +.text 0x080000c0 0x4d80 0x080000c0 . = ALIGN (0x4) *(.text) .text 0x080000c0 0x48 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o @@ -3118,403 +3182,406 @@ LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext .text.MX_GPIO_Init 0x08000dbc 0x124 ./Core/Src/main.o .text.HAL_TIM_PeriodElapsedCallback - 0x08000ee0 0x144 ./Core/Src/main.o + 0x08000ee0 0x17c ./Core/Src/main.o 0x08000ee0 HAL_TIM_PeriodElapsedCallback .text.HAL_UARTEx_RxEventCallback - 0x08001024 0x84 ./Core/Src/main.o - 0x08001024 HAL_UARTEx_RxEventCallback + 0x0800105c 0x84 ./Core/Src/main.o + 0x0800105c HAL_UARTEx_RxEventCallback + .text.set_Feeder_PWM + 0x080010e0 0x4c ./Core/Src/main.o + 0x080010e0 set_Feeder_PWM .text.Error_Handler - 0x080010a8 0xc ./Core/Src/main.o - 0x080010a8 Error_Handler + 0x0800112c 0xc ./Core/Src/main.o + 0x0800112c Error_Handler .text.HAL_MspInit - 0x080010b4 0x48 ./Core/Src/stm32c0xx_hal_msp.o - 0x080010b4 HAL_MspInit + 0x08001138 0x48 ./Core/Src/stm32c0xx_hal_msp.o + 0x08001138 HAL_MspInit .text.HAL_TIM_Base_MspInit - 0x080010fc 0xf4 ./Core/Src/stm32c0xx_hal_msp.o - 0x080010fc HAL_TIM_Base_MspInit + 0x08001180 0xf4 ./Core/Src/stm32c0xx_hal_msp.o + 0x08001180 HAL_TIM_Base_MspInit .text.HAL_TIM_Encoder_MspInit - 0x080011f0 0x94 ./Core/Src/stm32c0xx_hal_msp.o - 0x080011f0 HAL_TIM_Encoder_MspInit + 0x08001274 0x94 ./Core/Src/stm32c0xx_hal_msp.o + 0x08001274 HAL_TIM_Encoder_MspInit .text.HAL_TIM_MspPostInit - 0x08001284 0xa8 ./Core/Src/stm32c0xx_hal_msp.o - 0x08001284 HAL_TIM_MspPostInit + 0x08001308 0xa8 ./Core/Src/stm32c0xx_hal_msp.o + 0x08001308 HAL_TIM_MspPostInit .text.HAL_UART_MspInit - 0x0800132c 0x1f0 ./Core/Src/stm32c0xx_hal_msp.o - 0x0800132c HAL_UART_MspInit + 0x080013b0 0x1f0 ./Core/Src/stm32c0xx_hal_msp.o + 0x080013b0 HAL_UART_MspInit .text.NMI_Handler - 0x0800151c 0x8 ./Core/Src/stm32c0xx_it.o - 0x0800151c NMI_Handler + 0x080015a0 0x8 ./Core/Src/stm32c0xx_it.o + 0x080015a0 NMI_Handler .text.HardFault_Handler - 0x08001524 0x8 ./Core/Src/stm32c0xx_it.o - 0x08001524 HardFault_Handler + 0x080015a8 0x8 ./Core/Src/stm32c0xx_it.o + 0x080015a8 HardFault_Handler .text.SVC_Handler - 0x0800152c 0xa ./Core/Src/stm32c0xx_it.o - 0x0800152c SVC_Handler + 0x080015b0 0xa ./Core/Src/stm32c0xx_it.o + 0x080015b0 SVC_Handler .text.PendSV_Handler - 0x08001536 0xa ./Core/Src/stm32c0xx_it.o - 0x08001536 PendSV_Handler + 0x080015ba 0xa ./Core/Src/stm32c0xx_it.o + 0x080015ba PendSV_Handler .text.SysTick_Handler - 0x08001540 0xe ./Core/Src/stm32c0xx_it.o - 0x08001540 SysTick_Handler + 0x080015c4 0xe ./Core/Src/stm32c0xx_it.o + 0x080015c4 SysTick_Handler .text.EXTI4_15_IRQHandler - 0x0800154e 0x1e ./Core/Src/stm32c0xx_it.o - 0x0800154e EXTI4_15_IRQHandler + 0x080015d2 0x1e ./Core/Src/stm32c0xx_it.o + 0x080015d2 EXTI4_15_IRQHandler .text.DMA1_Channel1_IRQHandler - 0x0800156c 0x18 ./Core/Src/stm32c0xx_it.o - 0x0800156c DMA1_Channel1_IRQHandler + 0x080015f0 0x18 ./Core/Src/stm32c0xx_it.o + 0x080015f0 DMA1_Channel1_IRQHandler .text.DMA1_Channel2_3_IRQHandler - 0x08001584 0x18 ./Core/Src/stm32c0xx_it.o - 0x08001584 DMA1_Channel2_3_IRQHandler + 0x08001608 0x18 ./Core/Src/stm32c0xx_it.o + 0x08001608 DMA1_Channel2_3_IRQHandler .text.TIM14_IRQHandler - 0x0800159c 0x18 ./Core/Src/stm32c0xx_it.o - 0x0800159c TIM14_IRQHandler + 0x08001620 0x18 ./Core/Src/stm32c0xx_it.o + 0x08001620 TIM14_IRQHandler .text.TIM16_IRQHandler - 0x080015b4 0x18 ./Core/Src/stm32c0xx_it.o - 0x080015b4 TIM16_IRQHandler + 0x08001638 0x18 ./Core/Src/stm32c0xx_it.o + 0x08001638 TIM16_IRQHandler .text.TIM17_IRQHandler - 0x080015cc 0x18 ./Core/Src/stm32c0xx_it.o - 0x080015cc TIM17_IRQHandler + 0x08001650 0x18 ./Core/Src/stm32c0xx_it.o + 0x08001650 TIM17_IRQHandler .text.SystemInit - 0x080015e4 0x18 ./Core/Src/system_stm32c0xx.o - 0x080015e4 SystemInit + 0x08001668 0x18 ./Core/Src/system_stm32c0xx.o + 0x08001668 SystemInit .text.Reset_Handler - 0x080015fc 0x50 ./Core/Startup/startup_stm32c051c6tx.o - 0x080015fc Reset_Handler + 0x08001680 0x50 ./Core/Startup/startup_stm32c051c6tx.o + 0x08001680 Reset_Handler .text.Default_Handler - 0x0800164c 0x2 ./Core/Startup/startup_stm32c051c6tx.o - 0x0800164c TIM1_CC_IRQHandler - 0x0800164c I2C1_IRQHandler - 0x0800164c SPI1_IRQHandler - 0x0800164c EXTI2_3_IRQHandler - 0x0800164c ADC1_IRQHandler - 0x0800164c I2C2_IRQHandler - 0x0800164c RTC_IRQHandler - 0x0800164c TIM3_IRQHandler - 0x0800164c RCC_IRQHandler - 0x0800164c Default_Handler - 0x0800164c EXTI0_1_IRQHandler - 0x0800164c SPI2_IRQHandler - 0x0800164c WWDG_IRQHandler - 0x0800164c TIM2_IRQHandler - 0x0800164c DMAMUX1_DMA1_CH4_5_IRQHandler - 0x0800164c USART2_IRQHandler - 0x0800164c FLASH_IRQHandler - 0x0800164c USART1_IRQHandler - 0x0800164c TIM1_BRK_UP_TRG_COM_IRQHandler + 0x080016d0 0x2 ./Core/Startup/startup_stm32c051c6tx.o + 0x080016d0 TIM1_CC_IRQHandler + 0x080016d0 I2C1_IRQHandler + 0x080016d0 SPI1_IRQHandler + 0x080016d0 EXTI2_3_IRQHandler + 0x080016d0 ADC1_IRQHandler + 0x080016d0 I2C2_IRQHandler + 0x080016d0 RTC_IRQHandler + 0x080016d0 TIM3_IRQHandler + 0x080016d0 RCC_IRQHandler + 0x080016d0 Default_Handler + 0x080016d0 EXTI0_1_IRQHandler + 0x080016d0 SPI2_IRQHandler + 0x080016d0 WWDG_IRQHandler + 0x080016d0 TIM2_IRQHandler + 0x080016d0 DMAMUX1_DMA1_CH4_5_IRQHandler + 0x080016d0 USART2_IRQHandler + 0x080016d0 FLASH_IRQHandler + 0x080016d0 USART1_IRQHandler + 0x080016d0 TIM1_BRK_UP_TRG_COM_IRQHandler .text.HAL_Init - 0x0800164e 0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o - 0x0800164e HAL_Init + 0x080016d2 0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o + 0x080016d2 HAL_Init .text.HAL_InitTick - 0x0800167c 0x94 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o - 0x0800167c HAL_InitTick + 0x08001700 0x94 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o + 0x08001700 HAL_InitTick .text.HAL_IncTick - 0x08001710 0x24 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o - 0x08001710 HAL_IncTick + 0x08001794 0x24 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o + 0x08001794 HAL_IncTick .text.HAL_GetTick - 0x08001734 0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o - 0x08001734 HAL_GetTick + 0x080017b8 0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o + 0x080017b8 HAL_GetTick .text.HAL_GetUIDw0 - 0x08001748 0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o - 0x08001748 HAL_GetUIDw0 + 0x080017cc 0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o + 0x080017cc HAL_GetUIDw0 .text.HAL_GetUIDw1 - 0x0800175c 0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o - 0x0800175c HAL_GetUIDw1 + 0x080017e0 0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o + 0x080017e0 HAL_GetUIDw1 .text.HAL_GetUIDw2 - 0x08001770 0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o - 0x08001770 HAL_GetUIDw2 + 0x080017f4 0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o + 0x080017f4 HAL_GetUIDw2 .text.__NVIC_EnableIRQ - 0x08001784 0x34 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o + 0x08001808 0x34 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o .text.__NVIC_SetPriority - 0x080017b8 0xdc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o + 0x0800183c 0xdc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o .text.SysTick_Config - 0x08001894 0x48 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o + 0x08001918 0x48 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o .text.HAL_NVIC_SetPriority - 0x080018dc 0x2a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o - 0x080018dc HAL_NVIC_SetPriority + 0x08001960 0x2a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o + 0x08001960 HAL_NVIC_SetPriority .text.HAL_NVIC_EnableIRQ - 0x08001906 0x20 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o - 0x08001906 HAL_NVIC_EnableIRQ + 0x0800198a 0x20 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o + 0x0800198a HAL_NVIC_EnableIRQ .text.HAL_SYSTICK_Config - 0x08001926 0x1a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o - 0x08001926 HAL_SYSTICK_Config + 0x080019aa 0x1a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o + 0x080019aa HAL_SYSTICK_Config .text.HAL_DMA_Init - 0x08001940 0x114 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o - 0x08001940 HAL_DMA_Init + 0x080019c4 0x114 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o + 0x080019c4 HAL_DMA_Init .text.HAL_DMA_Start_IT - 0x08001a54 0x10e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o - 0x08001a54 HAL_DMA_Start_IT - *fill* 0x08001b62 0x2 + 0x08001ad8 0x10e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o + 0x08001ad8 HAL_DMA_Start_IT + *fill* 0x08001be6 0x2 .text.HAL_DMA_IRQHandler - 0x08001b64 0x164 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o - 0x08001b64 HAL_DMA_IRQHandler + 0x08001be8 0x164 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o + 0x08001be8 HAL_DMA_IRQHandler .text.DMA_SetConfig - 0x08001cc8 0x80 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o + 0x08001d4c 0x80 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o .text.DMA_CalcDMAMUXChannelBaseAndMask - 0x08001d48 0x58 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o + 0x08001dcc 0x58 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o .text.DMA_CalcDMAMUXRequestGenBaseAndMask - 0x08001da0 0x48 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o + 0x08001e24 0x48 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o .text.HAL_GPIO_Init - 0x08001de8 0x2e4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o - 0x08001de8 HAL_GPIO_Init + 0x08001e6c 0x2e4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o + 0x08001e6c HAL_GPIO_Init .text.HAL_GPIO_ReadPin - 0x080020cc 0x3a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o - 0x080020cc HAL_GPIO_ReadPin + 0x08002150 0x3a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o + 0x08002150 HAL_GPIO_ReadPin .text.HAL_GPIO_WritePin - 0x08002106 0x3a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o - 0x08002106 HAL_GPIO_WritePin + 0x0800218a 0x3a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o + 0x0800218a HAL_GPIO_WritePin .text.HAL_GPIO_EXTI_IRQHandler - 0x08002140 0x54 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o - 0x08002140 HAL_GPIO_EXTI_IRQHandler + 0x080021c4 0x54 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o + 0x080021c4 HAL_GPIO_EXTI_IRQHandler .text.HAL_GPIO_EXTI_Rising_Callback - 0x08002194 0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o - 0x08002194 HAL_GPIO_EXTI_Rising_Callback + 0x08002218 0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o + 0x08002218 HAL_GPIO_EXTI_Rising_Callback .text.HAL_GPIO_EXTI_Falling_Callback - 0x080021a8 0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o - 0x080021a8 HAL_GPIO_EXTI_Falling_Callback + 0x0800222c 0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o + 0x0800222c HAL_GPIO_EXTI_Falling_Callback .text.HAL_RCC_OscConfig - 0x080021bc 0x3c8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o - 0x080021bc HAL_RCC_OscConfig + 0x08002240 0x3c8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o + 0x08002240 HAL_RCC_OscConfig .text.HAL_RCC_ClockConfig - 0x08002584 0x214 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o - 0x08002584 HAL_RCC_ClockConfig + 0x08002608 0x214 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o + 0x08002608 HAL_RCC_ClockConfig .text.HAL_RCC_GetSysClockFreq - 0x08002798 0xa0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o - 0x08002798 HAL_RCC_GetSysClockFreq + 0x0800281c 0xa0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o + 0x0800281c HAL_RCC_GetSysClockFreq .text.HAL_RCC_GetHCLKFreq - 0x08002838 0x3c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o - 0x08002838 HAL_RCC_GetHCLKFreq + 0x080028bc 0x3c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o + 0x080028bc HAL_RCC_GetHCLKFreq .text.HAL_RCC_GetPCLK1Freq - 0x08002874 0x30 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o - 0x08002874 HAL_RCC_GetPCLK1Freq + 0x080028f8 0x30 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o + 0x080028f8 HAL_RCC_GetPCLK1Freq .text.HAL_RCCEx_PeriphCLKConfig - 0x080028a4 0x1d8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o - 0x080028a4 HAL_RCCEx_PeriphCLKConfig + 0x08002928 0x1d8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o + 0x08002928 HAL_RCCEx_PeriphCLKConfig .text.HAL_TIM_Base_Init - 0x08002a7c 0xb0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o - 0x08002a7c HAL_TIM_Base_Init + 0x08002b00 0xb0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x08002b00 HAL_TIM_Base_Init .text.HAL_TIM_PWM_Init - 0x08002b2c 0xb0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o - 0x08002b2c HAL_TIM_PWM_Init + 0x08002bb0 0xb0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x08002bb0 HAL_TIM_PWM_Init .text.HAL_TIM_PWM_MspInit - 0x08002bdc 0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o - 0x08002bdc HAL_TIM_PWM_MspInit + 0x08002c60 0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x08002c60 HAL_TIM_PWM_MspInit .text.HAL_TIM_Encoder_Init - 0x08002bec 0x150 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o - 0x08002bec HAL_TIM_Encoder_Init + 0x08002c70 0x150 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x08002c70 HAL_TIM_Encoder_Init .text.HAL_TIM_IRQHandler - 0x08002d3c 0x210 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o - 0x08002d3c HAL_TIM_IRQHandler + 0x08002dc0 0x210 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x08002dc0 HAL_TIM_IRQHandler .text.HAL_TIM_PWM_ConfigChannel - 0x08002f4c 0x200 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o - 0x08002f4c HAL_TIM_PWM_ConfigChannel + 0x08002fd0 0x200 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x08002fd0 HAL_TIM_PWM_ConfigChannel .text.HAL_TIM_ConfigClockSource - 0x0800314c 0x1ac ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o - 0x0800314c HAL_TIM_ConfigClockSource + 0x080031d0 0x1ac ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x080031d0 HAL_TIM_ConfigClockSource .text.HAL_TIM_OC_DelayElapsedCallback - 0x080032f8 0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o - 0x080032f8 HAL_TIM_OC_DelayElapsedCallback + 0x0800337c 0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x0800337c HAL_TIM_OC_DelayElapsedCallback .text.HAL_TIM_IC_CaptureCallback - 0x08003308 0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o - 0x08003308 HAL_TIM_IC_CaptureCallback + 0x0800338c 0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x0800338c HAL_TIM_IC_CaptureCallback .text.HAL_TIM_PWM_PulseFinishedCallback - 0x08003318 0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o - 0x08003318 HAL_TIM_PWM_PulseFinishedCallback + 0x0800339c 0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x0800339c HAL_TIM_PWM_PulseFinishedCallback .text.HAL_TIM_TriggerCallback - 0x08003328 0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o - 0x08003328 HAL_TIM_TriggerCallback + 0x080033ac 0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x080033ac HAL_TIM_TriggerCallback .text.TIM_Base_SetConfig - 0x08003338 0xf8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o - 0x08003338 TIM_Base_SetConfig + 0x080033bc 0xf8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x080033bc TIM_Base_SetConfig .text.TIM_OC1_SetConfig - 0x08003430 0x100 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x080034b4 0x100 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o .text.TIM_OC2_SetConfig - 0x08003530 0xfc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o - 0x08003530 TIM_OC2_SetConfig + 0x080035b4 0xfc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x080035b4 TIM_OC2_SetConfig .text.TIM_OC3_SetConfig - 0x0800362c 0x104 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x080036b0 0x104 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o .text.TIM_OC4_SetConfig - 0x08003730 0xc8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x080037b4 0xc8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o .text.TIM_OC5_SetConfig - 0x080037f8 0xb4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x0800387c 0xb4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o .text.TIM_OC6_SetConfig - 0x080038ac 0xbc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x08003930 0xbc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o .text.TIM_TI1_ConfigInputStage - 0x08003968 0x5c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x080039ec 0x5c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o .text.TIM_TI2_ConfigInputStage - 0x080039c4 0x64 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x08003a48 0x64 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o .text.TIM_ITRx_SetConfig - 0x08003a28 0x38 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x08003aac 0x38 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o .text.TIM_ETR_SetConfig - 0x08003a60 0x40 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o - 0x08003a60 TIM_ETR_SetConfig + 0x08003ae4 0x40 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x08003ae4 TIM_ETR_SetConfig .text.HAL_TIMEx_MasterConfigSynchronization - 0x08003aa0 0xd0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o - 0x08003aa0 HAL_TIMEx_MasterConfigSynchronization + 0x08003b24 0xd0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o + 0x08003b24 HAL_TIMEx_MasterConfigSynchronization .text.HAL_TIMEx_ConfigBreakDeadTime - 0x08003b70 0x138 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o - 0x08003b70 HAL_TIMEx_ConfigBreakDeadTime + 0x08003bf4 0x138 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o + 0x08003bf4 HAL_TIMEx_ConfigBreakDeadTime .text.HAL_TIMEx_CommutCallback - 0x08003ca8 0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o - 0x08003ca8 HAL_TIMEx_CommutCallback + 0x08003d2c 0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o + 0x08003d2c HAL_TIMEx_CommutCallback .text.HAL_TIMEx_BreakCallback - 0x08003cb8 0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o - 0x08003cb8 HAL_TIMEx_BreakCallback + 0x08003d3c 0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o + 0x08003d3c HAL_TIMEx_BreakCallback .text.HAL_TIMEx_Break2Callback - 0x08003cc8 0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o - 0x08003cc8 HAL_TIMEx_Break2Callback + 0x08003d4c 0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o + 0x08003d4c HAL_TIMEx_Break2Callback .text.HAL_UART_Init - 0x08003cd8 0xac ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o - 0x08003cd8 HAL_UART_Init + 0x08003d5c 0xac ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o + 0x08003d5c HAL_UART_Init .text.HAL_UART_RxCpltCallback - 0x08003d84 0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o - 0x08003d84 HAL_UART_RxCpltCallback + 0x08003e08 0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o + 0x08003e08 HAL_UART_RxCpltCallback .text.HAL_UART_RxHalfCpltCallback - 0x08003d94 0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o - 0x08003d94 HAL_UART_RxHalfCpltCallback + 0x08003e18 0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o + 0x08003e18 HAL_UART_RxHalfCpltCallback .text.HAL_UART_ErrorCallback - 0x08003da4 0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o - 0x08003da4 HAL_UART_ErrorCallback + 0x08003e28 0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o + 0x08003e28 HAL_UART_ErrorCallback .text.UART_SetConfig - 0x08003db4 0x2fc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o - 0x08003db4 UART_SetConfig + 0x08003e38 0x2fc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o + 0x08003e38 UART_SetConfig .text.UART_AdvFeatureConfig - 0x080040b0 0x168 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o - 0x080040b0 UART_AdvFeatureConfig + 0x08004134 0x168 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o + 0x08004134 UART_AdvFeatureConfig .text.UART_CheckIdleState - 0x08004218 0x154 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o - 0x08004218 UART_CheckIdleState + 0x0800429c 0x154 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o + 0x0800429c UART_CheckIdleState .text.UART_WaitOnFlagUntilTimeout - 0x0800436c 0xde ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o - 0x0800436c UART_WaitOnFlagUntilTimeout - *fill* 0x0800444a 0x2 + 0x080043f0 0xde ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o + 0x080043f0 UART_WaitOnFlagUntilTimeout + *fill* 0x080044ce 0x2 .text.UART_Start_Receive_DMA - 0x0800444c 0x14c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o - 0x0800444c UART_Start_Receive_DMA + 0x080044d0 0x14c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o + 0x080044d0 UART_Start_Receive_DMA .text.UART_EndTxTransfer - 0x08004598 0x80 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o + 0x0800461c 0x80 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o .text.UART_EndRxTransfer - 0x08004618 0xcc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o + 0x0800469c 0xcc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o .text.UART_DMAReceiveCplt - 0x080046e4 0x168 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o + 0x08004768 0x168 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o .text.UART_DMARxHalfCplt - 0x0800484c 0x7e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o + 0x080048d0 0x7e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o .text.UART_DMAError - 0x080048ca 0x86 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o + 0x0800494e 0x86 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o .text.HAL_RS485Ex_Init - 0x08004950 0xe4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o - 0x08004950 HAL_RS485Ex_Init + 0x080049d4 0xe4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o + 0x080049d4 HAL_RS485Ex_Init .text.HAL_UARTEx_DisableFifoMode - 0x08004a34 0x74 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o - 0x08004a34 HAL_UARTEx_DisableFifoMode + 0x08004ab8 0x74 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o + 0x08004ab8 HAL_UARTEx_DisableFifoMode .text.HAL_UARTEx_SetTxFifoThreshold - 0x08004aa8 0x7e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o - 0x08004aa8 HAL_UARTEx_SetTxFifoThreshold - *fill* 0x08004b26 0x2 + 0x08004b2c 0x7e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o + 0x08004b2c HAL_UARTEx_SetTxFifoThreshold + *fill* 0x08004baa 0x2 .text.HAL_UARTEx_SetRxFifoThreshold - 0x08004b28 0x84 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o - 0x08004b28 HAL_UARTEx_SetRxFifoThreshold + 0x08004bac 0x84 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o + 0x08004bac HAL_UARTEx_SetRxFifoThreshold .text.HAL_UARTEx_ReceiveToIdle_DMA - 0x08004bac 0xd0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o - 0x08004bac HAL_UARTEx_ReceiveToIdle_DMA + 0x08004c30 0xd0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o + 0x08004c30 HAL_UARTEx_ReceiveToIdle_DMA .text.UARTEx_SetNbDataToProcess - 0x08004c7c 0xbc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o - .text.memset 0x08004d38 0x10 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memset.o) - 0x08004d38 memset + 0x08004d00 0xbc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o + .text.memset 0x08004dbc 0x10 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memset.o) + 0x08004dbc memset .text.__libc_init_array - 0x08004d48 0x48 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-init.o) - 0x08004d48 __libc_init_array - .text.memcpy 0x08004d90 0x12 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memcpy-stub.o) - 0x08004d90 memcpy + 0x08004dcc 0x48 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-init.o) + 0x08004dcc __libc_init_array + .text.memcpy 0x08004e14 0x12 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memcpy-stub.o) + 0x08004e14 memcpy *(.glue_7) - .glue_7 0x08004da2 0x0 linker stubs + .glue_7 0x08004e26 0x0 linker stubs *(.glue_7t) - .glue_7t 0x08004da2 0x0 linker stubs + .glue_7t 0x08004e26 0x0 linker stubs *(.eh_frame) - *fill* 0x08004da2 0x2 - .eh_frame 0x08004da4 0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o + *fill* 0x08004e26 0x2 + .eh_frame 0x08004e28 0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o *(.init) - .init 0x08004da4 0x4 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crti.o - 0x08004da4 _init - .init 0x08004da8 0x8 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtn.o + .init 0x08004e28 0x4 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crti.o + 0x08004e28 _init + .init 0x08004e2c 0x8 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtn.o *(.fini) - .fini 0x08004db0 0x4 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crti.o - 0x08004db0 _fini - .fini 0x08004db4 0x8 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtn.o - 0x08004dbc . = ALIGN (0x4) - 0x08004dbc _etext = . + .fini 0x08004e34 0x4 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crti.o + 0x08004e34 _fini + .fini 0x08004e38 0x8 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtn.o + 0x08004e40 . = ALIGN (0x4) + 0x08004e40 _etext = . -.vfp11_veneer 0x08004dbc 0x0 - .vfp11_veneer 0x08004dbc 0x0 linker stubs +.vfp11_veneer 0x08004e40 0x0 + .vfp11_veneer 0x08004e40 0x0 linker stubs -.v4_bx 0x08004dbc 0x0 - .v4_bx 0x08004dbc 0x0 linker stubs +.v4_bx 0x08004e40 0x0 + .v4_bx 0x08004e40 0x0 linker stubs -.iplt 0x08004dbc 0x0 - .iplt 0x08004dbc 0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o +.iplt 0x08004e40 0x0 + .iplt 0x08004e40 0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o -.rodata 0x08004dbc 0xdc - 0x08004dbc . = ALIGN (0x4) +.rodata 0x08004e40 0xdc + 0x08004e40 . = ALIGN (0x4) *(.rodata) *(.rodata*) .rodata.AHBPrescTable - 0x08004dbc 0x40 ./Core/Src/system_stm32c0xx.o - 0x08004dbc AHBPrescTable + 0x08004e40 0x40 ./Core/Src/system_stm32c0xx.o + 0x08004e40 AHBPrescTable .rodata.APBPrescTable - 0x08004dfc 0x20 ./Core/Src/system_stm32c0xx.o - 0x08004dfc APBPrescTable + 0x08004e80 0x20 ./Core/Src/system_stm32c0xx.o + 0x08004e80 APBPrescTable .rodata.HAL_TIM_PWM_ConfigChannel - 0x08004e1c 0x54 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x08004ea0 0x54 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o .rodata.UARTPrescTable - 0x08004e70 0x18 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o - 0x08004e70 UARTPrescTable + 0x08004ef4 0x18 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o + 0x08004ef4 UARTPrescTable .rodata.numerator.1 - 0x08004e88 0x8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o + 0x08004f0c 0x8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o .rodata.denominator.0 - 0x08004e90 0x8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o - 0x08004e98 . = ALIGN (0x4) + 0x08004f14 0x8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o + 0x08004f1c . = ALIGN (0x4) -.ARM.extab 0x08004e98 0x0 - 0x08004e98 . = ALIGN (0x4) +.ARM.extab 0x08004f1c 0x0 + 0x08004f1c . = ALIGN (0x4) *(.ARM.extab* .gnu.linkonce.armextab.*) - 0x08004e98 . = ALIGN (0x4) + 0x08004f1c . = ALIGN (0x4) -.ARM 0x08004e98 0x0 - 0x08004e98 . = ALIGN (0x4) - 0x08004e98 __exidx_start = . +.ARM 0x08004f1c 0x0 + 0x08004f1c . = ALIGN (0x4) + 0x08004f1c __exidx_start = . *(.ARM.exidx*) - 0x08004e98 __exidx_end = . - 0x08004e98 . = ALIGN (0x4) + 0x08004f1c __exidx_end = . + 0x08004f1c . = ALIGN (0x4) -.preinit_array 0x08004e98 0x0 - 0x08004e98 . = ALIGN (0x4) - 0x08004e98 PROVIDE (__preinit_array_start = .) +.preinit_array 0x08004f1c 0x0 + 0x08004f1c . = ALIGN (0x4) + 0x08004f1c PROVIDE (__preinit_array_start = .) *(.preinit_array*) - 0x08004e98 PROVIDE (__preinit_array_end = .) - 0x08004e98 . = ALIGN (0x4) + 0x08004f1c PROVIDE (__preinit_array_end = .) + 0x08004f1c . = ALIGN (0x4) -.init_array 0x08004e98 0x4 - 0x08004e98 . = ALIGN (0x4) - 0x08004e98 PROVIDE (__init_array_start = .) +.init_array 0x08004f1c 0x4 + 0x08004f1c . = ALIGN (0x4) + 0x08004f1c PROVIDE (__init_array_start = .) *(SORT_BY_NAME(.init_array.*)) *(.init_array*) - .init_array 0x08004e98 0x4 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o - 0x08004e9c PROVIDE (__init_array_end = .) - 0x08004e9c . = ALIGN (0x4) + .init_array 0x08004f1c 0x4 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o + 0x08004f20 PROVIDE (__init_array_end = .) + 0x08004f20 . = ALIGN (0x4) -.fini_array 0x08004e9c 0x4 - 0x08004e9c . = ALIGN (0x4) +.fini_array 0x08004f20 0x4 + 0x08004f20 . = ALIGN (0x4) [!provide] PROVIDE (__fini_array_start = .) *(SORT_BY_NAME(.fini_array.*)) *(.fini_array*) - .fini_array 0x08004e9c 0x4 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o + .fini_array 0x08004f20 0x4 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o [!provide] PROVIDE (__fini_array_end = .) - 0x08004ea0 . = ALIGN (0x4) - 0x08004ea0 _sidata = LOADADDR (.data) + 0x08004f24 . = ALIGN (0x4) + 0x08004f24 _sidata = LOADADDR (.data) -.rel.dyn 0x08004ea0 0x0 - .rel.iplt 0x08004ea0 0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o +.rel.dyn 0x08004f24 0x0 + .rel.iplt 0x08004f24 0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o -.data 0x20000000 0x24 load address 0x08004ea0 +.data 0x20000000 0x24 load address 0x08004f24 0x20000000 . = ALIGN (0x4) 0x20000000 _sdata = . *(.data) @@ -3552,11 +3619,11 @@ LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext *fill* 0x20000021 0x3 0x20000024 _edata = . -.igot.plt 0x20000024 0x0 load address 0x08004ec4 +.igot.plt 0x20000024 0x0 load address 0x08004f48 .igot.plt 0x20000024 0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o 0x20000024 . = ALIGN (0x4) -.bss 0x20000024 0x48c load address 0x08004ec4 +.bss 0x20000024 0x490 load address 0x08004f48 0x20000024 _sbss = . 0x20000024 __bss_start__ = _sbss *(.bss) @@ -3621,23 +3688,26 @@ LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext .bss.motor_cmd 0x200004a8 0x4 ./Core/Src/main.o 0x200004a8 motor_cmd - .bss.uwTick 0x200004ac 0x4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o - 0x200004ac uwTick + .bss.pid_add 0x200004ac 0x4 ./Core/Src/main.o + 0x200004ac pid_add + .bss.uwTick 0x200004b0 0x4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o + 0x200004b0 uwTick *(COMMON) - 0x200004b0 . = ALIGN (0x4) - 0x200004b0 _ebss = . - 0x200004b0 __bss_end__ = _ebss + 0x200004b4 . = ALIGN (0x4) + 0x200004b4 _ebss = . + 0x200004b4 __bss_end__ = _ebss ._user_heap_stack - 0x200004b0 0x600 load address 0x08004ec4 - 0x200004b0 . = ALIGN (0x8) + 0x200004b4 0x604 load address 0x08004f48 + 0x200004b8 . = ALIGN (0x8) + *fill* 0x200004b4 0x4 [!provide] PROVIDE (end = .) - 0x200004b0 PROVIDE (_end = .) - 0x200006b0 . = (. + _Min_Heap_Size) - *fill* 0x200004b0 0x200 - 0x20000ab0 . = (. + _Min_Stack_Size) - *fill* 0x200006b0 0x400 - 0x20000ab0 . = ALIGN (0x8) + 0x200004b8 PROVIDE (_end = .) + 0x200006b8 . = (. + _Min_Heap_Size) + *fill* 0x200004b8 0x200 + 0x20000ab8 . = (. + _Min_Stack_Size) + *fill* 0x200006b8 0x400 + 0x20000ab8 . = ALIGN (0x8) /DISCARD/ libc.a(*) @@ -3701,232 +3771,224 @@ LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libm.a LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a -.debug_info 0x00000000 0x104fc - .debug_info 0x00000000 0x1e6f ./Core/Src/main.o - .debug_info 0x00001e6f 0x1215 ./Core/Src/stm32c0xx_hal_msp.o - .debug_info 0x00003084 0x849 ./Core/Src/stm32c0xx_it.o - .debug_info 0x000038cd 0x36f ./Core/Src/system_stm32c0xx.o - .debug_info 0x00003c3c 0x30 ./Core/Startup/startup_stm32c051c6tx.o - .debug_info 0x00003c6c 0x844 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o - .debug_info 0x000044b0 0x88d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o - .debug_info 0x00004d3d 0x830 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o - .debug_info 0x0000556d 0x5b7 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o - .debug_info 0x00005b24 0x915 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o - .debug_info 0x00006439 0x551 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o - .debug_info 0x0000698a 0x2b65 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o - .debug_info 0x000094ef 0x1878 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o - .debug_info 0x0000ad67 0x4828 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o - .debug_info 0x0000f58f 0xf6d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o +.debug_info 0x00000000 0x10a96 + .debug_info 0x00000000 0x2409 ./Core/Src/main.o + .debug_info 0x00002409 0x1215 ./Core/Src/stm32c0xx_hal_msp.o + .debug_info 0x0000361e 0x849 ./Core/Src/stm32c0xx_it.o + .debug_info 0x00003e67 0x36f ./Core/Src/system_stm32c0xx.o + .debug_info 0x000041d6 0x30 ./Core/Startup/startup_stm32c051c6tx.o + .debug_info 0x00004206 0x844 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o + .debug_info 0x00004a4a 0x88d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o + .debug_info 0x000052d7 0x830 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o + .debug_info 0x00005b07 0x5b7 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o + .debug_info 0x000060be 0x915 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o + .debug_info 0x000069d3 0x551 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o + .debug_info 0x00006f24 0x2b65 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + .debug_info 0x00009a89 0x1878 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o + .debug_info 0x0000b301 0x4828 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o + .debug_info 0x0000fb29 0xf6d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o -.debug_abbrev 0x00000000 0x21de - .debug_abbrev 0x00000000 0x389 ./Core/Src/main.o - .debug_abbrev 0x00000389 0x25f ./Core/Src/stm32c0xx_hal_msp.o - .debug_abbrev 0x000005e8 0x1a6 ./Core/Src/stm32c0xx_it.o - .debug_abbrev 0x0000078e 0x11b ./Core/Src/system_stm32c0xx.o - .debug_abbrev 0x000008a9 0x24 ./Core/Startup/startup_stm32c051c6tx.o - .debug_abbrev 0x000008cd 0x2cb ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o - .debug_abbrev 0x00000b98 0x2b7 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o - .debug_abbrev 0x00000e4f 0x1dc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o - .debug_abbrev 0x0000102b 0x1d6 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o - .debug_abbrev 0x00001201 0x28b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o - .debug_abbrev 0x0000148c 0x225 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o - .debug_abbrev 0x000016b1 0x28a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o - .debug_abbrev 0x0000193b 0x2aa ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o - .debug_abbrev 0x00001be5 0x314 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o - .debug_abbrev 0x00001ef9 0x2e5 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o +.debug_abbrev 0x00000000 0x2210 + .debug_abbrev 0x00000000 0x3bb ./Core/Src/main.o + .debug_abbrev 0x000003bb 0x25f ./Core/Src/stm32c0xx_hal_msp.o + .debug_abbrev 0x0000061a 0x1a6 ./Core/Src/stm32c0xx_it.o + .debug_abbrev 0x000007c0 0x11b ./Core/Src/system_stm32c0xx.o + .debug_abbrev 0x000008db 0x24 ./Core/Startup/startup_stm32c051c6tx.o + .debug_abbrev 0x000008ff 0x2cb ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o + .debug_abbrev 0x00000bca 0x2b7 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o + .debug_abbrev 0x00000e81 0x1dc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o + .debug_abbrev 0x0000105d 0x1d6 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o + .debug_abbrev 0x00001233 0x28b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o + .debug_abbrev 0x000014be 0x225 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o + .debug_abbrev 0x000016e3 0x28a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + .debug_abbrev 0x0000196d 0x2aa ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o + .debug_abbrev 0x00001c17 0x314 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o + .debug_abbrev 0x00001f2b 0x2e5 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o -.debug_aranges 0x00000000 0xe00 +.debug_aranges 0x00000000 0xe18 .debug_aranges - 0x00000000 0xc0 ./Core/Src/main.o + 0x00000000 0xd8 ./Core/Src/main.o .debug_aranges - 0x000000c0 0x58 ./Core/Src/stm32c0xx_hal_msp.o + 0x000000d8 0x58 ./Core/Src/stm32c0xx_hal_msp.o .debug_aranges - 0x00000118 0x70 ./Core/Src/stm32c0xx_it.o + 0x00000130 0x70 ./Core/Src/stm32c0xx_it.o .debug_aranges - 0x00000188 0x28 ./Core/Src/system_stm32c0xx.o + 0x000001a0 0x28 ./Core/Src/system_stm32c0xx.o .debug_aranges - 0x000001b0 0x28 ./Core/Startup/startup_stm32c051c6tx.o + 0x000001c8 0x28 ./Core/Startup/startup_stm32c051c6tx.o .debug_aranges - 0x000001d8 0x100 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o + 0x000001f0 0x100 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o .debug_aranges - 0x000002d8 0xe8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o + 0x000002f0 0xe8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o .debug_aranges - 0x000003c0 0x90 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o + 0x000003d8 0x90 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o .debug_aranges - 0x00000450 0x68 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o + 0x00000468 0x68 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o .debug_aranges - 0x000004b8 0xa0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o + 0x000004d0 0xa0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o .debug_aranges - 0x00000558 0x40 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o + 0x00000570 0x40 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o .debug_aranges - 0x00000598 0x3e0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x000005b0 0x3e0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o .debug_aranges - 0x00000978 0x198 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o + 0x00000990 0x198 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o .debug_aranges - 0x00000b10 0x248 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o + 0x00000b28 0x248 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o .debug_aranges - 0x00000d58 0xa8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o + 0x00000d70 0xa8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o .debug_rnglists - 0x00000000 0xb16 + 0x00000000 0xb29 .debug_rnglists - 0x00000000 0x96 ./Core/Src/main.o + 0x00000000 0xa9 ./Core/Src/main.o .debug_rnglists - 0x00000096 0x43 ./Core/Src/stm32c0xx_hal_msp.o + 0x000000a9 0x43 ./Core/Src/stm32c0xx_hal_msp.o .debug_rnglists - 0x000000d9 0x4f ./Core/Src/stm32c0xx_it.o + 0x000000ec 0x4f ./Core/Src/stm32c0xx_it.o .debug_rnglists - 0x00000128 0x1a ./Core/Src/system_stm32c0xx.o + 0x0000013b 0x1a ./Core/Src/system_stm32c0xx.o .debug_rnglists - 0x00000142 0x19 ./Core/Startup/startup_stm32c051c6tx.o + 0x00000155 0x19 ./Core/Startup/startup_stm32c051c6tx.o .debug_rnglists - 0x0000015b 0xbc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o + 0x0000016e 0xbc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o .debug_rnglists - 0x00000217 0xaa ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o + 0x0000022a 0xaa ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o .debug_rnglists - 0x000002c1 0x72 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o + 0x000002d4 0x72 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o .debug_rnglists - 0x00000333 0x4b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o + 0x00000346 0x4b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o .debug_rnglists - 0x0000037e 0x78 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o + 0x00000391 0x78 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o .debug_rnglists - 0x000003f6 0x2d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o + 0x00000409 0x2d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o .debug_rnglists - 0x00000423 0x32a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x00000436 0x32a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o .debug_rnglists - 0x0000074d 0x14e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o + 0x00000760 0x14e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o .debug_rnglists - 0x0000089b 0x1fb ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o + 0x000008ae 0x1fb ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o .debug_rnglists - 0x00000a96 0x80 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o + 0x00000aa9 0x80 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o -.debug_macro 0x00000000 0x14883 - .debug_macro 0x00000000 0x330 ./Core/Src/main.o - .debug_macro 0x00000330 0xaae ./Core/Src/main.o - .debug_macro 0x00000dde 0x2e ./Core/Src/main.o - .debug_macro 0x00000e0c 0x28 ./Core/Src/main.o - .debug_macro 0x00000e34 0x22 ./Core/Src/main.o - .debug_macro 0x00000e56 0x8e ./Core/Src/main.o - .debug_macro 0x00000ee4 0x51 ./Core/Src/main.o - .debug_macro 0x00000f35 0x103 ./Core/Src/main.o - .debug_macro 0x00001038 0x6a ./Core/Src/main.o - .debug_macro 0x000010a2 0x1df ./Core/Src/main.o - .debug_macro 0x00001281 0x1c ./Core/Src/main.o - .debug_macro 0x0000129d 0x22 ./Core/Src/main.o - .debug_macro 0x000012bf 0xd1 ./Core/Src/main.o - .debug_macro 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./Core/Src/stm32c0xx_it.o + .debug_frame 0x00000554 0x4c ./Core/Src/system_stm32c0xx.o + .debug_frame 0x000005a0 0x368 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o + .debug_frame 0x00000908 0x33c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o + .debug_frame 0x00000c44 0x1f0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o + .debug_frame 0x00000e34 0x150 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o + .debug_frame 0x00000f84 0x214 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o + .debug_frame 0x00001198 0xac ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o + .debug_frame 0x00001244 0xf40 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + .debug_frame 0x00002184 0x620 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o + .debug_frame 0x000027a4 0x8d4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o + .debug_frame 0x00003078 0x258 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o + .debug_frame 0x000032d0 0x20 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memset.o) + .debug_frame 0x000032f0 0x2c C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-init.o) + .debug_frame 0x0000331c 0x28 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memcpy-stub.o) + .debug_frame 0x00003344 0x20 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a(_udivsi3.o) + .debug_frame 0x00003364 0x20 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a(_divsi3.o) .debug_line_str 0x00000000 0x4d diff --git a/code/Debug/objects.list b/code/Debug/objects.list index 0a962c1..f188521 100644 --- a/code/Debug/objects.list +++ b/code/Debug/objects.list @@ -1,3 +1,4 @@ +"./Core/Src/crc.o" "./Core/Src/main.o" "./Core/Src/stm32c0xx_hal_msp.o" "./Core/Src/stm32c0xx_it.o"