diff --git a/code/Core/Inc/crc.h b/code/Core/Inc/crc.h new file mode 100644 index 0000000..a4627b0 --- /dev/null +++ b/code/Core/Inc/crc.h @@ -0,0 +1,26 @@ +/* + * crc.h + * + * Created on: 19 Dec 2025 + * Author: janik + */ + +#ifndef INC_CRC_H_ +#define INC_CRC_H_ + +#include +#include + +typedef struct { + uint32_t crc; +} CRC8_107; + +static inline void CRC8_107_init(CRC8_107 *ctx) +{ + ctx->crc = 0x0u; +} + +void CRC8_107_add(CRC8_107 *ctx, uint8_t data); +uint8_t CRC8_107_getChecksum(const CRC8_107 *ctx); + +#endif /* INC_CRC_H_ */ diff --git a/code/Core/Inc/photon_protocol.h b/code/Core/Inc/photon_protocol.h new file mode 100644 index 0000000..b4739b4 --- /dev/null +++ b/code/Core/Inc/photon_protocol.h @@ -0,0 +1,140 @@ +/* + * photon_protocol.h + * + * Created on: 19 Dec 2025 + * Author: janik + */ + +#ifndef INC_PHOTON_PROTOCOL_H_ +#define INC_PHOTON_PROTOCOL_H_ + +#define UUID_LENGTH 12 // 12 8bit values +#define PHOTON_NETWORK_CONTROLLER_ADDRESS 0x00 +#define PHOTON_NETWORK_BROADCAST_ADDRESS 0xFF +#define VENDOR_SPECIFIC_OPTIONS_LENGTH 16 + + +typedef enum { + STATUS_OK = 0x00, + STATUS_WRONG_FEEDER_ID = 0x01, + STATUS_COULDNT_REACH = 0x02, + STATUS_UNINITIALIZED_FEEDER = 0x03, + STATUS_FEEDING_IN_PROGRESS = 0x04, + STATUS_FAIL = 0x05, + + STATUS_TIMEOUT = 0xFE, + STATUS_UNKNOWN_ERROR = 0xFF +} FeederStatus; + +typedef enum { + // Unicast Commands + GET_FEEDER_ID = 0x01, + INITIALIZE_FEEDER = 0x02, + GET_VERSION = 0x03, + MOVE_FEED_FORWARD = 0x04, + MOVE_FEED_BACKWARD = 0x05, + MOVE_FEED_STATUS = 0x06, + + VENDOR_OPTIONS = 0xbf, + + // Broadcast Commands + GET_FEEDER_ADDRESS = 0xc0, + IDENTIFY_FEEDER = 0xc1, + PROGRAM_FEEDER_FLOOR = 0xc2, + UNINITIALIZED_FEEDERS_RESPOND = 0xc3 + // EXTENDED_COMMAND = 0xff, Unused, reserved for future use +} FeederCommand; + + + +/* ---------- Packet Header ---------- */ + +typedef struct __attribute__((packed)) { + uint8_t toAddress; + uint8_t fromAddress; + uint8_t packetId; + uint8_t payloadLength; + uint8_t crc; +} PhotonPacketHeader; + +/* ---------- Command Payloads ---------- */ + +typedef struct __attribute__((packed)) { + uint8_t distance; +} MoveCommand; + +typedef struct __attribute__((packed)) { + uint8_t uuid[UUID_LENGTH]; +} GetFeederAddressCommand; + +typedef struct __attribute__((packed)) { + uint8_t uuid[UUID_LENGTH]; +} InitializeFeederCommand; + +typedef struct __attribute__((packed)) { + uint8_t options[VENDOR_SPECIFIC_OPTIONS_LENGTH]; +} VendorOptionsCommand; + +typedef struct __attribute__((packed)) { + uint8_t uuid[UUID_LENGTH]; + uint8_t address; +} ProgramFeederFloorAddressCommand; + +typedef struct __attribute__((packed)) { + uint8_t uuid[UUID_LENGTH]; +} IdentifyFeederCommand; + +/* ---------- Full Command Packet ---------- */ + +typedef struct __attribute__((packed)) { + PhotonPacketHeader header; + uint8_t commandId; + union { + MoveCommand move; + GetFeederAddressCommand getFeederAddress; + InitializeFeederCommand initializeFeeder; + VendorOptionsCommand vendorOptions; + ProgramFeederFloorAddressCommand programFeederFloorAddress; + IdentifyFeederCommand identifyFeeder; + } payload; +} PhotonCommand; + +/* ---------- Response Payloads ---------- */ + +typedef struct __attribute__((packed)) { + uint8_t uuid[UUID_LENGTH]; +} GetFeederIdResponse; + +typedef struct __attribute__((packed)) { + uint8_t uuid[UUID_LENGTH]; +} InitializeFeederResponse; + +typedef struct __attribute__((packed)) { + uint8_t version; +} GetProtocolVersionResponse; + +typedef struct __attribute__((packed)) { + uint16_t expectedFeedTime; +} FeedDistanceResponse; + +typedef struct __attribute__((packed)) { + uint8_t options[VENDOR_SPECIFIC_OPTIONS_LENGTH]; +} VendorOptionsResponse; + +/* ---------- Full Response Packet ---------- */ + +typedef struct __attribute__((packed)) { + PhotonPacketHeader header; + uint8_t status; + union { + GetFeederIdResponse getFeederId; + InitializeFeederResponse initializeFeeder; + GetProtocolVersionResponse protocolVersion; + FeedDistanceResponse expectedTimeToFeed; + VendorOptionsResponse vendorOptions; + } payload; +} PhotonResponse; + + + +#endif /* INC_PHOTON_PROTOCOL_H_ */ diff --git a/code/Core/Inc/pid.h b/code/Core/Inc/pid.h new file mode 100644 index 0000000..e3ebb30 --- /dev/null +++ b/code/Core/Inc/pid.h @@ -0,0 +1,137 @@ +/* + * pid.h + * + * Created on: 19 Dec 2025 + * Author: janik + */ + +#ifndef INC_PID_H_ +#define INC_PID_H_ + +// pid_motor_wrap_i32.h +typedef struct +{ + // Gains + int32_t kp; + int32_t ki; + int32_t kd; + + // State + int32_t integrator; + int32_t prev_error; + + // Limits + int32_t integrator_min; + int32_t integrator_max; + int32_t out_max; // max |u|, e.g. 2400 + + // Slew limit + int32_t max_output_step; // max |u(k) - u(k-1)| per control step + int32_t last_output; // u(k-1) +} pid_i32_t; + +typedef struct +{ + uint16_t pwm; // 0..out_max + uint8_t dir; // 0 or 1 +} pid_motor_cmd_t; + +static inline int32_t clamp_i32(int32_t x, int32_t lo, int32_t hi) +{ + if (x < lo) return lo; + if (x > hi) return hi; + return x; +} + +static inline void pid_init(pid_i32_t *pid, + int32_t kp, + int32_t ki, + int32_t kd, + int32_t integrator_min, + int32_t integrator_max, + int32_t out_max, + int32_t max_output_step) +{ + pid->kp = kp; + pid->ki = ki; + pid->kd = kd; + + pid->integrator = 0; + pid->prev_error = 0; + + pid->integrator_min = integrator_min; + pid->integrator_max = integrator_max; + pid->out_max = out_max; + + pid->max_output_step = max_output_step; + pid->last_output = 0; +} + +static inline void pid_reset(pid_i32_t *pid) +{ + pid->integrator = 0; + pid->prev_error = 0; + pid->last_output = 0; +} + +static inline pid_motor_cmd_t pid_update_motor(pid_i32_t *pid, + int32_t setpoint, + int32_t position) +{ + pid_motor_cmd_t cmd; + + // Basic PID (no overflow protection, as requested) + int32_t error = setpoint - position; + + int32_t p = pid->kp * error; + + int32_t i = pid->integrator + pid->ki * error; + i = clamp_i32(i, pid->integrator_min, pid->integrator_max); + pid->integrator = i; + + int32_t d_error = error - pid->prev_error; + int32_t d = pid->kd * d_error; + pid->prev_error = error; + + // Raw control effort + int32_t u_raw = p + i + d; + + // Clamp to [-out_max, +out_max] + if (u_raw > pid->out_max) u_raw = pid->out_max; + if (u_raw < -pid->out_max) u_raw = -pid->out_max; + + // ---------- Slew limit: avoid instant full reverse ---------- + int32_t u_prev = pid->last_output; + int32_t u = u_raw; + + int32_t max_step = pid->max_output_step; + if (max_step > 0) { + int32_t du = u_raw - u_prev; + + if (du > max_step) { + u = u_prev + max_step; + } else if (du < -max_step) { + u = u_prev - max_step; + } else { + u = u_raw; + } + } + + // Save for next time + pid->last_output = u; + + // Map signed u to dir + pwm + if (u >= 0) { + cmd.dir = 1; + cmd.pwm = (uint16_t)u; + } else { + cmd.dir = 0; + cmd.pwm = (uint16_t)(-u); + } + + if (cmd.pwm > pid->out_max) + cmd.pwm = (uint16_t)pid->out_max; + + return cmd; +} +#endif /* INC_PID_H_ */ diff --git a/code/Core/Inc/stm32c0xx_it.h b/code/Core/Inc/stm32c0xx_it.h index f96a7c6..6da51f5 100644 --- a/code/Core/Inc/stm32c0xx_it.h +++ b/code/Core/Inc/stm32c0xx_it.h @@ -53,6 +53,7 @@ void PendSV_Handler(void); void SysTick_Handler(void); void EXTI4_15_IRQHandler(void); void DMA1_Channel1_IRQHandler(void); +void DMA1_Channel2_3_IRQHandler(void); void TIM14_IRQHandler(void); void TIM16_IRQHandler(void); void TIM17_IRQHandler(void); diff --git a/code/Core/Src/crc.c b/code/Core/Src/crc.c new file mode 100644 index 0000000..d6fb709 --- /dev/null +++ b/code/Core/Src/crc.c @@ -0,0 +1,24 @@ +/* + * crc.c + * + * Created on: 19 Dec 2025 + * Author: janik + */ + +#include "crc.h" + +void CRC8_107_add(CRC8_107 *ctx, uint8_t data) +{ + ctx->crc ^= ((uint32_t)data << 8); + for (size_t bit_n = 0; bit_n < 8; bit_n++) { + if (ctx->crc & 0x8000u) { + ctx->crc ^= ((uint32_t)0x1070u << 3); // same as 0x8380 + } + ctx->crc <<= 1; + } +} + +uint8_t CRC8_107_getChecksum(const CRC8_107 *ctx) +{ + return (uint8_t)(ctx->crc >> 8); +} diff --git a/code/Core/Src/main.c b/code/Core/Src/main.c index 812c7e3..2918c68 100644 --- a/code/Core/Src/main.c +++ b/code/Core/Src/main.c @@ -21,6 +21,12 @@ /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ +#include "photon_protocol.h" +#include +#include +#include +#include "pid.h" +#include "crc.h" /* USER CODE END Includes */ @@ -37,6 +43,12 @@ #define CNT_MAX 65535 #define CNT_LIMIT_ZONE 1000 +#define UUID_LENGTH 12 // 12 8bit values +#define PHOTON_NETWORK_CONTROLLER_ADDRESS 0x00 +#define PHOTON_NETWORK_BROADCAST_ADDRESS 0xFF +#define PWM_MAX 2400 +#define MAX_PWM_DIFFERENCE 10 + /* USER CODE END PD */ /* Private macro -------------------------------------------------------------*/ @@ -51,16 +63,35 @@ TIM_HandleTypeDef htim3; TIM_HandleTypeDef htim14; TIM_HandleTypeDef htim16; TIM_HandleTypeDef htim17; -DMA_HandleTypeDef hdma_tim3_up; UART_HandleTypeDef huart1; UART_HandleTypeDef huart2; +DMA_HandleTypeDef hdma_usart2_rx; +DMA_HandleTypeDef hdma_usart2_tx; /* USER CODE BEGIN PV */ uint8_t sw1_pressed,sw2_pressed = 0; int32_t encoder_count_extra=0; uint16_t encoder_previous=0; - +uint8_t UUID[UUID_LENGTH]; +uint8_t is_initialized=0; +uint8_t network_buffer_RX[64]; +uint8_t msg_buffer1_empty = 1; +uint8_t msg_buffer2_empty = 1; +uint8_t msg_buffer1 [64]; +uint8_t msg_buffer2 [64]; +uint8_t DMA_buffer[64]; +uint8_t my_address = 0xFF; +int32_t total_count = 0; +int32_t target_count = 0; +int32_t kp = 4; +int32_t ki = 1; +int32_t kd = 0; +int32_t i_min = -500; +int32_t i_max = 500; +int32_t pid_max_step = 10; +pid_i32_t motor_pid; +pid_motor_cmd_t motor_cmd; /* USER CODE END PV */ /* Private function prototypes -----------------------------------------------*/ @@ -76,6 +107,10 @@ static void MX_TIM17_Init(void); static void MX_TIM14_Init(void); /* USER CODE BEGIN PFP */ +void set_LED (uint8_t R, uint8_t G, uint8_t B); +void handleRS485Message(uint8_t *buffer, uint8_t size); +void set_Feeder_PWM(uint16_t PWM, uint8_t direction); + /* USER CODE END PFP */ /* Private user code ---------------------------------------------------------*/ @@ -101,6 +136,8 @@ int main(void) /* USER CODE BEGIN Init */ + pid_init(&motor_pid,kp,ki,kd,i_min,i_max,PWM_MAX,pid_max_step); + /* USER CODE END Init */ /* Configure the system clock */ @@ -122,12 +159,67 @@ int main(void) MX_TIM14_Init(); /* USER CODE BEGIN 2 */ + uint32_t * puuid = (uint32_t *)UUID; + *puuid = HAL_GetUIDw0(); + *(puuid+1) = HAL_GetUIDw1(); + *(puuid+2) = HAL_GetUIDw2(); + + HAL_UARTEx_ReceiveToIdle_DMA (&huart2,DMA_buffer,64); + /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) { + if (sw1_pressed) + { + uint16_t time_pressed = htim16.Instance->CNT; + if ((HAL_GPIO_ReadPin(SW1_GPIO_Port,SW1_Pin)) && (time_pressed > 750)) // button still pressed + { + // todo long button action + } + else if (!HAL_GPIO_ReadPin(SW1_GPIO_Port,SW1_Pin) && (time_pressed <= 750) && (time_pressed >75)) // release in short window + { + // todo short button action + sw1_pressed = 0; + } + else if (!HAL_GPIO_ReadPin(SW1_GPIO_Port,SW1_Pin)) sw1_pressed = 0; // release in long window + } + + if (sw2_pressed) + { + uint16_t time_pressed = htim17.Instance->CNT; + if ((HAL_GPIO_ReadPin(SW2_GPIO_Port,SW2_Pin)) && (time_pressed > 750)) // button still pressed + { + // todo long button action + } + else if (!HAL_GPIO_ReadPin(SW2_GPIO_Port,SW2_Pin) && (time_pressed <= 750)) // release in short window + { + // todo short button action + sw2_pressed = 0; + } + else if (!HAL_GPIO_ReadPin(SW2_GPIO_Port,SW2_Pin)) sw2_pressed = 0; // release in long window + } + + if (!msg_buffer2_empty) // msg 2 buffer has a message + { + // decode message from msg_buffer2 + for (uint8_t i = 0; i<64 ; i++) + { + msg_buffer2[i]=0; + } + msg_buffer2_empty = 1; + } + if (!msg_buffer1_empty) + { + for (uint8_t i = 0; i<64 ; i++) + { + msg_buffer1[i]=0; + } + msg_buffer1_empty = 1; + } + /* USER CODE END WHILE */ @@ -476,7 +568,7 @@ static void MX_USART2_UART_Init(void) /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; - huart2.Init.BaudRate = 115200; + huart2.Init.BaudRate = 57600; huart2.Init.WordLength = UART_WORDLENGTH_8B; huart2.Init.StopBits = UART_STOPBITS_1; huart2.Init.Parity = UART_PARITY_NONE; @@ -490,11 +582,11 @@ static void MX_USART2_UART_Init(void) { Error_Handler(); } - if (HAL_UARTEx_SetTxFifoThreshold(&huart2, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) + if (HAL_UARTEx_SetTxFifoThreshold(&huart2, UART_TXFIFO_THRESHOLD_1_2) != HAL_OK) { Error_Handler(); } - if (HAL_UARTEx_SetRxFifoThreshold(&huart2, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) + if (HAL_UARTEx_SetRxFifoThreshold(&huart2, UART_RXFIFO_THRESHOLD_1_2) != HAL_OK) { Error_Handler(); } @@ -521,6 +613,9 @@ static void MX_DMA_Init(void) /* DMA1_Channel1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0); HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); + /* DMA1_Channel2_3_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Channel2_3_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(DMA1_Channel2_3_IRQn); } @@ -595,8 +690,20 @@ void HAL_TIM_PeriodElapsedCallback (TIM_HandleTypeDef * htim) return; } - int32_t total_count = (encoder_count_extra * CNT_MAX) + count; - // todo run PID on target position with previous error and current error (assume previous target == current target) + total_count = (encoder_count_extra * CNT_MAX) + count; + if (total_count > INT32_MAX/2) + { + total_count-= INT32_MAX/4; + target_count-= INT32_MAX/4; + } + else if (total_count < INT32_MIN/2) + { + total_count+= INT32_MAX/4; + target_count+= INT32_MAX/4; + } + + motor_cmd = pid_update_motor(&motor_pid,target_count,total_count); + set_Feeder_PWM(motor_cmd.pwm,motor_cmd.dir); } if (htim == &htim3) return; // PWM timer @@ -638,6 +745,102 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) } } +void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) +{ + if (Size > 64) return; // todo error handling + if (msg_buffer1_empty) + { + memcpy(DMA_buffer,msg_buffer1,Size); + msg_buffer1_empty = 0; + } + else if (msg_buffer2_empty) + { + memcpy(DMA_buffer,msg_buffer2,Size); + msg_buffer2_empty = 0; + } + else // no free buffer available todo error handling + { + return; + } + HAL_UARTEx_ReceiveToIdle_DMA(&huart2, DMA_buffer, 64); +} + +void set_LED (uint8_t R, uint8_t G, uint8_t B) +{ + if (R) R = GPIO_PIN_SET; + if (G) G = GPIO_PIN_SET; + if (B) B = GPIO_PIN_SET; + HAL_GPIO_WritePin(LED_R_GPIO_Port,LED_R_Pin,R); + HAL_GPIO_WritePin(LED_G_GPIO_Port,LED_G_Pin,G); + HAL_GPIO_WritePin(LED_B_GPIO_Port,LED_B_Pin,B); +} + +void handleRS485Message(uint8_t *buffer, uint8_t size) +{ + PhotonPacketHeader *header = (PhotonPacketHeader *) buffer; + // check if message is for this device or is broadcast + if (!(header->toAddress == PHOTON_NETWORK_BROADCAST_ADDRESS)) + { + if (!(header->toAddress == my_address)) + { + return; + } + } + else // this message is relevant to this device + { + PhotonCommand *command = (PhotonCommand *) buffer; + PhotonResponse response; + response.header.fromAddress = my_address; + response.header.packetId = command->header.packetId; + response.header.toAddress = command->header.fromAddress; + switch (command->commandId) + { + case GET_FEEDER_ID: + + break; + case INITIALIZE_FEEDER: + break; + case GET_VERSION: + break; + case MOVE_FEED_FORWARD: + break; + case MOVE_FEED_BACKWARD: + break; + case MOVE_FEED_STATUS: + break; + case VENDOR_OPTIONS: + break; + case GET_FEEDER_ADDRESS: + break; + case IDENTIFY_FEEDER: + break; + case PROGRAM_FEEDER_FLOOR: + break; + case UNINITIALIZED_FEEDERS_RESPOND: + break; + default: + // todo error handling + break; + } + + + } +} + +void set_Feeder_PWM(uint16_t PWM, uint8_t direction) +{ + if (direction) + { + htim1.Instance->CCR1 = PWM; + htim1.Instance->CCR2 = 0; + } + else + { + htim1.Instance->CCR1 = 0; + htim1.Instance->CCR2 = PWM; + } +} + /* USER CODE END 4 */ diff --git a/code/Core/Src/stm32c0xx_hal_msp.c b/code/Core/Src/stm32c0xx_hal_msp.c index 320a550..8fd23f1 100644 --- a/code/Core/Src/stm32c0xx_hal_msp.c +++ b/code/Core/Src/stm32c0xx_hal_msp.c @@ -23,7 +23,9 @@ /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ -extern DMA_HandleTypeDef hdma_tim3_up; +extern DMA_HandleTypeDef hdma_usart2_rx; + +extern DMA_HandleTypeDef hdma_usart2_tx; /* Private typedef -----------------------------------------------------------*/ /* USER CODE BEGIN TD */ @@ -173,24 +175,6 @@ void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* htim_encoder) GPIO_InitStruct.Alternate = GPIO_AF1_TIM3; HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - /* TIM3 DMA Init */ - /* TIM3_UP Init */ - hdma_tim3_up.Instance = DMA1_Channel1; - hdma_tim3_up.Init.Request = DMA_REQUEST_TIM3_UP; - hdma_tim3_up.Init.Direction = DMA_PERIPH_TO_MEMORY; - hdma_tim3_up.Init.PeriphInc = DMA_PINC_DISABLE; - hdma_tim3_up.Init.MemInc = DMA_MINC_ENABLE; - hdma_tim3_up.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; - hdma_tim3_up.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; - hdma_tim3_up.Init.Mode = DMA_NORMAL; - hdma_tim3_up.Init.Priority = DMA_PRIORITY_LOW; - if (HAL_DMA_Init(&hdma_tim3_up) != HAL_OK) - { - Error_Handler(); - } - - __HAL_LINKDMA(htim_encoder,hdma[TIM_DMA_ID_UPDATE],hdma_tim3_up); - /* USER CODE BEGIN TIM3_MspInit 1 */ /* USER CODE END TIM3_MspInit 1 */ @@ -321,8 +305,6 @@ void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef* htim_encoder) */ HAL_GPIO_DeInit(GPIOC, QUAD_A_Pin|QUAD_B_Pin); - /* TIM3 DMA DeInit */ - HAL_DMA_DeInit(htim_encoder->hdma[TIM_DMA_ID_UPDATE]); /* USER CODE BEGIN TIM3_MspDeInit 1 */ /* USER CODE END TIM3_MspDeInit 1 */ @@ -396,6 +378,41 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) GPIO_InitStruct.Alternate = GPIO_AF1_USART2; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + /* USART2 DMA Init */ + /* USART2_RX Init */ + hdma_usart2_rx.Instance = DMA1_Channel2; + hdma_usart2_rx.Init.Request = DMA_REQUEST_USART2_RX; + hdma_usart2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_usart2_rx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE; + hdma_usart2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + hdma_usart2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + hdma_usart2_rx.Init.Mode = DMA_NORMAL; + hdma_usart2_rx.Init.Priority = DMA_PRIORITY_MEDIUM; + if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(huart,hdmarx,hdma_usart2_rx); + + /* USART2_TX Init */ + hdma_usart2_tx.Instance = DMA1_Channel1; + hdma_usart2_tx.Init.Request = DMA_REQUEST_USART2_TX; + hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; + hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE; + hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + hdma_usart2_tx.Init.Mode = DMA_NORMAL; + hdma_usart2_tx.Init.Priority = DMA_PRIORITY_HIGH; + if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(huart,hdmatx,hdma_usart2_tx); + /* USER CODE BEGIN USART2_MspInit 1 */ /* USER CODE END USART2_MspInit 1 */ @@ -444,6 +461,9 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5); + /* USART2 DMA DeInit */ + HAL_DMA_DeInit(huart->hdmarx); + HAL_DMA_DeInit(huart->hdmatx); /* USER CODE BEGIN USART2_MspDeInit 1 */ /* USER CODE END USART2_MspDeInit 1 */ diff --git a/code/Core/Src/stm32c0xx_it.c b/code/Core/Src/stm32c0xx_it.c index 1b70edf..bf2500f 100644 --- a/code/Core/Src/stm32c0xx_it.c +++ b/code/Core/Src/stm32c0xx_it.c @@ -55,10 +55,11 @@ /* USER CODE END 0 */ /* External variables --------------------------------------------------------*/ -extern DMA_HandleTypeDef hdma_tim3_up; extern TIM_HandleTypeDef htim14; extern TIM_HandleTypeDef htim16; extern TIM_HandleTypeDef htim17; +extern DMA_HandleTypeDef hdma_usart2_rx; +extern DMA_HandleTypeDef hdma_usart2_tx; /* USER CODE BEGIN EV */ /* USER CODE END EV */ @@ -166,12 +167,26 @@ void DMA1_Channel1_IRQHandler(void) /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */ /* USER CODE END DMA1_Channel1_IRQn 0 */ - HAL_DMA_IRQHandler(&hdma_tim3_up); + HAL_DMA_IRQHandler(&hdma_usart2_tx); /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */ /* USER CODE END DMA1_Channel1_IRQn 1 */ } +/** + * @brief This function handles DMA1 channel 2 and channel 3 interrupts. + */ +void DMA1_Channel2_3_IRQHandler(void) +{ + /* USER CODE BEGIN DMA1_Channel2_3_IRQn 0 */ + + /* USER CODE END DMA1_Channel2_3_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_usart2_rx); + /* USER CODE BEGIN DMA1_Channel2_3_IRQn 1 */ + + /* USER CODE END DMA1_Channel2_3_IRQn 1 */ +} + /** * @brief This function handles TIM14 global interrupt. */ diff --git a/code/Debug/Core/Src/main.cyclo b/code/Debug/Core/Src/main.cyclo index 5b9f36a..f4e59af 100644 --- a/code/Debug/Core/Src/main.cyclo +++ b/code/Debug/Core/Src/main.cyclo @@ -1,13 +1,21 @@ -../Core/Src/main.c:85:5:main 1 -../Core/Src/main.c:136:6:SystemClock_Config 3 -../Core/Src/main.c:175:13:MX_TIM1_Init 10 -../Core/Src/main.c:269:13:MX_TIM3_Init 3 -../Core/Src/main.c:318:13:MX_TIM16_Init 2 -../Core/Src/main.c:350:13:MX_TIM17_Init 2 -../Core/Src/main.c:382:13:MX_USART1_UART_Init 5 -../Core/Src/main.c:430:13:MX_USART2_UART_Init 5 -../Core/Src/main.c:476:13:MX_DMA_Init 1 -../Core/Src/main.c:494:13:MX_GPIO_Init 1 -../Core/Src/main.c:544:6:HAL_TIM_PeriodElapsedCallback 1 -../Core/Src/main.c:561:6:HAL_GPIO_EXTI_Callback 5 -../Core/Src/main.c:590:6:Error_Handler 1 +../Core/Inc/pid.h:39:23:clamp_i32 3 +../Core/Inc/pid.h:46:20:pid_init 1 +../Core/Inc/pid.h:77:31:pid_update_motor 8 +../Core/Src/main.c:124:5:main 18 +../Core/Src/main.c:234:6:SystemClock_Config 3 +../Core/Src/main.c:273:13:MX_TIM1_Init 10 +../Core/Src/main.c:367:13:MX_TIM3_Init 3 +../Core/Src/main.c:416:13:MX_TIM14_Init 2 +../Core/Src/main.c:447:13:MX_TIM16_Init 2 +../Core/Src/main.c:479:13:MX_TIM17_Init 2 +../Core/Src/main.c:511:13:MX_USART1_UART_Init 5 +../Core/Src/main.c:559:13:MX_USART2_UART_Init 5 +../Core/Src/main.c:605:13:MX_DMA_Init 1 +../Core/Src/main.c:626:13:MX_GPIO_Init 1 +../Core/Src/main.c:676:6:HAL_TIM_PeriodElapsedCallback 11 +../Core/Src/main.c:724:6:HAL_GPIO_EXTI_Callback 5 +../Core/Src/main.c:746:6:HAL_UARTEx_RxEventCallback 4 +../Core/Src/main.c:766:6:set_LED 4 +../Core/Src/main.c:776:6:handleRS485Message 1 +../Core/Src/main.c:794:6:set_Feeder_PWM 2 +../Core/Src/main.c:815:6:Error_Handler 1 diff --git a/code/Debug/Core/Src/main.d b/code/Debug/Core/Src/main.d index b1aa0f1..f1773c5 100644 --- a/code/Debug/Core/Src/main.d +++ b/code/Debug/Core/Src/main.d @@ -28,7 +28,8 @@ Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ - ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h + ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h \ + ../Core/Inc/photon_protocol.h ../Core/Inc/pid.h ../Core/Inc/main.h: ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: @@ -60,3 +61,5 @@ Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: +../Core/Inc/photon_protocol.h: +../Core/Inc/pid.h: diff --git a/code/Debug/Core/Src/main.o b/code/Debug/Core/Src/main.o index 8444bb2..15d8e5a 100644 Binary files a/code/Debug/Core/Src/main.o and b/code/Debug/Core/Src/main.o differ diff --git a/code/Debug/Core/Src/main.su b/code/Debug/Core/Src/main.su index b0f63a4..c6ad22a 100644 --- a/code/Debug/Core/Src/main.su +++ b/code/Debug/Core/Src/main.su @@ -1,13 +1,21 @@ -../Core/Src/main.c:85:5:main 8 static -../Core/Src/main.c:136:6:SystemClock_Config 64 static -../Core/Src/main.c:175:13:MX_TIM1_Init 120 static -../Core/Src/main.c:269:13:MX_TIM3_Init 64 static -../Core/Src/main.c:318:13:MX_TIM16_Init 8 static -../Core/Src/main.c:350:13:MX_TIM17_Init 8 static -../Core/Src/main.c:382:13:MX_USART1_UART_Init 8 static -../Core/Src/main.c:430:13:MX_USART2_UART_Init 8 static -../Core/Src/main.c:476:13:MX_DMA_Init 16 static -../Core/Src/main.c:494:13:MX_GPIO_Init 56 static -../Core/Src/main.c:544:6:HAL_TIM_PeriodElapsedCallback 16 static -../Core/Src/main.c:561:6:HAL_GPIO_EXTI_Callback 16 static -../Core/Src/main.c:590:6:Error_Handler 8 static,ignoring_inline_asm +../Core/Inc/pid.h:39:23:clamp_i32 24 static +../Core/Inc/pid.h:46:20:pid_init 24 static +../Core/Inc/pid.h:77:31:pid_update_motor 72 static +../Core/Src/main.c:124:5:main 56 static +../Core/Src/main.c:234:6:SystemClock_Config 64 static +../Core/Src/main.c:273:13:MX_TIM1_Init 120 static +../Core/Src/main.c:367:13:MX_TIM3_Init 64 static +../Core/Src/main.c:416:13:MX_TIM14_Init 8 static +../Core/Src/main.c:447:13:MX_TIM16_Init 8 static +../Core/Src/main.c:479:13:MX_TIM17_Init 8 static +../Core/Src/main.c:511:13:MX_USART1_UART_Init 8 static +../Core/Src/main.c:559:13:MX_USART2_UART_Init 8 static +../Core/Src/main.c:605:13:MX_DMA_Init 16 static +../Core/Src/main.c:626:13:MX_GPIO_Init 56 static +../Core/Src/main.c:676:6:HAL_TIM_PeriodElapsedCallback 24 static +../Core/Src/main.c:724:6:HAL_GPIO_EXTI_Callback 16 static +../Core/Src/main.c:746:6:HAL_UARTEx_RxEventCallback 16 static +../Core/Src/main.c:766:6:set_LED 24 static +../Core/Src/main.c:776:6:handleRS485Message 24 static +../Core/Src/main.c:794:6:set_Feeder_PWM 16 static +../Core/Src/main.c:815:6:Error_Handler 8 static,ignoring_inline_asm diff --git a/code/Debug/Core/Src/stm32c0xx_hal_msp.cyclo b/code/Debug/Core/Src/stm32c0xx_hal_msp.cyclo index fa320e9..2af659c 100644 --- a/code/Debug/Core/Src/stm32c0xx_hal_msp.cyclo +++ b/code/Debug/Core/Src/stm32c0xx_hal_msp.cyclo @@ -1,8 +1,8 @@ -../Core/Src/stm32c0xx_hal_msp.c:66:6:HAL_MspInit 1 -../Core/Src/stm32c0xx_hal_msp.c:89:6:HAL_TIM_Base_MspInit 4 -../Core/Src/stm32c0xx_hal_msp.c:139:6:HAL_TIM_Encoder_MspInit 3 -../Core/Src/stm32c0xx_hal_msp.c:188:6:HAL_TIM_MspPostInit 2 -../Core/Src/stm32c0xx_hal_msp.c:230:6:HAL_TIM_Base_MspDeInit 4 -../Core/Src/stm32c0xx_hal_msp.c:280:6:HAL_TIM_Encoder_MspDeInit 2 -../Core/Src/stm32c0xx_hal_msp.c:311:6:HAL_UART_MspInit 4 -../Core/Src/stm32c0xx_hal_msp.c:384:6:HAL_UART_MspDeInit 3 +../Core/Src/stm32c0xx_hal_msp.c:68:6:HAL_MspInit 1 +../Core/Src/stm32c0xx_hal_msp.c:91:6:HAL_TIM_Base_MspInit 5 +../Core/Src/stm32c0xx_hal_msp.c:155:6:HAL_TIM_Encoder_MspInit 2 +../Core/Src/stm32c0xx_hal_msp.c:186:6:HAL_TIM_MspPostInit 2 +../Core/Src/stm32c0xx_hal_msp.c:228:6:HAL_TIM_Base_MspDeInit 5 +../Core/Src/stm32c0xx_hal_msp.c:292:6:HAL_TIM_Encoder_MspDeInit 2 +../Core/Src/stm32c0xx_hal_msp.c:321:6:HAL_UART_MspInit 6 +../Core/Src/stm32c0xx_hal_msp.c:429:6:HAL_UART_MspDeInit 3 diff --git a/code/Debug/Core/Src/stm32c0xx_hal_msp.o b/code/Debug/Core/Src/stm32c0xx_hal_msp.o index 155d040..98fc117 100644 Binary files a/code/Debug/Core/Src/stm32c0xx_hal_msp.o and b/code/Debug/Core/Src/stm32c0xx_hal_msp.o differ diff --git a/code/Debug/Core/Src/stm32c0xx_hal_msp.su b/code/Debug/Core/Src/stm32c0xx_hal_msp.su index 3eba228..1a8c7e1 100644 --- a/code/Debug/Core/Src/stm32c0xx_hal_msp.su +++ b/code/Debug/Core/Src/stm32c0xx_hal_msp.su @@ -1,8 +1,8 @@ -../Core/Src/stm32c0xx_hal_msp.c:66:6:HAL_MspInit 16 static -../Core/Src/stm32c0xx_hal_msp.c:89:6:HAL_TIM_Base_MspInit 32 static -../Core/Src/stm32c0xx_hal_msp.c:139:6:HAL_TIM_Encoder_MspInit 56 static -../Core/Src/stm32c0xx_hal_msp.c:188:6:HAL_TIM_MspPostInit 48 static -../Core/Src/stm32c0xx_hal_msp.c:230:6:HAL_TIM_Base_MspDeInit 16 static -../Core/Src/stm32c0xx_hal_msp.c:280:6:HAL_TIM_Encoder_MspDeInit 16 static -../Core/Src/stm32c0xx_hal_msp.c:311:6:HAL_UART_MspInit 88 static -../Core/Src/stm32c0xx_hal_msp.c:384:6:HAL_UART_MspDeInit 16 static +../Core/Src/stm32c0xx_hal_msp.c:68:6:HAL_MspInit 16 static +../Core/Src/stm32c0xx_hal_msp.c:91:6:HAL_TIM_Base_MspInit 32 static +../Core/Src/stm32c0xx_hal_msp.c:155:6:HAL_TIM_Encoder_MspInit 56 static +../Core/Src/stm32c0xx_hal_msp.c:186:6:HAL_TIM_MspPostInit 48 static +../Core/Src/stm32c0xx_hal_msp.c:228:6:HAL_TIM_Base_MspDeInit 16 static +../Core/Src/stm32c0xx_hal_msp.c:292:6:HAL_TIM_Encoder_MspDeInit 16 static +../Core/Src/stm32c0xx_hal_msp.c:321:6:HAL_UART_MspInit 88 static +../Core/Src/stm32c0xx_hal_msp.c:429:6:HAL_UART_MspDeInit 16 static diff --git a/code/Debug/Core/Src/stm32c0xx_it.cyclo b/code/Debug/Core/Src/stm32c0xx_it.cyclo index 7bd0e10..c6d4709 100644 --- a/code/Debug/Core/Src/stm32c0xx_it.cyclo +++ b/code/Debug/Core/Src/stm32c0xx_it.cyclo @@ -1,9 +1,11 @@ -../Core/Src/stm32c0xx_it.c:71:6:NMI_Handler 1 -../Core/Src/stm32c0xx_it.c:86:6:HardFault_Handler 1 -../Core/Src/stm32c0xx_it.c:101:6:SVC_Handler 1 -../Core/Src/stm32c0xx_it.c:114:6:PendSV_Handler 1 -../Core/Src/stm32c0xx_it.c:127:6:SysTick_Handler 1 -../Core/Src/stm32c0xx_it.c:148:6:EXTI4_15_IRQHandler 1 -../Core/Src/stm32c0xx_it.c:163:6:DMA1_Channel1_IRQHandler 1 -../Core/Src/stm32c0xx_it.c:177:6:TIM16_IRQHandler 1 -../Core/Src/stm32c0xx_it.c:191:6:TIM17_IRQHandler 1 +../Core/Src/stm32c0xx_it.c:73:6:NMI_Handler 1 +../Core/Src/stm32c0xx_it.c:88:6:HardFault_Handler 1 +../Core/Src/stm32c0xx_it.c:103:6:SVC_Handler 1 +../Core/Src/stm32c0xx_it.c:116:6:PendSV_Handler 1 +../Core/Src/stm32c0xx_it.c:129:6:SysTick_Handler 1 +../Core/Src/stm32c0xx_it.c:150:6:EXTI4_15_IRQHandler 1 +../Core/Src/stm32c0xx_it.c:165:6:DMA1_Channel1_IRQHandler 1 +../Core/Src/stm32c0xx_it.c:179:6:DMA1_Channel2_3_IRQHandler 1 +../Core/Src/stm32c0xx_it.c:193:6:TIM14_IRQHandler 1 +../Core/Src/stm32c0xx_it.c:207:6:TIM16_IRQHandler 1 +../Core/Src/stm32c0xx_it.c:221:6:TIM17_IRQHandler 1 diff --git a/code/Debug/Core/Src/stm32c0xx_it.o b/code/Debug/Core/Src/stm32c0xx_it.o index 310ca26..7eb2f0f 100644 Binary files a/code/Debug/Core/Src/stm32c0xx_it.o and b/code/Debug/Core/Src/stm32c0xx_it.o differ diff --git a/code/Debug/Core/Src/stm32c0xx_it.su b/code/Debug/Core/Src/stm32c0xx_it.su index 25d12cc..4994dfb 100644 --- a/code/Debug/Core/Src/stm32c0xx_it.su +++ b/code/Debug/Core/Src/stm32c0xx_it.su @@ -1,9 +1,11 @@ -../Core/Src/stm32c0xx_it.c:71:6:NMI_Handler 8 static -../Core/Src/stm32c0xx_it.c:86:6:HardFault_Handler 8 static -../Core/Src/stm32c0xx_it.c:101:6:SVC_Handler 8 static -../Core/Src/stm32c0xx_it.c:114:6:PendSV_Handler 8 static -../Core/Src/stm32c0xx_it.c:127:6:SysTick_Handler 8 static -../Core/Src/stm32c0xx_it.c:148:6:EXTI4_15_IRQHandler 8 static -../Core/Src/stm32c0xx_it.c:163:6:DMA1_Channel1_IRQHandler 8 static -../Core/Src/stm32c0xx_it.c:177:6:TIM16_IRQHandler 8 static -../Core/Src/stm32c0xx_it.c:191:6:TIM17_IRQHandler 8 static +../Core/Src/stm32c0xx_it.c:73:6:NMI_Handler 8 static +../Core/Src/stm32c0xx_it.c:88:6:HardFault_Handler 8 static +../Core/Src/stm32c0xx_it.c:103:6:SVC_Handler 8 static +../Core/Src/stm32c0xx_it.c:116:6:PendSV_Handler 8 static +../Core/Src/stm32c0xx_it.c:129:6:SysTick_Handler 8 static +../Core/Src/stm32c0xx_it.c:150:6:EXTI4_15_IRQHandler 8 static +../Core/Src/stm32c0xx_it.c:165:6:DMA1_Channel1_IRQHandler 8 static +../Core/Src/stm32c0xx_it.c:179:6:DMA1_Channel2_3_IRQHandler 8 static +../Core/Src/stm32c0xx_it.c:193:6:TIM14_IRQHandler 8 static +../Core/Src/stm32c0xx_it.c:207:6:TIM16_IRQHandler 8 static +../Core/Src/stm32c0xx_it.c:221:6:TIM17_IRQHandler 8 static diff --git a/code/Debug/Core/Src/syscalls.o b/code/Debug/Core/Src/syscalls.o index ad7fad9..5bf0dfa 100644 Binary files a/code/Debug/Core/Src/syscalls.o and b/code/Debug/Core/Src/syscalls.o differ diff --git a/code/Debug/Core/Src/sysmem.o b/code/Debug/Core/Src/sysmem.o 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differ diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o index 0e983d0..7849a05 100644 Binary files a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o and b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o differ diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o index 0c98a75..87de05b 100644 Binary files a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o and b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o differ diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o index e010c9a..d03b9c1 100644 Binary files a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o and b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o differ diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o index c1038b1..c7fc96c 100644 Binary files a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o and b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o differ diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o index 7169490..ea12657 100644 Binary files a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o and b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o differ diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o index 8c750a5..f85387e 100644 Binary files a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o and 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a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o and b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o differ diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o index 1cac1e6..deb3aed 100644 Binary files a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o and b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o differ diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o index 808daa9..597aa5b 100644 Binary files a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o and b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o differ diff --git a/code/Debug/feeder_mk2.elf b/code/Debug/feeder_mk2.elf index 4029d5e..8a29e07 100644 Binary files a/code/Debug/feeder_mk2.elf and b/code/Debug/feeder_mk2.elf differ diff --git a/code/Debug/feeder_mk2.list b/code/Debug/feeder_mk2.list index 7cc70a2..bd31efc 100644 --- a/code/Debug/feeder_mk2.list +++ b/code/Debug/feeder_mk2.list @@ -5,47 +5,47 @@ Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000000c0 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA - 1 .text 00003eec 080000c0 080000c0 000010c0 2**2 + 1 .text 00004cfc 080000c0 080000c0 000010c0 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE - 2 .rodata 000000dc 08003fac 08003fac 00004fac 2**2 + 2 .rodata 000000dc 08004dbc 08004dbc 00005dbc 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA - 3 .ARM.extab 00000000 08004088 08004088 0000600c 2**0 + 3 .ARM.extab 00000000 08004e98 08004e98 00006024 2**0 CONTENTS, READONLY - 4 .ARM 00000000 08004088 08004088 0000600c 2**0 + 4 .ARM 00000000 08004e98 08004e98 00006024 2**0 CONTENTS, READONLY - 5 .preinit_array 00000000 08004088 08004088 0000600c 2**0 + 5 .preinit_array 00000000 08004e98 08004e98 00006024 2**0 CONTENTS, ALLOC, LOAD, DATA - 6 .init_array 00000004 08004088 08004088 00005088 2**2 + 6 .init_array 00000004 08004e98 08004e98 00005e98 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA - 7 .fini_array 00000004 0800408c 0800408c 0000508c 2**2 + 7 .fini_array 00000004 08004e9c 08004e9c 00005e9c 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA - 8 .data 0000000c 20000000 08004090 00006000 2**2 + 8 .data 00000024 20000000 08004ea0 00006000 2**2 CONTENTS, ALLOC, LOAD, DATA - 9 .bss 000002d4 2000000c 0800409c 0000600c 2**2 + 9 .bss 0000048c 20000024 08004ec4 00006024 2**2 ALLOC - 10 ._user_heap_stack 00000600 200002e0 0800409c 000062e0 2**0 + 10 ._user_heap_stack 00000600 200004b0 08004ec4 000064b0 2**0 ALLOC - 11 .ARM.attributes 00000028 00000000 00000000 0000600c 2**0 + 11 .ARM.attributes 00000028 00000000 00000000 00006024 2**0 CONTENTS, READONLY - 12 .debug_info 0000fde5 00000000 00000000 00006034 2**0 + 12 .debug_info 000104fc 00000000 00000000 0000604c 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 13 .debug_abbrev 00002143 00000000 00000000 00015e19 2**0 + 13 .debug_abbrev 000021de 00000000 00000000 00016548 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 14 .debug_aranges 00000db0 00000000 00000000 00017f60 2**3 + 14 .debug_aranges 00000e00 00000000 00000000 00018728 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS - 15 .debug_rnglists 00000ad4 00000000 00000000 00018d10 2**0 + 15 .debug_rnglists 00000b16 00000000 00000000 00019528 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 16 .debug_macro 00013d7b 00000000 00000000 000197e4 2**0 + 16 .debug_macro 00014883 00000000 00000000 0001a03e 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 17 .debug_line 0001085f 00000000 00000000 0002d55f 2**0 + 17 .debug_line 00010e4c 00000000 00000000 0002e8c1 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 18 .debug_str 00080580 00000000 00000000 0003ddbe 2**0 + 18 .debug_str 000840c3 00000000 00000000 0003f70d 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 19 .comment 00000086 00000000 00000000 000be33e 2**0 + 19 .comment 00000043 00000000 00000000 000c37d0 2**0 CONTENTS, READONLY - 20 .debug_frame 000031bc 00000000 00000000 000be3c4 2**2 + 20 .debug_frame 00003320 00000000 00000000 000c3814 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS - 21 .debug_line_str 0000004d 00000000 00000000 000c1580 2**0 + 21 .debug_line_str 0000004d 00000000 00000000 000c6b34 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: @@ -65,9 +65,9 @@ Disassembly of section .text: 80000d6: 2301 movs r3, #1 80000d8: 7023 strb r3, [r4, #0] 80000da: bd10 pop {r4, pc} - 80000dc: 2000000c .word 0x2000000c + 80000dc: 20000024 .word 0x20000024 80000e0: 00000000 .word 0x00000000 - 80000e4: 08003f94 .word 0x08003f94 + 80000e4: 08004da4 .word 0x08004da4 080000e8 : 80000e8: 4b04 ldr r3, [pc, #16] @ (80000fc ) @@ -81,8 +81,8 @@ Disassembly of section .text: 80000f8: bd10 pop {r4, pc} 80000fa: 46c0 nop @ (mov r8, r8) 80000fc: 00000000 .word 0x00000000 - 8000100: 20000010 .word 0x20000010 - 8000104: 08003f94 .word 0x08003f94 + 8000100: 20000028 .word 0x20000028 + 8000104: 08004da4 .word 0x08004da4 08000108 <__udivsi3>: 8000108: 2200 movs r2, #0 @@ -466,11340 +466,13856 @@ Disassembly of section .text: 80003f0: 4770 bx lr 80003f2: 46c0 nop @ (mov r8, r8) -080003f4
: +080003f4 : + uint16_t pwm; // 0..out_max + uint8_t dir; // 0 or 1 +} pid_motor_cmd_t; + +static inline int32_t clamp_i32(int32_t x, int32_t lo, int32_t hi) +{ + 80003f4: b580 push {r7, lr} + 80003f6: b084 sub sp, #16 + 80003f8: af00 add r7, sp, #0 + 80003fa: 60f8 str r0, [r7, #12] + 80003fc: 60b9 str r1, [r7, #8] + 80003fe: 607a str r2, [r7, #4] + if (x < lo) return lo; + 8000400: 68fa ldr r2, [r7, #12] + 8000402: 68bb ldr r3, [r7, #8] + 8000404: 429a cmp r2, r3 + 8000406: da01 bge.n 800040c + 8000408: 68bb ldr r3, [r7, #8] + 800040a: e006 b.n 800041a + if (x > hi) return hi; + 800040c: 68fa ldr r2, [r7, #12] + 800040e: 687b ldr r3, [r7, #4] + 8000410: 429a cmp r2, r3 + 8000412: dd01 ble.n 8000418 + 8000414: 687b ldr r3, [r7, #4] + 8000416: e000 b.n 800041a + return x; + 8000418: 68fb ldr r3, [r7, #12] +} + 800041a: 0018 movs r0, r3 + 800041c: 46bd mov sp, r7 + 800041e: b004 add sp, #16 + 8000420: bd80 pop {r7, pc} + +08000422 : + int32_t kd, + int32_t integrator_min, + int32_t integrator_max, + int32_t out_max, + int32_t max_output_step) +{ + 8000422: b580 push {r7, lr} + 8000424: b084 sub sp, #16 + 8000426: af00 add r7, sp, #0 + 8000428: 60f8 str r0, [r7, #12] + 800042a: 60b9 str r1, [r7, #8] + 800042c: 607a str r2, [r7, #4] + 800042e: 603b str r3, [r7, #0] + pid->kp = kp; + 8000430: 68fb ldr r3, [r7, #12] + 8000432: 68ba ldr r2, [r7, #8] + 8000434: 601a str r2, [r3, #0] + pid->ki = ki; + 8000436: 68fb ldr r3, [r7, #12] + 8000438: 687a ldr r2, [r7, #4] + 800043a: 605a str r2, [r3, #4] + pid->kd = kd; + 800043c: 68fb ldr r3, [r7, #12] + 800043e: 683a ldr r2, [r7, #0] + 8000440: 609a str r2, [r3, #8] + + pid->integrator = 0; + 8000442: 68fb ldr r3, [r7, #12] + 8000444: 2200 movs r2, #0 + 8000446: 60da str r2, [r3, #12] + pid->prev_error = 0; + 8000448: 68fb ldr r3, [r7, #12] + 800044a: 2200 movs r2, #0 + 800044c: 611a str r2, [r3, #16] + + pid->integrator_min = integrator_min; + 800044e: 68fb ldr r3, [r7, #12] + 8000450: 69ba ldr r2, [r7, #24] + 8000452: 615a str r2, [r3, #20] + pid->integrator_max = integrator_max; + 8000454: 68fb ldr r3, [r7, #12] + 8000456: 69fa ldr r2, [r7, #28] + 8000458: 619a str r2, [r3, #24] + pid->out_max = out_max; + 800045a: 68fb ldr r3, [r7, #12] + 800045c: 6a3a ldr r2, [r7, #32] + 800045e: 61da str r2, [r3, #28] + + pid->max_output_step = max_output_step; + 8000460: 68fb ldr r3, [r7, #12] + 8000462: 6a7a ldr r2, [r7, #36] @ 0x24 + 8000464: 621a str r2, [r3, #32] + pid->last_output = 0; + 8000466: 68fb ldr r3, [r7, #12] + 8000468: 2200 movs r2, #0 + 800046a: 625a str r2, [r3, #36] @ 0x24 +} + 800046c: 46c0 nop @ (mov r8, r8) + 800046e: 46bd mov sp, r7 + 8000470: b004 add sp, #16 + 8000472: bd80 pop {r7, pc} + +08000474 : +} + +static inline pid_motor_cmd_t pid_update_motor(pid_i32_t *pid, + int32_t setpoint, + int32_t position) +{ + 8000474: b580 push {r7, lr} + 8000476: b090 sub sp, #64 @ 0x40 + 8000478: af00 add r7, sp, #0 + 800047a: 60f8 str r0, [r7, #12] + 800047c: 60b9 str r1, [r7, #8] + 800047e: 607a str r2, [r7, #4] + pid_motor_cmd_t cmd; + + // Basic PID (no overflow protection, as requested) + int32_t error = setpoint - position; + 8000480: 68ba ldr r2, [r7, #8] + 8000482: 687b ldr r3, [r7, #4] + 8000484: 1ad3 subs r3, r2, r3 + 8000486: 637b str r3, [r7, #52] @ 0x34 + + int32_t p = pid->kp * error; + 8000488: 68fb ldr r3, [r7, #12] + 800048a: 681a ldr r2, [r3, #0] + 800048c: 6b7b ldr r3, [r7, #52] @ 0x34 + 800048e: 4353 muls r3, r2 + 8000490: 633b str r3, [r7, #48] @ 0x30 + + int32_t i = pid->integrator + pid->ki * error; + 8000492: 68fb ldr r3, [r7, #12] + 8000494: 68da ldr r2, [r3, #12] + 8000496: 68fb ldr r3, [r7, #12] + 8000498: 685b ldr r3, [r3, #4] + 800049a: 6b79 ldr r1, [r7, #52] @ 0x34 + 800049c: 434b muls r3, r1 + 800049e: 18d3 adds r3, r2, r3 + 80004a0: 62fb str r3, [r7, #44] @ 0x2c + i = clamp_i32(i, pid->integrator_min, pid->integrator_max); + 80004a2: 68fb ldr r3, [r7, #12] + 80004a4: 6959 ldr r1, [r3, #20] + 80004a6: 68fb ldr r3, [r7, #12] + 80004a8: 699a ldr r2, [r3, #24] + 80004aa: 6afb ldr r3, [r7, #44] @ 0x2c + 80004ac: 0018 movs r0, r3 + 80004ae: f7ff ffa1 bl 80003f4 + 80004b2: 0003 movs r3, r0 + 80004b4: 62fb str r3, [r7, #44] @ 0x2c + pid->integrator = i; + 80004b6: 68fb ldr r3, [r7, #12] + 80004b8: 6afa ldr r2, [r7, #44] @ 0x2c + 80004ba: 60da str r2, [r3, #12] + + int32_t d_error = error - pid->prev_error; + 80004bc: 68fb ldr r3, [r7, #12] + 80004be: 691b ldr r3, [r3, #16] + 80004c0: 6b7a ldr r2, [r7, #52] @ 0x34 + 80004c2: 1ad3 subs r3, r2, r3 + 80004c4: 62bb str r3, [r7, #40] @ 0x28 + int32_t d = pid->kd * d_error; + 80004c6: 68fb ldr r3, [r7, #12] + 80004c8: 689a ldr r2, [r3, #8] + 80004ca: 6abb ldr r3, [r7, #40] @ 0x28 + 80004cc: 4353 muls r3, r2 + 80004ce: 627b str r3, [r7, #36] @ 0x24 + pid->prev_error = error; + 80004d0: 68fb ldr r3, [r7, #12] + 80004d2: 6b7a ldr r2, [r7, #52] @ 0x34 + 80004d4: 611a str r2, [r3, #16] + + // Raw control effort + int32_t u_raw = p + i + d; + 80004d6: 6b3a ldr r2, [r7, #48] @ 0x30 + 80004d8: 6afb ldr r3, [r7, #44] @ 0x2c + 80004da: 18d3 adds r3, r2, r3 + 80004dc: 6a7a ldr r2, [r7, #36] @ 0x24 + 80004de: 18d3 adds r3, r2, r3 + 80004e0: 63fb str r3, [r7, #60] @ 0x3c + + // Clamp to [-out_max, +out_max] + if (u_raw > pid->out_max) u_raw = pid->out_max; + 80004e2: 68fb ldr r3, [r7, #12] + 80004e4: 69db ldr r3, [r3, #28] + 80004e6: 6bfa ldr r2, [r7, #60] @ 0x3c + 80004e8: 429a cmp r2, r3 + 80004ea: dd02 ble.n 80004f2 + 80004ec: 68fb ldr r3, [r7, #12] + 80004ee: 69db ldr r3, [r3, #28] + 80004f0: 63fb str r3, [r7, #60] @ 0x3c + if (u_raw < -pid->out_max) u_raw = -pid->out_max; + 80004f2: 68fb ldr r3, [r7, #12] + 80004f4: 69db ldr r3, [r3, #28] + 80004f6: 425b negs r3, r3 + 80004f8: 6bfa ldr r2, [r7, #60] @ 0x3c + 80004fa: 429a cmp r2, r3 + 80004fc: da03 bge.n 8000506 + 80004fe: 68fb ldr r3, [r7, #12] + 8000500: 69db ldr r3, [r3, #28] + 8000502: 425b negs r3, r3 + 8000504: 63fb str r3, [r7, #60] @ 0x3c + + // ---------- Slew limit: avoid instant full reverse ---------- + int32_t u_prev = pid->last_output; + 8000506: 68fb ldr r3, [r7, #12] + 8000508: 6a5b ldr r3, [r3, #36] @ 0x24 + 800050a: 623b str r3, [r7, #32] + int32_t u = u_raw; + 800050c: 6bfb ldr r3, [r7, #60] @ 0x3c + 800050e: 63bb str r3, [r7, #56] @ 0x38 + + int32_t max_step = pid->max_output_step; + 8000510: 68fb ldr r3, [r7, #12] + 8000512: 6a1b ldr r3, [r3, #32] + 8000514: 61fb str r3, [r7, #28] + if (max_step > 0) { + 8000516: 69fb ldr r3, [r7, #28] + 8000518: 2b00 cmp r3, #0 + 800051a: dd18 ble.n 800054e + int32_t du = u_raw - u_prev; + 800051c: 6bfa ldr r2, [r7, #60] @ 0x3c + 800051e: 6a3b ldr r3, [r7, #32] + 8000520: 1ad3 subs r3, r2, r3 + 8000522: 61bb str r3, [r7, #24] + + if (du > max_step) { + 8000524: 69ba ldr r2, [r7, #24] + 8000526: 69fb ldr r3, [r7, #28] + 8000528: 429a cmp r2, r3 + 800052a: dd04 ble.n 8000536 + u = u_prev + max_step; + 800052c: 6a3a ldr r2, [r7, #32] + 800052e: 69fb ldr r3, [r7, #28] + 8000530: 18d3 adds r3, r2, r3 + 8000532: 63bb str r3, [r7, #56] @ 0x38 + 8000534: e00b b.n 800054e + } else if (du < -max_step) { + 8000536: 69fb ldr r3, [r7, #28] + 8000538: 425b negs r3, r3 + 800053a: 69ba ldr r2, [r7, #24] + 800053c: 429a cmp r2, r3 + 800053e: da04 bge.n 800054a + u = u_prev - max_step; + 8000540: 6a3a ldr r2, [r7, #32] + 8000542: 69fb ldr r3, [r7, #28] + 8000544: 1ad3 subs r3, r2, r3 + 8000546: 63bb str r3, [r7, #56] @ 0x38 + 8000548: e001 b.n 800054e + } else { + u = u_raw; + 800054a: 6bfb ldr r3, [r7, #60] @ 0x3c + 800054c: 63bb str r3, [r7, #56] @ 0x38 + } + } + + // Save for next time + pid->last_output = u; + 800054e: 68fb ldr r3, [r7, #12] + 8000550: 6bba ldr r2, [r7, #56] @ 0x38 + 8000552: 625a str r2, [r3, #36] @ 0x24 + + // Map signed u to dir + pwm + if (u >= 0) { + 8000554: 6bbb ldr r3, [r7, #56] @ 0x38 + 8000556: 2b00 cmp r3, #0 + 8000558: db08 blt.n 800056c + cmd.dir = 1; + 800055a: 2110 movs r1, #16 + 800055c: 187b adds r3, r7, r1 + 800055e: 2201 movs r2, #1 + 8000560: 709a strb r2, [r3, #2] + cmd.pwm = (uint16_t)u; + 8000562: 6bbb ldr r3, [r7, #56] @ 0x38 + 8000564: b29a uxth r2, r3 + 8000566: 187b adds r3, r7, r1 + 8000568: 801a strh r2, [r3, #0] + 800056a: e009 b.n 8000580 + } else { + cmd.dir = 0; + 800056c: 2110 movs r1, #16 + 800056e: 187b adds r3, r7, r1 + 8000570: 2200 movs r2, #0 + 8000572: 709a strb r2, [r3, #2] + cmd.pwm = (uint16_t)(-u); + 8000574: 6bbb ldr r3, [r7, #56] @ 0x38 + 8000576: b29b uxth r3, r3 + 8000578: 425b negs r3, r3 + 800057a: b29a uxth r2, r3 + 800057c: 187b adds r3, r7, r1 + 800057e: 801a strh r2, [r3, #0] + } + + if (cmd.pwm > pid->out_max) + 8000580: 2110 movs r1, #16 + 8000582: 187b adds r3, r7, r1 + 8000584: 881b ldrh r3, [r3, #0] + 8000586: 001a movs r2, r3 + 8000588: 68fb ldr r3, [r7, #12] + 800058a: 69db ldr r3, [r3, #28] + 800058c: 429a cmp r2, r3 + 800058e: dd04 ble.n 800059a + cmd.pwm = (uint16_t)pid->out_max; + 8000590: 68fb ldr r3, [r7, #12] + 8000592: 69db ldr r3, [r3, #28] + 8000594: b29a uxth r2, r3 + 8000596: 187b adds r3, r7, r1 + 8000598: 801a strh r2, [r3, #0] + + return cmd; + 800059a: 2114 movs r1, #20 + 800059c: 187b adds r3, r7, r1 + 800059e: 2210 movs r2, #16 + 80005a0: 18ba adds r2, r7, r2 + 80005a2: 6812 ldr r2, [r2, #0] + 80005a4: 601a str r2, [r3, #0] + 80005a6: 187a adds r2, r7, r1 + 80005a8: 2300 movs r3, #0 + 80005aa: 8811 ldrh r1, [r2, #0] + 80005ac: 0409 lsls r1, r1, #16 + 80005ae: 0c09 lsrs r1, r1, #16 + 80005b0: 0c1b lsrs r3, r3, #16 + 80005b2: 041b lsls r3, r3, #16 + 80005b4: 430b orrs r3, r1 + 80005b6: 8852 ldrh r2, [r2, #2] + 80005b8: 0412 lsls r2, r2, #16 + 80005ba: 041b lsls r3, r3, #16 + 80005bc: 0c1b lsrs r3, r3, #16 + 80005be: 4313 orrs r3, r2 +} + 80005c0: 0018 movs r0, r3 + 80005c2: 46bd mov sp, r7 + 80005c4: b010 add sp, #64 @ 0x40 + 80005c6: bd80 pop {r7, pc} + +080005c8
: /** * @brief The application entry point. * @retval int */ int main(void) { - 80003f4: b580 push {r7, lr} - 80003f6: af00 add r7, sp, #0 + 80005c8: b5f0 push {r4, r5, r6, r7, lr} + 80005ca: b089 sub sp, #36 @ 0x24 + 80005cc: af04 add r7, sp, #16 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); - 80003f8: f000 fdc9 bl 8000f8e + 80005ce: f001 f83e bl 800164e + /* USER CODE BEGIN Init */ + pid_init(&motor_pid,kp,ki,kd,i_min,i_max,PWM_MAX,pid_max_step); + 80005d2: 4b77 ldr r3, [pc, #476] @ (80007b0 ) + 80005d4: 681c ldr r4, [r3, #0] + 80005d6: 4b77 ldr r3, [pc, #476] @ (80007b4 ) + 80005d8: 681d ldr r5, [r3, #0] + 80005da: 4b77 ldr r3, [pc, #476] @ (80007b8 ) + 80005dc: 681e ldr r6, [r3, #0] + 80005de: 4b77 ldr r3, [pc, #476] @ (80007bc ) + 80005e0: 681a ldr r2, [r3, #0] + 80005e2: 4b77 ldr r3, [pc, #476] @ (80007c0 ) + 80005e4: 6819 ldr r1, [r3, #0] + 80005e6: 4b77 ldr r3, [pc, #476] @ (80007c4 ) + 80005e8: 681b ldr r3, [r3, #0] + 80005ea: 4877 ldr r0, [pc, #476] @ (80007c8 ) + 80005ec: 9303 str r3, [sp, #12] + 80005ee: 2396 movs r3, #150 @ 0x96 + 80005f0: 011b lsls r3, r3, #4 + 80005f2: 9302 str r3, [sp, #8] + 80005f4: 9101 str r1, [sp, #4] + 80005f6: 9200 str r2, [sp, #0] + 80005f8: 0033 movs r3, r6 + 80005fa: 002a movs r2, r5 + 80005fc: 0021 movs r1, r4 + 80005fe: f7ff ff10 bl 8000422 + /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); - 80003fc: f000 f812 bl 8000424 + 8000602: f000 f8fd bl 8000800 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); - 8000400: f000 fabe bl 8000980 + 8000606: f000 fbd9 bl 8000dbc MX_DMA_Init(); - 8000404: f000 fa9e bl 8000944 + 800060a: f000 fbb1 bl 8000d70 MX_TIM1_Init(); - 8000408: f000 f85a bl 80004c0 + 800060e: f000 f945 bl 800089c MX_TIM3_Init(); - 800040c: f000 f944 bl 8000698 + 8000612: f000 fa2f bl 8000a74 MX_USART1_UART_Init(); - 8000410: f000 f9fa bl 8000808 + 8000616: f000 fb09 bl 8000c2c MX_USART2_UART_Init(); - 8000414: f000 fa46 bl 80008a4 + 800061a: f000 fb55 bl 8000cc8 MX_TIM16_Init(); - 8000418: f000 f9a2 bl 8000760 + 800061e: f000 fab1 bl 8000b84 MX_TIM17_Init(); - 800041c: f000 f9ca bl 80007b4 + 8000622: f000 fad9 bl 8000bd8 + MX_TIM14_Init(); + 8000626: f000 fa89 bl 8000b3c + /* USER CODE BEGIN 2 */ - /* USER CODE END 2 */ + uint32_t * puuid = (uint32_t *)UUID; + 800062a: 4b68 ldr r3, [pc, #416] @ (80007cc ) + 800062c: 60bb str r3, [r7, #8] + *puuid = HAL_GetUIDw0(); + 800062e: f001 f88b bl 8001748 + 8000632: 0002 movs r2, r0 + 8000634: 68bb ldr r3, [r7, #8] + 8000636: 601a str r2, [r3, #0] + *(puuid+1) = HAL_GetUIDw1(); + 8000638: 68bb ldr r3, [r7, #8] + 800063a: 1d1c adds r4, r3, #4 + 800063c: f001 f88e bl 800175c + 8000640: 0003 movs r3, r0 + 8000642: 6023 str r3, [r4, #0] + *(puuid+2) = HAL_GetUIDw2(); + 8000644: 68bb ldr r3, [r7, #8] + 8000646: 3308 adds r3, #8 + 8000648: 001c movs r4, r3 + 800064a: f001 f891 bl 8001770 + 800064e: 0003 movs r3, r0 + 8000650: 6023 str r3, [r4, #0] + + HAL_UARTEx_ReceiveToIdle_DMA (&huart2,DMA_buffer,64); + 8000652: 495f ldr r1, [pc, #380] @ (80007d0 ) + 8000654: 4b5f ldr r3, [pc, #380] @ (80007d4 ) + 8000656: 2240 movs r2, #64 @ 0x40 + 8000658: 0018 movs r0, r3 + 800065a: f004 faa7 bl 8004bac /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) - 8000420: 46c0 nop @ (mov r8, r8) - 8000422: e7fd b.n 8000420 + { + if (sw1_pressed) + 800065e: 4b5e ldr r3, [pc, #376] @ (80007d8 ) + 8000660: 781b ldrb r3, [r3, #0] + 8000662: 2b00 cmp r3, #0 + 8000664: d034 beq.n 80006d0 + { + uint16_t time_pressed = htim16.Instance->CNT; + 8000666: 4b5d ldr r3, [pc, #372] @ (80007dc ) + 8000668: 681b ldr r3, [r3, #0] + 800066a: 6a5a ldr r2, [r3, #36] @ 0x24 + 800066c: 1dbb adds r3, r7, #6 + 800066e: 801a strh r2, [r3, #0] + if ((HAL_GPIO_ReadPin(SW1_GPIO_Port,SW1_Pin)) && (time_pressed > 750)) // button still pressed + 8000670: 2380 movs r3, #128 @ 0x80 + 8000672: 009b lsls r3, r3, #2 + 8000674: 4a5a ldr r2, [pc, #360] @ (80007e0 ) + 8000676: 0019 movs r1, r3 + 8000678: 0010 movs r0, r2 + 800067a: f001 fd27 bl 80020cc + 800067e: 1e03 subs r3, r0, #0 + 8000680: d004 beq.n 800068c + 8000682: 1dbb adds r3, r7, #6 + 8000684: 881b ldrh r3, [r3, #0] + 8000686: 4a57 ldr r2, [pc, #348] @ (80007e4 ) + 8000688: 4293 cmp r3, r2 + 800068a: d821 bhi.n 80006d0 + { + // todo long button action + } + else if (!HAL_GPIO_ReadPin(SW1_GPIO_Port,SW1_Pin) && (time_pressed <= 750) && (time_pressed >75)) // release in short window + 800068c: 2380 movs r3, #128 @ 0x80 + 800068e: 009b lsls r3, r3, #2 + 8000690: 4a53 ldr r2, [pc, #332] @ (80007e0 ) + 8000692: 0019 movs r1, r3 + 8000694: 0010 movs r0, r2 + 8000696: f001 fd19 bl 80020cc + 800069a: 1e03 subs r3, r0, #0 + 800069c: d10c bne.n 80006b8 + 800069e: 1dbb adds r3, r7, #6 + 80006a0: 881b ldrh r3, [r3, #0] + 80006a2: 4a50 ldr r2, [pc, #320] @ (80007e4 ) + 80006a4: 4293 cmp r3, r2 + 80006a6: d807 bhi.n 80006b8 + 80006a8: 1dbb adds r3, r7, #6 + 80006aa: 881b ldrh r3, [r3, #0] + 80006ac: 2b4b cmp r3, #75 @ 0x4b + 80006ae: d903 bls.n 80006b8 + { + // todo short button action + sw1_pressed = 0; + 80006b0: 4b49 ldr r3, [pc, #292] @ (80007d8 ) + 80006b2: 2200 movs r2, #0 + 80006b4: 701a strb r2, [r3, #0] + 80006b6: e00b b.n 80006d0 + } + else if (!HAL_GPIO_ReadPin(SW1_GPIO_Port,SW1_Pin)) sw1_pressed = 0; // release in long window + 80006b8: 2380 movs r3, #128 @ 0x80 + 80006ba: 009b lsls r3, r3, #2 + 80006bc: 4a48 ldr r2, [pc, #288] @ (80007e0 ) + 80006be: 0019 movs r1, r3 + 80006c0: 0010 movs r0, r2 + 80006c2: f001 fd03 bl 80020cc + 80006c6: 1e03 subs r3, r0, #0 + 80006c8: d102 bne.n 80006d0 + 80006ca: 4b43 ldr r3, [pc, #268] @ (80007d8 ) + 80006cc: 2200 movs r2, #0 + 80006ce: 701a strb r2, [r3, #0] + } -08000424 : + if (sw2_pressed) + 80006d0: 4b45 ldr r3, [pc, #276] @ (80007e8 ) + 80006d2: 781b ldrb r3, [r3, #0] + 80006d4: 2b00 cmp r3, #0 + 80006d6: d030 beq.n 800073a + { + uint16_t time_pressed = htim17.Instance->CNT; + 80006d8: 4b44 ldr r3, [pc, #272] @ (80007ec ) + 80006da: 681b ldr r3, [r3, #0] + 80006dc: 6a5a ldr r2, [r3, #36] @ 0x24 + 80006de: 1d3b adds r3, r7, #4 + 80006e0: 801a strh r2, [r3, #0] + if ((HAL_GPIO_ReadPin(SW2_GPIO_Port,SW2_Pin)) && (time_pressed > 750)) // button still pressed + 80006e2: 2380 movs r3, #128 @ 0x80 + 80006e4: 005b lsls r3, r3, #1 + 80006e6: 4a3e ldr r2, [pc, #248] @ (80007e0 ) + 80006e8: 0019 movs r1, r3 + 80006ea: 0010 movs r0, r2 + 80006ec: f001 fcee bl 80020cc + 80006f0: 1e03 subs r3, r0, #0 + 80006f2: d004 beq.n 80006fe + 80006f4: 1d3b adds r3, r7, #4 + 80006f6: 881b ldrh r3, [r3, #0] + 80006f8: 4a3a ldr r2, [pc, #232] @ (80007e4 ) + 80006fa: 4293 cmp r3, r2 + 80006fc: d81d bhi.n 800073a + { + // todo long button action + } + else if (!HAL_GPIO_ReadPin(SW2_GPIO_Port,SW2_Pin) && (time_pressed <= 750)) // release in short window + 80006fe: 2380 movs r3, #128 @ 0x80 + 8000700: 005b lsls r3, r3, #1 + 8000702: 4a37 ldr r2, [pc, #220] @ (80007e0 ) + 8000704: 0019 movs r1, r3 + 8000706: 0010 movs r0, r2 + 8000708: f001 fce0 bl 80020cc + 800070c: 1e03 subs r3, r0, #0 + 800070e: d108 bne.n 8000722 + 8000710: 1d3b adds r3, r7, #4 + 8000712: 881b ldrh r3, [r3, #0] + 8000714: 4a33 ldr r2, [pc, #204] @ (80007e4 ) + 8000716: 4293 cmp r3, r2 + 8000718: d803 bhi.n 8000722 + { + // todo short button action + sw2_pressed = 0; + 800071a: 4b33 ldr r3, [pc, #204] @ (80007e8 ) + 800071c: 2200 movs r2, #0 + 800071e: 701a strb r2, [r3, #0] + 8000720: e00b b.n 800073a + } + else if (!HAL_GPIO_ReadPin(SW2_GPIO_Port,SW2_Pin)) sw2_pressed = 0; // release in long window + 8000722: 2380 movs r3, #128 @ 0x80 + 8000724: 005b lsls r3, r3, #1 + 8000726: 4a2e ldr r2, [pc, #184] @ (80007e0 ) + 8000728: 0019 movs r1, r3 + 800072a: 0010 movs r0, r2 + 800072c: f001 fcce bl 80020cc + 8000730: 1e03 subs r3, r0, #0 + 8000732: d102 bne.n 800073a + 8000734: 4b2c ldr r3, [pc, #176] @ (80007e8 ) + 8000736: 2200 movs r2, #0 + 8000738: 701a strb r2, [r3, #0] + } + + if (!msg_buffer2_empty) // msg 2 buffer has a message + 800073a: 4b2d ldr r3, [pc, #180] @ (80007f0 ) + 800073c: 781b ldrb r3, [r3, #0] + 800073e: 2b00 cmp r3, #0 + 8000740: d117 bne.n 8000772 + { + // decode message from msg_buffer2 + for (uint8_t i = 0; i<64 ; i++) + 8000742: 230f movs r3, #15 + 8000744: 18fb adds r3, r7, r3 + 8000746: 2200 movs r2, #0 + 8000748: 701a strb r2, [r3, #0] + 800074a: e00a b.n 8000762 + { + msg_buffer2[i]=0; + 800074c: 200f movs r0, #15 + 800074e: 183b adds r3, r7, r0 + 8000750: 781b ldrb r3, [r3, #0] + 8000752: 4a28 ldr r2, [pc, #160] @ (80007f4 ) + 8000754: 2100 movs r1, #0 + 8000756: 54d1 strb r1, [r2, r3] + for (uint8_t i = 0; i<64 ; i++) + 8000758: 183b adds r3, r7, r0 + 800075a: 781a ldrb r2, [r3, #0] + 800075c: 183b adds r3, r7, r0 + 800075e: 3201 adds r2, #1 + 8000760: 701a strb r2, [r3, #0] + 8000762: 230f movs r3, #15 + 8000764: 18fb adds r3, r7, r3 + 8000766: 781b ldrb r3, [r3, #0] + 8000768: 2b3f cmp r3, #63 @ 0x3f + 800076a: d9ef bls.n 800074c + } + msg_buffer2_empty = 1; + 800076c: 4b20 ldr r3, [pc, #128] @ (80007f0 ) + 800076e: 2201 movs r2, #1 + 8000770: 701a strb r2, [r3, #0] + } + if (!msg_buffer1_empty) + 8000772: 4b21 ldr r3, [pc, #132] @ (80007f8 ) + 8000774: 781b ldrb r3, [r3, #0] + 8000776: 2b00 cmp r3, #0 + 8000778: d000 beq.n 800077c + 800077a: e770 b.n 800065e + { + for (uint8_t i = 0; i<64 ; i++) + 800077c: 230e movs r3, #14 + 800077e: 18fb adds r3, r7, r3 + 8000780: 2200 movs r2, #0 + 8000782: 701a strb r2, [r3, #0] + 8000784: e00a b.n 800079c + { + msg_buffer1[i]=0; + 8000786: 200e movs r0, #14 + 8000788: 183b adds r3, r7, r0 + 800078a: 781b ldrb r3, [r3, #0] + 800078c: 4a1b ldr r2, [pc, #108] @ (80007fc ) + 800078e: 2100 movs r1, #0 + 8000790: 54d1 strb r1, [r2, r3] + for (uint8_t i = 0; i<64 ; i++) + 8000792: 183b adds r3, r7, r0 + 8000794: 781a ldrb r2, [r3, #0] + 8000796: 183b adds r3, r7, r0 + 8000798: 3201 adds r2, #1 + 800079a: 701a strb r2, [r3, #0] + 800079c: 230e movs r3, #14 + 800079e: 18fb adds r3, r7, r3 + 80007a0: 781b ldrb r3, [r3, #0] + 80007a2: 2b3f cmp r3, #63 @ 0x3f + 80007a4: d9ef bls.n 8000786 + } + msg_buffer1_empty = 1; + 80007a6: 4b14 ldr r3, [pc, #80] @ (80007f8 ) + 80007a8: 2201 movs r2, #1 + 80007aa: 701a strb r2, [r3, #0] + if (sw1_pressed) + 80007ac: e757 b.n 800065e + 80007ae: 46c0 nop @ (mov r8, r8) + 80007b0: 20000004 .word 0x20000004 + 80007b4: 20000008 .word 0x20000008 + 80007b8: 2000047c .word 0x2000047c + 80007bc: 2000000c .word 0x2000000c + 80007c0: 20000010 .word 0x20000010 + 80007c4: 20000014 .word 0x20000014 + 80007c8: 20000480 .word 0x20000480 + 80007cc: 200003a8 .word 0x200003a8 + 80007d0: 20000434 .word 0x20000434 + 80007d4: 20000250 .word 0x20000250 + 80007d8: 2000039c .word 0x2000039c + 80007dc: 20000124 .word 0x20000124 + 80007e0: 50000400 .word 0x50000400 + 80007e4: 000002ee .word 0x000002ee + 80007e8: 2000039d .word 0x2000039d + 80007ec: 20000170 .word 0x20000170 + 80007f0: 20000001 .word 0x20000001 + 80007f4: 200003f4 .word 0x200003f4 + 80007f8: 20000000 .word 0x20000000 + 80007fc: 200003b4 .word 0x200003b4 + +08000800 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { - 8000424: b590 push {r4, r7, lr} - 8000426: b08d sub sp, #52 @ 0x34 - 8000428: af00 add r7, sp, #0 + 8000800: b590 push {r4, r7, lr} + 8000802: b08d sub sp, #52 @ 0x34 + 8000804: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - 800042a: 2414 movs r4, #20 - 800042c: 193b adds r3, r7, r4 - 800042e: 0018 movs r0, r3 - 8000430: 231c movs r3, #28 - 8000432: 001a movs r2, r3 - 8000434: 2100 movs r1, #0 - 8000436: f003 fd81 bl 8003f3c + 8000806: 2414 movs r4, #20 + 8000808: 193b adds r3, r7, r4 + 800080a: 0018 movs r0, r3 + 800080c: 231c movs r3, #28 + 800080e: 001a movs r2, r3 + 8000810: 2100 movs r1, #0 + 8000812: f004 fa91 bl 8004d38 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - 800043a: 003b movs r3, r7 - 800043c: 0018 movs r0, r3 - 800043e: 2314 movs r3, #20 - 8000440: 001a movs r2, r3 - 8000442: 2100 movs r1, #0 - 8000444: f003 fd7a bl 8003f3c + 8000816: 003b movs r3, r7 + 8000818: 0018 movs r0, r3 + 800081a: 2314 movs r3, #20 + 800081c: 001a movs r2, r3 + 800081e: 2100 movs r1, #0 + 8000820: f004 fa8a bl 8004d38 __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_1); - 8000448: 4b1c ldr r3, [pc, #112] @ (80004bc ) - 800044a: 681b ldr r3, [r3, #0] - 800044c: 2207 movs r2, #7 - 800044e: 4393 bics r3, r2 - 8000450: 001a movs r2, r3 - 8000452: 4b1a ldr r3, [pc, #104] @ (80004bc ) - 8000454: 2101 movs r1, #1 - 8000456: 430a orrs r2, r1 - 8000458: 601a str r2, [r3, #0] + 8000824: 4b1c ldr r3, [pc, #112] @ (8000898 ) + 8000826: 681b ldr r3, [r3, #0] + 8000828: 2207 movs r2, #7 + 800082a: 4393 bics r3, r2 + 800082c: 001a movs r2, r3 + 800082e: 4b1a ldr r3, [pc, #104] @ (8000898 ) + 8000830: 2101 movs r1, #1 + 8000832: 430a orrs r2, r1 + 8000834: 601a str r2, [r3, #0] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; - 800045a: 193b adds r3, r7, r4 - 800045c: 2202 movs r2, #2 - 800045e: 601a str r2, [r3, #0] + 8000836: 193b adds r3, r7, r4 + 8000838: 2202 movs r2, #2 + 800083a: 601a str r2, [r3, #0] RCC_OscInitStruct.HSIState = RCC_HSI_ON; - 8000460: 193b adds r3, r7, r4 - 8000462: 2280 movs r2, #128 @ 0x80 - 8000464: 0052 lsls r2, r2, #1 - 8000466: 60da str r2, [r3, #12] + 800083c: 193b adds r3, r7, r4 + 800083e: 2280 movs r2, #128 @ 0x80 + 8000840: 0052 lsls r2, r2, #1 + 8000842: 60da str r2, [r3, #12] RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1; - 8000468: 193b adds r3, r7, r4 - 800046a: 2200 movs r2, #0 - 800046c: 611a str r2, [r3, #16] + 8000844: 193b adds r3, r7, r4 + 8000846: 2200 movs r2, #0 + 8000848: 611a str r2, [r3, #16] RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - 800046e: 193b adds r3, r7, r4 - 8000470: 2240 movs r2, #64 @ 0x40 - 8000472: 615a str r2, [r3, #20] + 800084a: 193b adds r3, r7, r4 + 800084c: 2240 movs r2, #64 @ 0x40 + 800084e: 615a str r2, [r3, #20] if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - 8000474: 193b adds r3, r7, r4 - 8000476: 0018 movs r0, r3 - 8000478: f001 fa3e bl 80018f8 - 800047c: 1e03 subs r3, r0, #0 - 800047e: d001 beq.n 8000484 + 8000850: 193b adds r3, r7, r4 + 8000852: 0018 movs r0, r3 + 8000854: f001 fcb2 bl 80021bc + 8000858: 1e03 subs r3, r0, #0 + 800085a: d001 beq.n 8000860 { Error_Handler(); - 8000480: f000 fb17 bl 8000ab2 + 800085c: f000 fc24 bl 80010a8 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - 8000484: 003b movs r3, r7 - 8000486: 2207 movs r2, #7 - 8000488: 601a str r2, [r3, #0] + 8000860: 003b movs r3, r7 + 8000862: 2207 movs r2, #7 + 8000864: 601a str r2, [r3, #0] |RCC_CLOCKTYPE_PCLK1; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; - 800048a: 003b movs r3, r7 - 800048c: 2200 movs r2, #0 - 800048e: 605a str r2, [r3, #4] + 8000866: 003b movs r3, r7 + 8000868: 2200 movs r2, #0 + 800086a: 605a str r2, [r3, #4] RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; - 8000490: 003b movs r3, r7 - 8000492: 2200 movs r2, #0 - 8000494: 609a str r2, [r3, #8] + 800086c: 003b movs r3, r7 + 800086e: 2200 movs r2, #0 + 8000870: 609a str r2, [r3, #8] RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1; - 8000496: 003b movs r3, r7 - 8000498: 2200 movs r2, #0 - 800049a: 60da str r2, [r3, #12] + 8000872: 003b movs r3, r7 + 8000874: 2200 movs r2, #0 + 8000876: 60da str r2, [r3, #12] RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1; - 800049c: 003b movs r3, r7 - 800049e: 2200 movs r2, #0 - 80004a0: 611a str r2, [r3, #16] + 8000878: 003b movs r3, r7 + 800087a: 2200 movs r2, #0 + 800087c: 611a str r2, [r3, #16] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) - 80004a2: 003b movs r3, r7 - 80004a4: 2101 movs r1, #1 - 80004a6: 0018 movs r0, r3 - 80004a8: f001 fc0a bl 8001cc0 - 80004ac: 1e03 subs r3, r0, #0 - 80004ae: d001 beq.n 80004b4 + 800087e: 003b movs r3, r7 + 8000880: 2101 movs r1, #1 + 8000882: 0018 movs r0, r3 + 8000884: f001 fe7e bl 8002584 + 8000888: 1e03 subs r3, r0, #0 + 800088a: d001 beq.n 8000890 { Error_Handler(); - 80004b0: f000 faff bl 8000ab2 + 800088c: f000 fc0c bl 80010a8 } } - 80004b4: 46c0 nop @ (mov r8, r8) - 80004b6: 46bd mov sp, r7 - 80004b8: b00d add sp, #52 @ 0x34 - 80004ba: bd90 pop {r4, r7, pc} - 80004bc: 40022000 .word 0x40022000 + 8000890: 46c0 nop @ (mov r8, r8) + 8000892: 46bd mov sp, r7 + 8000894: b00d add sp, #52 @ 0x34 + 8000896: bd90 pop {r4, r7, pc} + 8000898: 40022000 .word 0x40022000 -080004c0 : +0800089c : * @brief TIM1 Initialization Function * @param None * @retval None */ static void MX_TIM1_Init(void) { - 80004c0: b580 push {r7, lr} - 80004c2: b09c sub sp, #112 @ 0x70 - 80004c4: af00 add r7, sp, #0 + 800089c: b580 push {r7, lr} + 800089e: b09c sub sp, #112 @ 0x70 + 80008a0: af00 add r7, sp, #0 /* USER CODE BEGIN TIM1_Init 0 */ /* USER CODE END TIM1_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; - 80004c6: 2360 movs r3, #96 @ 0x60 - 80004c8: 18fb adds r3, r7, r3 - 80004ca: 0018 movs r0, r3 - 80004cc: 2310 movs r3, #16 - 80004ce: 001a movs r2, r3 - 80004d0: 2100 movs r1, #0 - 80004d2: f003 fd33 bl 8003f3c + 80008a2: 2360 movs r3, #96 @ 0x60 + 80008a4: 18fb adds r3, r7, r3 + 80008a6: 0018 movs r0, r3 + 80008a8: 2310 movs r3, #16 + 80008aa: 001a movs r2, r3 + 80008ac: 2100 movs r1, #0 + 80008ae: f004 fa43 bl 8004d38 TIM_MasterConfigTypeDef sMasterConfig = {0}; - 80004d6: 2354 movs r3, #84 @ 0x54 - 80004d8: 18fb adds r3, r7, r3 - 80004da: 0018 movs r0, r3 - 80004dc: 230c movs r3, #12 - 80004de: 001a movs r2, r3 - 80004e0: 2100 movs r1, #0 - 80004e2: f003 fd2b bl 8003f3c + 80008b2: 2354 movs r3, #84 @ 0x54 + 80008b4: 18fb adds r3, r7, r3 + 80008b6: 0018 movs r0, r3 + 80008b8: 230c movs r3, #12 + 80008ba: 001a movs r2, r3 + 80008bc: 2100 movs r1, #0 + 80008be: f004 fa3b bl 8004d38 TIM_OC_InitTypeDef sConfigOC = {0}; - 80004e6: 2338 movs r3, #56 @ 0x38 - 80004e8: 18fb adds r3, r7, r3 - 80004ea: 0018 movs r0, r3 - 80004ec: 231c movs r3, #28 - 80004ee: 001a movs r2, r3 - 80004f0: 2100 movs r1, #0 - 80004f2: f003 fd23 bl 8003f3c + 80008c2: 2338 movs r3, #56 @ 0x38 + 80008c4: 18fb adds r3, r7, r3 + 80008c6: 0018 movs r0, r3 + 80008c8: 231c movs r3, #28 + 80008ca: 001a movs r2, r3 + 80008cc: 2100 movs r1, #0 + 80008ce: f004 fa33 bl 8004d38 TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0}; - 80004f6: 1d3b adds r3, r7, #4 - 80004f8: 0018 movs r0, r3 - 80004fa: 2334 movs r3, #52 @ 0x34 - 80004fc: 001a movs r2, r3 - 80004fe: 2100 movs r1, #0 - 8000500: f003 fd1c bl 8003f3c + 80008d2: 1d3b adds r3, r7, #4 + 80008d4: 0018 movs r0, r3 + 80008d6: 2334 movs r3, #52 @ 0x34 + 80008d8: 001a movs r2, r3 + 80008da: 2100 movs r1, #0 + 80008dc: f004 fa2c bl 8004d38 /* USER CODE BEGIN TIM1_Init 1 */ /* USER CODE END TIM1_Init 1 */ htim1.Instance = TIM1; - 8000504: 4b62 ldr r3, [pc, #392] @ (8000690 ) - 8000506: 4a63 ldr r2, [pc, #396] @ (8000694 ) - 8000508: 601a str r2, [r3, #0] + 80008e0: 4b62 ldr r3, [pc, #392] @ (8000a6c ) + 80008e2: 4a63 ldr r2, [pc, #396] @ (8000a70 ) + 80008e4: 601a str r2, [r3, #0] htim1.Init.Prescaler = 0; - 800050a: 4b61 ldr r3, [pc, #388] @ (8000690 ) - 800050c: 2200 movs r2, #0 - 800050e: 605a str r2, [r3, #4] + 80008e6: 4b61 ldr r3, [pc, #388] @ (8000a6c ) + 80008e8: 2200 movs r2, #0 + 80008ea: 605a str r2, [r3, #4] htim1.Init.CounterMode = TIM_COUNTERMODE_UP; - 8000510: 4b5f ldr r3, [pc, #380] @ (8000690 ) - 8000512: 2200 movs r2, #0 - 8000514: 609a str r2, [r3, #8] + 80008ec: 4b5f ldr r3, [pc, #380] @ (8000a6c ) + 80008ee: 2200 movs r2, #0 + 80008f0: 609a str r2, [r3, #8] htim1.Init.Period = 2400; - 8000516: 4b5e ldr r3, [pc, #376] @ (8000690 ) - 8000518: 2296 movs r2, #150 @ 0x96 - 800051a: 0112 lsls r2, r2, #4 - 800051c: 60da str r2, [r3, #12] + 80008f2: 4b5e ldr r3, [pc, #376] @ (8000a6c ) + 80008f4: 2296 movs r2, #150 @ 0x96 + 80008f6: 0112 lsls r2, r2, #4 + 80008f8: 60da str r2, [r3, #12] htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; - 800051e: 4b5c ldr r3, [pc, #368] @ (8000690 ) - 8000520: 2200 movs r2, #0 - 8000522: 611a str r2, [r3, #16] + 80008fa: 4b5c ldr r3, [pc, #368] @ (8000a6c ) + 80008fc: 2200 movs r2, #0 + 80008fe: 611a str r2, [r3, #16] htim1.Init.RepetitionCounter = 0; - 8000524: 4b5a ldr r3, [pc, #360] @ (8000690 ) - 8000526: 2200 movs r2, #0 - 8000528: 615a str r2, [r3, #20] + 8000900: 4b5a ldr r3, [pc, #360] @ (8000a6c ) + 8000902: 2200 movs r2, #0 + 8000904: 615a str r2, [r3, #20] htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; - 800052a: 4b59 ldr r3, [pc, #356] @ (8000690 ) - 800052c: 2200 movs r2, #0 - 800052e: 619a str r2, [r3, #24] + 8000906: 4b59 ldr r3, [pc, #356] @ (8000a6c ) + 8000908: 2200 movs r2, #0 + 800090a: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim1) != HAL_OK) - 8000530: 4b57 ldr r3, [pc, #348] @ (8000690 ) - 8000532: 0018 movs r0, r3 - 8000534: f001 fe40 bl 80021b8 - 8000538: 1e03 subs r3, r0, #0 - 800053a: d001 beq.n 8000540 + 800090c: 4b57 ldr r3, [pc, #348] @ (8000a6c ) + 800090e: 0018 movs r0, r3 + 8000910: f002 f8b4 bl 8002a7c + 8000914: 1e03 subs r3, r0, #0 + 8000916: d001 beq.n 800091c { Error_Handler(); - 800053c: f000 fab9 bl 8000ab2 + 8000918: f000 fbc6 bl 80010a8 } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; - 8000540: 2160 movs r1, #96 @ 0x60 - 8000542: 187b adds r3, r7, r1 - 8000544: 2280 movs r2, #128 @ 0x80 - 8000546: 0152 lsls r2, r2, #5 - 8000548: 601a str r2, [r3, #0] + 800091c: 2160 movs r1, #96 @ 0x60 + 800091e: 187b adds r3, r7, r1 + 8000920: 2280 movs r2, #128 @ 0x80 + 8000922: 0152 lsls r2, r2, #5 + 8000924: 601a str r2, [r3, #0] if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK) - 800054a: 187a adds r2, r7, r1 - 800054c: 4b50 ldr r3, [pc, #320] @ (8000690 ) - 800054e: 0011 movs r1, r2 - 8000550: 0018 movs r0, r3 - 8000552: f002 f999 bl 8002888 - 8000556: 1e03 subs r3, r0, #0 - 8000558: d001 beq.n 800055e + 8000926: 187a adds r2, r7, r1 + 8000928: 4b50 ldr r3, [pc, #320] @ (8000a6c ) + 800092a: 0011 movs r1, r2 + 800092c: 0018 movs r0, r3 + 800092e: f002 fc0d bl 800314c + 8000932: 1e03 subs r3, r0, #0 + 8000934: d001 beq.n 800093a { Error_Handler(); - 800055a: f000 faaa bl 8000ab2 + 8000936: f000 fbb7 bl 80010a8 } if (HAL_TIM_PWM_Init(&htim1) != HAL_OK) - 800055e: 4b4c ldr r3, [pc, #304] @ (8000690 ) - 8000560: 0018 movs r0, r3 - 8000562: f001 fe81 bl 8002268 - 8000566: 1e03 subs r3, r0, #0 - 8000568: d001 beq.n 800056e + 800093a: 4b4c ldr r3, [pc, #304] @ (8000a6c ) + 800093c: 0018 movs r0, r3 + 800093e: f002 f8f5 bl 8002b2c + 8000942: 1e03 subs r3, r0, #0 + 8000944: d001 beq.n 800094a { Error_Handler(); - 800056a: f000 faa2 bl 8000ab2 + 8000946: f000 fbaf bl 80010a8 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; - 800056e: 2154 movs r1, #84 @ 0x54 - 8000570: 187b adds r3, r7, r1 - 8000572: 2200 movs r2, #0 - 8000574: 601a str r2, [r3, #0] + 800094a: 2154 movs r1, #84 @ 0x54 + 800094c: 187b adds r3, r7, r1 + 800094e: 2200 movs r2, #0 + 8000950: 601a str r2, [r3, #0] sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; - 8000576: 187b adds r3, r7, r1 - 8000578: 2200 movs r2, #0 - 800057a: 605a str r2, [r3, #4] + 8000952: 187b adds r3, r7, r1 + 8000954: 2200 movs r2, #0 + 8000956: 605a str r2, [r3, #4] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; - 800057c: 187b adds r3, r7, r1 - 800057e: 2200 movs r2, #0 - 8000580: 609a str r2, [r3, #8] + 8000958: 187b adds r3, r7, r1 + 800095a: 2200 movs r2, #0 + 800095c: 609a str r2, [r3, #8] if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK) - 8000582: 187a adds r2, r7, r1 - 8000584: 4b42 ldr r3, [pc, #264] @ (8000690 ) - 8000586: 0011 movs r1, r2 - 8000588: 0018 movs r0, r3 - 800058a: f002 fe27 bl 80031dc - 800058e: 1e03 subs r3, r0, #0 - 8000590: d001 beq.n 8000596 + 800095e: 187a adds r2, r7, r1 + 8000960: 4b42 ldr r3, [pc, #264] @ (8000a6c ) + 8000962: 0011 movs r1, r2 + 8000964: 0018 movs r0, r3 + 8000966: f003 f89b bl 8003aa0 + 800096a: 1e03 subs r3, r0, #0 + 800096c: d001 beq.n 8000972 { Error_Handler(); - 8000592: f000 fa8e bl 8000ab2 + 800096e: f000 fb9b bl 80010a8 } sConfigOC.OCMode = TIM_OCMODE_PWM1; - 8000596: 2138 movs r1, #56 @ 0x38 - 8000598: 187b adds r3, r7, r1 - 800059a: 2260 movs r2, #96 @ 0x60 - 800059c: 601a str r2, [r3, #0] + 8000972: 2138 movs r1, #56 @ 0x38 + 8000974: 187b adds r3, r7, r1 + 8000976: 2260 movs r2, #96 @ 0x60 + 8000978: 601a str r2, [r3, #0] sConfigOC.Pulse = 0; - 800059e: 187b adds r3, r7, r1 - 80005a0: 2200 movs r2, #0 - 80005a2: 605a str r2, [r3, #4] + 800097a: 187b adds r3, r7, r1 + 800097c: 2200 movs r2, #0 + 800097e: 605a str r2, [r3, #4] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; - 80005a4: 187b adds r3, r7, r1 - 80005a6: 2200 movs r2, #0 - 80005a8: 609a str r2, [r3, #8] + 8000980: 187b adds r3, r7, r1 + 8000982: 2200 movs r2, #0 + 8000984: 609a str r2, [r3, #8] sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH; - 80005aa: 187b adds r3, r7, r1 - 80005ac: 2200 movs r2, #0 - 80005ae: 60da str r2, [r3, #12] + 8000986: 187b adds r3, r7, r1 + 8000988: 2200 movs r2, #0 + 800098a: 60da str r2, [r3, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; - 80005b0: 187b adds r3, r7, r1 - 80005b2: 2200 movs r2, #0 - 80005b4: 611a str r2, [r3, #16] + 800098c: 187b adds r3, r7, r1 + 800098e: 2200 movs r2, #0 + 8000990: 611a str r2, [r3, #16] sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; - 80005b6: 187b adds r3, r7, r1 - 80005b8: 2200 movs r2, #0 - 80005ba: 615a str r2, [r3, #20] + 8000992: 187b adds r3, r7, r1 + 8000994: 2200 movs r2, #0 + 8000996: 615a str r2, [r3, #20] sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET; - 80005bc: 187b adds r3, r7, r1 - 80005be: 2200 movs r2, #0 - 80005c0: 619a str r2, [r3, #24] + 8000998: 187b adds r3, r7, r1 + 800099a: 2200 movs r2, #0 + 800099c: 619a str r2, [r3, #24] if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) - 80005c2: 1879 adds r1, r7, r1 - 80005c4: 4b32 ldr r3, [pc, #200] @ (8000690 ) - 80005c6: 2200 movs r2, #0 - 80005c8: 0018 movs r0, r3 - 80005ca: f002 f85d bl 8002688 - 80005ce: 1e03 subs r3, r0, #0 - 80005d0: d001 beq.n 80005d6 + 800099e: 1879 adds r1, r7, r1 + 80009a0: 4b32 ldr r3, [pc, #200] @ (8000a6c ) + 80009a2: 2200 movs r2, #0 + 80009a4: 0018 movs r0, r3 + 80009a6: f002 fad1 bl 8002f4c + 80009aa: 1e03 subs r3, r0, #0 + 80009ac: d001 beq.n 80009b2 { Error_Handler(); - 80005d2: f000 fa6e bl 8000ab2 + 80009ae: f000 fb7b bl 80010a8 } if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) - 80005d6: 2338 movs r3, #56 @ 0x38 - 80005d8: 18f9 adds r1, r7, r3 - 80005da: 4b2d ldr r3, [pc, #180] @ (8000690 ) - 80005dc: 2204 movs r2, #4 - 80005de: 0018 movs r0, r3 - 80005e0: f002 f852 bl 8002688 - 80005e4: 1e03 subs r3, r0, #0 - 80005e6: d001 beq.n 80005ec + 80009b2: 2338 movs r3, #56 @ 0x38 + 80009b4: 18f9 adds r1, r7, r3 + 80009b6: 4b2d ldr r3, [pc, #180] @ (8000a6c ) + 80009b8: 2204 movs r2, #4 + 80009ba: 0018 movs r0, r3 + 80009bc: f002 fac6 bl 8002f4c + 80009c0: 1e03 subs r3, r0, #0 + 80009c2: d001 beq.n 80009c8 { Error_Handler(); - 80005e8: f000 fa63 bl 8000ab2 + 80009c4: f000 fb70 bl 80010a8 } if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) - 80005ec: 2338 movs r3, #56 @ 0x38 - 80005ee: 18f9 adds r1, r7, r3 - 80005f0: 4b27 ldr r3, [pc, #156] @ (8000690 ) - 80005f2: 2208 movs r2, #8 - 80005f4: 0018 movs r0, r3 - 80005f6: f002 f847 bl 8002688 - 80005fa: 1e03 subs r3, r0, #0 - 80005fc: d001 beq.n 8000602 + 80009c8: 2338 movs r3, #56 @ 0x38 + 80009ca: 18f9 adds r1, r7, r3 + 80009cc: 4b27 ldr r3, [pc, #156] @ (8000a6c ) + 80009ce: 2208 movs r2, #8 + 80009d0: 0018 movs r0, r3 + 80009d2: f002 fabb bl 8002f4c + 80009d6: 1e03 subs r3, r0, #0 + 80009d8: d001 beq.n 80009de { Error_Handler(); - 80005fe: f000 fa58 bl 8000ab2 + 80009da: f000 fb65 bl 80010a8 } if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) - 8000602: 2338 movs r3, #56 @ 0x38 - 8000604: 18f9 adds r1, r7, r3 - 8000606: 4b22 ldr r3, [pc, #136] @ (8000690 ) - 8000608: 220c movs r2, #12 - 800060a: 0018 movs r0, r3 - 800060c: f002 f83c bl 8002688 - 8000610: 1e03 subs r3, r0, #0 - 8000612: d001 beq.n 8000618 + 80009de: 2338 movs r3, #56 @ 0x38 + 80009e0: 18f9 adds r1, r7, r3 + 80009e2: 4b22 ldr r3, [pc, #136] @ (8000a6c ) + 80009e4: 220c movs r2, #12 + 80009e6: 0018 movs r0, r3 + 80009e8: f002 fab0 bl 8002f4c + 80009ec: 1e03 subs r3, r0, #0 + 80009ee: d001 beq.n 80009f4 { Error_Handler(); - 8000614: f000 fa4d bl 8000ab2 + 80009f0: f000 fb5a bl 80010a8 } sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE; - 8000618: 1d3b adds r3, r7, #4 - 800061a: 2200 movs r2, #0 - 800061c: 601a str r2, [r3, #0] + 80009f4: 1d3b adds r3, r7, #4 + 80009f6: 2200 movs r2, #0 + 80009f8: 601a str r2, [r3, #0] sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE; - 800061e: 1d3b adds r3, r7, #4 - 8000620: 2200 movs r2, #0 - 8000622: 605a str r2, [r3, #4] + 80009fa: 1d3b adds r3, r7, #4 + 80009fc: 2200 movs r2, #0 + 80009fe: 605a str r2, [r3, #4] sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF; - 8000624: 1d3b adds r3, r7, #4 - 8000626: 2200 movs r2, #0 - 8000628: 609a str r2, [r3, #8] + 8000a00: 1d3b adds r3, r7, #4 + 8000a02: 2200 movs r2, #0 + 8000a04: 609a str r2, [r3, #8] sBreakDeadTimeConfig.DeadTime = 0; - 800062a: 1d3b adds r3, r7, #4 - 800062c: 2200 movs r2, #0 - 800062e: 60da str r2, [r3, #12] + 8000a06: 1d3b adds r3, r7, #4 + 8000a08: 2200 movs r2, #0 + 8000a0a: 60da str r2, [r3, #12] sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; - 8000630: 1d3b adds r3, r7, #4 - 8000632: 2200 movs r2, #0 - 8000634: 611a str r2, [r3, #16] + 8000a0c: 1d3b adds r3, r7, #4 + 8000a0e: 2200 movs r2, #0 + 8000a10: 611a str r2, [r3, #16] sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH; - 8000636: 1d3b adds r3, r7, #4 - 8000638: 2280 movs r2, #128 @ 0x80 - 800063a: 0192 lsls r2, r2, #6 - 800063c: 615a str r2, [r3, #20] + 8000a12: 1d3b adds r3, r7, #4 + 8000a14: 2280 movs r2, #128 @ 0x80 + 8000a16: 0192 lsls r2, r2, #6 + 8000a18: 615a str r2, [r3, #20] sBreakDeadTimeConfig.BreakFilter = 0; - 800063e: 1d3b adds r3, r7, #4 - 8000640: 2200 movs r2, #0 - 8000642: 619a str r2, [r3, #24] + 8000a1a: 1d3b adds r3, r7, #4 + 8000a1c: 2200 movs r2, #0 + 8000a1e: 619a str r2, [r3, #24] sBreakDeadTimeConfig.BreakAFMode = TIM_BREAK_AFMODE_INPUT; - 8000644: 1d3b adds r3, r7, #4 - 8000646: 2200 movs r2, #0 - 8000648: 61da str r2, [r3, #28] + 8000a20: 1d3b adds r3, r7, #4 + 8000a22: 2200 movs r2, #0 + 8000a24: 61da str r2, [r3, #28] sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE; - 800064a: 1d3b adds r3, r7, #4 - 800064c: 2200 movs r2, #0 - 800064e: 621a str r2, [r3, #32] + 8000a26: 1d3b adds r3, r7, #4 + 8000a28: 2200 movs r2, #0 + 8000a2a: 621a str r2, [r3, #32] sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH; - 8000650: 1d3b adds r3, r7, #4 - 8000652: 2280 movs r2, #128 @ 0x80 - 8000654: 0492 lsls r2, r2, #18 - 8000656: 625a str r2, [r3, #36] @ 0x24 + 8000a2c: 1d3b adds r3, r7, #4 + 8000a2e: 2280 movs r2, #128 @ 0x80 + 8000a30: 0492 lsls r2, r2, #18 + 8000a32: 625a str r2, [r3, #36] @ 0x24 sBreakDeadTimeConfig.Break2Filter = 0; - 8000658: 1d3b adds r3, r7, #4 - 800065a: 2200 movs r2, #0 - 800065c: 629a str r2, [r3, #40] @ 0x28 + 8000a34: 1d3b adds r3, r7, #4 + 8000a36: 2200 movs r2, #0 + 8000a38: 629a str r2, [r3, #40] @ 0x28 sBreakDeadTimeConfig.Break2AFMode = TIM_BREAK_AFMODE_INPUT; - 800065e: 1d3b adds r3, r7, #4 - 8000660: 2200 movs r2, #0 - 8000662: 62da str r2, [r3, #44] @ 0x2c + 8000a3a: 1d3b adds r3, r7, #4 + 8000a3c: 2200 movs r2, #0 + 8000a3e: 62da str r2, [r3, #44] @ 0x2c sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; - 8000664: 1d3b adds r3, r7, #4 - 8000666: 2200 movs r2, #0 - 8000668: 631a str r2, [r3, #48] @ 0x30 + 8000a40: 1d3b adds r3, r7, #4 + 8000a42: 2200 movs r2, #0 + 8000a44: 631a str r2, [r3, #48] @ 0x30 if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK) - 800066a: 1d3a adds r2, r7, #4 - 800066c: 4b08 ldr r3, [pc, #32] @ (8000690 ) - 800066e: 0011 movs r1, r2 - 8000670: 0018 movs r0, r3 - 8000672: f002 fe1b bl 80032ac - 8000676: 1e03 subs r3, r0, #0 - 8000678: d001 beq.n 800067e + 8000a46: 1d3a adds r2, r7, #4 + 8000a48: 4b08 ldr r3, [pc, #32] @ (8000a6c ) + 8000a4a: 0011 movs r1, r2 + 8000a4c: 0018 movs r0, r3 + 8000a4e: f003 f88f bl 8003b70 + 8000a52: 1e03 subs r3, r0, #0 + 8000a54: d001 beq.n 8000a5a { Error_Handler(); - 800067a: f000 fa1a bl 8000ab2 + 8000a56: f000 fb27 bl 80010a8 } /* USER CODE BEGIN TIM1_Init 2 */ /* USER CODE END TIM1_Init 2 */ HAL_TIM_MspPostInit(&htim1); - 800067e: 4b04 ldr r3, [pc, #16] @ (8000690 ) - 8000680: 0018 movs r0, r3 - 8000682: f000 fb15 bl 8000cb0 + 8000a5a: 4b04 ldr r3, [pc, #16] @ (8000a6c ) + 8000a5c: 0018 movs r0, r3 + 8000a5e: f000 fc11 bl 8001284 } - 8000686: 46c0 nop @ (mov r8, r8) - 8000688: 46bd mov sp, r7 - 800068a: b01c add sp, #112 @ 0x70 - 800068c: bd80 pop {r7, pc} - 800068e: 46c0 nop @ (mov r8, r8) - 8000690: 20000028 .word 0x20000028 - 8000694: 40012c00 .word 0x40012c00 + 8000a62: 46c0 nop @ (mov r8, r8) + 8000a64: 46bd mov sp, r7 + 8000a66: b01c add sp, #112 @ 0x70 + 8000a68: bd80 pop {r7, pc} + 8000a6a: 46c0 nop @ (mov r8, r8) + 8000a6c: 20000040 .word 0x20000040 + 8000a70: 40012c00 .word 0x40012c00 -08000698 : +08000a74 : * @brief TIM3 Initialization Function * @param None * @retval None */ static void MX_TIM3_Init(void) { - 8000698: b590 push {r4, r7, lr} - 800069a: b08d sub sp, #52 @ 0x34 - 800069c: af00 add r7, sp, #0 + 8000a74: b590 push {r4, r7, lr} + 8000a76: b08d sub sp, #52 @ 0x34 + 8000a78: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_Encoder_InitTypeDef sConfig = {0}; - 800069e: 240c movs r4, #12 - 80006a0: 193b adds r3, r7, r4 - 80006a2: 0018 movs r0, r3 - 80006a4: 2324 movs r3, #36 @ 0x24 - 80006a6: 001a movs r2, r3 - 80006a8: 2100 movs r1, #0 - 80006aa: f003 fc47 bl 8003f3c + 8000a7a: 240c movs r4, #12 + 8000a7c: 193b adds r3, r7, r4 + 8000a7e: 0018 movs r0, r3 + 8000a80: 2324 movs r3, #36 @ 0x24 + 8000a82: 001a movs r2, r3 + 8000a84: 2100 movs r1, #0 + 8000a86: f004 f957 bl 8004d38 TIM_MasterConfigTypeDef sMasterConfig = {0}; - 80006ae: 003b movs r3, r7 - 80006b0: 0018 movs r0, r3 - 80006b2: 230c movs r3, #12 - 80006b4: 001a movs r2, r3 - 80006b6: 2100 movs r1, #0 - 80006b8: f003 fc40 bl 8003f3c + 8000a8a: 003b movs r3, r7 + 8000a8c: 0018 movs r0, r3 + 8000a8e: 230c movs r3, #12 + 8000a90: 001a movs r2, r3 + 8000a92: 2100 movs r1, #0 + 8000a94: f004 f950 bl 8004d38 /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; - 80006bc: 4b25 ldr r3, [pc, #148] @ (8000754 ) - 80006be: 4a26 ldr r2, [pc, #152] @ (8000758 ) - 80006c0: 601a str r2, [r3, #0] + 8000a98: 4b25 ldr r3, [pc, #148] @ (8000b30 ) + 8000a9a: 4a26 ldr r2, [pc, #152] @ (8000b34 ) + 8000a9c: 601a str r2, [r3, #0] htim3.Init.Prescaler = 0; - 80006c2: 4b24 ldr r3, [pc, #144] @ (8000754 ) - 80006c4: 2200 movs r2, #0 - 80006c6: 605a str r2, [r3, #4] + 8000a9e: 4b24 ldr r3, [pc, #144] @ (8000b30 ) + 8000aa0: 2200 movs r2, #0 + 8000aa2: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; - 80006c8: 4b22 ldr r3, [pc, #136] @ (8000754 ) - 80006ca: 2200 movs r2, #0 - 80006cc: 609a str r2, [r3, #8] + 8000aa4: 4b22 ldr r3, [pc, #136] @ (8000b30 ) + 8000aa6: 2200 movs r2, #0 + 8000aa8: 609a str r2, [r3, #8] htim3.Init.Period = 65535; - 80006ce: 4b21 ldr r3, [pc, #132] @ (8000754 ) - 80006d0: 4a22 ldr r2, [pc, #136] @ (800075c ) - 80006d2: 60da str r2, [r3, #12] + 8000aaa: 4b21 ldr r3, [pc, #132] @ (8000b30 ) + 8000aac: 4a22 ldr r2, [pc, #136] @ (8000b38 ) + 8000aae: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; - 80006d4: 4b1f ldr r3, [pc, #124] @ (8000754 ) - 80006d6: 2200 movs r2, #0 - 80006d8: 611a str r2, [r3, #16] + 8000ab0: 4b1f ldr r3, [pc, #124] @ (8000b30 ) + 8000ab2: 2200 movs r2, #0 + 8000ab4: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; - 80006da: 4b1e ldr r3, [pc, #120] @ (8000754 ) - 80006dc: 2200 movs r2, #0 - 80006de: 619a str r2, [r3, #24] + 8000ab6: 4b1e ldr r3, [pc, #120] @ (8000b30 ) + 8000ab8: 2200 movs r2, #0 + 8000aba: 619a str r2, [r3, #24] sConfig.EncoderMode = TIM_ENCODERMODE_TI12; - 80006e0: 0021 movs r1, r4 - 80006e2: 187b adds r3, r7, r1 - 80006e4: 2203 movs r2, #3 - 80006e6: 601a str r2, [r3, #0] + 8000abc: 0021 movs r1, r4 + 8000abe: 187b adds r3, r7, r1 + 8000ac0: 2203 movs r2, #3 + 8000ac2: 601a str r2, [r3, #0] sConfig.IC1Polarity = TIM_ICPOLARITY_RISING; - 80006e8: 187b adds r3, r7, r1 - 80006ea: 2200 movs r2, #0 - 80006ec: 605a str r2, [r3, #4] + 8000ac4: 187b adds r3, r7, r1 + 8000ac6: 2200 movs r2, #0 + 8000ac8: 605a str r2, [r3, #4] sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI; - 80006ee: 187b adds r3, r7, r1 - 80006f0: 2201 movs r2, #1 - 80006f2: 609a str r2, [r3, #8] + 8000aca: 187b adds r3, r7, r1 + 8000acc: 2201 movs r2, #1 + 8000ace: 609a str r2, [r3, #8] sConfig.IC1Prescaler = TIM_ICPSC_DIV1; - 80006f4: 187b adds r3, r7, r1 - 80006f6: 2200 movs r2, #0 - 80006f8: 60da str r2, [r3, #12] + 8000ad0: 187b adds r3, r7, r1 + 8000ad2: 2200 movs r2, #0 + 8000ad4: 60da str r2, [r3, #12] sConfig.IC1Filter = 0; - 80006fa: 187b adds r3, r7, r1 - 80006fc: 2200 movs r2, #0 - 80006fe: 611a str r2, [r3, #16] + 8000ad6: 187b adds r3, r7, r1 + 8000ad8: 2200 movs r2, #0 + 8000ada: 611a str r2, [r3, #16] sConfig.IC2Polarity = TIM_ICPOLARITY_RISING; - 8000700: 187b adds r3, r7, r1 - 8000702: 2200 movs r2, #0 - 8000704: 615a str r2, [r3, #20] + 8000adc: 187b adds r3, r7, r1 + 8000ade: 2200 movs r2, #0 + 8000ae0: 615a str r2, [r3, #20] sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI; - 8000706: 187b adds r3, r7, r1 - 8000708: 2201 movs r2, #1 - 800070a: 619a str r2, [r3, #24] + 8000ae2: 187b adds r3, r7, r1 + 8000ae4: 2201 movs r2, #1 + 8000ae6: 619a str r2, [r3, #24] sConfig.IC2Prescaler = TIM_ICPSC_DIV1; - 800070c: 187b adds r3, r7, r1 - 800070e: 2200 movs r2, #0 - 8000710: 61da str r2, [r3, #28] + 8000ae8: 187b adds r3, r7, r1 + 8000aea: 2200 movs r2, #0 + 8000aec: 61da str r2, [r3, #28] sConfig.IC2Filter = 0; - 8000712: 187b adds r3, r7, r1 - 8000714: 2200 movs r2, #0 - 8000716: 621a str r2, [r3, #32] + 8000aee: 187b adds r3, r7, r1 + 8000af0: 2200 movs r2, #0 + 8000af2: 621a str r2, [r3, #32] if (HAL_TIM_Encoder_Init(&htim3, &sConfig) != HAL_OK) - 8000718: 187a adds r2, r7, r1 - 800071a: 4b0e ldr r3, [pc, #56] @ (8000754 ) - 800071c: 0011 movs r1, r2 - 800071e: 0018 movs r0, r3 - 8000720: f001 fe02 bl 8002328 - 8000724: 1e03 subs r3, r0, #0 - 8000726: d001 beq.n 800072c + 8000af4: 187a adds r2, r7, r1 + 8000af6: 4b0e ldr r3, [pc, #56] @ (8000b30 ) + 8000af8: 0011 movs r1, r2 + 8000afa: 0018 movs r0, r3 + 8000afc: f002 f876 bl 8002bec + 8000b00: 1e03 subs r3, r0, #0 + 8000b02: d001 beq.n 8000b08 { Error_Handler(); - 8000728: f000 f9c3 bl 8000ab2 + 8000b04: f000 fad0 bl 80010a8 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; - 800072c: 003b movs r3, r7 - 800072e: 2200 movs r2, #0 - 8000730: 601a str r2, [r3, #0] + 8000b08: 003b movs r3, r7 + 8000b0a: 2200 movs r2, #0 + 8000b0c: 601a str r2, [r3, #0] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; - 8000732: 003b movs r3, r7 - 8000734: 2200 movs r2, #0 - 8000736: 609a str r2, [r3, #8] + 8000b0e: 003b movs r3, r7 + 8000b10: 2200 movs r2, #0 + 8000b12: 609a str r2, [r3, #8] if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) - 8000738: 003a movs r2, r7 - 800073a: 4b06 ldr r3, [pc, #24] @ (8000754 ) - 800073c: 0011 movs r1, r2 - 800073e: 0018 movs r0, r3 - 8000740: f002 fd4c bl 80031dc - 8000744: 1e03 subs r3, r0, #0 - 8000746: d001 beq.n 800074c + 8000b14: 003a movs r2, r7 + 8000b16: 4b06 ldr r3, [pc, #24] @ (8000b30 ) + 8000b18: 0011 movs r1, r2 + 8000b1a: 0018 movs r0, r3 + 8000b1c: f002 ffc0 bl 8003aa0 + 8000b20: 1e03 subs r3, r0, #0 + 8000b22: d001 beq.n 8000b28 { Error_Handler(); - 8000748: f000 f9b3 bl 8000ab2 + 8000b24: f000 fac0 bl 80010a8 } /* USER CODE BEGIN TIM3_Init 2 */ /* USER CODE END TIM3_Init 2 */ } - 800074c: 46c0 nop @ (mov r8, r8) - 800074e: 46bd mov sp, r7 - 8000750: b00d add sp, #52 @ 0x34 - 8000752: bd90 pop {r4, r7, pc} - 8000754: 20000074 .word 0x20000074 - 8000758: 40000400 .word 0x40000400 - 800075c: 0000ffff .word 0x0000ffff + 8000b28: 46c0 nop @ (mov r8, r8) + 8000b2a: 46bd mov sp, r7 + 8000b2c: b00d add sp, #52 @ 0x34 + 8000b2e: bd90 pop {r4, r7, pc} + 8000b30: 2000008c .word 0x2000008c + 8000b34: 40000400 .word 0x40000400 + 8000b38: 0000ffff .word 0x0000ffff -08000760 : +08000b3c : + * @brief TIM14 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM14_Init(void) +{ + 8000b3c: b580 push {r7, lr} + 8000b3e: af00 add r7, sp, #0 + /* USER CODE END TIM14_Init 0 */ + + /* USER CODE BEGIN TIM14_Init 1 */ + + /* USER CODE END TIM14_Init 1 */ + htim14.Instance = TIM14; + 8000b40: 4b0e ldr r3, [pc, #56] @ (8000b7c ) + 8000b42: 4a0f ldr r2, [pc, #60] @ (8000b80 ) + 8000b44: 601a str r2, [r3, #0] + htim14.Init.Prescaler = 480-1; + 8000b46: 4b0d ldr r3, [pc, #52] @ (8000b7c ) + 8000b48: 22e0 movs r2, #224 @ 0xe0 + 8000b4a: 32ff adds r2, #255 @ 0xff + 8000b4c: 605a str r2, [r3, #4] + htim14.Init.CounterMode = TIM_COUNTERMODE_UP; + 8000b4e: 4b0b ldr r3, [pc, #44] @ (8000b7c ) + 8000b50: 2200 movs r2, #0 + 8000b52: 609a str r2, [r3, #8] + htim14.Init.Period = 50; + 8000b54: 4b09 ldr r3, [pc, #36] @ (8000b7c ) + 8000b56: 2232 movs r2, #50 @ 0x32 + 8000b58: 60da str r2, [r3, #12] + htim14.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 8000b5a: 4b08 ldr r3, [pc, #32] @ (8000b7c ) + 8000b5c: 2200 movs r2, #0 + 8000b5e: 611a str r2, [r3, #16] + htim14.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + 8000b60: 4b06 ldr r3, [pc, #24] @ (8000b7c ) + 8000b62: 2200 movs r2, #0 + 8000b64: 619a str r2, [r3, #24] + if (HAL_TIM_Base_Init(&htim14) != HAL_OK) + 8000b66: 4b05 ldr r3, [pc, #20] @ (8000b7c ) + 8000b68: 0018 movs r0, r3 + 8000b6a: f001 ff87 bl 8002a7c + 8000b6e: 1e03 subs r3, r0, #0 + 8000b70: d001 beq.n 8000b76 + { + Error_Handler(); + 8000b72: f000 fa99 bl 80010a8 + } + /* USER CODE BEGIN TIM14_Init 2 */ + + /* USER CODE END TIM14_Init 2 */ + +} + 8000b76: 46c0 nop @ (mov r8, r8) + 8000b78: 46bd mov sp, r7 + 8000b7a: bd80 pop {r7, pc} + 8000b7c: 200000d8 .word 0x200000d8 + 8000b80: 40002000 .word 0x40002000 + +08000b84 : * @brief TIM16 Initialization Function * @param None * @retval None */ static void MX_TIM16_Init(void) { - 8000760: b580 push {r7, lr} - 8000762: af00 add r7, sp, #0 + 8000b84: b580 push {r7, lr} + 8000b86: af00 add r7, sp, #0 /* USER CODE END TIM16_Init 0 */ /* USER CODE BEGIN TIM16_Init 1 */ /* USER CODE END TIM16_Init 1 */ htim16.Instance = TIM16; - 8000764: 4b0f ldr r3, [pc, #60] @ (80007a4 ) - 8000766: 4a10 ldr r2, [pc, #64] @ (80007a8 ) - 8000768: 601a str r2, [r3, #0] + 8000b88: 4b0f ldr r3, [pc, #60] @ (8000bc8 ) + 8000b8a: 4a10 ldr r2, [pc, #64] @ (8000bcc ) + 8000b8c: 601a str r2, [r3, #0] htim16.Init.Prescaler = 48000-1; - 800076a: 4b0e ldr r3, [pc, #56] @ (80007a4 ) - 800076c: 4a0f ldr r2, [pc, #60] @ (80007ac ) - 800076e: 605a str r2, [r3, #4] + 8000b8e: 4b0e ldr r3, [pc, #56] @ (8000bc8 ) + 8000b90: 4a0f ldr r2, [pc, #60] @ (8000bd0 ) + 8000b92: 605a str r2, [r3, #4] htim16.Init.CounterMode = TIM_COUNTERMODE_UP; - 8000770: 4b0c ldr r3, [pc, #48] @ (80007a4 ) - 8000772: 2200 movs r2, #0 - 8000774: 609a str r2, [r3, #8] + 8000b94: 4b0c ldr r3, [pc, #48] @ (8000bc8 ) + 8000b96: 2200 movs r2, #0 + 8000b98: 609a str r2, [r3, #8] htim16.Init.Period = 65535; - 8000776: 4b0b ldr r3, [pc, #44] @ (80007a4 ) - 8000778: 4a0d ldr r2, [pc, #52] @ (80007b0 ) - 800077a: 60da str r2, [r3, #12] + 8000b9a: 4b0b ldr r3, [pc, #44] @ (8000bc8 ) + 8000b9c: 4a0d ldr r2, [pc, #52] @ (8000bd4 ) + 8000b9e: 60da str r2, [r3, #12] htim16.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; - 800077c: 4b09 ldr r3, [pc, #36] @ (80007a4 ) - 800077e: 2200 movs r2, #0 - 8000780: 611a str r2, [r3, #16] + 8000ba0: 4b09 ldr r3, [pc, #36] @ (8000bc8 ) + 8000ba2: 2200 movs r2, #0 + 8000ba4: 611a str r2, [r3, #16] htim16.Init.RepetitionCounter = 0; - 8000782: 4b08 ldr r3, [pc, #32] @ (80007a4 ) - 8000784: 2200 movs r2, #0 - 8000786: 615a str r2, [r3, #20] + 8000ba6: 4b08 ldr r3, [pc, #32] @ (8000bc8 ) + 8000ba8: 2200 movs r2, #0 + 8000baa: 615a str r2, [r3, #20] htim16.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; - 8000788: 4b06 ldr r3, [pc, #24] @ (80007a4 ) - 800078a: 2200 movs r2, #0 - 800078c: 619a str r2, [r3, #24] + 8000bac: 4b06 ldr r3, [pc, #24] @ (8000bc8 ) + 8000bae: 2200 movs r2, #0 + 8000bb0: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim16) != HAL_OK) - 800078e: 4b05 ldr r3, [pc, #20] @ (80007a4 ) - 8000790: 0018 movs r0, r3 - 8000792: f001 fd11 bl 80021b8 - 8000796: 1e03 subs r3, r0, #0 - 8000798: d001 beq.n 800079e + 8000bb2: 4b05 ldr r3, [pc, #20] @ (8000bc8 ) + 8000bb4: 0018 movs r0, r3 + 8000bb6: f001 ff61 bl 8002a7c + 8000bba: 1e03 subs r3, r0, #0 + 8000bbc: d001 beq.n 8000bc2 { Error_Handler(); - 800079a: f000 f98a bl 8000ab2 + 8000bbe: f000 fa73 bl 80010a8 } /* USER CODE BEGIN TIM16_Init 2 */ /* USER CODE END TIM16_Init 2 */ } - 800079e: 46c0 nop @ (mov r8, r8) - 80007a0: 46bd mov sp, r7 - 80007a2: bd80 pop {r7, pc} - 80007a4: 200000c0 .word 0x200000c0 - 80007a8: 40014400 .word 0x40014400 - 80007ac: 0000bb7f .word 0x0000bb7f - 80007b0: 0000ffff .word 0x0000ffff + 8000bc2: 46c0 nop @ (mov r8, r8) + 8000bc4: 46bd mov sp, r7 + 8000bc6: bd80 pop {r7, pc} + 8000bc8: 20000124 .word 0x20000124 + 8000bcc: 40014400 .word 0x40014400 + 8000bd0: 0000bb7f .word 0x0000bb7f + 8000bd4: 0000ffff .word 0x0000ffff -080007b4 : +08000bd8 : * @brief TIM17 Initialization Function * @param None * @retval None */ static void MX_TIM17_Init(void) { - 80007b4: b580 push {r7, lr} - 80007b6: af00 add r7, sp, #0 + 8000bd8: b580 push {r7, lr} + 8000bda: af00 add r7, sp, #0 /* USER CODE END TIM17_Init 0 */ /* USER CODE BEGIN TIM17_Init 1 */ /* USER CODE END TIM17_Init 1 */ htim17.Instance = TIM17; - 80007b8: 4b0f ldr r3, [pc, #60] @ (80007f8 ) - 80007ba: 4a10 ldr r2, [pc, #64] @ (80007fc ) - 80007bc: 601a str r2, [r3, #0] + 8000bdc: 4b0f ldr r3, [pc, #60] @ (8000c1c ) + 8000bde: 4a10 ldr r2, [pc, #64] @ (8000c20 ) + 8000be0: 601a str r2, [r3, #0] htim17.Init.Prescaler = 48000-1; - 80007be: 4b0e ldr r3, [pc, #56] @ (80007f8 ) - 80007c0: 4a0f ldr r2, [pc, #60] @ (8000800 ) - 80007c2: 605a str r2, [r3, #4] + 8000be2: 4b0e ldr r3, [pc, #56] @ (8000c1c ) + 8000be4: 4a0f ldr r2, [pc, #60] @ (8000c24 ) + 8000be6: 605a str r2, [r3, #4] htim17.Init.CounterMode = TIM_COUNTERMODE_UP; - 80007c4: 4b0c ldr r3, [pc, #48] @ (80007f8 ) - 80007c6: 2200 movs r2, #0 - 80007c8: 609a str r2, [r3, #8] + 8000be8: 4b0c ldr r3, [pc, #48] @ (8000c1c ) + 8000bea: 2200 movs r2, #0 + 8000bec: 609a str r2, [r3, #8] htim17.Init.Period = 65535; - 80007ca: 4b0b ldr r3, [pc, #44] @ (80007f8 ) - 80007cc: 4a0d ldr r2, [pc, #52] @ (8000804 ) - 80007ce: 60da str r2, [r3, #12] + 8000bee: 4b0b ldr r3, [pc, #44] @ (8000c1c ) + 8000bf0: 4a0d ldr r2, [pc, #52] @ (8000c28 ) + 8000bf2: 60da str r2, [r3, #12] htim17.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; - 80007d0: 4b09 ldr r3, [pc, #36] @ (80007f8 ) - 80007d2: 2200 movs r2, #0 - 80007d4: 611a str r2, [r3, #16] + 8000bf4: 4b09 ldr r3, [pc, #36] @ (8000c1c ) + 8000bf6: 2200 movs r2, #0 + 8000bf8: 611a str r2, [r3, #16] htim17.Init.RepetitionCounter = 0; - 80007d6: 4b08 ldr r3, [pc, #32] @ (80007f8 ) - 80007d8: 2200 movs r2, #0 - 80007da: 615a str r2, [r3, #20] + 8000bfa: 4b08 ldr r3, [pc, #32] @ (8000c1c ) + 8000bfc: 2200 movs r2, #0 + 8000bfe: 615a str r2, [r3, #20] htim17.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; - 80007dc: 4b06 ldr r3, [pc, #24] @ (80007f8 ) - 80007de: 2200 movs r2, #0 - 80007e0: 619a str r2, [r3, #24] + 8000c00: 4b06 ldr r3, [pc, #24] @ (8000c1c ) + 8000c02: 2200 movs r2, #0 + 8000c04: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim17) != HAL_OK) - 80007e2: 4b05 ldr r3, [pc, #20] @ (80007f8 ) - 80007e4: 0018 movs r0, r3 - 80007e6: f001 fce7 bl 80021b8 - 80007ea: 1e03 subs r3, r0, #0 - 80007ec: d001 beq.n 80007f2 + 8000c06: 4b05 ldr r3, [pc, #20] @ (8000c1c ) + 8000c08: 0018 movs r0, r3 + 8000c0a: f001 ff37 bl 8002a7c + 8000c0e: 1e03 subs r3, r0, #0 + 8000c10: d001 beq.n 8000c16 { Error_Handler(); - 80007ee: f000 f960 bl 8000ab2 + 8000c12: f000 fa49 bl 80010a8 } /* USER CODE BEGIN TIM17_Init 2 */ /* USER CODE END TIM17_Init 2 */ } - 80007f2: 46c0 nop @ (mov r8, r8) - 80007f4: 46bd mov sp, r7 - 80007f6: bd80 pop {r7, pc} - 80007f8: 2000010c .word 0x2000010c - 80007fc: 40014800 .word 0x40014800 - 8000800: 0000bb7f .word 0x0000bb7f - 8000804: 0000ffff .word 0x0000ffff + 8000c16: 46c0 nop @ (mov r8, r8) + 8000c18: 46bd mov sp, r7 + 8000c1a: bd80 pop {r7, pc} + 8000c1c: 20000170 .word 0x20000170 + 8000c20: 40014800 .word 0x40014800 + 8000c24: 0000bb7f .word 0x0000bb7f + 8000c28: 0000ffff .word 0x0000ffff -08000808 : +08000c2c : * @brief USART1 Initialization Function * @param None * @retval None */ static void MX_USART1_UART_Init(void) { - 8000808: b580 push {r7, lr} - 800080a: af00 add r7, sp, #0 + 8000c2c: b580 push {r7, lr} + 8000c2e: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; - 800080c: 4b23 ldr r3, [pc, #140] @ (800089c ) - 800080e: 4a24 ldr r2, [pc, #144] @ (80008a0 ) - 8000810: 601a str r2, [r3, #0] + 8000c30: 4b23 ldr r3, [pc, #140] @ (8000cc0 ) + 8000c32: 4a24 ldr r2, [pc, #144] @ (8000cc4 ) + 8000c34: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; - 8000812: 4b22 ldr r3, [pc, #136] @ (800089c ) - 8000814: 22e1 movs r2, #225 @ 0xe1 - 8000816: 0252 lsls r2, r2, #9 - 8000818: 605a str r2, [r3, #4] + 8000c36: 4b22 ldr r3, [pc, #136] @ (8000cc0 ) + 8000c38: 22e1 movs r2, #225 @ 0xe1 + 8000c3a: 0252 lsls r2, r2, #9 + 8000c3c: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; - 800081a: 4b20 ldr r3, [pc, #128] @ (800089c ) - 800081c: 2200 movs r2, #0 - 800081e: 609a str r2, [r3, #8] + 8000c3e: 4b20 ldr r3, [pc, #128] @ (8000cc0 ) + 8000c40: 2200 movs r2, #0 + 8000c42: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; - 8000820: 4b1e ldr r3, [pc, #120] @ (800089c ) - 8000822: 2200 movs r2, #0 - 8000824: 60da str r2, [r3, #12] + 8000c44: 4b1e ldr r3, [pc, #120] @ (8000cc0 ) + 8000c46: 2200 movs r2, #0 + 8000c48: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; - 8000826: 4b1d ldr r3, [pc, #116] @ (800089c ) - 8000828: 2200 movs r2, #0 - 800082a: 611a str r2, [r3, #16] + 8000c4a: 4b1d ldr r3, [pc, #116] @ (8000cc0 ) + 8000c4c: 2200 movs r2, #0 + 8000c4e: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; - 800082c: 4b1b ldr r3, [pc, #108] @ (800089c ) - 800082e: 220c movs r2, #12 - 8000830: 615a str r2, [r3, #20] + 8000c50: 4b1b ldr r3, [pc, #108] @ (8000cc0 ) + 8000c52: 220c movs r2, #12 + 8000c54: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; - 8000832: 4b1a ldr r3, [pc, #104] @ (800089c ) - 8000834: 2200 movs r2, #0 - 8000836: 619a str r2, [r3, #24] + 8000c56: 4b1a ldr r3, [pc, #104] @ (8000cc0 ) + 8000c58: 2200 movs r2, #0 + 8000c5a: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; - 8000838: 4b18 ldr r3, [pc, #96] @ (800089c ) - 800083a: 2200 movs r2, #0 - 800083c: 61da str r2, [r3, #28] + 8000c5c: 4b18 ldr r3, [pc, #96] @ (8000cc0 ) + 8000c5e: 2200 movs r2, #0 + 8000c60: 61da str r2, [r3, #28] huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; - 800083e: 4b17 ldr r3, [pc, #92] @ (800089c ) - 8000840: 2200 movs r2, #0 - 8000842: 621a str r2, [r3, #32] + 8000c62: 4b17 ldr r3, [pc, #92] @ (8000cc0 ) + 8000c64: 2200 movs r2, #0 + 8000c66: 621a str r2, [r3, #32] huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; - 8000844: 4b15 ldr r3, [pc, #84] @ (800089c ) - 8000846: 2200 movs r2, #0 - 8000848: 625a str r2, [r3, #36] @ 0x24 + 8000c68: 4b15 ldr r3, [pc, #84] @ (8000cc0 ) + 8000c6a: 2200 movs r2, #0 + 8000c6c: 625a str r2, [r3, #36] @ 0x24 huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; - 800084a: 4b14 ldr r3, [pc, #80] @ (800089c ) - 800084c: 2200 movs r2, #0 - 800084e: 629a str r2, [r3, #40] @ 0x28 + 8000c6e: 4b14 ldr r3, [pc, #80] @ (8000cc0 ) + 8000c70: 2200 movs r2, #0 + 8000c72: 629a str r2, [r3, #40] @ 0x28 if (HAL_UART_Init(&huart1) != HAL_OK) - 8000850: 4b12 ldr r3, [pc, #72] @ (800089c ) - 8000852: 0018 movs r0, r3 - 8000854: f002 fdde bl 8003414 - 8000858: 1e03 subs r3, r0, #0 - 800085a: d001 beq.n 8000860 + 8000c74: 4b12 ldr r3, [pc, #72] @ (8000cc0 ) + 8000c76: 0018 movs r0, r3 + 8000c78: f003 f82e bl 8003cd8 + 8000c7c: 1e03 subs r3, r0, #0 + 8000c7e: d001 beq.n 8000c84 { Error_Handler(); - 800085c: f000 f929 bl 8000ab2 + 8000c80: f000 fa12 bl 80010a8 } if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) - 8000860: 4b0e ldr r3, [pc, #56] @ (800089c ) - 8000862: 2100 movs r1, #0 - 8000864: 0018 movs r0, r3 - 8000866: f003 fa89 bl 8003d7c - 800086a: 1e03 subs r3, r0, #0 - 800086c: d001 beq.n 8000872 + 8000c84: 4b0e ldr r3, [pc, #56] @ (8000cc0 ) + 8000c86: 2100 movs r1, #0 + 8000c88: 0018 movs r0, r3 + 8000c8a: f003 ff0d bl 8004aa8 + 8000c8e: 1e03 subs r3, r0, #0 + 8000c90: d001 beq.n 8000c96 { Error_Handler(); - 800086e: f000 f920 bl 8000ab2 + 8000c92: f000 fa09 bl 80010a8 } if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) - 8000872: 4b0a ldr r3, [pc, #40] @ (800089c ) - 8000874: 2100 movs r1, #0 - 8000876: 0018 movs r0, r3 - 8000878: f003 fac0 bl 8003dfc - 800087c: 1e03 subs r3, r0, #0 - 800087e: d001 beq.n 8000884 + 8000c96: 4b0a ldr r3, [pc, #40] @ (8000cc0 ) + 8000c98: 2100 movs r1, #0 + 8000c9a: 0018 movs r0, r3 + 8000c9c: f003 ff44 bl 8004b28 + 8000ca0: 1e03 subs r3, r0, #0 + 8000ca2: d001 beq.n 8000ca8 { Error_Handler(); - 8000880: f000 f917 bl 8000ab2 + 8000ca4: f000 fa00 bl 80010a8 } if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK) - 8000884: 4b05 ldr r3, [pc, #20] @ (800089c ) - 8000886: 0018 movs r0, r3 - 8000888: f003 fa3e bl 8003d08 - 800088c: 1e03 subs r3, r0, #0 - 800088e: d001 beq.n 8000894 + 8000ca8: 4b05 ldr r3, [pc, #20] @ (8000cc0 ) + 8000caa: 0018 movs r0, r3 + 8000cac: f003 fec2 bl 8004a34 + 8000cb0: 1e03 subs r3, r0, #0 + 8000cb2: d001 beq.n 8000cb8 { Error_Handler(); - 8000890: f000 f90f bl 8000ab2 + 8000cb4: f000 f9f8 bl 80010a8 } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } - 8000894: 46c0 nop @ (mov r8, r8) - 8000896: 46bd mov sp, r7 - 8000898: bd80 pop {r7, pc} - 800089a: 46c0 nop @ (mov r8, r8) - 800089c: 200001b4 .word 0x200001b4 - 80008a0: 40013800 .word 0x40013800 + 8000cb8: 46c0 nop @ (mov r8, r8) + 8000cba: 46bd mov sp, r7 + 8000cbc: bd80 pop {r7, pc} + 8000cbe: 46c0 nop @ (mov r8, r8) + 8000cc0: 200001bc .word 0x200001bc + 8000cc4: 40013800 .word 0x40013800 -080008a4 : +08000cc8 : * @brief USART2 Initialization Function * @param None * @retval None */ static void MX_USART2_UART_Init(void) { - 80008a4: b580 push {r7, lr} - 80008a6: af00 add r7, sp, #0 + 8000cc8: b580 push {r7, lr} + 8000cca: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; - 80008a8: 4b24 ldr r3, [pc, #144] @ (800093c ) - 80008aa: 4a25 ldr r2, [pc, #148] @ (8000940 ) - 80008ac: 601a str r2, [r3, #0] - huart2.Init.BaudRate = 115200; - 80008ae: 4b23 ldr r3, [pc, #140] @ (800093c ) - 80008b0: 22e1 movs r2, #225 @ 0xe1 - 80008b2: 0252 lsls r2, r2, #9 - 80008b4: 605a str r2, [r3, #4] + 8000ccc: 4b26 ldr r3, [pc, #152] @ (8000d68 ) + 8000cce: 4a27 ldr r2, [pc, #156] @ (8000d6c ) + 8000cd0: 601a str r2, [r3, #0] + huart2.Init.BaudRate = 57600; + 8000cd2: 4b25 ldr r3, [pc, #148] @ (8000d68 ) + 8000cd4: 22e1 movs r2, #225 @ 0xe1 + 8000cd6: 0212 lsls r2, r2, #8 + 8000cd8: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; - 80008b6: 4b21 ldr r3, [pc, #132] @ (800093c ) - 80008b8: 2200 movs r2, #0 - 80008ba: 609a str r2, [r3, #8] + 8000cda: 4b23 ldr r3, [pc, #140] @ (8000d68 ) + 8000cdc: 2200 movs r2, #0 + 8000cde: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; - 80008bc: 4b1f ldr r3, [pc, #124] @ (800093c ) - 80008be: 2200 movs r2, #0 - 80008c0: 60da str r2, [r3, #12] + 8000ce0: 4b21 ldr r3, [pc, #132] @ (8000d68 ) + 8000ce2: 2200 movs r2, #0 + 8000ce4: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; - 80008c2: 4b1e ldr r3, [pc, #120] @ (800093c ) - 80008c4: 2200 movs r2, #0 - 80008c6: 611a str r2, [r3, #16] + 8000ce6: 4b20 ldr r3, [pc, #128] @ (8000d68 ) + 8000ce8: 2200 movs r2, #0 + 8000cea: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; - 80008c8: 4b1c ldr r3, [pc, #112] @ (800093c ) - 80008ca: 220c movs r2, #12 - 80008cc: 615a str r2, [r3, #20] + 8000cec: 4b1e ldr r3, [pc, #120] @ (8000d68 ) + 8000cee: 220c movs r2, #12 + 8000cf0: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; - 80008ce: 4b1b ldr r3, [pc, #108] @ (800093c ) - 80008d0: 2200 movs r2, #0 - 80008d2: 619a str r2, [r3, #24] + 8000cf2: 4b1d ldr r3, [pc, #116] @ (8000d68 ) + 8000cf4: 2200 movs r2, #0 + 8000cf6: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; - 80008d4: 4b19 ldr r3, [pc, #100] @ (800093c ) - 80008d6: 2200 movs r2, #0 - 80008d8: 61da str r2, [r3, #28] + 8000cf8: 4b1b ldr r3, [pc, #108] @ (8000d68 ) + 8000cfa: 2200 movs r2, #0 + 8000cfc: 61da str r2, [r3, #28] huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; - 80008da: 4b18 ldr r3, [pc, #96] @ (800093c ) - 80008dc: 2200 movs r2, #0 - 80008de: 621a str r2, [r3, #32] + 8000cfe: 4b1a ldr r3, [pc, #104] @ (8000d68 ) + 8000d00: 2200 movs r2, #0 + 8000d02: 621a str r2, [r3, #32] huart2.Init.ClockPrescaler = UART_PRESCALER_DIV1; - 80008e0: 4b16 ldr r3, [pc, #88] @ (800093c ) - 80008e2: 2200 movs r2, #0 - 80008e4: 625a str r2, [r3, #36] @ 0x24 + 8000d04: 4b18 ldr r3, [pc, #96] @ (8000d68 ) + 8000d06: 2200 movs r2, #0 + 8000d08: 625a str r2, [r3, #36] @ 0x24 huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; - 80008e6: 4b15 ldr r3, [pc, #84] @ (800093c ) - 80008e8: 2200 movs r2, #0 - 80008ea: 629a str r2, [r3, #40] @ 0x28 + 8000d0a: 4b17 ldr r3, [pc, #92] @ (8000d68 ) + 8000d0c: 2200 movs r2, #0 + 8000d0e: 629a str r2, [r3, #40] @ 0x28 if (HAL_RS485Ex_Init(&huart2, UART_DE_POLARITY_HIGH, 0, 0) != HAL_OK) - 80008ec: 4813 ldr r0, [pc, #76] @ (800093c ) - 80008ee: 2300 movs r3, #0 - 80008f0: 2200 movs r2, #0 - 80008f2: 2100 movs r1, #0 - 80008f4: f003 f996 bl 8003c24 - 80008f8: 1e03 subs r3, r0, #0 - 80008fa: d001 beq.n 8000900 + 8000d10: 4815 ldr r0, [pc, #84] @ (8000d68 ) + 8000d12: 2300 movs r3, #0 + 8000d14: 2200 movs r2, #0 + 8000d16: 2100 movs r1, #0 + 8000d18: f003 fe1a bl 8004950 + 8000d1c: 1e03 subs r3, r0, #0 + 8000d1e: d001 beq.n 8000d24 { Error_Handler(); - 80008fc: f000 f8d9 bl 8000ab2 + 8000d20: f000 f9c2 bl 80010a8 } - if (HAL_UARTEx_SetTxFifoThreshold(&huart2, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) - 8000900: 4b0e ldr r3, [pc, #56] @ (800093c ) - 8000902: 2100 movs r1, #0 - 8000904: 0018 movs r0, r3 - 8000906: f003 fa39 bl 8003d7c - 800090a: 1e03 subs r3, r0, #0 - 800090c: d001 beq.n 8000912 + if (HAL_UARTEx_SetTxFifoThreshold(&huart2, UART_TXFIFO_THRESHOLD_1_2) != HAL_OK) + 8000d24: 2380 movs r3, #128 @ 0x80 + 8000d26: 05da lsls r2, r3, #23 + 8000d28: 4b0f ldr r3, [pc, #60] @ (8000d68 ) + 8000d2a: 0011 movs r1, r2 + 8000d2c: 0018 movs r0, r3 + 8000d2e: f003 febb bl 8004aa8 + 8000d32: 1e03 subs r3, r0, #0 + 8000d34: d001 beq.n 8000d3a { Error_Handler(); - 800090e: f000 f8d0 bl 8000ab2 + 8000d36: f000 f9b7 bl 80010a8 } - if (HAL_UARTEx_SetRxFifoThreshold(&huart2, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) - 8000912: 4b0a ldr r3, [pc, #40] @ (800093c ) - 8000914: 2100 movs r1, #0 - 8000916: 0018 movs r0, r3 - 8000918: f003 fa70 bl 8003dfc - 800091c: 1e03 subs r3, r0, #0 - 800091e: d001 beq.n 8000924 + if (HAL_UARTEx_SetRxFifoThreshold(&huart2, UART_RXFIFO_THRESHOLD_1_2) != HAL_OK) + 8000d3a: 2380 movs r3, #128 @ 0x80 + 8000d3c: 04da lsls r2, r3, #19 + 8000d3e: 4b0a ldr r3, [pc, #40] @ (8000d68 ) + 8000d40: 0011 movs r1, r2 + 8000d42: 0018 movs r0, r3 + 8000d44: f003 fef0 bl 8004b28 + 8000d48: 1e03 subs r3, r0, #0 + 8000d4a: d001 beq.n 8000d50 { Error_Handler(); - 8000920: f000 f8c7 bl 8000ab2 + 8000d4c: f000 f9ac bl 80010a8 } if (HAL_UARTEx_DisableFifoMode(&huart2) != HAL_OK) - 8000924: 4b05 ldr r3, [pc, #20] @ (800093c ) - 8000926: 0018 movs r0, r3 - 8000928: f003 f9ee bl 8003d08 - 800092c: 1e03 subs r3, r0, #0 - 800092e: d001 beq.n 8000934 + 8000d50: 4b05 ldr r3, [pc, #20] @ (8000d68 ) + 8000d52: 0018 movs r0, r3 + 8000d54: f003 fe6e bl 8004a34 + 8000d58: 1e03 subs r3, r0, #0 + 8000d5a: d001 beq.n 8000d60 { Error_Handler(); - 8000930: f000 f8bf bl 8000ab2 + 8000d5c: f000 f9a4 bl 80010a8 } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } - 8000934: 46c0 nop @ (mov r8, r8) - 8000936: 46bd mov sp, r7 - 8000938: bd80 pop {r7, pc} - 800093a: 46c0 nop @ (mov r8, r8) - 800093c: 20000248 .word 0x20000248 - 8000940: 40004400 .word 0x40004400 + 8000d60: 46c0 nop @ (mov r8, r8) + 8000d62: 46bd mov sp, r7 + 8000d64: bd80 pop {r7, pc} + 8000d66: 46c0 nop @ (mov r8, r8) + 8000d68: 20000250 .word 0x20000250 + 8000d6c: 40004400 .word 0x40004400 -08000944 : +08000d70 : /** * Enable DMA controller clock */ static void MX_DMA_Init(void) { - 8000944: b580 push {r7, lr} - 8000946: b082 sub sp, #8 - 8000948: af00 add r7, sp, #0 + 8000d70: b580 push {r7, lr} + 8000d72: b082 sub sp, #8 + 8000d74: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); - 800094a: 4b0c ldr r3, [pc, #48] @ (800097c ) - 800094c: 6b9a ldr r2, [r3, #56] @ 0x38 - 800094e: 4b0b ldr r3, [pc, #44] @ (800097c ) - 8000950: 2101 movs r1, #1 - 8000952: 430a orrs r2, r1 - 8000954: 639a str r2, [r3, #56] @ 0x38 - 8000956: 4b09 ldr r3, [pc, #36] @ (800097c ) - 8000958: 6b9b ldr r3, [r3, #56] @ 0x38 - 800095a: 2201 movs r2, #1 - 800095c: 4013 ands r3, r2 - 800095e: 607b str r3, [r7, #4] - 8000960: 687b ldr r3, [r7, #4] + 8000d76: 4b10 ldr r3, [pc, #64] @ (8000db8 ) + 8000d78: 6b9a ldr r2, [r3, #56] @ 0x38 + 8000d7a: 4b0f ldr r3, [pc, #60] @ (8000db8 ) + 8000d7c: 2101 movs r1, #1 + 8000d7e: 430a orrs r2, r1 + 8000d80: 639a str r2, [r3, #56] @ 0x38 + 8000d82: 4b0d ldr r3, [pc, #52] @ (8000db8 ) + 8000d84: 6b9b ldr r3, [r3, #56] @ 0x38 + 8000d86: 2201 movs r2, #1 + 8000d88: 4013 ands r3, r2 + 8000d8a: 607b str r3, [r7, #4] + 8000d8c: 687b ldr r3, [r7, #4] /* DMA interrupt init */ /* DMA1_Channel1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0); - 8000962: 2200 movs r2, #0 - 8000964: 2100 movs r1, #0 - 8000966: 2009 movs r0, #9 - 8000968: f000 fc3a bl 80011e0 + 8000d8e: 2200 movs r2, #0 + 8000d90: 2100 movs r1, #0 + 8000d92: 2009 movs r0, #9 + 8000d94: f000 fda2 bl 80018dc HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); - 800096c: 2009 movs r0, #9 - 800096e: f000 fc4c bl 800120a + 8000d98: 2009 movs r0, #9 + 8000d9a: f000 fdb4 bl 8001906 + /* DMA1_Channel2_3_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Channel2_3_IRQn, 0, 0); + 8000d9e: 2200 movs r2, #0 + 8000da0: 2100 movs r1, #0 + 8000da2: 200a movs r0, #10 + 8000da4: f000 fd9a bl 80018dc + HAL_NVIC_EnableIRQ(DMA1_Channel2_3_IRQn); + 8000da8: 200a movs r0, #10 + 8000daa: f000 fdac bl 8001906 } - 8000972: 46c0 nop @ (mov r8, r8) - 8000974: 46bd mov sp, r7 - 8000976: b002 add sp, #8 - 8000978: bd80 pop {r7, pc} - 800097a: 46c0 nop @ (mov r8, r8) - 800097c: 40021000 .word 0x40021000 + 8000dae: 46c0 nop @ (mov r8, r8) + 8000db0: 46bd mov sp, r7 + 8000db2: b002 add sp, #8 + 8000db4: bd80 pop {r7, pc} + 8000db6: 46c0 nop @ (mov r8, r8) + 8000db8: 40021000 .word 0x40021000 -08000980 : +08000dbc : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { - 8000980: b590 push {r4, r7, lr} - 8000982: b08b sub sp, #44 @ 0x2c - 8000984: af00 add r7, sp, #0 + 8000dbc: b590 push {r4, r7, lr} + 8000dbe: b08b sub sp, #44 @ 0x2c + 8000dc0: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; - 8000986: 2414 movs r4, #20 - 8000988: 193b adds r3, r7, r4 - 800098a: 0018 movs r0, r3 - 800098c: 2314 movs r3, #20 - 800098e: 001a movs r2, r3 - 8000990: 2100 movs r1, #0 - 8000992: f003 fad3 bl 8003f3c + 8000dc2: 2414 movs r4, #20 + 8000dc4: 193b adds r3, r7, r4 + 8000dc6: 0018 movs r0, r3 + 8000dc8: 2314 movs r3, #20 + 8000dca: 001a movs r2, r3 + 8000dcc: 2100 movs r1, #0 + 8000dce: f003 ffb3 bl 8004d38 /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOF_CLK_ENABLE(); - 8000996: 4b3f ldr r3, [pc, #252] @ (8000a94 ) - 8000998: 6b5a ldr r2, [r3, #52] @ 0x34 - 800099a: 4b3e ldr r3, [pc, #248] @ (8000a94 ) - 800099c: 2120 movs r1, #32 - 800099e: 430a orrs r2, r1 - 80009a0: 635a str r2, [r3, #52] @ 0x34 - 80009a2: 4b3c ldr r3, [pc, #240] @ (8000a94 ) - 80009a4: 6b5b ldr r3, [r3, #52] @ 0x34 - 80009a6: 2220 movs r2, #32 - 80009a8: 4013 ands r3, r2 - 80009aa: 613b str r3, [r7, #16] - 80009ac: 693b ldr r3, [r7, #16] + 8000dd2: 4b3f ldr r3, [pc, #252] @ (8000ed0 ) + 8000dd4: 6b5a ldr r2, [r3, #52] @ 0x34 + 8000dd6: 4b3e ldr r3, [pc, #248] @ (8000ed0 ) + 8000dd8: 2120 movs r1, #32 + 8000dda: 430a orrs r2, r1 + 8000ddc: 635a str r2, [r3, #52] @ 0x34 + 8000dde: 4b3c ldr r3, [pc, #240] @ (8000ed0 ) + 8000de0: 6b5b ldr r3, [r3, #52] @ 0x34 + 8000de2: 2220 movs r2, #32 + 8000de4: 4013 ands r3, r2 + 8000de6: 613b str r3, [r7, #16] + 8000de8: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); - 80009ae: 4b39 ldr r3, [pc, #228] @ (8000a94 ) - 80009b0: 6b5a ldr r2, [r3, #52] @ 0x34 - 80009b2: 4b38 ldr r3, [pc, #224] @ (8000a94 ) - 80009b4: 2101 movs r1, #1 - 80009b6: 430a orrs r2, r1 - 80009b8: 635a str r2, [r3, #52] @ 0x34 - 80009ba: 4b36 ldr r3, [pc, #216] @ (8000a94 ) - 80009bc: 6b5b ldr r3, [r3, #52] @ 0x34 - 80009be: 2201 movs r2, #1 - 80009c0: 4013 ands r3, r2 - 80009c2: 60fb str r3, [r7, #12] - 80009c4: 68fb ldr r3, [r7, #12] + 8000dea: 4b39 ldr r3, [pc, #228] @ (8000ed0 ) + 8000dec: 6b5a ldr r2, [r3, #52] @ 0x34 + 8000dee: 4b38 ldr r3, [pc, #224] @ (8000ed0 ) + 8000df0: 2101 movs r1, #1 + 8000df2: 430a orrs r2, r1 + 8000df4: 635a str r2, [r3, #52] @ 0x34 + 8000df6: 4b36 ldr r3, [pc, #216] @ (8000ed0 ) + 8000df8: 6b5b ldr r3, [r3, #52] @ 0x34 + 8000dfa: 2201 movs r2, #1 + 8000dfc: 4013 ands r3, r2 + 8000dfe: 60fb str r3, [r7, #12] + 8000e00: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOC_CLK_ENABLE(); - 80009c6: 4b33 ldr r3, [pc, #204] @ (8000a94 ) - 80009c8: 6b5a ldr r2, [r3, #52] @ 0x34 - 80009ca: 4b32 ldr r3, [pc, #200] @ (8000a94 ) - 80009cc: 2104 movs r1, #4 - 80009ce: 430a orrs r2, r1 - 80009d0: 635a str r2, [r3, #52] @ 0x34 - 80009d2: 4b30 ldr r3, [pc, #192] @ (8000a94 ) - 80009d4: 6b5b ldr r3, [r3, #52] @ 0x34 - 80009d6: 2204 movs r2, #4 - 80009d8: 4013 ands r3, r2 - 80009da: 60bb str r3, [r7, #8] - 80009dc: 68bb ldr r3, [r7, #8] + 8000e02: 4b33 ldr r3, [pc, #204] @ (8000ed0 ) + 8000e04: 6b5a ldr r2, [r3, #52] @ 0x34 + 8000e06: 4b32 ldr r3, [pc, #200] @ (8000ed0 ) + 8000e08: 2104 movs r1, #4 + 8000e0a: 430a orrs r2, r1 + 8000e0c: 635a str r2, [r3, #52] @ 0x34 + 8000e0e: 4b30 ldr r3, [pc, #192] @ (8000ed0 ) + 8000e10: 6b5b ldr r3, [r3, #52] @ 0x34 + 8000e12: 2204 movs r2, #4 + 8000e14: 4013 ands r3, r2 + 8000e16: 60bb str r3, [r7, #8] + 8000e18: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); - 80009de: 4b2d ldr r3, [pc, #180] @ (8000a94 ) - 80009e0: 6b5a ldr r2, [r3, #52] @ 0x34 - 80009e2: 4b2c ldr r3, [pc, #176] @ (8000a94 ) - 80009e4: 2102 movs r1, #2 - 80009e6: 430a orrs r2, r1 - 80009e8: 635a str r2, [r3, #52] @ 0x34 - 80009ea: 4b2a ldr r3, [pc, #168] @ (8000a94 ) - 80009ec: 6b5b ldr r3, [r3, #52] @ 0x34 - 80009ee: 2202 movs r2, #2 - 80009f0: 4013 ands r3, r2 - 80009f2: 607b str r3, [r7, #4] - 80009f4: 687b ldr r3, [r7, #4] + 8000e1a: 4b2d ldr r3, [pc, #180] @ (8000ed0 ) + 8000e1c: 6b5a ldr r2, [r3, #52] @ 0x34 + 8000e1e: 4b2c ldr r3, [pc, #176] @ (8000ed0 ) + 8000e20: 2102 movs r1, #2 + 8000e22: 430a orrs r2, r1 + 8000e24: 635a str r2, [r3, #52] @ 0x34 + 8000e26: 4b2a ldr r3, [pc, #168] @ (8000ed0 ) + 8000e28: 6b5b ldr r3, [r3, #52] @ 0x34 + 8000e2a: 2202 movs r2, #2 + 8000e2c: 4013 ands r3, r2 + 8000e2e: 607b str r3, [r7, #4] + 8000e30: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, USART2_NRE_Pin|ONEWIRE_Pin, GPIO_PIN_RESET); - 80009f6: 4928 ldr r1, [pc, #160] @ (8000a98 ) - 80009f8: 23a0 movs r3, #160 @ 0xa0 - 80009fa: 05db lsls r3, r3, #23 - 80009fc: 2200 movs r2, #0 - 80009fe: 0018 movs r0, r3 - 8000a00: f000 ff1e bl 8001840 + 8000e32: 4928 ldr r1, [pc, #160] @ (8000ed4 ) + 8000e34: 23a0 movs r3, #160 @ 0xa0 + 8000e36: 05db lsls r3, r3, #23 + 8000e38: 2200 movs r2, #0 + 8000e3a: 0018 movs r0, r3 + 8000e3c: f001 f963 bl 8002106 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, LED_R_Pin|LED_B_Pin|LED_G_Pin, GPIO_PIN_RESET); - 8000a04: 4b25 ldr r3, [pc, #148] @ (8000a9c ) - 8000a06: 2200 movs r2, #0 - 8000a08: 2138 movs r1, #56 @ 0x38 - 8000a0a: 0018 movs r0, r3 - 8000a0c: f000 ff18 bl 8001840 + 8000e40: 4b25 ldr r3, [pc, #148] @ (8000ed8 ) + 8000e42: 2200 movs r2, #0 + 8000e44: 2138 movs r1, #56 @ 0x38 + 8000e46: 0018 movs r0, r3 + 8000e48: f001 f95d bl 8002106 /*Configure GPIO pins : USART2_NRE_Pin ONEWIRE_Pin */ GPIO_InitStruct.Pin = USART2_NRE_Pin|ONEWIRE_Pin; - 8000a10: 193b adds r3, r7, r4 - 8000a12: 4a21 ldr r2, [pc, #132] @ (8000a98 ) - 8000a14: 601a str r2, [r3, #0] + 8000e4c: 193b adds r3, r7, r4 + 8000e4e: 4a21 ldr r2, [pc, #132] @ (8000ed4 ) + 8000e50: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - 8000a16: 193b adds r3, r7, r4 - 8000a18: 2201 movs r2, #1 - 8000a1a: 605a str r2, [r3, #4] + 8000e52: 193b adds r3, r7, r4 + 8000e54: 2201 movs r2, #1 + 8000e56: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; - 8000a1c: 193b adds r3, r7, r4 - 8000a1e: 2200 movs r2, #0 - 8000a20: 609a str r2, [r3, #8] + 8000e58: 193b adds r3, r7, r4 + 8000e5a: 2200 movs r2, #0 + 8000e5c: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - 8000a22: 193b adds r3, r7, r4 - 8000a24: 2200 movs r2, #0 - 8000a26: 60da str r2, [r3, #12] + 8000e5e: 193b adds r3, r7, r4 + 8000e60: 2200 movs r2, #0 + 8000e62: 60da str r2, [r3, #12] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - 8000a28: 193a adds r2, r7, r4 - 8000a2a: 23a0 movs r3, #160 @ 0xa0 - 8000a2c: 05db lsls r3, r3, #23 - 8000a2e: 0011 movs r1, r2 - 8000a30: 0018 movs r0, r3 - 8000a32: f000 fd93 bl 800155c + 8000e64: 193a adds r2, r7, r4 + 8000e66: 23a0 movs r3, #160 @ 0xa0 + 8000e68: 05db lsls r3, r3, #23 + 8000e6a: 0011 movs r1, r2 + 8000e6c: 0018 movs r0, r3 + 8000e6e: f000 ffbb bl 8001de8 /*Configure GPIO pins : LED_R_Pin LED_B_Pin LED_G_Pin */ GPIO_InitStruct.Pin = LED_R_Pin|LED_B_Pin|LED_G_Pin; - 8000a36: 193b adds r3, r7, r4 - 8000a38: 2238 movs r2, #56 @ 0x38 - 8000a3a: 601a str r2, [r3, #0] + 8000e72: 193b adds r3, r7, r4 + 8000e74: 2238 movs r2, #56 @ 0x38 + 8000e76: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - 8000a3c: 193b adds r3, r7, r4 - 8000a3e: 2201 movs r2, #1 - 8000a40: 605a str r2, [r3, #4] + 8000e78: 193b adds r3, r7, r4 + 8000e7a: 2201 movs r2, #1 + 8000e7c: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; - 8000a42: 193b adds r3, r7, r4 - 8000a44: 2200 movs r2, #0 - 8000a46: 609a str r2, [r3, #8] + 8000e7e: 193b adds r3, r7, r4 + 8000e80: 2200 movs r2, #0 + 8000e82: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - 8000a48: 193b adds r3, r7, r4 - 8000a4a: 2200 movs r2, #0 - 8000a4c: 60da str r2, [r3, #12] + 8000e84: 193b adds r3, r7, r4 + 8000e86: 2200 movs r2, #0 + 8000e88: 60da str r2, [r3, #12] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - 8000a4e: 193b adds r3, r7, r4 - 8000a50: 4a12 ldr r2, [pc, #72] @ (8000a9c ) - 8000a52: 0019 movs r1, r3 - 8000a54: 0010 movs r0, r2 - 8000a56: f000 fd81 bl 800155c + 8000e8a: 193b adds r3, r7, r4 + 8000e8c: 4a12 ldr r2, [pc, #72] @ (8000ed8 ) + 8000e8e: 0019 movs r1, r3 + 8000e90: 0010 movs r0, r2 + 8000e92: f000 ffa9 bl 8001de8 /*Configure GPIO pins : SW2_Pin SW1_Pin */ GPIO_InitStruct.Pin = SW2_Pin|SW1_Pin; - 8000a5a: 0021 movs r1, r4 - 8000a5c: 187b adds r3, r7, r1 - 8000a5e: 22c0 movs r2, #192 @ 0xc0 - 8000a60: 0092 lsls r2, r2, #2 - 8000a62: 601a str r2, [r3, #0] + 8000e96: 0021 movs r1, r4 + 8000e98: 187b adds r3, r7, r1 + 8000e9a: 22c0 movs r2, #192 @ 0xc0 + 8000e9c: 0092 lsls r2, r2, #2 + 8000e9e: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; - 8000a64: 187b adds r3, r7, r1 - 8000a66: 4a0e ldr r2, [pc, #56] @ (8000aa0 ) - 8000a68: 605a str r2, [r3, #4] + 8000ea0: 187b adds r3, r7, r1 + 8000ea2: 4a0e ldr r2, [pc, #56] @ (8000edc ) + 8000ea4: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; - 8000a6a: 187b adds r3, r7, r1 - 8000a6c: 2200 movs r2, #0 - 8000a6e: 609a str r2, [r3, #8] + 8000ea6: 187b adds r3, r7, r1 + 8000ea8: 2200 movs r2, #0 + 8000eaa: 609a str r2, [r3, #8] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - 8000a70: 187b adds r3, r7, r1 - 8000a72: 4a0a ldr r2, [pc, #40] @ (8000a9c ) - 8000a74: 0019 movs r1, r3 - 8000a76: 0010 movs r0, r2 - 8000a78: f000 fd70 bl 800155c + 8000eac: 187b adds r3, r7, r1 + 8000eae: 4a0a ldr r2, [pc, #40] @ (8000ed8 ) + 8000eb0: 0019 movs r1, r3 + 8000eb2: 0010 movs r0, r2 + 8000eb4: f000 ff98 bl 8001de8 /* EXTI interrupt init*/ HAL_NVIC_SetPriority(EXTI4_15_IRQn, 0, 0); - 8000a7c: 2200 movs r2, #0 - 8000a7e: 2100 movs r1, #0 - 8000a80: 2007 movs r0, #7 - 8000a82: f000 fbad bl 80011e0 + 8000eb8: 2200 movs r2, #0 + 8000eba: 2100 movs r1, #0 + 8000ebc: 2007 movs r0, #7 + 8000ebe: f000 fd0d bl 80018dc HAL_NVIC_EnableIRQ(EXTI4_15_IRQn); - 8000a86: 2007 movs r0, #7 - 8000a88: f000 fbbf bl 800120a + 8000ec2: 2007 movs r0, #7 + 8000ec4: f000 fd1f bl 8001906 /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } - 8000a8c: 46c0 nop @ (mov r8, r8) - 8000a8e: 46bd mov sp, r7 - 8000a90: b00b add sp, #44 @ 0x2c - 8000a92: bd90 pop {r4, r7, pc} - 8000a94: 40021000 .word 0x40021000 - 8000a98: 00000401 .word 0x00000401 - 8000a9c: 50000400 .word 0x50000400 - 8000aa0: 10210000 .word 0x10210000 + 8000ec8: 46c0 nop @ (mov r8, r8) + 8000eca: 46bd mov sp, r7 + 8000ecc: b00b add sp, #44 @ 0x2c + 8000ece: bd90 pop {r4, r7, pc} + 8000ed0: 40021000 .word 0x40021000 + 8000ed4: 00000401 .word 0x00000401 + 8000ed8: 50000400 .word 0x50000400 + 8000edc: 10210000 .word 0x10210000 -08000aa4 : +08000ee0 : /* USER CODE BEGIN 4 */ void HAL_TIM_PeriodElapsedCallback (TIM_HandleTypeDef * htim) { - 8000aa4: b580 push {r7, lr} - 8000aa6: b082 sub sp, #8 - 8000aa8: af00 add r7, sp, #0 - 8000aaa: 6078 str r0, [r7, #4] + 8000ee0: b580 push {r7, lr} + 8000ee2: b084 sub sp, #16 + 8000ee4: af00 add r7, sp, #0 + 8000ee6: 6078 str r0, [r7, #4] + if (htim == &htim14) // encoder check timer (runs at 20khz) + 8000ee8: 687a ldr r2, [r7, #4] + 8000eea: 4b3f ldr r3, [pc, #252] @ (8000fe8 ) + 8000eec: 429a cmp r2, r3 + 8000eee: d162 bne.n 8000fb6 + { + uint16_t count = htim3.Instance->CNT; + 8000ef0: 4b3e ldr r3, [pc, #248] @ (8000fec ) + 8000ef2: 681b ldr r3, [r3, #0] + 8000ef4: 6a5a ldr r2, [r3, #36] @ 0x24 + 8000ef6: 210e movs r1, #14 + 8000ef8: 187b adds r3, r7, r1 + 8000efa: 801a strh r2, [r3, #0] + if ((encoder_previous > (CNT_MAX-CNT_LIMIT_ZONE)) && (count < CNT_LIMIT_ZONE)) // positive turnaround + 8000efc: 4b3c ldr r3, [pc, #240] @ (8000ff0 ) + 8000efe: 881b ldrh r3, [r3, #0] + 8000f00: 4a3c ldr r2, [pc, #240] @ (8000ff4 ) + 8000f02: 4293 cmp r3, r2 + 8000f04: d90b bls.n 8000f1e + 8000f06: 187b adds r3, r7, r1 + 8000f08: 881a ldrh r2, [r3, #0] + 8000f0a: 23fa movs r3, #250 @ 0xfa + 8000f0c: 009b lsls r3, r3, #2 + 8000f0e: 429a cmp r2, r3 + 8000f10: d205 bcs.n 8000f1e + { + encoder_count_extra ++; + 8000f12: 4b39 ldr r3, [pc, #228] @ (8000ff8 ) + 8000f14: 681b ldr r3, [r3, #0] + 8000f16: 1c5a adds r2, r3, #1 + 8000f18: 4b37 ldr r3, [pc, #220] @ (8000ff8 ) + 8000f1a: 601a str r2, [r3, #0] + return; + 8000f1c: e060 b.n 8000fe0 + } + else if ((encoder_previous < CNT_LIMIT_ZONE) && (count > CNT_MAX-CNT_LIMIT_ZONE)) // negative turnaround + 8000f1e: 4b34 ldr r3, [pc, #208] @ (8000ff0 ) + 8000f20: 881a ldrh r2, [r3, #0] + 8000f22: 23fa movs r3, #250 @ 0xfa + 8000f24: 009b lsls r3, r3, #2 + 8000f26: 429a cmp r2, r3 + 8000f28: d20b bcs.n 8000f42 + 8000f2a: 230e movs r3, #14 + 8000f2c: 18fb adds r3, r7, r3 + 8000f2e: 881b ldrh r3, [r3, #0] + 8000f30: 4a30 ldr r2, [pc, #192] @ (8000ff4 ) + 8000f32: 4293 cmp r3, r2 + 8000f34: d905 bls.n 8000f42 + { + encoder_count_extra --; + 8000f36: 4b30 ldr r3, [pc, #192] @ (8000ff8 ) + 8000f38: 681b ldr r3, [r3, #0] + 8000f3a: 1e5a subs r2, r3, #1 + 8000f3c: 4b2e ldr r3, [pc, #184] @ (8000ff8 ) + 8000f3e: 601a str r2, [r3, #0] + return; + 8000f40: e04e b.n 8000fe0 + } + + total_count = (encoder_count_extra * CNT_MAX) + count; + 8000f42: 4b2d ldr r3, [pc, #180] @ (8000ff8 ) + 8000f44: 681a ldr r2, [r3, #0] + 8000f46: 0013 movs r3, r2 + 8000f48: 041b lsls r3, r3, #16 + 8000f4a: 1a9a subs r2, r3, r2 + 8000f4c: 230e movs r3, #14 + 8000f4e: 18fb adds r3, r7, r3 + 8000f50: 881b ldrh r3, [r3, #0] + 8000f52: 18d2 adds r2, r2, r3 + 8000f54: 4b29 ldr r3, [pc, #164] @ (8000ffc ) + 8000f56: 601a str r2, [r3, #0] + if (total_count > INT32_MAX/2) + 8000f58: 4b28 ldr r3, [pc, #160] @ (8000ffc ) + 8000f5a: 681a ldr r2, [r3, #0] + 8000f5c: 2380 movs r3, #128 @ 0x80 + 8000f5e: 05db lsls r3, r3, #23 + 8000f60: 429a cmp r2, r3 + 8000f62: db0b blt.n 8000f7c + { + total_count-= INT32_MAX/4; + 8000f64: 4b25 ldr r3, [pc, #148] @ (8000ffc ) + 8000f66: 681b ldr r3, [r3, #0] + 8000f68: 4925 ldr r1, [pc, #148] @ (8001000 ) + 8000f6a: 185a adds r2, r3, r1 + 8000f6c: 4b23 ldr r3, [pc, #140] @ (8000ffc ) + 8000f6e: 601a str r2, [r3, #0] + target_count-= INT32_MAX/4; + 8000f70: 4b24 ldr r3, [pc, #144] @ (8001004 ) + 8000f72: 681b ldr r3, [r3, #0] + 8000f74: 185a adds r2, r3, r1 + 8000f76: 4b23 ldr r3, [pc, #140] @ (8001004 ) + 8000f78: 601a str r2, [r3, #0] + 8000f7a: e010 b.n 8000f9e + } + else if (total_count < INT32_MIN/2) + 8000f7c: 4b1f ldr r3, [pc, #124] @ (8000ffc ) + 8000f7e: 681a ldr r2, [r3, #0] + 8000f80: 23c0 movs r3, #192 @ 0xc0 + 8000f82: 061b lsls r3, r3, #24 + 8000f84: 429a cmp r2, r3 + 8000f86: da0a bge.n 8000f9e + { + total_count+= INT32_MAX/4; + 8000f88: 4b1c ldr r3, [pc, #112] @ (8000ffc ) + 8000f8a: 681b ldr r3, [r3, #0] + 8000f8c: 491e ldr r1, [pc, #120] @ (8001008 ) + 8000f8e: 185a adds r2, r3, r1 + 8000f90: 4b1a ldr r3, [pc, #104] @ (8000ffc ) + 8000f92: 601a str r2, [r3, #0] + target_count+= INT32_MAX/4; + 8000f94: 4b1b ldr r3, [pc, #108] @ (8001004 ) + 8000f96: 681b ldr r3, [r3, #0] + 8000f98: 185a adds r2, r3, r1 + 8000f9a: 4b1a ldr r3, [pc, #104] @ (8001004 ) + 8000f9c: 601a str r2, [r3, #0] + } + + motor_cmd = pid_update_motor(&motor_pid,target_count,total_count); + 8000f9e: 4b19 ldr r3, [pc, #100] @ (8001004 ) + 8000fa0: 6819 ldr r1, [r3, #0] + 8000fa2: 4b16 ldr r3, [pc, #88] @ (8000ffc ) + 8000fa4: 681a ldr r2, [r3, #0] + 8000fa6: 4b19 ldr r3, [pc, #100] @ (800100c ) + 8000fa8: 0018 movs r0, r3 + 8000faa: f7ff fa63 bl 8000474 + 8000fae: 0003 movs r3, r0 + 8000fb0: 001a movs r2, r3 + 8000fb2: 4b17 ldr r3, [pc, #92] @ (8001010 ) + 8000fb4: 601a str r2, [r3, #0] + + } + if (htim == &htim3) return; // PWM timer + 8000fb6: 687a ldr r2, [r7, #4] + 8000fb8: 4b0c ldr r3, [pc, #48] @ (8000fec ) + 8000fba: 429a cmp r2, r3 + 8000fbc: d00f beq.n 8000fde + else if (htim == &htim3) // encoder overflow + { + // will this fire on rising / falling overflow the same ? + } + if (htim == &htim16) //SW1 timer + 8000fbe: 687a ldr r2, [r7, #4] + 8000fc0: 4b14 ldr r3, [pc, #80] @ (8001014 ) + 8000fc2: 429a cmp r2, r3 + 8000fc4: d103 bne.n 8000fce + { + sw1_pressed = 0; + 8000fc6: 4b14 ldr r3, [pc, #80] @ (8001018 ) + 8000fc8: 2200 movs r2, #0 + 8000fca: 701a strb r2, [r3, #0] + 8000fcc: e008 b.n 8000fe0 + //todo handle overflow after ~65seconds (48MHz / 48000) * } else if (htim == &htim17) //SW2 timer + 8000fce: 687a ldr r2, [r7, #4] + 8000fd0: 4b12 ldr r3, [pc, #72] @ (800101c ) + 8000fd2: 429a cmp r2, r3 + 8000fd4: d104 bne.n 8000fe0 { //todo + sw2_pressed = 0; + 8000fd6: 4b12 ldr r3, [pc, #72] @ (8001020 ) + 8000fd8: 2200 movs r2, #0 + 8000fda: 701a strb r2, [r3, #0] + 8000fdc: e000 b.n 8000fe0 + if (htim == &htim3) return; // PWM timer + 8000fde: 46c0 nop @ (mov r8, r8) } } - 8000aac: 46bd mov sp, r7 - 8000aae: b002 add sp, #8 - 8000ab0: bd80 pop {r7, pc} + 8000fe0: 46bd mov sp, r7 + 8000fe2: b004 add sp, #16 + 8000fe4: bd80 pop {r7, pc} + 8000fe6: 46c0 nop @ (mov r8, r8) + 8000fe8: 200000d8 .word 0x200000d8 + 8000fec: 2000008c .word 0x2000008c + 8000ff0: 200003a4 .word 0x200003a4 + 8000ff4: 0000fc17 .word 0x0000fc17 + 8000ff8: 200003a0 .word 0x200003a0 + 8000ffc: 20000474 .word 0x20000474 + 8001000: e0000001 .word 0xe0000001 + 8001004: 20000478 .word 0x20000478 + 8001008: 1fffffff .word 0x1fffffff + 800100c: 20000480 .word 0x20000480 + 8001010: 200004a8 .word 0x200004a8 + 8001014: 20000124 .word 0x20000124 + 8001018: 2000039c .word 0x2000039c + 800101c: 20000170 .word 0x20000170 + 8001020: 2000039d .word 0x2000039d -08000ab2 : +08001024 : + } + } +} + +void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) +{ + 8001024: b580 push {r7, lr} + 8001026: b082 sub sp, #8 + 8001028: af00 add r7, sp, #0 + 800102a: 6078 str r0, [r7, #4] + 800102c: 000a movs r2, r1 + 800102e: 1cbb adds r3, r7, #2 + 8001030: 801a strh r2, [r3, #0] + if (Size > 64) return; // todo error handling + 8001032: 1cbb adds r3, r7, #2 + 8001034: 881b ldrh r3, [r3, #0] + 8001036: 2b40 cmp r3, #64 @ 0x40 + 8001038: d823 bhi.n 8001082 + if (msg_buffer1_empty) + 800103a: 4b15 ldr r3, [pc, #84] @ (8001090 ) + 800103c: 781b ldrb r3, [r3, #0] + 800103e: 2b00 cmp r3, #0 + 8001040: d00a beq.n 8001058 + { + memcpy(DMA_buffer,msg_buffer1,Size); + 8001042: 1cbb adds r3, r7, #2 + 8001044: 881a ldrh r2, [r3, #0] + 8001046: 4913 ldr r1, [pc, #76] @ (8001094 ) + 8001048: 4b13 ldr r3, [pc, #76] @ (8001098 ) + 800104a: 0018 movs r0, r3 + 800104c: f003 fea0 bl 8004d90 + msg_buffer1_empty = 0; + 8001050: 4b0f ldr r3, [pc, #60] @ (8001090 ) + 8001052: 2200 movs r2, #0 + 8001054: 701a strb r2, [r3, #0] + 8001056: e00d b.n 8001074 + } + else if (msg_buffer2_empty) + 8001058: 4b10 ldr r3, [pc, #64] @ (800109c ) + 800105a: 781b ldrb r3, [r3, #0] + 800105c: 2b00 cmp r3, #0 + 800105e: d012 beq.n 8001086 + { + memcpy(DMA_buffer,msg_buffer2,Size); + 8001060: 1cbb adds r3, r7, #2 + 8001062: 881a ldrh r2, [r3, #0] + 8001064: 490e ldr r1, [pc, #56] @ (80010a0 ) + 8001066: 4b0c ldr r3, [pc, #48] @ (8001098 ) + 8001068: 0018 movs r0, r3 + 800106a: f003 fe91 bl 8004d90 + msg_buffer2_empty = 0; + 800106e: 4b0b ldr r3, [pc, #44] @ (800109c ) + 8001070: 2200 movs r2, #0 + 8001072: 701a strb r2, [r3, #0] + } + else // no free buffer available todo error handling + { + return; + } + HAL_UARTEx_ReceiveToIdle_DMA(&huart2, DMA_buffer, 64); + 8001074: 4908 ldr r1, [pc, #32] @ (8001098 ) + 8001076: 4b0b ldr r3, [pc, #44] @ (80010a4 ) + 8001078: 2240 movs r2, #64 @ 0x40 + 800107a: 0018 movs r0, r3 + 800107c: f003 fd96 bl 8004bac + 8001080: e002 b.n 8001088 + if (Size > 64) return; // todo error handling + 8001082: 46c0 nop @ (mov r8, r8) + 8001084: e000 b.n 8001088 + return; + 8001086: 46c0 nop @ (mov r8, r8) +} + 8001088: 46bd mov sp, r7 + 800108a: b002 add sp, #8 + 800108c: bd80 pop {r7, pc} + 800108e: 46c0 nop @ (mov r8, r8) + 8001090: 20000000 .word 0x20000000 + 8001094: 200003b4 .word 0x200003b4 + 8001098: 20000434 .word 0x20000434 + 800109c: 20000001 .word 0x20000001 + 80010a0: 200003f4 .word 0x200003f4 + 80010a4: 20000250 .word 0x20000250 + +080010a8 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { - 8000ab2: b580 push {r7, lr} - 8000ab4: af00 add r7, sp, #0 + 80010a8: b580 push {r7, lr} + 80010aa: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting special-purpose register PRIMASK. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); - 8000ab6: b672 cpsid i + 80010ac: b672 cpsid i } - 8000ab8: 46c0 nop @ (mov r8, r8) + 80010ae: 46c0 nop @ (mov r8, r8) /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) - 8000aba: 46c0 nop @ (mov r8, r8) - 8000abc: e7fd b.n 8000aba - ... + 80010b0: 46c0 nop @ (mov r8, r8) + 80010b2: e7fd b.n 80010b0 -08000ac0 : +080010b4 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. */ void HAL_MspInit(void) { - 8000ac0: b580 push {r7, lr} - 8000ac2: b082 sub sp, #8 - 8000ac4: af00 add r7, sp, #0 + 80010b4: b580 push {r7, lr} + 80010b6: b082 sub sp, #8 + 80010b8: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); - 8000ac6: 4b0f ldr r3, [pc, #60] @ (8000b04 ) - 8000ac8: 6c1a ldr r2, [r3, #64] @ 0x40 - 8000aca: 4b0e ldr r3, [pc, #56] @ (8000b04 ) - 8000acc: 2101 movs r1, #1 - 8000ace: 430a orrs r2, r1 - 8000ad0: 641a str r2, [r3, #64] @ 0x40 - 8000ad2: 4b0c ldr r3, [pc, #48] @ (8000b04 ) - 8000ad4: 6c1b ldr r3, [r3, #64] @ 0x40 - 8000ad6: 2201 movs r2, #1 - 8000ad8: 4013 ands r3, r2 - 8000ada: 607b str r3, [r7, #4] - 8000adc: 687b ldr r3, [r7, #4] + 80010ba: 4b0f ldr r3, [pc, #60] @ (80010f8 ) + 80010bc: 6c1a ldr r2, [r3, #64] @ 0x40 + 80010be: 4b0e ldr r3, [pc, #56] @ (80010f8 ) + 80010c0: 2101 movs r1, #1 + 80010c2: 430a orrs r2, r1 + 80010c4: 641a str r2, [r3, #64] @ 0x40 + 80010c6: 4b0c ldr r3, [pc, #48] @ (80010f8 ) + 80010c8: 6c1b ldr r3, [r3, #64] @ 0x40 + 80010ca: 2201 movs r2, #1 + 80010cc: 4013 ands r3, r2 + 80010ce: 607b str r3, [r7, #4] + 80010d0: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); - 8000ade: 4b09 ldr r3, [pc, #36] @ (8000b04 ) - 8000ae0: 6bda ldr r2, [r3, #60] @ 0x3c - 8000ae2: 4b08 ldr r3, [pc, #32] @ (8000b04 ) - 8000ae4: 2180 movs r1, #128 @ 0x80 - 8000ae6: 0549 lsls r1, r1, #21 - 8000ae8: 430a orrs r2, r1 - 8000aea: 63da str r2, [r3, #60] @ 0x3c - 8000aec: 4b05 ldr r3, [pc, #20] @ (8000b04 ) - 8000aee: 6bda ldr r2, [r3, #60] @ 0x3c - 8000af0: 2380 movs r3, #128 @ 0x80 - 8000af2: 055b lsls r3, r3, #21 - 8000af4: 4013 ands r3, r2 - 8000af6: 603b str r3, [r7, #0] - 8000af8: 683b ldr r3, [r7, #0] + 80010d2: 4b09 ldr r3, [pc, #36] @ (80010f8 ) + 80010d4: 6bda ldr r2, [r3, #60] @ 0x3c + 80010d6: 4b08 ldr r3, [pc, #32] @ (80010f8 ) + 80010d8: 2180 movs r1, #128 @ 0x80 + 80010da: 0549 lsls r1, r1, #21 + 80010dc: 430a orrs r2, r1 + 80010de: 63da str r2, [r3, #60] @ 0x3c + 80010e0: 4b05 ldr r3, [pc, #20] @ (80010f8 ) + 80010e2: 6bda ldr r2, [r3, #60] @ 0x3c + 80010e4: 2380 movs r3, #128 @ 0x80 + 80010e6: 055b lsls r3, r3, #21 + 80010e8: 4013 ands r3, r2 + 80010ea: 603b str r3, [r7, #0] + 80010ec: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } - 8000afa: 46c0 nop @ (mov r8, r8) - 8000afc: 46bd mov sp, r7 - 8000afe: b002 add sp, #8 - 8000b00: bd80 pop {r7, pc} - 8000b02: 46c0 nop @ (mov r8, r8) - 8000b04: 40021000 .word 0x40021000 + 80010ee: 46c0 nop @ (mov r8, r8) + 80010f0: 46bd mov sp, r7 + 80010f2: b002 add sp, #8 + 80010f4: bd80 pop {r7, pc} + 80010f6: 46c0 nop @ (mov r8, r8) + 80010f8: 40021000 .word 0x40021000 -08000b08 : +080010fc : * This function configures the hardware resources used in this example * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { - 8000b08: b580 push {r7, lr} - 8000b0a: b086 sub sp, #24 - 8000b0c: af00 add r7, sp, #0 - 8000b0e: 6078 str r0, [r7, #4] + 80010fc: b580 push {r7, lr} + 80010fe: b086 sub sp, #24 + 8001100: af00 add r7, sp, #0 + 8001102: 6078 str r0, [r7, #4] if(htim_base->Instance==TIM1) - 8000b10: 687b ldr r3, [r7, #4] - 8000b12: 681b ldr r3, [r3, #0] - 8000b14: 4a26 ldr r2, [pc, #152] @ (8000bb0 ) - 8000b16: 4293 cmp r3, r2 - 8000b18: d10e bne.n 8000b38 + 8001104: 687b ldr r3, [r7, #4] + 8001106: 681b ldr r3, [r3, #0] + 8001108: 4a34 ldr r2, [pc, #208] @ (80011dc ) + 800110a: 4293 cmp r3, r2 + 800110c: d10e bne.n 800112c { /* USER CODE BEGIN TIM1_MspInit 0 */ /* USER CODE END TIM1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM1_CLK_ENABLE(); - 8000b1a: 4b26 ldr r3, [pc, #152] @ (8000bb4 ) - 8000b1c: 6c1a ldr r2, [r3, #64] @ 0x40 - 8000b1e: 4b25 ldr r3, [pc, #148] @ (8000bb4 ) - 8000b20: 2180 movs r1, #128 @ 0x80 - 8000b22: 0109 lsls r1, r1, #4 - 8000b24: 430a orrs r2, r1 - 8000b26: 641a str r2, [r3, #64] @ 0x40 - 8000b28: 4b22 ldr r3, [pc, #136] @ (8000bb4 ) - 8000b2a: 6c1a ldr r2, [r3, #64] @ 0x40 - 8000b2c: 2380 movs r3, #128 @ 0x80 - 8000b2e: 011b lsls r3, r3, #4 - 8000b30: 4013 ands r3, r2 - 8000b32: 617b str r3, [r7, #20] - 8000b34: 697b ldr r3, [r7, #20] + 800110e: 4b34 ldr r3, [pc, #208] @ (80011e0 ) + 8001110: 6c1a ldr r2, [r3, #64] @ 0x40 + 8001112: 4b33 ldr r3, [pc, #204] @ (80011e0 ) + 8001114: 2180 movs r1, #128 @ 0x80 + 8001116: 0109 lsls r1, r1, #4 + 8001118: 430a orrs r2, r1 + 800111a: 641a str r2, [r3, #64] @ 0x40 + 800111c: 4b30 ldr r3, [pc, #192] @ (80011e0 ) + 800111e: 6c1a ldr r2, [r3, #64] @ 0x40 + 8001120: 2380 movs r3, #128 @ 0x80 + 8001122: 011b lsls r3, r3, #4 + 8001124: 4013 ands r3, r2 + 8001126: 617b str r3, [r7, #20] + 8001128: 697b ldr r3, [r7, #20] /* USER CODE BEGIN TIM17_MspInit 1 */ /* USER CODE END TIM17_MspInit 1 */ } } - 8000b36: e036 b.n 8000ba6 + 800112a: e052 b.n 80011d2 + else if(htim_base->Instance==TIM14) + 800112c: 687b ldr r3, [r7, #4] + 800112e: 681b ldr r3, [r3, #0] + 8001130: 4a2c ldr r2, [pc, #176] @ (80011e4 ) + 8001132: 4293 cmp r3, r2 + 8001134: d116 bne.n 8001164 + __HAL_RCC_TIM14_CLK_ENABLE(); + 8001136: 4b2a ldr r3, [pc, #168] @ (80011e0 ) + 8001138: 6c1a ldr r2, [r3, #64] @ 0x40 + 800113a: 4b29 ldr r3, [pc, #164] @ (80011e0 ) + 800113c: 2180 movs r1, #128 @ 0x80 + 800113e: 0209 lsls r1, r1, #8 + 8001140: 430a orrs r2, r1 + 8001142: 641a str r2, [r3, #64] @ 0x40 + 8001144: 4b26 ldr r3, [pc, #152] @ (80011e0 ) + 8001146: 6c1a ldr r2, [r3, #64] @ 0x40 + 8001148: 2380 movs r3, #128 @ 0x80 + 800114a: 021b lsls r3, r3, #8 + 800114c: 4013 ands r3, r2 + 800114e: 613b str r3, [r7, #16] + 8001150: 693b ldr r3, [r7, #16] + HAL_NVIC_SetPriority(TIM14_IRQn, 0, 0); + 8001152: 2200 movs r2, #0 + 8001154: 2100 movs r1, #0 + 8001156: 2013 movs r0, #19 + 8001158: f000 fbc0 bl 80018dc + HAL_NVIC_EnableIRQ(TIM14_IRQn); + 800115c: 2013 movs r0, #19 + 800115e: f000 fbd2 bl 8001906 +} + 8001162: e036 b.n 80011d2 else if(htim_base->Instance==TIM16) - 8000b38: 687b ldr r3, [r7, #4] - 8000b3a: 681b ldr r3, [r3, #0] - 8000b3c: 4a1e ldr r2, [pc, #120] @ (8000bb8 ) - 8000b3e: 4293 cmp r3, r2 - 8000b40: d116 bne.n 8000b70 + 8001164: 687b ldr r3, [r7, #4] + 8001166: 681b ldr r3, [r3, #0] + 8001168: 4a1f ldr r2, [pc, #124] @ (80011e8 ) + 800116a: 4293 cmp r3, r2 + 800116c: d116 bne.n 800119c __HAL_RCC_TIM16_CLK_ENABLE(); - 8000b42: 4b1c ldr r3, [pc, #112] @ (8000bb4 ) - 8000b44: 6c1a ldr r2, [r3, #64] @ 0x40 - 8000b46: 4b1b ldr r3, [pc, #108] @ (8000bb4 ) - 8000b48: 2180 movs r1, #128 @ 0x80 - 8000b4a: 0289 lsls r1, r1, #10 - 8000b4c: 430a orrs r2, r1 - 8000b4e: 641a str r2, [r3, #64] @ 0x40 - 8000b50: 4b18 ldr r3, [pc, #96] @ (8000bb4 ) - 8000b52: 6c1a ldr r2, [r3, #64] @ 0x40 - 8000b54: 2380 movs r3, #128 @ 0x80 - 8000b56: 029b lsls r3, r3, #10 - 8000b58: 4013 ands r3, r2 - 8000b5a: 613b str r3, [r7, #16] - 8000b5c: 693b ldr r3, [r7, #16] + 800116e: 4b1c ldr r3, [pc, #112] @ (80011e0 ) + 8001170: 6c1a ldr r2, [r3, #64] @ 0x40 + 8001172: 4b1b ldr r3, [pc, #108] @ (80011e0 ) + 8001174: 2180 movs r1, #128 @ 0x80 + 8001176: 0289 lsls r1, r1, #10 + 8001178: 430a orrs r2, r1 + 800117a: 641a str r2, [r3, #64] @ 0x40 + 800117c: 4b18 ldr r3, [pc, #96] @ (80011e0 ) + 800117e: 6c1a ldr r2, [r3, #64] @ 0x40 + 8001180: 2380 movs r3, #128 @ 0x80 + 8001182: 029b lsls r3, r3, #10 + 8001184: 4013 ands r3, r2 + 8001186: 60fb str r3, [r7, #12] + 8001188: 68fb ldr r3, [r7, #12] HAL_NVIC_SetPriority(TIM16_IRQn, 0, 0); - 8000b5e: 2200 movs r2, #0 - 8000b60: 2100 movs r1, #0 - 8000b62: 2015 movs r0, #21 - 8000b64: f000 fb3c bl 80011e0 + 800118a: 2200 movs r2, #0 + 800118c: 2100 movs r1, #0 + 800118e: 2015 movs r0, #21 + 8001190: f000 fba4 bl 80018dc HAL_NVIC_EnableIRQ(TIM16_IRQn); - 8000b68: 2015 movs r0, #21 - 8000b6a: f000 fb4e bl 800120a + 8001194: 2015 movs r0, #21 + 8001196: f000 fbb6 bl 8001906 } - 8000b6e: e01a b.n 8000ba6 + 800119a: e01a b.n 80011d2 else if(htim_base->Instance==TIM17) - 8000b70: 687b ldr r3, [r7, #4] - 8000b72: 681b ldr r3, [r3, #0] - 8000b74: 4a11 ldr r2, [pc, #68] @ (8000bbc ) - 8000b76: 4293 cmp r3, r2 - 8000b78: d115 bne.n 8000ba6 + 800119c: 687b ldr r3, [r7, #4] + 800119e: 681b ldr r3, [r3, #0] + 80011a0: 4a12 ldr r2, [pc, #72] @ (80011ec ) + 80011a2: 4293 cmp r3, r2 + 80011a4: d115 bne.n 80011d2 __HAL_RCC_TIM17_CLK_ENABLE(); - 8000b7a: 4b0e ldr r3, [pc, #56] @ (8000bb4 ) - 8000b7c: 6c1a ldr r2, [r3, #64] @ 0x40 - 8000b7e: 4b0d ldr r3, [pc, #52] @ (8000bb4 ) - 8000b80: 2180 movs r1, #128 @ 0x80 - 8000b82: 02c9 lsls r1, r1, #11 - 8000b84: 430a orrs r2, r1 - 8000b86: 641a str r2, [r3, #64] @ 0x40 - 8000b88: 4b0a ldr r3, [pc, #40] @ (8000bb4 ) - 8000b8a: 6c1a ldr r2, [r3, #64] @ 0x40 - 8000b8c: 2380 movs r3, #128 @ 0x80 - 8000b8e: 02db lsls r3, r3, #11 - 8000b90: 4013 ands r3, r2 - 8000b92: 60fb str r3, [r7, #12] - 8000b94: 68fb ldr r3, [r7, #12] + 80011a6: 4b0e ldr r3, [pc, #56] @ (80011e0 ) + 80011a8: 6c1a ldr r2, [r3, #64] @ 0x40 + 80011aa: 4b0d ldr r3, [pc, #52] @ (80011e0 ) + 80011ac: 2180 movs r1, #128 @ 0x80 + 80011ae: 02c9 lsls r1, r1, #11 + 80011b0: 430a orrs r2, r1 + 80011b2: 641a str r2, [r3, #64] @ 0x40 + 80011b4: 4b0a ldr r3, [pc, #40] @ (80011e0 ) + 80011b6: 6c1a ldr r2, [r3, #64] @ 0x40 + 80011b8: 2380 movs r3, #128 @ 0x80 + 80011ba: 02db lsls r3, r3, #11 + 80011bc: 4013 ands r3, r2 + 80011be: 60bb str r3, [r7, #8] + 80011c0: 68bb ldr r3, [r7, #8] HAL_NVIC_SetPriority(TIM17_IRQn, 0, 0); - 8000b96: 2200 movs r2, #0 - 8000b98: 2100 movs r1, #0 - 8000b9a: 2016 movs r0, #22 - 8000b9c: f000 fb20 bl 80011e0 + 80011c2: 2200 movs r2, #0 + 80011c4: 2100 movs r1, #0 + 80011c6: 2016 movs r0, #22 + 80011c8: f000 fb88 bl 80018dc HAL_NVIC_EnableIRQ(TIM17_IRQn); - 8000ba0: 2016 movs r0, #22 - 8000ba2: f000 fb32 bl 800120a + 80011cc: 2016 movs r0, #22 + 80011ce: f000 fb9a bl 8001906 } - 8000ba6: 46c0 nop @ (mov r8, r8) - 8000ba8: 46bd mov sp, r7 - 8000baa: b006 add sp, #24 - 8000bac: bd80 pop {r7, pc} - 8000bae: 46c0 nop @ (mov r8, r8) - 8000bb0: 40012c00 .word 0x40012c00 - 8000bb4: 40021000 .word 0x40021000 - 8000bb8: 40014400 .word 0x40014400 - 8000bbc: 40014800 .word 0x40014800 + 80011d2: 46c0 nop @ (mov r8, r8) + 80011d4: 46bd mov sp, r7 + 80011d6: b006 add sp, #24 + 80011d8: bd80 pop {r7, pc} + 80011da: 46c0 nop @ (mov r8, r8) + 80011dc: 40012c00 .word 0x40012c00 + 80011e0: 40021000 .word 0x40021000 + 80011e4: 40002000 .word 0x40002000 + 80011e8: 40014400 .word 0x40014400 + 80011ec: 40014800 .word 0x40014800 -08000bc0 : +080011f0 : * This function configures the hardware resources used in this example * @param htim_encoder: TIM_Encoder handle pointer * @retval None */ void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* htim_encoder) { - 8000bc0: b590 push {r4, r7, lr} - 8000bc2: b08b sub sp, #44 @ 0x2c - 8000bc4: af00 add r7, sp, #0 - 8000bc6: 6078 str r0, [r7, #4] + 80011f0: b590 push {r4, r7, lr} + 80011f2: b08b sub sp, #44 @ 0x2c + 80011f4: af00 add r7, sp, #0 + 80011f6: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; - 8000bc8: 2414 movs r4, #20 - 8000bca: 193b adds r3, r7, r4 - 8000bcc: 0018 movs r0, r3 - 8000bce: 2314 movs r3, #20 - 8000bd0: 001a movs r2, r3 - 8000bd2: 2100 movs r1, #0 - 8000bd4: f003 f9b2 bl 8003f3c + 80011f8: 2414 movs r4, #20 + 80011fa: 193b adds r3, r7, r4 + 80011fc: 0018 movs r0, r3 + 80011fe: 2314 movs r3, #20 + 8001200: 001a movs r2, r3 + 8001202: 2100 movs r1, #0 + 8001204: f003 fd98 bl 8004d38 if(htim_encoder->Instance==TIM3) - 8000bd8: 687b ldr r3, [r7, #4] - 8000bda: 681b ldr r3, [r3, #0] - 8000bdc: 4a2f ldr r2, [pc, #188] @ (8000c9c ) - 8000bde: 4293 cmp r3, r2 - 8000be0: d158 bne.n 8000c94 + 8001208: 687b ldr r3, [r7, #4] + 800120a: 681b ldr r3, [r3, #0] + 800120c: 4a1a ldr r2, [pc, #104] @ (8001278 ) + 800120e: 4293 cmp r3, r2 + 8001210: d12d bne.n 800126e { /* USER CODE BEGIN TIM3_MspInit 0 */ /* USER CODE END TIM3_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM3_CLK_ENABLE(); - 8000be2: 4b2f ldr r3, [pc, #188] @ (8000ca0 ) - 8000be4: 6bda ldr r2, [r3, #60] @ 0x3c - 8000be6: 4b2e ldr r3, [pc, #184] @ (8000ca0 ) - 8000be8: 2102 movs r1, #2 - 8000bea: 430a orrs r2, r1 - 8000bec: 63da str r2, [r3, #60] @ 0x3c - 8000bee: 4b2c ldr r3, [pc, #176] @ (8000ca0 ) - 8000bf0: 6bdb ldr r3, [r3, #60] @ 0x3c - 8000bf2: 2202 movs r2, #2 - 8000bf4: 4013 ands r3, r2 - 8000bf6: 613b str r3, [r7, #16] - 8000bf8: 693b ldr r3, [r7, #16] + 8001212: 4b1a ldr r3, [pc, #104] @ (800127c ) + 8001214: 6bda ldr r2, [r3, #60] @ 0x3c + 8001216: 4b19 ldr r3, [pc, #100] @ (800127c ) + 8001218: 2102 movs r1, #2 + 800121a: 430a orrs r2, r1 + 800121c: 63da str r2, [r3, #60] @ 0x3c + 800121e: 4b17 ldr r3, [pc, #92] @ (800127c ) + 8001220: 6bdb ldr r3, [r3, #60] @ 0x3c + 8001222: 2202 movs r2, #2 + 8001224: 4013 ands r3, r2 + 8001226: 613b str r3, [r7, #16] + 8001228: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOC_CLK_ENABLE(); - 8000bfa: 4b29 ldr r3, [pc, #164] @ (8000ca0 ) - 8000bfc: 6b5a ldr r2, [r3, #52] @ 0x34 - 8000bfe: 4b28 ldr r3, [pc, #160] @ (8000ca0 ) - 8000c00: 2104 movs r1, #4 - 8000c02: 430a orrs r2, r1 - 8000c04: 635a str r2, [r3, #52] @ 0x34 - 8000c06: 4b26 ldr r3, [pc, #152] @ (8000ca0 ) - 8000c08: 6b5b ldr r3, [r3, #52] @ 0x34 - 8000c0a: 2204 movs r2, #4 - 8000c0c: 4013 ands r3, r2 - 8000c0e: 60fb str r3, [r7, #12] - 8000c10: 68fb ldr r3, [r7, #12] + 800122a: 4b14 ldr r3, [pc, #80] @ (800127c ) + 800122c: 6b5a ldr r2, [r3, #52] @ 0x34 + 800122e: 4b13 ldr r3, [pc, #76] @ (800127c ) + 8001230: 2104 movs r1, #4 + 8001232: 430a orrs r2, r1 + 8001234: 635a str r2, [r3, #52] @ 0x34 + 8001236: 4b11 ldr r3, [pc, #68] @ (800127c ) + 8001238: 6b5b ldr r3, [r3, #52] @ 0x34 + 800123a: 2204 movs r2, #4 + 800123c: 4013 ands r3, r2 + 800123e: 60fb str r3, [r7, #12] + 8001240: 68fb ldr r3, [r7, #12] /**TIM3 GPIO Configuration PC6 ------> TIM3_CH1 PC7 ------> TIM3_CH2 */ GPIO_InitStruct.Pin = QUAD_A_Pin|QUAD_B_Pin; - 8000c12: 0021 movs r1, r4 - 8000c14: 187b adds r3, r7, r1 - 8000c16: 22c0 movs r2, #192 @ 0xc0 - 8000c18: 601a str r2, [r3, #0] + 8001242: 0021 movs r1, r4 + 8001244: 187b adds r3, r7, r1 + 8001246: 22c0 movs r2, #192 @ 0xc0 + 8001248: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - 8000c1a: 187b adds r3, r7, r1 - 8000c1c: 2202 movs r2, #2 - 8000c1e: 605a str r2, [r3, #4] + 800124a: 187b adds r3, r7, r1 + 800124c: 2202 movs r2, #2 + 800124e: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; - 8000c20: 187b adds r3, r7, r1 - 8000c22: 2200 movs r2, #0 - 8000c24: 609a str r2, [r3, #8] + 8001250: 187b adds r3, r7, r1 + 8001252: 2200 movs r2, #0 + 8001254: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - 8000c26: 187b adds r3, r7, r1 - 8000c28: 2200 movs r2, #0 - 8000c2a: 60da str r2, [r3, #12] + 8001256: 187b adds r3, r7, r1 + 8001258: 2200 movs r2, #0 + 800125a: 60da str r2, [r3, #12] GPIO_InitStruct.Alternate = GPIO_AF1_TIM3; - 8000c2c: 187b adds r3, r7, r1 - 8000c2e: 2201 movs r2, #1 - 8000c30: 611a str r2, [r3, #16] + 800125c: 187b adds r3, r7, r1 + 800125e: 2201 movs r2, #1 + 8001260: 611a str r2, [r3, #16] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - 8000c32: 187b adds r3, r7, r1 - 8000c34: 4a1b ldr r2, [pc, #108] @ (8000ca4 ) - 8000c36: 0019 movs r1, r3 - 8000c38: 0010 movs r0, r2 - 8000c3a: f000 fc8f bl 800155c - - /* TIM3 DMA Init */ - /* TIM3_UP Init */ - hdma_tim3_up.Instance = DMA1_Channel1; - 8000c3e: 4b1a ldr r3, [pc, #104] @ (8000ca8 ) - 8000c40: 4a1a ldr r2, [pc, #104] @ (8000cac ) - 8000c42: 601a str r2, [r3, #0] - hdma_tim3_up.Init.Request = DMA_REQUEST_TIM3_UP; - 8000c44: 4b18 ldr r3, [pc, #96] @ (8000ca8 ) - 8000c46: 2225 movs r2, #37 @ 0x25 - 8000c48: 605a str r2, [r3, #4] - hdma_tim3_up.Init.Direction = DMA_PERIPH_TO_MEMORY; - 8000c4a: 4b17 ldr r3, [pc, #92] @ (8000ca8 ) - 8000c4c: 2200 movs r2, #0 - 8000c4e: 609a str r2, [r3, #8] - hdma_tim3_up.Init.PeriphInc = DMA_PINC_DISABLE; - 8000c50: 4b15 ldr r3, [pc, #84] @ (8000ca8 ) - 8000c52: 2200 movs r2, #0 - 8000c54: 60da str r2, [r3, #12] - hdma_tim3_up.Init.MemInc = DMA_MINC_ENABLE; - 8000c56: 4b14 ldr r3, [pc, #80] @ (8000ca8 ) - 8000c58: 2280 movs r2, #128 @ 0x80 - 8000c5a: 611a str r2, [r3, #16] - hdma_tim3_up.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; - 8000c5c: 4b12 ldr r3, [pc, #72] @ (8000ca8 ) - 8000c5e: 2280 movs r2, #128 @ 0x80 - 8000c60: 0052 lsls r2, r2, #1 - 8000c62: 615a str r2, [r3, #20] - hdma_tim3_up.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; - 8000c64: 4b10 ldr r3, [pc, #64] @ (8000ca8 ) - 8000c66: 2280 movs r2, #128 @ 0x80 - 8000c68: 00d2 lsls r2, r2, #3 - 8000c6a: 619a str r2, [r3, #24] - hdma_tim3_up.Init.Mode = DMA_NORMAL; - 8000c6c: 4b0e ldr r3, [pc, #56] @ (8000ca8 ) - 8000c6e: 2200 movs r2, #0 - 8000c70: 61da str r2, [r3, #28] - hdma_tim3_up.Init.Priority = DMA_PRIORITY_LOW; - 8000c72: 4b0d ldr r3, [pc, #52] @ (8000ca8 ) - 8000c74: 2200 movs r2, #0 - 8000c76: 621a str r2, [r3, #32] - if (HAL_DMA_Init(&hdma_tim3_up) != HAL_OK) - 8000c78: 4b0b ldr r3, [pc, #44] @ (8000ca8 ) - 8000c7a: 0018 movs r0, r3 - 8000c7c: f000 fae2 bl 8001244 - 8000c80: 1e03 subs r3, r0, #0 - 8000c82: d001 beq.n 8000c88 - { - Error_Handler(); - 8000c84: f7ff ff15 bl 8000ab2 - } - - __HAL_LINKDMA(htim_encoder,hdma[TIM_DMA_ID_UPDATE],hdma_tim3_up); - 8000c88: 687b ldr r3, [r7, #4] - 8000c8a: 4a07 ldr r2, [pc, #28] @ (8000ca8 ) - 8000c8c: 621a str r2, [r3, #32] - 8000c8e: 4b06 ldr r3, [pc, #24] @ (8000ca8 ) - 8000c90: 687a ldr r2, [r7, #4] - 8000c92: 629a str r2, [r3, #40] @ 0x28 + 8001262: 187b adds r3, r7, r1 + 8001264: 4a06 ldr r2, [pc, #24] @ (8001280 ) + 8001266: 0019 movs r1, r3 + 8001268: 0010 movs r0, r2 + 800126a: f000 fdbd bl 8001de8 /* USER CODE END TIM3_MspInit 1 */ } } - 8000c94: 46c0 nop @ (mov r8, r8) - 8000c96: 46bd mov sp, r7 - 8000c98: b00b add sp, #44 @ 0x2c - 8000c9a: bd90 pop {r4, r7, pc} - 8000c9c: 40000400 .word 0x40000400 - 8000ca0: 40021000 .word 0x40021000 - 8000ca4: 50000800 .word 0x50000800 - 8000ca8: 20000158 .word 0x20000158 - 8000cac: 40020008 .word 0x40020008 + 800126e: 46c0 nop @ (mov r8, r8) + 8001270: 46bd mov sp, r7 + 8001272: b00b add sp, #44 @ 0x2c + 8001274: bd90 pop {r4, r7, pc} + 8001276: 46c0 nop @ (mov r8, r8) + 8001278: 40000400 .word 0x40000400 + 800127c: 40021000 .word 0x40021000 + 8001280: 50000800 .word 0x50000800 -08000cb0 : +08001284 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) { - 8000cb0: b590 push {r4, r7, lr} - 8000cb2: b089 sub sp, #36 @ 0x24 - 8000cb4: af00 add r7, sp, #0 - 8000cb6: 6078 str r0, [r7, #4] + 8001284: b590 push {r4, r7, lr} + 8001286: b089 sub sp, #36 @ 0x24 + 8001288: af00 add r7, sp, #0 + 800128a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; - 8000cb8: 240c movs r4, #12 - 8000cba: 193b adds r3, r7, r4 - 8000cbc: 0018 movs r0, r3 - 8000cbe: 2314 movs r3, #20 - 8000cc0: 001a movs r2, r3 - 8000cc2: 2100 movs r1, #0 - 8000cc4: f003 f93a bl 8003f3c + 800128c: 240c movs r4, #12 + 800128e: 193b adds r3, r7, r4 + 8001290: 0018 movs r0, r3 + 8001292: 2314 movs r3, #20 + 8001294: 001a movs r2, r3 + 8001296: 2100 movs r1, #0 + 8001298: f003 fd4e bl 8004d38 if(htim->Instance==TIM1) - 8000cc8: 687b ldr r3, [r7, #4] - 8000cca: 681b ldr r3, [r3, #0] - 8000ccc: 4a20 ldr r2, [pc, #128] @ (8000d50 ) - 8000cce: 4293 cmp r3, r2 - 8000cd0: d139 bne.n 8000d46 + 800129c: 687b ldr r3, [r7, #4] + 800129e: 681b ldr r3, [r3, #0] + 80012a0: 4a20 ldr r2, [pc, #128] @ (8001324 ) + 80012a2: 4293 cmp r3, r2 + 80012a4: d139 bne.n 800131a { /* USER CODE BEGIN TIM1_MspPostInit 0 */ /* USER CODE END TIM1_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); - 8000cd2: 4b20 ldr r3, [pc, #128] @ (8000d54 ) - 8000cd4: 6b5a ldr r2, [r3, #52] @ 0x34 - 8000cd6: 4b1f ldr r3, [pc, #124] @ (8000d54 ) - 8000cd8: 2101 movs r1, #1 - 8000cda: 430a orrs r2, r1 - 8000cdc: 635a str r2, [r3, #52] @ 0x34 - 8000cde: 4b1d ldr r3, [pc, #116] @ (8000d54 ) - 8000ce0: 6b5b ldr r3, [r3, #52] @ 0x34 - 8000ce2: 2201 movs r2, #1 - 8000ce4: 4013 ands r3, r2 - 8000ce6: 60bb str r3, [r7, #8] - 8000ce8: 68bb ldr r3, [r7, #8] + 80012a6: 4b20 ldr r3, [pc, #128] @ (8001328 ) + 80012a8: 6b5a ldr r2, [r3, #52] @ 0x34 + 80012aa: 4b1f ldr r3, [pc, #124] @ (8001328 ) + 80012ac: 2101 movs r1, #1 + 80012ae: 430a orrs r2, r1 + 80012b0: 635a str r2, [r3, #52] @ 0x34 + 80012b2: 4b1d ldr r3, [pc, #116] @ (8001328 ) + 80012b4: 6b5b ldr r3, [r3, #52] @ 0x34 + 80012b6: 2201 movs r2, #1 + 80012b8: 4013 ands r3, r2 + 80012ba: 60bb str r3, [r7, #8] + 80012bc: 68bb ldr r3, [r7, #8] PA2 ------> TIM1_CH3 PA3 ------> TIM1_CH4 PA8 ------> TIM1_CH1 PA9 ------> TIM1_CH2 */ GPIO_InitStruct.Pin = PEEL1_Pin|PEEL2_Pin; - 8000cea: 193b adds r3, r7, r4 - 8000cec: 220c movs r2, #12 - 8000cee: 601a str r2, [r3, #0] + 80012be: 193b adds r3, r7, r4 + 80012c0: 220c movs r2, #12 + 80012c2: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - 8000cf0: 193b adds r3, r7, r4 - 8000cf2: 2202 movs r2, #2 - 8000cf4: 605a str r2, [r3, #4] + 80012c4: 193b adds r3, r7, r4 + 80012c6: 2202 movs r2, #2 + 80012c8: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; - 8000cf6: 193b adds r3, r7, r4 - 8000cf8: 2200 movs r2, #0 - 8000cfa: 609a str r2, [r3, #8] + 80012ca: 193b adds r3, r7, r4 + 80012cc: 2200 movs r2, #0 + 80012ce: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - 8000cfc: 193b adds r3, r7, r4 - 8000cfe: 2200 movs r2, #0 - 8000d00: 60da str r2, [r3, #12] + 80012d0: 193b adds r3, r7, r4 + 80012d2: 2200 movs r2, #0 + 80012d4: 60da str r2, [r3, #12] GPIO_InitStruct.Alternate = GPIO_AF5_TIM1; - 8000d02: 193b adds r3, r7, r4 - 8000d04: 2205 movs r2, #5 - 8000d06: 611a str r2, [r3, #16] + 80012d6: 193b adds r3, r7, r4 + 80012d8: 2205 movs r2, #5 + 80012da: 611a str r2, [r3, #16] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - 8000d08: 193a adds r2, r7, r4 - 8000d0a: 23a0 movs r3, #160 @ 0xa0 - 8000d0c: 05db lsls r3, r3, #23 - 8000d0e: 0011 movs r1, r2 - 8000d10: 0018 movs r0, r3 - 8000d12: f000 fc23 bl 800155c + 80012dc: 193a adds r2, r7, r4 + 80012de: 23a0 movs r3, #160 @ 0xa0 + 80012e0: 05db lsls r3, r3, #23 + 80012e2: 0011 movs r1, r2 + 80012e4: 0018 movs r0, r3 + 80012e6: f000 fd7f bl 8001de8 GPIO_InitStruct.Pin = DRIVE1_Pin|DRIVE2_Pin; - 8000d16: 0021 movs r1, r4 - 8000d18: 187b adds r3, r7, r1 - 8000d1a: 22c0 movs r2, #192 @ 0xc0 - 8000d1c: 0092 lsls r2, r2, #2 - 8000d1e: 601a str r2, [r3, #0] + 80012ea: 0021 movs r1, r4 + 80012ec: 187b adds r3, r7, r1 + 80012ee: 22c0 movs r2, #192 @ 0xc0 + 80012f0: 0092 lsls r2, r2, #2 + 80012f2: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - 8000d20: 187b adds r3, r7, r1 - 8000d22: 2202 movs r2, #2 - 8000d24: 605a str r2, [r3, #4] + 80012f4: 187b adds r3, r7, r1 + 80012f6: 2202 movs r2, #2 + 80012f8: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; - 8000d26: 187b adds r3, r7, r1 - 8000d28: 2200 movs r2, #0 - 8000d2a: 609a str r2, [r3, #8] + 80012fa: 187b adds r3, r7, r1 + 80012fc: 2200 movs r2, #0 + 80012fe: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - 8000d2c: 187b adds r3, r7, r1 - 8000d2e: 2200 movs r2, #0 - 8000d30: 60da str r2, [r3, #12] + 8001300: 187b adds r3, r7, r1 + 8001302: 2200 movs r2, #0 + 8001304: 60da str r2, [r3, #12] GPIO_InitStruct.Alternate = GPIO_AF2_TIM1; - 8000d32: 187b adds r3, r7, r1 - 8000d34: 2202 movs r2, #2 - 8000d36: 611a str r2, [r3, #16] + 8001306: 187b adds r3, r7, r1 + 8001308: 2202 movs r2, #2 + 800130a: 611a str r2, [r3, #16] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - 8000d38: 187a adds r2, r7, r1 - 8000d3a: 23a0 movs r3, #160 @ 0xa0 - 8000d3c: 05db lsls r3, r3, #23 - 8000d3e: 0011 movs r1, r2 - 8000d40: 0018 movs r0, r3 - 8000d42: f000 fc0b bl 800155c + 800130c: 187a adds r2, r7, r1 + 800130e: 23a0 movs r3, #160 @ 0xa0 + 8001310: 05db lsls r3, r3, #23 + 8001312: 0011 movs r1, r2 + 8001314: 0018 movs r0, r3 + 8001316: f000 fd67 bl 8001de8 /* USER CODE BEGIN TIM1_MspPostInit 1 */ /* USER CODE END TIM1_MspPostInit 1 */ } } - 8000d46: 46c0 nop @ (mov r8, r8) - 8000d48: 46bd mov sp, r7 - 8000d4a: b009 add sp, #36 @ 0x24 - 8000d4c: bd90 pop {r4, r7, pc} - 8000d4e: 46c0 nop @ (mov r8, r8) - 8000d50: 40012c00 .word 0x40012c00 - 8000d54: 40021000 .word 0x40021000 + 800131a: 46c0 nop @ (mov r8, r8) + 800131c: 46bd mov sp, r7 + 800131e: b009 add sp, #36 @ 0x24 + 8001320: bd90 pop {r4, r7, pc} + 8001322: 46c0 nop @ (mov r8, r8) + 8001324: 40012c00 .word 0x40012c00 + 8001328: 40021000 .word 0x40021000 -08000d58 : +0800132c : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { - 8000d58: b590 push {r4, r7, lr} - 8000d5a: b093 sub sp, #76 @ 0x4c - 8000d5c: af00 add r7, sp, #0 - 8000d5e: 6078 str r0, [r7, #4] + 800132c: b590 push {r4, r7, lr} + 800132e: b093 sub sp, #76 @ 0x4c + 8001330: af00 add r7, sp, #0 + 8001332: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; - 8000d60: 2334 movs r3, #52 @ 0x34 - 8000d62: 18fb adds r3, r7, r3 - 8000d64: 0018 movs r0, r3 - 8000d66: 2314 movs r3, #20 - 8000d68: 001a movs r2, r3 - 8000d6a: 2100 movs r1, #0 - 8000d6c: f003 f8e6 bl 8003f3c + 8001334: 2334 movs r3, #52 @ 0x34 + 8001336: 18fb adds r3, r7, r3 + 8001338: 0018 movs r0, r3 + 800133a: 2314 movs r3, #20 + 800133c: 001a movs r2, r3 + 800133e: 2100 movs r1, #0 + 8001340: f003 fcfa bl 8004d38 RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - 8000d70: 2418 movs r4, #24 - 8000d72: 193b adds r3, r7, r4 - 8000d74: 0018 movs r0, r3 - 8000d76: 231c movs r3, #28 - 8000d78: 001a movs r2, r3 - 8000d7a: 2100 movs r1, #0 - 8000d7c: f003 f8de bl 8003f3c + 8001344: 2418 movs r4, #24 + 8001346: 193b adds r3, r7, r4 + 8001348: 0018 movs r0, r3 + 800134a: 231c movs r3, #28 + 800134c: 001a movs r2, r3 + 800134e: 2100 movs r1, #0 + 8001350: f003 fcf2 bl 8004d38 if(huart->Instance==USART1) - 8000d80: 687b ldr r3, [r7, #4] - 8000d82: 681b ldr r3, [r3, #0] - 8000d84: 4a3d ldr r2, [pc, #244] @ (8000e7c ) - 8000d86: 4293 cmp r3, r2 - 8000d88: d13e bne.n 8000e08 + 8001354: 687b ldr r3, [r7, #4] + 8001356: 681b ldr r3, [r3, #0] + 8001358: 4a68 ldr r2, [pc, #416] @ (80014fc ) + 800135a: 4293 cmp r3, r2 + 800135c: d13e bne.n 80013dc /* USER CODE END USART1_MspInit 0 */ /** Initializes the peripherals clocks */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1; - 8000d8a: 193b adds r3, r7, r4 - 8000d8c: 2201 movs r2, #1 - 8000d8e: 601a str r2, [r3, #0] + 800135e: 193b adds r3, r7, r4 + 8001360: 2201 movs r2, #1 + 8001362: 601a str r2, [r3, #0] PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK1; - 8000d90: 193b adds r3, r7, r4 - 8000d92: 2200 movs r2, #0 - 8000d94: 609a str r2, [r3, #8] + 8001364: 193b adds r3, r7, r4 + 8001366: 2200 movs r2, #0 + 8001368: 609a str r2, [r3, #8] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) - 8000d96: 193b adds r3, r7, r4 - 8000d98: 0018 movs r0, r3 - 8000d9a: f001 f921 bl 8001fe0 - 8000d9e: 1e03 subs r3, r0, #0 - 8000da0: d001 beq.n 8000da6 + 800136a: 193b adds r3, r7, r4 + 800136c: 0018 movs r0, r3 + 800136e: f001 fa99 bl 80028a4 + 8001372: 1e03 subs r3, r0, #0 + 8001374: d001 beq.n 800137a { Error_Handler(); - 8000da2: f7ff fe86 bl 8000ab2 + 8001376: f7ff fe97 bl 80010a8 } /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - 8000da6: 4b36 ldr r3, [pc, #216] @ (8000e80 ) - 8000da8: 6c1a ldr r2, [r3, #64] @ 0x40 - 8000daa: 4b35 ldr r3, [pc, #212] @ (8000e80 ) - 8000dac: 2180 movs r1, #128 @ 0x80 - 8000dae: 01c9 lsls r1, r1, #7 - 8000db0: 430a orrs r2, r1 - 8000db2: 641a str r2, [r3, #64] @ 0x40 - 8000db4: 4b32 ldr r3, [pc, #200] @ (8000e80 ) - 8000db6: 6c1a ldr r2, [r3, #64] @ 0x40 - 8000db8: 2380 movs r3, #128 @ 0x80 - 8000dba: 01db lsls r3, r3, #7 - 8000dbc: 4013 ands r3, r2 - 8000dbe: 617b str r3, [r7, #20] - 8000dc0: 697b ldr r3, [r7, #20] + 800137a: 4b61 ldr r3, [pc, #388] @ (8001500 ) + 800137c: 6c1a ldr r2, [r3, #64] @ 0x40 + 800137e: 4b60 ldr r3, [pc, #384] @ (8001500 ) + 8001380: 2180 movs r1, #128 @ 0x80 + 8001382: 01c9 lsls r1, r1, #7 + 8001384: 430a orrs r2, r1 + 8001386: 641a str r2, [r3, #64] @ 0x40 + 8001388: 4b5d ldr r3, [pc, #372] @ (8001500 ) + 800138a: 6c1a ldr r2, [r3, #64] @ 0x40 + 800138c: 2380 movs r3, #128 @ 0x80 + 800138e: 01db lsls r3, r3, #7 + 8001390: 4013 ands r3, r2 + 8001392: 617b str r3, [r7, #20] + 8001394: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOB_CLK_ENABLE(); - 8000dc2: 4b2f ldr r3, [pc, #188] @ (8000e80 ) - 8000dc4: 6b5a ldr r2, [r3, #52] @ 0x34 - 8000dc6: 4b2e ldr r3, [pc, #184] @ (8000e80 ) - 8000dc8: 2102 movs r1, #2 - 8000dca: 430a orrs r2, r1 - 8000dcc: 635a str r2, [r3, #52] @ 0x34 - 8000dce: 4b2c ldr r3, [pc, #176] @ (8000e80 ) - 8000dd0: 6b5b ldr r3, [r3, #52] @ 0x34 - 8000dd2: 2202 movs r2, #2 - 8000dd4: 4013 ands r3, r2 - 8000dd6: 613b str r3, [r7, #16] - 8000dd8: 693b ldr r3, [r7, #16] + 8001396: 4b5a ldr r3, [pc, #360] @ (8001500 ) + 8001398: 6b5a ldr r2, [r3, #52] @ 0x34 + 800139a: 4b59 ldr r3, [pc, #356] @ (8001500 ) + 800139c: 2102 movs r1, #2 + 800139e: 430a orrs r2, r1 + 80013a0: 635a str r2, [r3, #52] @ 0x34 + 80013a2: 4b57 ldr r3, [pc, #348] @ (8001500 ) + 80013a4: 6b5b ldr r3, [r3, #52] @ 0x34 + 80013a6: 2202 movs r2, #2 + 80013a8: 4013 ands r3, r2 + 80013aa: 613b str r3, [r7, #16] + 80013ac: 693b ldr r3, [r7, #16] /**USART1 GPIO Configuration PB6 ------> USART1_TX PB7 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; - 8000dda: 2134 movs r1, #52 @ 0x34 - 8000ddc: 187b adds r3, r7, r1 - 8000dde: 22c0 movs r2, #192 @ 0xc0 - 8000de0: 601a str r2, [r3, #0] + 80013ae: 2134 movs r1, #52 @ 0x34 + 80013b0: 187b adds r3, r7, r1 + 80013b2: 22c0 movs r2, #192 @ 0xc0 + 80013b4: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - 8000de2: 187b adds r3, r7, r1 - 8000de4: 2202 movs r2, #2 - 8000de6: 605a str r2, [r3, #4] + 80013b6: 187b adds r3, r7, r1 + 80013b8: 2202 movs r2, #2 + 80013ba: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; - 8000de8: 187b adds r3, r7, r1 - 8000dea: 2200 movs r2, #0 - 8000dec: 609a str r2, [r3, #8] + 80013bc: 187b adds r3, r7, r1 + 80013be: 2200 movs r2, #0 + 80013c0: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - 8000dee: 187b adds r3, r7, r1 - 8000df0: 2200 movs r2, #0 - 8000df2: 60da str r2, [r3, #12] + 80013c2: 187b adds r3, r7, r1 + 80013c4: 2200 movs r2, #0 + 80013c6: 60da str r2, [r3, #12] GPIO_InitStruct.Alternate = GPIO_AF0_USART1; - 8000df4: 187b adds r3, r7, r1 - 8000df6: 2200 movs r2, #0 - 8000df8: 611a str r2, [r3, #16] + 80013c8: 187b adds r3, r7, r1 + 80013ca: 2200 movs r2, #0 + 80013cc: 611a str r2, [r3, #16] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - 8000dfa: 187b adds r3, r7, r1 - 8000dfc: 4a21 ldr r2, [pc, #132] @ (8000e84 ) - 8000dfe: 0019 movs r1, r3 - 8000e00: 0010 movs r0, r2 - 8000e02: f000 fbab bl 800155c + 80013ce: 187b adds r3, r7, r1 + 80013d0: 4a4c ldr r2, [pc, #304] @ (8001504 ) + 80013d2: 0019 movs r1, r3 + 80013d4: 0010 movs r0, r2 + 80013d6: f000 fd07 bl 8001de8 /* USER CODE BEGIN USART2_MspInit 1 */ /* USER CODE END USART2_MspInit 1 */ } } - 8000e06: e035 b.n 8000e74 + 80013da: e08b b.n 80014f4 else if(huart->Instance==USART2) - 8000e08: 687b ldr r3, [r7, #4] - 8000e0a: 681b ldr r3, [r3, #0] - 8000e0c: 4a1e ldr r2, [pc, #120] @ (8000e88 ) - 8000e0e: 4293 cmp r3, r2 - 8000e10: d130 bne.n 8000e74 + 80013dc: 687b ldr r3, [r7, #4] + 80013de: 681b ldr r3, [r3, #0] + 80013e0: 4a49 ldr r2, [pc, #292] @ (8001508 ) + 80013e2: 4293 cmp r3, r2 + 80013e4: d000 beq.n 80013e8 + 80013e6: e085 b.n 80014f4 __HAL_RCC_USART2_CLK_ENABLE(); - 8000e12: 4b1b ldr r3, [pc, #108] @ (8000e80 ) - 8000e14: 6bda ldr r2, [r3, #60] @ 0x3c - 8000e16: 4b1a ldr r3, [pc, #104] @ (8000e80 ) - 8000e18: 2180 movs r1, #128 @ 0x80 - 8000e1a: 0289 lsls r1, r1, #10 - 8000e1c: 430a orrs r2, r1 - 8000e1e: 63da str r2, [r3, #60] @ 0x3c - 8000e20: 4b17 ldr r3, [pc, #92] @ (8000e80 ) - 8000e22: 6bda ldr r2, [r3, #60] @ 0x3c - 8000e24: 2380 movs r3, #128 @ 0x80 - 8000e26: 029b lsls r3, r3, #10 - 8000e28: 4013 ands r3, r2 - 8000e2a: 60fb str r3, [r7, #12] - 8000e2c: 68fb ldr r3, [r7, #12] + 80013e8: 4b45 ldr r3, [pc, #276] @ (8001500 ) + 80013ea: 6bda ldr r2, [r3, #60] @ 0x3c + 80013ec: 4b44 ldr r3, [pc, #272] @ (8001500 ) + 80013ee: 2180 movs r1, #128 @ 0x80 + 80013f0: 0289 lsls r1, r1, #10 + 80013f2: 430a orrs r2, r1 + 80013f4: 63da str r2, [r3, #60] @ 0x3c + 80013f6: 4b42 ldr r3, [pc, #264] @ (8001500 ) + 80013f8: 6bda ldr r2, [r3, #60] @ 0x3c + 80013fa: 2380 movs r3, #128 @ 0x80 + 80013fc: 029b lsls r3, r3, #10 + 80013fe: 4013 ands r3, r2 + 8001400: 60fb str r3, [r7, #12] + 8001402: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); - 8000e2e: 4b14 ldr r3, [pc, #80] @ (8000e80 ) - 8000e30: 6b5a ldr r2, [r3, #52] @ 0x34 - 8000e32: 4b13 ldr r3, [pc, #76] @ (8000e80 ) - 8000e34: 2101 movs r1, #1 - 8000e36: 430a orrs r2, r1 - 8000e38: 635a str r2, [r3, #52] @ 0x34 - 8000e3a: 4b11 ldr r3, [pc, #68] @ (8000e80 ) - 8000e3c: 6b5b ldr r3, [r3, #52] @ 0x34 - 8000e3e: 2201 movs r2, #1 - 8000e40: 4013 ands r3, r2 - 8000e42: 60bb str r3, [r7, #8] - 8000e44: 68bb ldr r3, [r7, #8] + 8001404: 4b3e ldr r3, [pc, #248] @ (8001500 ) + 8001406: 6b5a ldr r2, [r3, #52] @ 0x34 + 8001408: 4b3d ldr r3, [pc, #244] @ (8001500 ) + 800140a: 2101 movs r1, #1 + 800140c: 430a orrs r2, r1 + 800140e: 635a str r2, [r3, #52] @ 0x34 + 8001410: 4b3b ldr r3, [pc, #236] @ (8001500 ) + 8001412: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001414: 2201 movs r2, #1 + 8001416: 4013 ands r3, r2 + 8001418: 60bb str r3, [r7, #8] + 800141a: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5; - 8000e46: 2134 movs r1, #52 @ 0x34 - 8000e48: 187b adds r3, r7, r1 - 8000e4a: 2232 movs r2, #50 @ 0x32 - 8000e4c: 601a str r2, [r3, #0] + 800141c: 2134 movs r1, #52 @ 0x34 + 800141e: 187b adds r3, r7, r1 + 8001420: 2232 movs r2, #50 @ 0x32 + 8001422: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - 8000e4e: 187b adds r3, r7, r1 - 8000e50: 2202 movs r2, #2 - 8000e52: 605a str r2, [r3, #4] + 8001424: 187b adds r3, r7, r1 + 8001426: 2202 movs r2, #2 + 8001428: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; - 8000e54: 187b adds r3, r7, r1 - 8000e56: 2200 movs r2, #0 - 8000e58: 609a str r2, [r3, #8] + 800142a: 187b adds r3, r7, r1 + 800142c: 2200 movs r2, #0 + 800142e: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - 8000e5a: 187b adds r3, r7, r1 - 8000e5c: 2200 movs r2, #0 - 8000e5e: 60da str r2, [r3, #12] + 8001430: 187b adds r3, r7, r1 + 8001432: 2200 movs r2, #0 + 8001434: 60da str r2, [r3, #12] GPIO_InitStruct.Alternate = GPIO_AF1_USART2; - 8000e60: 187b adds r3, r7, r1 - 8000e62: 2201 movs r2, #1 - 8000e64: 611a str r2, [r3, #16] + 8001436: 187b adds r3, r7, r1 + 8001438: 2201 movs r2, #1 + 800143a: 611a str r2, [r3, #16] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - 8000e66: 187a adds r2, r7, r1 - 8000e68: 23a0 movs r3, #160 @ 0xa0 - 8000e6a: 05db lsls r3, r3, #23 - 8000e6c: 0011 movs r1, r2 - 8000e6e: 0018 movs r0, r3 - 8000e70: f000 fb74 bl 800155c + 800143c: 187a adds r2, r7, r1 + 800143e: 23a0 movs r3, #160 @ 0xa0 + 8001440: 05db lsls r3, r3, #23 + 8001442: 0011 movs r1, r2 + 8001444: 0018 movs r0, r3 + 8001446: f000 fccf bl 8001de8 + hdma_usart2_rx.Instance = DMA1_Channel2; + 800144a: 4b30 ldr r3, [pc, #192] @ (800150c ) + 800144c: 4a30 ldr r2, [pc, #192] @ (8001510 ) + 800144e: 601a str r2, [r3, #0] + hdma_usart2_rx.Init.Request = DMA_REQUEST_USART2_RX; + 8001450: 4b2e ldr r3, [pc, #184] @ (800150c ) + 8001452: 2234 movs r2, #52 @ 0x34 + 8001454: 605a str r2, [r3, #4] + hdma_usart2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; + 8001456: 4b2d ldr r3, [pc, #180] @ (800150c ) + 8001458: 2200 movs r2, #0 + 800145a: 609a str r2, [r3, #8] + hdma_usart2_rx.Init.PeriphInc = DMA_PINC_DISABLE; + 800145c: 4b2b ldr r3, [pc, #172] @ (800150c ) + 800145e: 2200 movs r2, #0 + 8001460: 60da str r2, [r3, #12] + hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE; + 8001462: 4b2a ldr r3, [pc, #168] @ (800150c ) + 8001464: 2280 movs r2, #128 @ 0x80 + 8001466: 611a str r2, [r3, #16] + hdma_usart2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + 8001468: 4b28 ldr r3, [pc, #160] @ (800150c ) + 800146a: 2200 movs r2, #0 + 800146c: 615a str r2, [r3, #20] + hdma_usart2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + 800146e: 4b27 ldr r3, [pc, #156] @ (800150c ) + 8001470: 2200 movs r2, #0 + 8001472: 619a str r2, [r3, #24] + hdma_usart2_rx.Init.Mode = DMA_NORMAL; + 8001474: 4b25 ldr r3, [pc, #148] @ (800150c ) + 8001476: 2200 movs r2, #0 + 8001478: 61da str r2, [r3, #28] + hdma_usart2_rx.Init.Priority = DMA_PRIORITY_MEDIUM; + 800147a: 4b24 ldr r3, [pc, #144] @ (800150c ) + 800147c: 2280 movs r2, #128 @ 0x80 + 800147e: 0152 lsls r2, r2, #5 + 8001480: 621a str r2, [r3, #32] + if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK) + 8001482: 4b22 ldr r3, [pc, #136] @ (800150c ) + 8001484: 0018 movs r0, r3 + 8001486: f000 fa5b bl 8001940 + 800148a: 1e03 subs r3, r0, #0 + 800148c: d001 beq.n 8001492 + Error_Handler(); + 800148e: f7ff fe0b bl 80010a8 + __HAL_LINKDMA(huart,hdmarx,hdma_usart2_rx); + 8001492: 687b ldr r3, [r7, #4] + 8001494: 2180 movs r1, #128 @ 0x80 + 8001496: 4a1d ldr r2, [pc, #116] @ (800150c ) + 8001498: 505a str r2, [r3, r1] + 800149a: 4b1c ldr r3, [pc, #112] @ (800150c ) + 800149c: 687a ldr r2, [r7, #4] + 800149e: 629a str r2, [r3, #40] @ 0x28 + hdma_usart2_tx.Instance = DMA1_Channel1; + 80014a0: 4b1c ldr r3, [pc, #112] @ (8001514 ) + 80014a2: 4a1d ldr r2, [pc, #116] @ (8001518 ) + 80014a4: 601a str r2, [r3, #0] + hdma_usart2_tx.Init.Request = DMA_REQUEST_USART2_TX; + 80014a6: 4b1b ldr r3, [pc, #108] @ (8001514 ) + 80014a8: 2235 movs r2, #53 @ 0x35 + 80014aa: 605a str r2, [r3, #4] + hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; + 80014ac: 4b19 ldr r3, [pc, #100] @ (8001514 ) + 80014ae: 2210 movs r2, #16 + 80014b0: 609a str r2, [r3, #8] + hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE; + 80014b2: 4b18 ldr r3, [pc, #96] @ (8001514 ) + 80014b4: 2200 movs r2, #0 + 80014b6: 60da str r2, [r3, #12] + hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE; + 80014b8: 4b16 ldr r3, [pc, #88] @ (8001514 ) + 80014ba: 2280 movs r2, #128 @ 0x80 + 80014bc: 611a str r2, [r3, #16] + hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + 80014be: 4b15 ldr r3, [pc, #84] @ (8001514 ) + 80014c0: 2200 movs r2, #0 + 80014c2: 615a str r2, [r3, #20] + hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + 80014c4: 4b13 ldr r3, [pc, #76] @ (8001514 ) + 80014c6: 2200 movs r2, #0 + 80014c8: 619a str r2, [r3, #24] + hdma_usart2_tx.Init.Mode = DMA_NORMAL; + 80014ca: 4b12 ldr r3, [pc, #72] @ (8001514 ) + 80014cc: 2200 movs r2, #0 + 80014ce: 61da str r2, [r3, #28] + hdma_usart2_tx.Init.Priority = DMA_PRIORITY_HIGH; + 80014d0: 4b10 ldr r3, [pc, #64] @ (8001514 ) + 80014d2: 2280 movs r2, #128 @ 0x80 + 80014d4: 0192 lsls r2, r2, #6 + 80014d6: 621a str r2, [r3, #32] + if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK) + 80014d8: 4b0e ldr r3, [pc, #56] @ (8001514 ) + 80014da: 0018 movs r0, r3 + 80014dc: f000 fa30 bl 8001940 + 80014e0: 1e03 subs r3, r0, #0 + 80014e2: d001 beq.n 80014e8 + Error_Handler(); + 80014e4: f7ff fde0 bl 80010a8 + __HAL_LINKDMA(huart,hdmatx,hdma_usart2_tx); + 80014e8: 687b ldr r3, [r7, #4] + 80014ea: 4a0a ldr r2, [pc, #40] @ (8001514 ) + 80014ec: 67da str r2, [r3, #124] @ 0x7c + 80014ee: 4b09 ldr r3, [pc, #36] @ (8001514 ) + 80014f0: 687a ldr r2, [r7, #4] + 80014f2: 629a str r2, [r3, #40] @ 0x28 } - 8000e74: 46c0 nop @ (mov r8, r8) - 8000e76: 46bd mov sp, r7 - 8000e78: b013 add sp, #76 @ 0x4c - 8000e7a: bd90 pop {r4, r7, pc} - 8000e7c: 40013800 .word 0x40013800 - 8000e80: 40021000 .word 0x40021000 - 8000e84: 50000400 .word 0x50000400 - 8000e88: 40004400 .word 0x40004400 + 80014f4: 46c0 nop @ (mov r8, r8) + 80014f6: 46bd mov sp, r7 + 80014f8: b013 add sp, #76 @ 0x4c + 80014fa: bd90 pop {r4, r7, pc} + 80014fc: 40013800 .word 0x40013800 + 8001500: 40021000 .word 0x40021000 + 8001504: 50000400 .word 0x50000400 + 8001508: 40004400 .word 0x40004400 + 800150c: 200002e4 .word 0x200002e4 + 8001510: 4002001c .word 0x4002001c + 8001514: 20000340 .word 0x20000340 + 8001518: 40020008 .word 0x40020008 -08000e8c : +0800151c : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { - 8000e8c: b580 push {r7, lr} - 8000e8e: af00 add r7, sp, #0 + 800151c: b580 push {r7, lr} + 800151e: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) - 8000e90: 46c0 nop @ (mov r8, r8) - 8000e92: e7fd b.n 8000e90 + 8001520: 46c0 nop @ (mov r8, r8) + 8001522: e7fd b.n 8001520 -08000e94 : +08001524 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { - 8000e94: b580 push {r7, lr} - 8000e96: af00 add r7, sp, #0 + 8001524: b580 push {r7, lr} + 8001526: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) - 8000e98: 46c0 nop @ (mov r8, r8) - 8000e9a: e7fd b.n 8000e98 + 8001528: 46c0 nop @ (mov r8, r8) + 800152a: e7fd b.n 8001528 -08000e9c : +0800152c : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { - 8000e9c: b580 push {r7, lr} - 8000e9e: af00 add r7, sp, #0 + 800152c: b580 push {r7, lr} + 800152e: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } - 8000ea0: 46c0 nop @ (mov r8, r8) - 8000ea2: 46bd mov sp, r7 - 8000ea4: bd80 pop {r7, pc} + 8001530: 46c0 nop @ (mov r8, r8) + 8001532: 46bd mov sp, r7 + 8001534: bd80 pop {r7, pc} -08000ea6 : +08001536 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { - 8000ea6: b580 push {r7, lr} - 8000ea8: af00 add r7, sp, #0 + 8001536: b580 push {r7, lr} + 8001538: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } - 8000eaa: 46c0 nop @ (mov r8, r8) - 8000eac: 46bd mov sp, r7 - 8000eae: bd80 pop {r7, pc} + 800153a: 46c0 nop @ (mov r8, r8) + 800153c: 46bd mov sp, r7 + 800153e: bd80 pop {r7, pc} -08000eb0 : +08001540 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { - 8000eb0: b580 push {r7, lr} - 8000eb2: af00 add r7, sp, #0 + 8001540: b580 push {r7, lr} + 8001542: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); - 8000eb4: f000 f8cc bl 8001050 + 8001544: f000 f8e4 bl 8001710 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } - 8000eb8: 46c0 nop @ (mov r8, r8) - 8000eba: 46bd mov sp, r7 - 8000ebc: bd80 pop {r7, pc} + 8001548: 46c0 nop @ (mov r8, r8) + 800154a: 46bd mov sp, r7 + 800154c: bd80 pop {r7, pc} -08000ebe : +0800154e : /** * @brief This function handles EXTI line 4 to 15 interrupts. */ void EXTI4_15_IRQHandler(void) { - 8000ebe: b580 push {r7, lr} - 8000ec0: af00 add r7, sp, #0 + 800154e: b580 push {r7, lr} + 8001550: af00 add r7, sp, #0 /* USER CODE BEGIN EXTI4_15_IRQn 0 */ /* USER CODE END EXTI4_15_IRQn 0 */ HAL_GPIO_EXTI_IRQHandler(SW2_Pin); - 8000ec2: 2380 movs r3, #128 @ 0x80 - 8000ec4: 005b lsls r3, r3, #1 - 8000ec6: 0018 movs r0, r3 - 8000ec8: f000 fcd8 bl 800187c + 8001552: 2380 movs r3, #128 @ 0x80 + 8001554: 005b lsls r3, r3, #1 + 8001556: 0018 movs r0, r3 + 8001558: f000 fdf2 bl 8002140 HAL_GPIO_EXTI_IRQHandler(SW1_Pin); - 8000ecc: 2380 movs r3, #128 @ 0x80 - 8000ece: 009b lsls r3, r3, #2 - 8000ed0: 0018 movs r0, r3 - 8000ed2: f000 fcd3 bl 800187c + 800155c: 2380 movs r3, #128 @ 0x80 + 800155e: 009b lsls r3, r3, #2 + 8001560: 0018 movs r0, r3 + 8001562: f000 fded bl 8002140 /* USER CODE BEGIN EXTI4_15_IRQn 1 */ /* USER CODE END EXTI4_15_IRQn 1 */ } - 8000ed6: 46c0 nop @ (mov r8, r8) - 8000ed8: 46bd mov sp, r7 - 8000eda: bd80 pop {r7, pc} + 8001566: 46c0 nop @ (mov r8, r8) + 8001568: 46bd mov sp, r7 + 800156a: bd80 pop {r7, pc} -08000edc : +0800156c : /** * @brief This function handles DMA1 channel 1 interrupt. */ void DMA1_Channel1_IRQHandler(void) { - 8000edc: b580 push {r7, lr} - 8000ede: af00 add r7, sp, #0 + 800156c: b580 push {r7, lr} + 800156e: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */ /* USER CODE END DMA1_Channel1_IRQn 0 */ - HAL_DMA_IRQHandler(&hdma_tim3_up); - 8000ee0: 4b03 ldr r3, [pc, #12] @ (8000ef0 ) - 8000ee2: 0018 movs r0, r3 - 8000ee4: f000 fa38 bl 8001358 + HAL_DMA_IRQHandler(&hdma_usart2_tx); + 8001570: 4b03 ldr r3, [pc, #12] @ (8001580 ) + 8001572: 0018 movs r0, r3 + 8001574: f000 faf6 bl 8001b64 /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */ /* USER CODE END DMA1_Channel1_IRQn 1 */ } - 8000ee8: 46c0 nop @ (mov r8, r8) - 8000eea: 46bd mov sp, r7 - 8000eec: bd80 pop {r7, pc} - 8000eee: 46c0 nop @ (mov r8, r8) - 8000ef0: 20000158 .word 0x20000158 + 8001578: 46c0 nop @ (mov r8, r8) + 800157a: 46bd mov sp, r7 + 800157c: bd80 pop {r7, pc} + 800157e: 46c0 nop @ (mov r8, r8) + 8001580: 20000340 .word 0x20000340 -08000ef4 : +08001584 : + +/** + * @brief This function handles DMA1 channel 2 and channel 3 interrupts. + */ +void DMA1_Channel2_3_IRQHandler(void) +{ + 8001584: b580 push {r7, lr} + 8001586: af00 add r7, sp, #0 + /* USER CODE BEGIN DMA1_Channel2_3_IRQn 0 */ + + /* USER CODE END DMA1_Channel2_3_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_usart2_rx); + 8001588: 4b03 ldr r3, [pc, #12] @ (8001598 ) + 800158a: 0018 movs r0, r3 + 800158c: f000 faea bl 8001b64 + /* USER CODE BEGIN DMA1_Channel2_3_IRQn 1 */ + + /* USER CODE END DMA1_Channel2_3_IRQn 1 */ +} + 8001590: 46c0 nop @ (mov r8, r8) + 8001592: 46bd mov sp, r7 + 8001594: bd80 pop {r7, pc} + 8001596: 46c0 nop @ (mov r8, r8) + 8001598: 200002e4 .word 0x200002e4 + +0800159c : + +/** + * @brief This function handles TIM14 global interrupt. + */ +void TIM14_IRQHandler(void) +{ + 800159c: b580 push {r7, lr} + 800159e: af00 add r7, sp, #0 + /* USER CODE BEGIN TIM14_IRQn 0 */ + + /* USER CODE END TIM14_IRQn 0 */ + HAL_TIM_IRQHandler(&htim14); + 80015a0: 4b03 ldr r3, [pc, #12] @ (80015b0 ) + 80015a2: 0018 movs r0, r3 + 80015a4: f001 fbca bl 8002d3c + /* USER CODE BEGIN TIM14_IRQn 1 */ + + /* USER CODE END TIM14_IRQn 1 */ +} + 80015a8: 46c0 nop @ (mov r8, r8) + 80015aa: 46bd mov sp, r7 + 80015ac: bd80 pop {r7, pc} + 80015ae: 46c0 nop @ (mov r8, r8) + 80015b0: 200000d8 .word 0x200000d8 + +080015b4 : /** * @brief This function handles TIM16 global interrupt. */ void TIM16_IRQHandler(void) { - 8000ef4: b580 push {r7, lr} - 8000ef6: af00 add r7, sp, #0 + 80015b4: b580 push {r7, lr} + 80015b6: af00 add r7, sp, #0 /* USER CODE BEGIN TIM16_IRQn 0 */ /* USER CODE END TIM16_IRQn 0 */ HAL_TIM_IRQHandler(&htim16); - 8000ef8: 4b03 ldr r3, [pc, #12] @ (8000f08 ) - 8000efa: 0018 movs r0, r3 - 8000efc: f001 fabc bl 8002478 + 80015b8: 4b03 ldr r3, [pc, #12] @ (80015c8 ) + 80015ba: 0018 movs r0, r3 + 80015bc: f001 fbbe bl 8002d3c /* USER CODE BEGIN TIM16_IRQn 1 */ /* USER CODE END TIM16_IRQn 1 */ } - 8000f00: 46c0 nop @ (mov r8, r8) - 8000f02: 46bd mov sp, r7 - 8000f04: bd80 pop {r7, pc} - 8000f06: 46c0 nop @ (mov r8, r8) - 8000f08: 200000c0 .word 0x200000c0 + 80015c0: 46c0 nop @ (mov r8, r8) + 80015c2: 46bd mov sp, r7 + 80015c4: bd80 pop {r7, pc} + 80015c6: 46c0 nop @ (mov r8, r8) + 80015c8: 20000124 .word 0x20000124 -08000f0c : +080015cc : /** * @brief This function handles TIM17 global interrupt. */ void TIM17_IRQHandler(void) { - 8000f0c: b580 push {r7, lr} - 8000f0e: af00 add r7, sp, #0 + 80015cc: b580 push {r7, lr} + 80015ce: af00 add r7, sp, #0 /* USER CODE BEGIN TIM17_IRQn 0 */ /* USER CODE END TIM17_IRQn 0 */ HAL_TIM_IRQHandler(&htim17); - 8000f10: 4b03 ldr r3, [pc, #12] @ (8000f20 ) - 8000f12: 0018 movs r0, r3 - 8000f14: f001 fab0 bl 8002478 + 80015d0: 4b03 ldr r3, [pc, #12] @ (80015e0 ) + 80015d2: 0018 movs r0, r3 + 80015d4: f001 fbb2 bl 8002d3c /* USER CODE BEGIN TIM17_IRQn 1 */ /* USER CODE END TIM17_IRQn 1 */ } - 8000f18: 46c0 nop @ (mov r8, r8) - 8000f1a: 46bd mov sp, r7 - 8000f1c: bd80 pop {r7, pc} - 8000f1e: 46c0 nop @ (mov r8, r8) - 8000f20: 2000010c .word 0x2000010c + 80015d8: 46c0 nop @ (mov r8, r8) + 80015da: 46bd mov sp, r7 + 80015dc: bd80 pop {r7, pc} + 80015de: 46c0 nop @ (mov r8, r8) + 80015e0: 20000170 .word 0x20000170 -08000f24 : +080015e4 : * @brief Setup the microcontroller system. * @param None * @retval None */ void SystemInit(void) { - 8000f24: b580 push {r7, lr} - 8000f26: af00 add r7, sp, #0 + 80015e4: b580 push {r7, lr} + 80015e6: af00 add r7, sp, #0 /* Configure the Vector Table location add offset address ------------------*/ #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #else SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ - 8000f28: 4b03 ldr r3, [pc, #12] @ (8000f38 ) - 8000f2a: 2280 movs r2, #128 @ 0x80 - 8000f2c: 0512 lsls r2, r2, #20 - 8000f2e: 609a str r2, [r3, #8] + 80015e8: 4b03 ldr r3, [pc, #12] @ (80015f8 ) + 80015ea: 2280 movs r2, #128 @ 0x80 + 80015ec: 0512 lsls r2, r2, #20 + 80015ee: 609a str r2, [r3, #8] #endif } - 8000f30: 46c0 nop @ (mov r8, r8) - 8000f32: 46bd mov sp, r7 - 8000f34: bd80 pop {r7, pc} - 8000f36: 46c0 nop @ (mov r8, r8) - 8000f38: e000ed00 .word 0xe000ed00 + 80015f0: 46c0 nop @ (mov r8, r8) + 80015f2: 46bd mov sp, r7 + 80015f4: bd80 pop {r7, pc} + 80015f6: 46c0 nop @ (mov r8, r8) + 80015f8: e000ed00 .word 0xe000ed00 -08000f3c : +080015fc : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr r0, =_estack - 8000f3c: 480d ldr r0, [pc, #52] @ (8000f74 ) + 80015fc: 480d ldr r0, [pc, #52] @ (8001634 ) mov sp, r0 /* set stack pointer */ - 8000f3e: 4685 mov sp, r0 + 80015fe: 4685 mov sp, r0 /* Call the clock system initialization function.*/ bl SystemInit - 8000f40: f7ff fff0 bl 8000f24 + 8001600: f7ff fff0 bl 80015e4 /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 - 8000f44: 2100 movs r1, #0 + 8001604: 2100 movs r1, #0 b LoopCopyDataInit - 8000f46: e003 b.n 8000f50 + 8001606: e003 b.n 8001610 -08000f48 : +08001608 : CopyDataInit: ldr r3, =_sidata - 8000f48: 4b0b ldr r3, [pc, #44] @ (8000f78 ) + 8001608: 4b0b ldr r3, [pc, #44] @ (8001638 ) ldr r3, [r3, r1] - 8000f4a: 585b ldr r3, [r3, r1] + 800160a: 585b ldr r3, [r3, r1] str r3, [r0, r1] - 8000f4c: 5043 str r3, [r0, r1] + 800160c: 5043 str r3, [r0, r1] adds r1, r1, #4 - 8000f4e: 3104 adds r1, #4 + 800160e: 3104 adds r1, #4 -08000f50 : +08001610 : LoopCopyDataInit: ldr r0, =_sdata - 8000f50: 480a ldr r0, [pc, #40] @ (8000f7c ) + 8001610: 480a ldr r0, [pc, #40] @ (800163c ) ldr r3, =_edata - 8000f52: 4b0b ldr r3, [pc, #44] @ (8000f80 ) + 8001612: 4b0b ldr r3, [pc, #44] @ (8001640 ) adds r2, r0, r1 - 8000f54: 1842 adds r2, r0, r1 + 8001614: 1842 adds r2, r0, r1 cmp r2, r3 - 8000f56: 429a cmp r2, r3 + 8001616: 429a cmp r2, r3 bcc CopyDataInit - 8000f58: d3f6 bcc.n 8000f48 + 8001618: d3f6 bcc.n 8001608 ldr r2, =_sbss - 8000f5a: 4a0a ldr r2, [pc, #40] @ (8000f84 ) + 800161a: 4a0a ldr r2, [pc, #40] @ (8001644 ) b LoopFillZerobss - 8000f5c: e002 b.n 8000f64 + 800161c: e002 b.n 8001624 -08000f5e : +0800161e : /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 - 8000f5e: 2300 movs r3, #0 + 800161e: 2300 movs r3, #0 str r3, [r2] - 8000f60: 6013 str r3, [r2, #0] + 8001620: 6013 str r3, [r2, #0] adds r2, r2, #4 - 8000f62: 3204 adds r2, #4 + 8001622: 3204 adds r2, #4 -08000f64 : +08001624 : LoopFillZerobss: ldr r3, = _ebss - 8000f64: 4b08 ldr r3, [pc, #32] @ (8000f88 ) + 8001624: 4b08 ldr r3, [pc, #32] @ (8001648 ) cmp r2, r3 - 8000f66: 429a cmp r2, r3 + 8001626: 429a cmp r2, r3 bcc FillZerobss - 8000f68: d3f9 bcc.n 8000f5e + 8001628: d3f9 bcc.n 800161e /* Call static constructors */ bl __libc_init_array - 8000f6a: f002 ffef bl 8003f4c <__libc_init_array> + 800162a: f003 fb8d bl 8004d48 <__libc_init_array> /* Call the application's entry point.*/ bl main - 8000f6e: f7ff fa41 bl 80003f4
+ 800162e: f7fe ffcb bl 80005c8
-08000f72 : +08001632 : LoopForever: b LoopForever - 8000f72: e7fe b.n 8000f72 + 8001632: e7fe b.n 8001632 ldr r0, =_estack - 8000f74: 20003000 .word 0x20003000 + 8001634: 20003000 .word 0x20003000 ldr r3, =_sidata - 8000f78: 08004090 .word 0x08004090 + 8001638: 08004ea0 .word 0x08004ea0 ldr r0, =_sdata - 8000f7c: 20000000 .word 0x20000000 + 800163c: 20000000 .word 0x20000000 ldr r3, =_edata - 8000f80: 2000000c .word 0x2000000c + 8001640: 20000024 .word 0x20000024 ldr r2, =_sbss - 8000f84: 2000000c .word 0x2000000c + 8001644: 20000024 .word 0x20000024 ldr r3, = _ebss - 8000f88: 200002e0 .word 0x200002e0 + 8001648: 200004b0 .word 0x200004b0 -08000f8c : +0800164c : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop - 8000f8c: e7fe b.n 8000f8c + 800164c: e7fe b.n 800164c -08000f8e : +0800164e : * each 1ms in the SysTick_Handler() interrupt handler. * * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { - 8000f8e: b580 push {r7, lr} - 8000f90: b082 sub sp, #8 - 8000f92: af00 add r7, sp, #0 + 800164e: b580 push {r7, lr} + 8001650: b082 sub sp, #8 + 8001652: af00 add r7, sp, #0 HAL_StatusTypeDef status = HAL_OK; - 8000f94: 1dfb adds r3, r7, #7 - 8000f96: 2200 movs r2, #0 - 8000f98: 701a strb r2, [r3, #0] + 8001654: 1dfb adds r3, r7, #7 + 8001656: 2200 movs r2, #0 + 8001658: 701a strb r2, [r3, #0] #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); #endif /* PREFETCH_ENABLE */ /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */ if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) - 8000f9a: 2003 movs r0, #3 - 8000f9c: f000 f80e bl 8000fbc - 8000fa0: 1e03 subs r3, r0, #0 - 8000fa2: d003 beq.n 8000fac + 800165a: 2003 movs r0, #3 + 800165c: f000 f80e bl 800167c + 8001660: 1e03 subs r3, r0, #0 + 8001662: d003 beq.n 800166c { status = HAL_ERROR; - 8000fa4: 1dfb adds r3, r7, #7 - 8000fa6: 2201 movs r2, #1 - 8000fa8: 701a strb r2, [r3, #0] - 8000faa: e001 b.n 8000fb0 + 8001664: 1dfb adds r3, r7, #7 + 8001666: 2201 movs r2, #1 + 8001668: 701a strb r2, [r3, #0] + 800166a: e001 b.n 8001670 } else { /* Init the low level hardware */ HAL_MspInit(); - 8000fac: f7ff fd88 bl 8000ac0 + 800166c: f7ff fd22 bl 80010b4 } /* Return function status */ return status; - 8000fb0: 1dfb adds r3, r7, #7 - 8000fb2: 781b ldrb r3, [r3, #0] + 8001670: 1dfb adds r3, r7, #7 + 8001672: 781b ldrb r3, [r3, #0] } - 8000fb4: 0018 movs r0, r3 - 8000fb6: 46bd mov sp, r7 - 8000fb8: b002 add sp, #8 - 8000fba: bd80 pop {r7, pc} + 8001674: 0018 movs r0, r3 + 8001676: 46bd mov sp, r7 + 8001678: b002 add sp, #8 + 800167a: bd80 pop {r7, pc} -08000fbc : +0800167c : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { - 8000fbc: b590 push {r4, r7, lr} - 8000fbe: b085 sub sp, #20 - 8000fc0: af00 add r7, sp, #0 - 8000fc2: 6078 str r0, [r7, #4] + 800167c: b590 push {r4, r7, lr} + 800167e: b085 sub sp, #20 + 8001680: af00 add r7, sp, #0 + 8001682: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; - 8000fc4: 230f movs r3, #15 - 8000fc6: 18fb adds r3, r7, r3 - 8000fc8: 2200 movs r2, #0 - 8000fca: 701a strb r2, [r3, #0] + 8001684: 230f movs r3, #15 + 8001686: 18fb adds r3, r7, r3 + 8001688: 2200 movs r2, #0 + 800168a: 701a strb r2, [r3, #0] if ((uint32_t)uwTickFreq != 0UL) - 8000fcc: 4b1d ldr r3, [pc, #116] @ (8001044 ) - 8000fce: 781b ldrb r3, [r3, #0] - 8000fd0: 2b00 cmp r3, #0 - 8000fd2: d02b beq.n 800102c + 800168c: 4b1d ldr r3, [pc, #116] @ (8001704 ) + 800168e: 781b ldrb r3, [r3, #0] + 8001690: 2b00 cmp r3, #0 + 8001692: d02b beq.n 80016ec { /*Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) == 0U) - 8000fd4: 4b1c ldr r3, [pc, #112] @ (8001048 ) - 8000fd6: 681c ldr r4, [r3, #0] - 8000fd8: 4b1a ldr r3, [pc, #104] @ (8001044 ) - 8000fda: 781b ldrb r3, [r3, #0] - 8000fdc: 0019 movs r1, r3 - 8000fde: 23fa movs r3, #250 @ 0xfa - 8000fe0: 0098 lsls r0, r3, #2 - 8000fe2: f7ff f891 bl 8000108 <__udivsi3> - 8000fe6: 0003 movs r3, r0 - 8000fe8: 0019 movs r1, r3 - 8000fea: 0020 movs r0, r4 - 8000fec: f7ff f88c bl 8000108 <__udivsi3> - 8000ff0: 0003 movs r3, r0 - 8000ff2: 0018 movs r0, r3 - 8000ff4: f000 f919 bl 800122a - 8000ff8: 1e03 subs r3, r0, #0 - 8000ffa: d112 bne.n 8001022 + 8001694: 4b1c ldr r3, [pc, #112] @ (8001708 ) + 8001696: 681c ldr r4, [r3, #0] + 8001698: 4b1a ldr r3, [pc, #104] @ (8001704 ) + 800169a: 781b ldrb r3, [r3, #0] + 800169c: 0019 movs r1, r3 + 800169e: 23fa movs r3, #250 @ 0xfa + 80016a0: 0098 lsls r0, r3, #2 + 80016a2: f7fe fd31 bl 8000108 <__udivsi3> + 80016a6: 0003 movs r3, r0 + 80016a8: 0019 movs r1, r3 + 80016aa: 0020 movs r0, r4 + 80016ac: f7fe fd2c bl 8000108 <__udivsi3> + 80016b0: 0003 movs r3, r0 + 80016b2: 0018 movs r0, r3 + 80016b4: f000 f937 bl 8001926 + 80016b8: 1e03 subs r3, r0, #0 + 80016ba: d112 bne.n 80016e2 { /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) - 8000ffc: 687b ldr r3, [r7, #4] - 8000ffe: 2b03 cmp r3, #3 - 8001000: d80a bhi.n 8001018 + 80016bc: 687b ldr r3, [r7, #4] + 80016be: 2b03 cmp r3, #3 + 80016c0: d80a bhi.n 80016d8 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); - 8001002: 6879 ldr r1, [r7, #4] - 8001004: 2301 movs r3, #1 - 8001006: 425b negs r3, r3 - 8001008: 2200 movs r2, #0 - 800100a: 0018 movs r0, r3 - 800100c: f000 f8e8 bl 80011e0 + 80016c2: 6879 ldr r1, [r7, #4] + 80016c4: 2301 movs r3, #1 + 80016c6: 425b negs r3, r3 + 80016c8: 2200 movs r2, #0 + 80016ca: 0018 movs r0, r3 + 80016cc: f000 f906 bl 80018dc uwTickPrio = TickPriority; - 8001010: 4b0e ldr r3, [pc, #56] @ (800104c ) - 8001012: 687a ldr r2, [r7, #4] - 8001014: 601a str r2, [r3, #0] - 8001016: e00d b.n 8001034 + 80016d0: 4b0e ldr r3, [pc, #56] @ (800170c ) + 80016d2: 687a ldr r2, [r7, #4] + 80016d4: 601a str r2, [r3, #0] + 80016d6: e00d b.n 80016f4 } else { status = HAL_ERROR; - 8001018: 230f movs r3, #15 - 800101a: 18fb adds r3, r7, r3 - 800101c: 2201 movs r2, #1 - 800101e: 701a strb r2, [r3, #0] - 8001020: e008 b.n 8001034 + 80016d8: 230f movs r3, #15 + 80016da: 18fb adds r3, r7, r3 + 80016dc: 2201 movs r2, #1 + 80016de: 701a strb r2, [r3, #0] + 80016e0: e008 b.n 80016f4 } } else { status = HAL_ERROR; - 8001022: 230f movs r3, #15 - 8001024: 18fb adds r3, r7, r3 - 8001026: 2201 movs r2, #1 - 8001028: 701a strb r2, [r3, #0] - 800102a: e003 b.n 8001034 + 80016e2: 230f movs r3, #15 + 80016e4: 18fb adds r3, r7, r3 + 80016e6: 2201 movs r2, #1 + 80016e8: 701a strb r2, [r3, #0] + 80016ea: e003 b.n 80016f4 } } else { status = HAL_ERROR; - 800102c: 230f movs r3, #15 - 800102e: 18fb adds r3, r7, r3 - 8001030: 2201 movs r2, #1 - 8001032: 701a strb r2, [r3, #0] + 80016ec: 230f movs r3, #15 + 80016ee: 18fb adds r3, r7, r3 + 80016f0: 2201 movs r2, #1 + 80016f2: 701a strb r2, [r3, #0] } /* Return function status */ return status; - 8001034: 230f movs r3, #15 - 8001036: 18fb adds r3, r7, r3 - 8001038: 781b ldrb r3, [r3, #0] + 80016f4: 230f movs r3, #15 + 80016f6: 18fb adds r3, r7, r3 + 80016f8: 781b ldrb r3, [r3, #0] } - 800103a: 0018 movs r0, r3 - 800103c: 46bd mov sp, r7 - 800103e: b005 add sp, #20 - 8001040: bd90 pop {r4, r7, pc} - 8001042: 46c0 nop @ (mov r8, r8) - 8001044: 20000008 .word 0x20000008 - 8001048: 20000000 .word 0x20000000 - 800104c: 20000004 .word 0x20000004 + 80016fa: 0018 movs r0, r3 + 80016fc: 46bd mov sp, r7 + 80016fe: b005 add sp, #20 + 8001700: bd90 pop {r4, r7, pc} + 8001702: 46c0 nop @ (mov r8, r8) + 8001704: 20000020 .word 0x20000020 + 8001708: 20000018 .word 0x20000018 + 800170c: 2000001c .word 0x2000001c -08001050 : +08001710 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { - 8001050: b580 push {r7, lr} - 8001052: af00 add r7, sp, #0 + 8001710: b580 push {r7, lr} + 8001712: af00 add r7, sp, #0 uwTick += (uint32_t)uwTickFreq; - 8001054: 4b05 ldr r3, [pc, #20] @ (800106c ) - 8001056: 781b ldrb r3, [r3, #0] - 8001058: 001a movs r2, r3 - 800105a: 4b05 ldr r3, [pc, #20] @ (8001070 ) - 800105c: 681b ldr r3, [r3, #0] - 800105e: 18d2 adds r2, r2, r3 - 8001060: 4b03 ldr r3, [pc, #12] @ (8001070 ) - 8001062: 601a str r2, [r3, #0] + 8001714: 4b05 ldr r3, [pc, #20] @ (800172c ) + 8001716: 781b ldrb r3, [r3, #0] + 8001718: 001a movs r2, r3 + 800171a: 4b05 ldr r3, [pc, #20] @ (8001730 ) + 800171c: 681b ldr r3, [r3, #0] + 800171e: 18d2 adds r2, r2, r3 + 8001720: 4b03 ldr r3, [pc, #12] @ (8001730 ) + 8001722: 601a str r2, [r3, #0] } - 8001064: 46c0 nop @ (mov r8, r8) - 8001066: 46bd mov sp, r7 - 8001068: bd80 pop {r7, pc} - 800106a: 46c0 nop @ (mov r8, r8) - 800106c: 20000008 .word 0x20000008 - 8001070: 200002dc .word 0x200002dc + 8001724: 46c0 nop @ (mov r8, r8) + 8001726: 46bd mov sp, r7 + 8001728: bd80 pop {r7, pc} + 800172a: 46c0 nop @ (mov r8, r8) + 800172c: 20000020 .word 0x20000020 + 8001730: 200004ac .word 0x200004ac -08001074 : +08001734 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { - 8001074: b580 push {r7, lr} - 8001076: af00 add r7, sp, #0 + 8001734: b580 push {r7, lr} + 8001736: af00 add r7, sp, #0 return uwTick; - 8001078: 4b02 ldr r3, [pc, #8] @ (8001084 ) - 800107a: 681b ldr r3, [r3, #0] + 8001738: 4b02 ldr r3, [pc, #8] @ (8001744 ) + 800173a: 681b ldr r3, [r3, #0] } - 800107c: 0018 movs r0, r3 - 800107e: 46bd mov sp, r7 - 8001080: bd80 pop {r7, pc} - 8001082: 46c0 nop @ (mov r8, r8) - 8001084: 200002dc .word 0x200002dc + 800173c: 0018 movs r0, r3 + 800173e: 46bd mov sp, r7 + 8001740: bd80 pop {r7, pc} + 8001742: 46c0 nop @ (mov r8, r8) + 8001744: 200004ac .word 0x200004ac -08001088 <__NVIC_EnableIRQ>: +08001748 : +/** + * @brief Returns first word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw0(void) +{ + 8001748: b580 push {r7, lr} + 800174a: af00 add r7, sp, #0 + return (READ_REG(*((uint32_t *)UID_BASE))); + 800174c: 4b02 ldr r3, [pc, #8] @ (8001758 ) + 800174e: 681b ldr r3, [r3, #0] +} + 8001750: 0018 movs r0, r3 + 8001752: 46bd mov sp, r7 + 8001754: bd80 pop {r7, pc} + 8001756: 46c0 nop @ (mov r8, r8) + 8001758: 1fff7550 .word 0x1fff7550 + +0800175c : +/** + * @brief Returns second word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw1(void) +{ + 800175c: b580 push {r7, lr} + 800175e: af00 add r7, sp, #0 + return (READ_REG(*((uint32_t *)(UID_BASE + 4U)))); + 8001760: 4b02 ldr r3, [pc, #8] @ (800176c ) + 8001762: 681b ldr r3, [r3, #0] +} + 8001764: 0018 movs r0, r3 + 8001766: 46bd mov sp, r7 + 8001768: bd80 pop {r7, pc} + 800176a: 46c0 nop @ (mov r8, r8) + 800176c: 1fff7554 .word 0x1fff7554 + +08001770 : +/** + * @brief Returns third word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw2(void) +{ + 8001770: b580 push {r7, lr} + 8001772: af00 add r7, sp, #0 + return (READ_REG(*((uint32_t *)(UID_BASE + 8U)))); + 8001774: 4b02 ldr r3, [pc, #8] @ (8001780 ) + 8001776: 681b ldr r3, [r3, #0] +} + 8001778: 0018 movs r0, r3 + 800177a: 46bd mov sp, r7 + 800177c: bd80 pop {r7, pc} + 800177e: 46c0 nop @ (mov r8, r8) + 8001780: 1fff7558 .word 0x1fff7558 + +08001784 <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { - 8001088: b580 push {r7, lr} - 800108a: b082 sub sp, #8 - 800108c: af00 add r7, sp, #0 - 800108e: 0002 movs r2, r0 - 8001090: 1dfb adds r3, r7, #7 - 8001092: 701a strb r2, [r3, #0] + 8001784: b580 push {r7, lr} + 8001786: b082 sub sp, #8 + 8001788: af00 add r7, sp, #0 + 800178a: 0002 movs r2, r0 + 800178c: 1dfb adds r3, r7, #7 + 800178e: 701a strb r2, [r3, #0] if ((int32_t)(IRQn) >= 0) - 8001094: 1dfb adds r3, r7, #7 - 8001096: 781b ldrb r3, [r3, #0] - 8001098: 2b7f cmp r3, #127 @ 0x7f - 800109a: d809 bhi.n 80010b0 <__NVIC_EnableIRQ+0x28> + 8001790: 1dfb adds r3, r7, #7 + 8001792: 781b ldrb r3, [r3, #0] + 8001794: 2b7f cmp r3, #127 @ 0x7f + 8001796: d809 bhi.n 80017ac <__NVIC_EnableIRQ+0x28> { __COMPILER_BARRIER(); NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - 800109c: 1dfb adds r3, r7, #7 - 800109e: 781b ldrb r3, [r3, #0] - 80010a0: 001a movs r2, r3 - 80010a2: 231f movs r3, #31 - 80010a4: 401a ands r2, r3 - 80010a6: 4b04 ldr r3, [pc, #16] @ (80010b8 <__NVIC_EnableIRQ+0x30>) - 80010a8: 2101 movs r1, #1 - 80010aa: 4091 lsls r1, r2 - 80010ac: 000a movs r2, r1 - 80010ae: 601a str r2, [r3, #0] + 8001798: 1dfb adds r3, r7, #7 + 800179a: 781b ldrb r3, [r3, #0] + 800179c: 001a movs r2, r3 + 800179e: 231f movs r3, #31 + 80017a0: 401a ands r2, r3 + 80017a2: 4b04 ldr r3, [pc, #16] @ (80017b4 <__NVIC_EnableIRQ+0x30>) + 80017a4: 2101 movs r1, #1 + 80017a6: 4091 lsls r1, r2 + 80017a8: 000a movs r2, r1 + 80017aa: 601a str r2, [r3, #0] __COMPILER_BARRIER(); } } - 80010b0: 46c0 nop @ (mov r8, r8) - 80010b2: 46bd mov sp, r7 - 80010b4: b002 add sp, #8 - 80010b6: bd80 pop {r7, pc} - 80010b8: e000e100 .word 0xe000e100 + 80017ac: 46c0 nop @ (mov r8, r8) + 80017ae: 46bd mov sp, r7 + 80017b0: b002 add sp, #8 + 80017b2: bd80 pop {r7, pc} + 80017b4: e000e100 .word 0xe000e100 -080010bc <__NVIC_SetPriority>: +080017b8 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { - 80010bc: b590 push {r4, r7, lr} - 80010be: b083 sub sp, #12 - 80010c0: af00 add r7, sp, #0 - 80010c2: 0002 movs r2, r0 - 80010c4: 6039 str r1, [r7, #0] - 80010c6: 1dfb adds r3, r7, #7 - 80010c8: 701a strb r2, [r3, #0] + 80017b8: b590 push {r4, r7, lr} + 80017ba: b083 sub sp, #12 + 80017bc: af00 add r7, sp, #0 + 80017be: 0002 movs r2, r0 + 80017c0: 6039 str r1, [r7, #0] + 80017c2: 1dfb adds r3, r7, #7 + 80017c4: 701a strb r2, [r3, #0] if ((int32_t)(IRQn) >= 0) - 80010ca: 1dfb adds r3, r7, #7 - 80010cc: 781b ldrb r3, [r3, #0] - 80010ce: 2b7f cmp r3, #127 @ 0x7f - 80010d0: d828 bhi.n 8001124 <__NVIC_SetPriority+0x68> + 80017c6: 1dfb adds r3, r7, #7 + 80017c8: 781b ldrb r3, [r3, #0] + 80017ca: 2b7f cmp r3, #127 @ 0x7f + 80017cc: d828 bhi.n 8001820 <__NVIC_SetPriority+0x68> { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - 80010d2: 4a2f ldr r2, [pc, #188] @ (8001190 <__NVIC_SetPriority+0xd4>) - 80010d4: 1dfb adds r3, r7, #7 - 80010d6: 781b ldrb r3, [r3, #0] - 80010d8: b25b sxtb r3, r3 - 80010da: 089b lsrs r3, r3, #2 - 80010dc: 33c0 adds r3, #192 @ 0xc0 - 80010de: 009b lsls r3, r3, #2 - 80010e0: 589b ldr r3, [r3, r2] - 80010e2: 1dfa adds r2, r7, #7 - 80010e4: 7812 ldrb r2, [r2, #0] - 80010e6: 0011 movs r1, r2 - 80010e8: 2203 movs r2, #3 - 80010ea: 400a ands r2, r1 - 80010ec: 00d2 lsls r2, r2, #3 - 80010ee: 21ff movs r1, #255 @ 0xff - 80010f0: 4091 lsls r1, r2 - 80010f2: 000a movs r2, r1 - 80010f4: 43d2 mvns r2, r2 - 80010f6: 401a ands r2, r3 - 80010f8: 0011 movs r1, r2 + 80017ce: 4a2f ldr r2, [pc, #188] @ (800188c <__NVIC_SetPriority+0xd4>) + 80017d0: 1dfb adds r3, r7, #7 + 80017d2: 781b ldrb r3, [r3, #0] + 80017d4: b25b sxtb r3, r3 + 80017d6: 089b lsrs r3, r3, #2 + 80017d8: 33c0 adds r3, #192 @ 0xc0 + 80017da: 009b lsls r3, r3, #2 + 80017dc: 589b ldr r3, [r3, r2] + 80017de: 1dfa adds r2, r7, #7 + 80017e0: 7812 ldrb r2, [r2, #0] + 80017e2: 0011 movs r1, r2 + 80017e4: 2203 movs r2, #3 + 80017e6: 400a ands r2, r1 + 80017e8: 00d2 lsls r2, r2, #3 + 80017ea: 21ff movs r1, #255 @ 0xff + 80017ec: 4091 lsls r1, r2 + 80017ee: 000a movs r2, r1 + 80017f0: 43d2 mvns r2, r2 + 80017f2: 401a ands r2, r3 + 80017f4: 0011 movs r1, r2 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - 80010fa: 683b ldr r3, [r7, #0] - 80010fc: 019b lsls r3, r3, #6 - 80010fe: 22ff movs r2, #255 @ 0xff - 8001100: 401a ands r2, r3 - 8001102: 1dfb adds r3, r7, #7 - 8001104: 781b ldrb r3, [r3, #0] - 8001106: 0018 movs r0, r3 - 8001108: 2303 movs r3, #3 - 800110a: 4003 ands r3, r0 - 800110c: 00db lsls r3, r3, #3 - 800110e: 409a lsls r2, r3 + 80017f6: 683b ldr r3, [r7, #0] + 80017f8: 019b lsls r3, r3, #6 + 80017fa: 22ff movs r2, #255 @ 0xff + 80017fc: 401a ands r2, r3 + 80017fe: 1dfb adds r3, r7, #7 + 8001800: 781b ldrb r3, [r3, #0] + 8001802: 0018 movs r0, r3 + 8001804: 2303 movs r3, #3 + 8001806: 4003 ands r3, r0 + 8001808: 00db lsls r3, r3, #3 + 800180a: 409a lsls r2, r3 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - 8001110: 481f ldr r0, [pc, #124] @ (8001190 <__NVIC_SetPriority+0xd4>) - 8001112: 1dfb adds r3, r7, #7 - 8001114: 781b ldrb r3, [r3, #0] - 8001116: b25b sxtb r3, r3 - 8001118: 089b lsrs r3, r3, #2 - 800111a: 430a orrs r2, r1 - 800111c: 33c0 adds r3, #192 @ 0xc0 - 800111e: 009b lsls r3, r3, #2 - 8001120: 501a str r2, [r3, r0] + 800180c: 481f ldr r0, [pc, #124] @ (800188c <__NVIC_SetPriority+0xd4>) + 800180e: 1dfb adds r3, r7, #7 + 8001810: 781b ldrb r3, [r3, #0] + 8001812: b25b sxtb r3, r3 + 8001814: 089b lsrs r3, r3, #2 + 8001816: 430a orrs r2, r1 + 8001818: 33c0 adds r3, #192 @ 0xc0 + 800181a: 009b lsls r3, r3, #2 + 800181c: 501a str r2, [r3, r0] else { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } - 8001122: e031 b.n 8001188 <__NVIC_SetPriority+0xcc> + 800181e: e031 b.n 8001884 <__NVIC_SetPriority+0xcc> SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - 8001124: 4a1b ldr r2, [pc, #108] @ (8001194 <__NVIC_SetPriority+0xd8>) - 8001126: 1dfb adds r3, r7, #7 - 8001128: 781b ldrb r3, [r3, #0] - 800112a: 0019 movs r1, r3 - 800112c: 230f movs r3, #15 - 800112e: 400b ands r3, r1 - 8001130: 3b08 subs r3, #8 - 8001132: 089b lsrs r3, r3, #2 - 8001134: 3306 adds r3, #6 - 8001136: 009b lsls r3, r3, #2 - 8001138: 18d3 adds r3, r2, r3 - 800113a: 3304 adds r3, #4 - 800113c: 681b ldr r3, [r3, #0] - 800113e: 1dfa adds r2, r7, #7 - 8001140: 7812 ldrb r2, [r2, #0] - 8001142: 0011 movs r1, r2 - 8001144: 2203 movs r2, #3 - 8001146: 400a ands r2, r1 - 8001148: 00d2 lsls r2, r2, #3 - 800114a: 21ff movs r1, #255 @ 0xff - 800114c: 4091 lsls r1, r2 - 800114e: 000a movs r2, r1 - 8001150: 43d2 mvns r2, r2 - 8001152: 401a ands r2, r3 - 8001154: 0011 movs r1, r2 + 8001820: 4a1b ldr r2, [pc, #108] @ (8001890 <__NVIC_SetPriority+0xd8>) + 8001822: 1dfb adds r3, r7, #7 + 8001824: 781b ldrb r3, [r3, #0] + 8001826: 0019 movs r1, r3 + 8001828: 230f movs r3, #15 + 800182a: 400b ands r3, r1 + 800182c: 3b08 subs r3, #8 + 800182e: 089b lsrs r3, r3, #2 + 8001830: 3306 adds r3, #6 + 8001832: 009b lsls r3, r3, #2 + 8001834: 18d3 adds r3, r2, r3 + 8001836: 3304 adds r3, #4 + 8001838: 681b ldr r3, [r3, #0] + 800183a: 1dfa adds r2, r7, #7 + 800183c: 7812 ldrb r2, [r2, #0] + 800183e: 0011 movs r1, r2 + 8001840: 2203 movs r2, #3 + 8001842: 400a ands r2, r1 + 8001844: 00d2 lsls r2, r2, #3 + 8001846: 21ff movs r1, #255 @ 0xff + 8001848: 4091 lsls r1, r2 + 800184a: 000a movs r2, r1 + 800184c: 43d2 mvns r2, r2 + 800184e: 401a ands r2, r3 + 8001850: 0011 movs r1, r2 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - 8001156: 683b ldr r3, [r7, #0] - 8001158: 019b lsls r3, r3, #6 - 800115a: 22ff movs r2, #255 @ 0xff - 800115c: 401a ands r2, r3 - 800115e: 1dfb adds r3, r7, #7 - 8001160: 781b ldrb r3, [r3, #0] - 8001162: 0018 movs r0, r3 - 8001164: 2303 movs r3, #3 - 8001166: 4003 ands r3, r0 - 8001168: 00db lsls r3, r3, #3 - 800116a: 409a lsls r2, r3 + 8001852: 683b ldr r3, [r7, #0] + 8001854: 019b lsls r3, r3, #6 + 8001856: 22ff movs r2, #255 @ 0xff + 8001858: 401a ands r2, r3 + 800185a: 1dfb adds r3, r7, #7 + 800185c: 781b ldrb r3, [r3, #0] + 800185e: 0018 movs r0, r3 + 8001860: 2303 movs r3, #3 + 8001862: 4003 ands r3, r0 + 8001864: 00db lsls r3, r3, #3 + 8001866: 409a lsls r2, r3 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - 800116c: 4809 ldr r0, [pc, #36] @ (8001194 <__NVIC_SetPriority+0xd8>) - 800116e: 1dfb adds r3, r7, #7 - 8001170: 781b ldrb r3, [r3, #0] - 8001172: 001c movs r4, r3 - 8001174: 230f movs r3, #15 - 8001176: 4023 ands r3, r4 - 8001178: 3b08 subs r3, #8 - 800117a: 089b lsrs r3, r3, #2 - 800117c: 430a orrs r2, r1 - 800117e: 3306 adds r3, #6 - 8001180: 009b lsls r3, r3, #2 - 8001182: 18c3 adds r3, r0, r3 - 8001184: 3304 adds r3, #4 - 8001186: 601a str r2, [r3, #0] + 8001868: 4809 ldr r0, [pc, #36] @ (8001890 <__NVIC_SetPriority+0xd8>) + 800186a: 1dfb adds r3, r7, #7 + 800186c: 781b ldrb r3, [r3, #0] + 800186e: 001c movs r4, r3 + 8001870: 230f movs r3, #15 + 8001872: 4023 ands r3, r4 + 8001874: 3b08 subs r3, #8 + 8001876: 089b lsrs r3, r3, #2 + 8001878: 430a orrs r2, r1 + 800187a: 3306 adds r3, #6 + 800187c: 009b lsls r3, r3, #2 + 800187e: 18c3 adds r3, r0, r3 + 8001880: 3304 adds r3, #4 + 8001882: 601a str r2, [r3, #0] } - 8001188: 46c0 nop @ (mov r8, r8) - 800118a: 46bd mov sp, r7 - 800118c: b003 add sp, #12 - 800118e: bd90 pop {r4, r7, pc} - 8001190: e000e100 .word 0xe000e100 - 8001194: e000ed00 .word 0xe000ed00 + 8001884: 46c0 nop @ (mov r8, r8) + 8001886: 46bd mov sp, r7 + 8001888: b003 add sp, #12 + 800188a: bd90 pop {r4, r7, pc} + 800188c: e000e100 .word 0xe000e100 + 8001890: e000ed00 .word 0xe000ed00 -08001198 : +08001894 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { - 8001198: b580 push {r7, lr} - 800119a: b082 sub sp, #8 - 800119c: af00 add r7, sp, #0 - 800119e: 6078 str r0, [r7, #4] + 8001894: b580 push {r7, lr} + 8001896: b082 sub sp, #8 + 8001898: af00 add r7, sp, #0 + 800189a: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - 80011a0: 687b ldr r3, [r7, #4] - 80011a2: 1e5a subs r2, r3, #1 - 80011a4: 2380 movs r3, #128 @ 0x80 - 80011a6: 045b lsls r3, r3, #17 - 80011a8: 429a cmp r2, r3 - 80011aa: d301 bcc.n 80011b0 + 800189c: 687b ldr r3, [r7, #4] + 800189e: 1e5a subs r2, r3, #1 + 80018a0: 2380 movs r3, #128 @ 0x80 + 80018a2: 045b lsls r3, r3, #17 + 80018a4: 429a cmp r2, r3 + 80018a6: d301 bcc.n 80018ac { return (1UL); /* Reload value impossible */ - 80011ac: 2301 movs r3, #1 - 80011ae: e010 b.n 80011d2 + 80018a8: 2301 movs r3, #1 + 80018aa: e010 b.n 80018ce } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - 80011b0: 4b0a ldr r3, [pc, #40] @ (80011dc ) - 80011b2: 687a ldr r2, [r7, #4] - 80011b4: 3a01 subs r2, #1 - 80011b6: 605a str r2, [r3, #4] + 80018ac: 4b0a ldr r3, [pc, #40] @ (80018d8 ) + 80018ae: 687a ldr r2, [r7, #4] + 80018b0: 3a01 subs r2, #1 + 80018b2: 605a str r2, [r3, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - 80011b8: 2301 movs r3, #1 - 80011ba: 425b negs r3, r3 - 80011bc: 2103 movs r1, #3 - 80011be: 0018 movs r0, r3 - 80011c0: f7ff ff7c bl 80010bc <__NVIC_SetPriority> + 80018b4: 2301 movs r3, #1 + 80018b6: 425b negs r3, r3 + 80018b8: 2103 movs r1, #3 + 80018ba: 0018 movs r0, r3 + 80018bc: f7ff ff7c bl 80017b8 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - 80011c4: 4b05 ldr r3, [pc, #20] @ (80011dc ) - 80011c6: 2200 movs r2, #0 - 80011c8: 609a str r2, [r3, #8] + 80018c0: 4b05 ldr r3, [pc, #20] @ (80018d8 ) + 80018c2: 2200 movs r2, #0 + 80018c4: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - 80011ca: 4b04 ldr r3, [pc, #16] @ (80011dc ) - 80011cc: 2207 movs r2, #7 - 80011ce: 601a str r2, [r3, #0] + 80018c6: 4b04 ldr r3, [pc, #16] @ (80018d8 ) + 80018c8: 2207 movs r2, #7 + 80018ca: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ - 80011d0: 2300 movs r3, #0 + 80018cc: 2300 movs r3, #0 } - 80011d2: 0018 movs r0, r3 - 80011d4: 46bd mov sp, r7 - 80011d6: b002 add sp, #8 - 80011d8: bd80 pop {r7, pc} - 80011da: 46c0 nop @ (mov r8, r8) - 80011dc: e000e010 .word 0xe000e010 + 80018ce: 0018 movs r0, r3 + 80018d0: 46bd mov sp, r7 + 80018d2: b002 add sp, #8 + 80018d4: bd80 pop {r7, pc} + 80018d6: 46c0 nop @ (mov r8, r8) + 80018d8: e000e010 .word 0xe000e010 -080011e0 : +080018dc : * with stm32c0xx devices, this parameter is a dummy value and it is ignored, because * no subpriority supported in Cortex M0+ based products. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { - 80011e0: b580 push {r7, lr} - 80011e2: b084 sub sp, #16 - 80011e4: af00 add r7, sp, #0 - 80011e6: 60b9 str r1, [r7, #8] - 80011e8: 607a str r2, [r7, #4] - 80011ea: 210f movs r1, #15 - 80011ec: 187b adds r3, r7, r1 - 80011ee: 1c02 adds r2, r0, #0 - 80011f0: 701a strb r2, [r3, #0] + 80018dc: b580 push {r7, lr} + 80018de: b084 sub sp, #16 + 80018e0: af00 add r7, sp, #0 + 80018e2: 60b9 str r1, [r7, #8] + 80018e4: 607a str r2, [r7, #4] + 80018e6: 210f movs r1, #15 + 80018e8: 187b adds r3, r7, r1 + 80018ea: 1c02 adds r2, r0, #0 + 80018ec: 701a strb r2, [r3, #0] /* Prevent unused argument(s) compilation warning */ UNUSED(SubPriority); /* Check the parameters */ assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); NVIC_SetPriority(IRQn, PreemptPriority); - 80011f2: 68ba ldr r2, [r7, #8] - 80011f4: 187b adds r3, r7, r1 - 80011f6: 781b ldrb r3, [r3, #0] - 80011f8: b25b sxtb r3, r3 - 80011fa: 0011 movs r1, r2 - 80011fc: 0018 movs r0, r3 - 80011fe: f7ff ff5d bl 80010bc <__NVIC_SetPriority> + 80018ee: 68ba ldr r2, [r7, #8] + 80018f0: 187b adds r3, r7, r1 + 80018f2: 781b ldrb r3, [r3, #0] + 80018f4: b25b sxtb r3, r3 + 80018f6: 0011 movs r1, r2 + 80018f8: 0018 movs r0, r3 + 80018fa: f7ff ff5d bl 80017b8 <__NVIC_SetPriority> } - 8001202: 46c0 nop @ (mov r8, r8) - 8001204: 46bd mov sp, r7 - 8001206: b004 add sp, #16 - 8001208: bd80 pop {r7, pc} + 80018fe: 46c0 nop @ (mov r8, r8) + 8001900: 46bd mov sp, r7 + 8001902: b004 add sp, #16 + 8001904: bd80 pop {r7, pc} -0800120a : +08001906 : * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate * CMSIS device file (stm32c0xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { - 800120a: b580 push {r7, lr} - 800120c: b082 sub sp, #8 - 800120e: af00 add r7, sp, #0 - 8001210: 0002 movs r2, r0 - 8001212: 1dfb adds r3, r7, #7 - 8001214: 701a strb r2, [r3, #0] + 8001906: b580 push {r7, lr} + 8001908: b082 sub sp, #8 + 800190a: af00 add r7, sp, #0 + 800190c: 0002 movs r2, r0 + 800190e: 1dfb adds r3, r7, #7 + 8001910: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); - 8001216: 1dfb adds r3, r7, #7 - 8001218: 781b ldrb r3, [r3, #0] - 800121a: b25b sxtb r3, r3 - 800121c: 0018 movs r0, r3 - 800121e: f7ff ff33 bl 8001088 <__NVIC_EnableIRQ> + 8001912: 1dfb adds r3, r7, #7 + 8001914: 781b ldrb r3, [r3, #0] + 8001916: b25b sxtb r3, r3 + 8001918: 0018 movs r0, r3 + 800191a: f7ff ff33 bl 8001784 <__NVIC_EnableIRQ> } - 8001222: 46c0 nop @ (mov r8, r8) - 8001224: 46bd mov sp, r7 - 8001226: b002 add sp, #8 - 8001228: bd80 pop {r7, pc} + 800191e: 46c0 nop @ (mov r8, r8) + 8001920: 46bd mov sp, r7 + 8001922: b002 add sp, #8 + 8001924: bd80 pop {r7, pc} -0800122a : +08001926 : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { - 800122a: b580 push {r7, lr} - 800122c: b082 sub sp, #8 - 800122e: af00 add r7, sp, #0 - 8001230: 6078 str r0, [r7, #4] + 8001926: b580 push {r7, lr} + 8001928: b082 sub sp, #8 + 800192a: af00 add r7, sp, #0 + 800192c: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); - 8001232: 687b ldr r3, [r7, #4] - 8001234: 0018 movs r0, r3 - 8001236: f7ff ffaf bl 8001198 - 800123a: 0003 movs r3, r0 + 800192e: 687b ldr r3, [r7, #4] + 8001930: 0018 movs r0, r3 + 8001932: f7ff ffaf bl 8001894 + 8001936: 0003 movs r3, r0 } - 800123c: 0018 movs r0, r3 - 800123e: 46bd mov sp, r7 - 8001240: b002 add sp, #8 - 8001242: bd80 pop {r7, pc} + 8001938: 0018 movs r0, r3 + 800193a: 46bd mov sp, r7 + 800193c: b002 add sp, #8 + 800193e: bd80 pop {r7, pc} -08001244 : +08001940 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { - 8001244: b580 push {r7, lr} - 8001246: b082 sub sp, #8 - 8001248: af00 add r7, sp, #0 - 800124a: 6078 str r0, [r7, #4] + 8001940: b580 push {r7, lr} + 8001942: b082 sub sp, #8 + 8001944: af00 add r7, sp, #0 + 8001946: 6078 str r0, [r7, #4] /* Check the DMA handle allocation */ if (hdma == NULL) - 800124c: 687b ldr r3, [r7, #4] - 800124e: 2b00 cmp r3, #0 - 8001250: d101 bne.n 8001256 + 8001948: 687b ldr r3, [r7, #4] + 800194a: 2b00 cmp r3, #0 + 800194c: d101 bne.n 8001952 { return HAL_ERROR; - 8001252: 2301 movs r3, #1 - 8001254: e077 b.n 8001346 + 800194e: 2301 movs r3, #1 + 8001950: e077 b.n 8001a42 assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); /* calculation of the channel index */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - \ - 8001256: 687b ldr r3, [r7, #4] - 8001258: 681b ldr r3, [r3, #0] - 800125a: 4a3d ldr r2, [pc, #244] @ (8001350 ) - 800125c: 4694 mov ip, r2 - 800125e: 4463 add r3, ip - 8001260: 2114 movs r1, #20 - 8001262: 0018 movs r0, r3 - 8001264: f7fe ff50 bl 8000108 <__udivsi3> - 8001268: 0003 movs r3, r0 + 8001952: 687b ldr r3, [r7, #4] + 8001954: 681b ldr r3, [r3, #0] + 8001956: 4a3d ldr r2, [pc, #244] @ (8001a4c ) + 8001958: 4694 mov ip, r2 + 800195a: 4463 add r3, ip + 800195c: 2114 movs r1, #20 + 800195e: 0018 movs r0, r3 + 8001960: f7fe fbd2 bl 8000108 <__udivsi3> + 8001964: 0003 movs r3, r0 (uint32_t)DMA1_Channel1)) << 2U; - 800126a: 009a lsls r2, r3, #2 + 8001966: 009a lsls r2, r3, #2 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - \ - 800126c: 687b ldr r3, [r7, #4] - 800126e: 641a str r2, [r3, #64] @ 0x40 + 8001968: 687b ldr r3, [r7, #4] + 800196a: 641a str r2, [r3, #64] @ 0x40 /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; - 8001270: 687b ldr r3, [r7, #4] - 8001272: 2225 movs r2, #37 @ 0x25 - 8001274: 2102 movs r1, #2 - 8001276: 5499 strb r1, [r3, r2] + 800196c: 687b ldr r3, [r7, #4] + 800196e: 2225 movs r2, #37 @ 0x25 + 8001970: 2102 movs r1, #2 + 8001972: 5499 strb r1, [r3, r2] /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */ CLEAR_BIT(hdma->Instance->CCR, (DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ - 8001278: 687b ldr r3, [r7, #4] - 800127a: 681b ldr r3, [r3, #0] - 800127c: 681a ldr r2, [r3, #0] - 800127e: 687b ldr r3, [r7, #4] - 8001280: 681b ldr r3, [r3, #0] - 8001282: 4934 ldr r1, [pc, #208] @ (8001354 ) - 8001284: 400a ands r2, r1 - 8001286: 601a str r2, [r3, #0] + 8001974: 687b ldr r3, [r7, #4] + 8001976: 681b ldr r3, [r3, #0] + 8001978: 681a ldr r2, [r3, #0] + 800197a: 687b ldr r3, [r7, #4] + 800197c: 681b ldr r3, [r3, #0] + 800197e: 4934 ldr r1, [pc, #208] @ (8001a50 ) + 8001980: 400a ands r2, r1 + 8001982: 601a str r2, [r3, #0] DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ DMA_CCR_DIR | DMA_CCR_MEM2MEM)); /* Set the DMA Channel configuration */ SET_BIT(hdma->Instance->CCR, (hdma->Init.Direction | \ - 8001288: 687b ldr r3, [r7, #4] - 800128a: 681b ldr r3, [r3, #0] - 800128c: 6819 ldr r1, [r3, #0] - 800128e: 687b ldr r3, [r7, #4] - 8001290: 689a ldr r2, [r3, #8] - 8001292: 687b ldr r3, [r7, #4] - 8001294: 68db ldr r3, [r3, #12] - 8001296: 431a orrs r2, r3 - 8001298: 687b ldr r3, [r7, #4] - 800129a: 691b ldr r3, [r3, #16] - 800129c: 431a orrs r2, r3 - 800129e: 687b ldr r3, [r7, #4] - 80012a0: 695b ldr r3, [r3, #20] - 80012a2: 431a orrs r2, r3 - 80012a4: 687b ldr r3, [r7, #4] - 80012a6: 699b ldr r3, [r3, #24] - 80012a8: 431a orrs r2, r3 - 80012aa: 687b ldr r3, [r7, #4] - 80012ac: 69db ldr r3, [r3, #28] - 80012ae: 431a orrs r2, r3 - 80012b0: 687b ldr r3, [r7, #4] - 80012b2: 6a1b ldr r3, [r3, #32] - 80012b4: 431a orrs r2, r3 - 80012b6: 687b ldr r3, [r7, #4] - 80012b8: 681b ldr r3, [r3, #0] - 80012ba: 430a orrs r2, r1 - 80012bc: 601a str r2, [r3, #0] + 8001984: 687b ldr r3, [r7, #4] + 8001986: 681b ldr r3, [r3, #0] + 8001988: 6819 ldr r1, [r3, #0] + 800198a: 687b ldr r3, [r7, #4] + 800198c: 689a ldr r2, [r3, #8] + 800198e: 687b ldr r3, [r7, #4] + 8001990: 68db ldr r3, [r3, #12] + 8001992: 431a orrs r2, r3 + 8001994: 687b ldr r3, [r7, #4] + 8001996: 691b ldr r3, [r3, #16] + 8001998: 431a orrs r2, r3 + 800199a: 687b ldr r3, [r7, #4] + 800199c: 695b ldr r3, [r3, #20] + 800199e: 431a orrs r2, r3 + 80019a0: 687b ldr r3, [r7, #4] + 80019a2: 699b ldr r3, [r3, #24] + 80019a4: 431a orrs r2, r3 + 80019a6: 687b ldr r3, [r7, #4] + 80019a8: 69db ldr r3, [r3, #28] + 80019aa: 431a orrs r2, r3 + 80019ac: 687b ldr r3, [r7, #4] + 80019ae: 6a1b ldr r3, [r3, #32] + 80019b0: 431a orrs r2, r3 + 80019b2: 687b ldr r3, [r7, #4] + 80019b4: 681b ldr r3, [r3, #0] + 80019b6: 430a orrs r2, r1 + 80019b8: 601a str r2, [r3, #0] hdma->Init.Mode | hdma->Init.Priority)); /* Initialize parameters for DMAMUX channel : DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ DMA_CalcDMAMUXChannelBaseAndMask(hdma); - 80012be: 687b ldr r3, [r7, #4] - 80012c0: 0018 movs r0, r3 - 80012c2: f000 f8fb bl 80014bc + 80019ba: 687b ldr r3, [r7, #4] + 80019bc: 0018 movs r0, r3 + 80019be: f000 f9c3 bl 8001d48 if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) - 80012c6: 687b ldr r3, [r7, #4] - 80012c8: 689a ldr r2, [r3, #8] - 80012ca: 2380 movs r3, #128 @ 0x80 - 80012cc: 01db lsls r3, r3, #7 - 80012ce: 429a cmp r2, r3 - 80012d0: d102 bne.n 80012d8 + 80019c2: 687b ldr r3, [r7, #4] + 80019c4: 689a ldr r2, [r3, #8] + 80019c6: 2380 movs r3, #128 @ 0x80 + 80019c8: 01db lsls r3, r3, #7 + 80019ca: 429a cmp r2, r3 + 80019cc: d102 bne.n 80019d4 { /* if memory to memory force the request to 0*/ hdma->Init.Request = DMA_REQUEST_MEM2MEM; - 80012d2: 687b ldr r3, [r7, #4] - 80012d4: 2200 movs r2, #0 - 80012d6: 605a str r2, [r3, #4] + 80019ce: 687b ldr r3, [r7, #4] + 80019d0: 2200 movs r2, #0 + 80019d2: 605a str r2, [r3, #4] } /* Set peripheral request to DMAMUX channel */ hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); - 80012d8: 687b ldr r3, [r7, #4] - 80012da: 685a ldr r2, [r3, #4] - 80012dc: 687b ldr r3, [r7, #4] - 80012de: 6c5b ldr r3, [r3, #68] @ 0x44 - 80012e0: 21ff movs r1, #255 @ 0xff - 80012e2: 400a ands r2, r1 - 80012e4: 601a str r2, [r3, #0] + 80019d4: 687b ldr r3, [r7, #4] + 80019d6: 685a ldr r2, [r3, #4] + 80019d8: 687b ldr r3, [r7, #4] + 80019da: 6c5b ldr r3, [r3, #68] @ 0x44 + 80019dc: 21ff movs r1, #255 @ 0xff + 80019de: 400a ands r2, r1 + 80019e0: 601a str r2, [r3, #0] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; - 80012e6: 687b ldr r3, [r7, #4] - 80012e8: 6c9b ldr r3, [r3, #72] @ 0x48 - 80012ea: 687a ldr r2, [r7, #4] - 80012ec: 6cd2 ldr r2, [r2, #76] @ 0x4c - 80012ee: 605a str r2, [r3, #4] + 80019e2: 687b ldr r3, [r7, #4] + 80019e4: 6c9b ldr r3, [r3, #72] @ 0x48 + 80019e6: 687a ldr r2, [r7, #4] + 80019e8: 6cd2 ldr r2, [r2, #76] @ 0x4c + 80019ea: 605a str r2, [r3, #4] if (((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) - 80012f0: 687b ldr r3, [r7, #4] - 80012f2: 685b ldr r3, [r3, #4] - 80012f4: 2b00 cmp r3, #0 - 80012f6: d011 beq.n 800131c - 80012f8: 687b ldr r3, [r7, #4] - 80012fa: 685b ldr r3, [r3, #4] - 80012fc: 2b04 cmp r3, #4 - 80012fe: d80d bhi.n 800131c + 80019ec: 687b ldr r3, [r7, #4] + 80019ee: 685b ldr r3, [r3, #4] + 80019f0: 2b00 cmp r3, #0 + 80019f2: d011 beq.n 8001a18 + 80019f4: 687b ldr r3, [r7, #4] + 80019f6: 685b ldr r3, [r3, #4] + 80019f8: 2b04 cmp r3, #4 + 80019fa: d80d bhi.n 8001a18 { /* Initialize parameters for DMAMUX request generator : DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); - 8001300: 687b ldr r3, [r7, #4] - 8001302: 0018 movs r0, r3 - 8001304: f000 f906 bl 8001514 + 80019fc: 687b ldr r3, [r7, #4] + 80019fe: 0018 movs r0, r3 + 8001a00: f000 f9ce bl 8001da0 /* Reset the DMAMUX request generator register*/ hdma->DMAmuxRequestGen->RGCR = 0U; - 8001308: 687b ldr r3, [r7, #4] - 800130a: 6d1b ldr r3, [r3, #80] @ 0x50 - 800130c: 2200 movs r2, #0 - 800130e: 601a str r2, [r3, #0] + 8001a04: 687b ldr r3, [r7, #4] + 8001a06: 6d1b ldr r3, [r3, #80] @ 0x50 + 8001a08: 2200 movs r2, #0 + 8001a0a: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; - 8001310: 687b ldr r3, [r7, #4] - 8001312: 6d5b ldr r3, [r3, #84] @ 0x54 - 8001314: 687a ldr r2, [r7, #4] - 8001316: 6d92 ldr r2, [r2, #88] @ 0x58 - 8001318: 605a str r2, [r3, #4] - 800131a: e008 b.n 800132e + 8001a0c: 687b ldr r3, [r7, #4] + 8001a0e: 6d5b ldr r3, [r3, #84] @ 0x54 + 8001a10: 687a ldr r2, [r7, #4] + 8001a12: 6d92 ldr r2, [r2, #88] @ 0x58 + 8001a14: 605a str r2, [r3, #4] + 8001a16: e008 b.n 8001a2a } else { hdma->DMAmuxRequestGen = 0U; - 800131c: 687b ldr r3, [r7, #4] - 800131e: 2200 movs r2, #0 - 8001320: 651a str r2, [r3, #80] @ 0x50 + 8001a18: 687b ldr r3, [r7, #4] + 8001a1a: 2200 movs r2, #0 + 8001a1c: 651a str r2, [r3, #80] @ 0x50 hdma->DMAmuxRequestGenStatus = 0U; - 8001322: 687b ldr r3, [r7, #4] - 8001324: 2200 movs r2, #0 - 8001326: 655a str r2, [r3, #84] @ 0x54 + 8001a1e: 687b ldr r3, [r7, #4] + 8001a20: 2200 movs r2, #0 + 8001a22: 655a str r2, [r3, #84] @ 0x54 hdma->DMAmuxRequestGenStatusMask = 0U; - 8001328: 687b ldr r3, [r7, #4] - 800132a: 2200 movs r2, #0 - 800132c: 659a str r2, [r3, #88] @ 0x58 + 8001a24: 687b ldr r3, [r7, #4] + 8001a26: 2200 movs r2, #0 + 8001a28: 659a str r2, [r3, #88] @ 0x58 } /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; - 800132e: 687b ldr r3, [r7, #4] - 8001330: 2200 movs r2, #0 - 8001332: 63da str r2, [r3, #60] @ 0x3c + 8001a2a: 687b ldr r3, [r7, #4] + 8001a2c: 2200 movs r2, #0 + 8001a2e: 63da str r2, [r3, #60] @ 0x3c /* Initialize the DMA state*/ hdma->State = HAL_DMA_STATE_READY; - 8001334: 687b ldr r3, [r7, #4] - 8001336: 2225 movs r2, #37 @ 0x25 - 8001338: 2101 movs r1, #1 - 800133a: 5499 strb r1, [r3, r2] + 8001a30: 687b ldr r3, [r7, #4] + 8001a32: 2225 movs r2, #37 @ 0x25 + 8001a34: 2101 movs r1, #1 + 8001a36: 5499 strb r1, [r3, r2] /* Release Lock */ __HAL_UNLOCK(hdma); - 800133c: 687b ldr r3, [r7, #4] - 800133e: 2224 movs r2, #36 @ 0x24 - 8001340: 2100 movs r1, #0 - 8001342: 5499 strb r1, [r3, r2] + 8001a38: 687b ldr r3, [r7, #4] + 8001a3a: 2224 movs r2, #36 @ 0x24 + 8001a3c: 2100 movs r1, #0 + 8001a3e: 5499 strb r1, [r3, r2] return HAL_OK; - 8001344: 2300 movs r3, #0 + 8001a40: 2300 movs r3, #0 } - 8001346: 0018 movs r0, r3 - 8001348: 46bd mov sp, r7 - 800134a: b002 add sp, #8 - 800134c: bd80 pop {r7, pc} - 800134e: 46c0 nop @ (mov r8, r8) - 8001350: bffdfff8 .word 0xbffdfff8 - 8001354: ffff800f .word 0xffff800f + 8001a42: 0018 movs r0, r3 + 8001a44: 46bd mov sp, r7 + 8001a46: b002 add sp, #8 + 8001a48: bd80 pop {r7, pc} + 8001a4a: 46c0 nop @ (mov r8, r8) + 8001a4c: bffdfff8 .word 0xbffdfff8 + 8001a50: ffff800f .word 0xffff800f -08001358 : +08001a54 : + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, + uint32_t DataLength) +{ + 8001a54: b580 push {r7, lr} + 8001a56: b086 sub sp, #24 + 8001a58: af00 add r7, sp, #0 + 8001a5a: 60f8 str r0, [r7, #12] + 8001a5c: 60b9 str r1, [r7, #8] + 8001a5e: 607a str r2, [r7, #4] + 8001a60: 603b str r3, [r7, #0] + HAL_StatusTypeDef status = HAL_OK; + 8001a62: 2317 movs r3, #23 + 8001a64: 18fb adds r3, r7, r3 + 8001a66: 2200 movs r2, #0 + 8001a68: 701a strb r2, [r3, #0] + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + 8001a6a: 68fb ldr r3, [r7, #12] + 8001a6c: 2224 movs r2, #36 @ 0x24 + 8001a6e: 5c9b ldrb r3, [r3, r2] + 8001a70: 2b01 cmp r3, #1 + 8001a72: d101 bne.n 8001a78 + 8001a74: 2302 movs r3, #2 + 8001a76: e070 b.n 8001b5a + 8001a78: 68fb ldr r3, [r7, #12] + 8001a7a: 2224 movs r2, #36 @ 0x24 + 8001a7c: 2101 movs r1, #1 + 8001a7e: 5499 strb r1, [r3, r2] + + if (HAL_DMA_STATE_READY == hdma->State) + 8001a80: 68fb ldr r3, [r7, #12] + 8001a82: 2225 movs r2, #37 @ 0x25 + 8001a84: 5c9b ldrb r3, [r3, r2] + 8001a86: b2db uxtb r3, r3 + 8001a88: 2b01 cmp r3, #1 + 8001a8a: d157 bne.n 8001b3c + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + 8001a8c: 68fb ldr r3, [r7, #12] + 8001a8e: 2225 movs r2, #37 @ 0x25 + 8001a90: 2102 movs r1, #2 + 8001a92: 5499 strb r1, [r3, r2] + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 8001a94: 68fb ldr r3, [r7, #12] + 8001a96: 2200 movs r2, #0 + 8001a98: 63da str r2, [r3, #60] @ 0x3c + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + 8001a9a: 68fb ldr r3, [r7, #12] + 8001a9c: 681b ldr r3, [r3, #0] + 8001a9e: 681a ldr r2, [r3, #0] + 8001aa0: 68fb ldr r3, [r7, #12] + 8001aa2: 681b ldr r3, [r3, #0] + 8001aa4: 2101 movs r1, #1 + 8001aa6: 438a bics r2, r1 + 8001aa8: 601a str r2, [r3, #0] + + /* Configure the source, destination address and the data length & clear flags*/ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + 8001aaa: 683b ldr r3, [r7, #0] + 8001aac: 687a ldr r2, [r7, #4] + 8001aae: 68b9 ldr r1, [r7, #8] + 8001ab0: 68f8 ldr r0, [r7, #12] + 8001ab2: f000 f909 bl 8001cc8 + + /* Enable the transfer complete interrupt */ + /* Enable the transfer Error interrupt */ + if (NULL != hdma->XferHalfCpltCallback) + 8001ab6: 68fb ldr r3, [r7, #12] + 8001ab8: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001aba: 2b00 cmp r3, #0 + 8001abc: d008 beq.n 8001ad0 + { + /* Enable the Half transfer complete interrupt as well */ + __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + 8001abe: 68fb ldr r3, [r7, #12] + 8001ac0: 681b ldr r3, [r3, #0] + 8001ac2: 681a ldr r2, [r3, #0] + 8001ac4: 68fb ldr r3, [r7, #12] + 8001ac6: 681b ldr r3, [r3, #0] + 8001ac8: 210e movs r1, #14 + 8001aca: 430a orrs r2, r1 + 8001acc: 601a str r2, [r3, #0] + 8001ace: e00f b.n 8001af0 + } + else + { + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + 8001ad0: 68fb ldr r3, [r7, #12] + 8001ad2: 681b ldr r3, [r3, #0] + 8001ad4: 681a ldr r2, [r3, #0] + 8001ad6: 68fb ldr r3, [r7, #12] + 8001ad8: 681b ldr r3, [r3, #0] + 8001ada: 2104 movs r1, #4 + 8001adc: 438a bics r2, r1 + 8001ade: 601a str r2, [r3, #0] + __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); + 8001ae0: 68fb ldr r3, [r7, #12] + 8001ae2: 681b ldr r3, [r3, #0] + 8001ae4: 681a ldr r2, [r3, #0] + 8001ae6: 68fb ldr r3, [r7, #12] + 8001ae8: 681b ldr r3, [r3, #0] + 8001aea: 210a movs r1, #10 + 8001aec: 430a orrs r2, r1 + 8001aee: 601a str r2, [r3, #0] + } + + /* Check if DMAMUX Synchronization is enabled*/ + if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) + 8001af0: 68fb ldr r3, [r7, #12] + 8001af2: 6c5b ldr r3, [r3, #68] @ 0x44 + 8001af4: 681a ldr r2, [r3, #0] + 8001af6: 2380 movs r3, #128 @ 0x80 + 8001af8: 025b lsls r3, r3, #9 + 8001afa: 4013 ands r3, r2 + 8001afc: d008 beq.n 8001b10 + { + /* Enable DMAMUX sync overrun IT*/ + hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; + 8001afe: 68fb ldr r3, [r7, #12] + 8001b00: 6c5b ldr r3, [r3, #68] @ 0x44 + 8001b02: 681a ldr r2, [r3, #0] + 8001b04: 68fb ldr r3, [r7, #12] + 8001b06: 6c5b ldr r3, [r3, #68] @ 0x44 + 8001b08: 2180 movs r1, #128 @ 0x80 + 8001b0a: 0049 lsls r1, r1, #1 + 8001b0c: 430a orrs r2, r1 + 8001b0e: 601a str r2, [r3, #0] + } + + if (hdma->DMAmuxRequestGen != 0U) + 8001b10: 68fb ldr r3, [r7, #12] + 8001b12: 6d1b ldr r3, [r3, #80] @ 0x50 + 8001b14: 2b00 cmp r3, #0 + 8001b16: d008 beq.n 8001b2a + { + /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ + /* enable the request gen overrun IT*/ + hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; + 8001b18: 68fb ldr r3, [r7, #12] + 8001b1a: 6d1b ldr r3, [r3, #80] @ 0x50 + 8001b1c: 681a ldr r2, [r3, #0] + 8001b1e: 68fb ldr r3, [r7, #12] + 8001b20: 6d1b ldr r3, [r3, #80] @ 0x50 + 8001b22: 2180 movs r1, #128 @ 0x80 + 8001b24: 0049 lsls r1, r1, #1 + 8001b26: 430a orrs r2, r1 + 8001b28: 601a str r2, [r3, #0] + } + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + 8001b2a: 68fb ldr r3, [r7, #12] + 8001b2c: 681b ldr r3, [r3, #0] + 8001b2e: 681a ldr r2, [r3, #0] + 8001b30: 68fb ldr r3, [r7, #12] + 8001b32: 681b ldr r3, [r3, #0] + 8001b34: 2101 movs r1, #1 + 8001b36: 430a orrs r2, r1 + 8001b38: 601a str r2, [r3, #0] + 8001b3a: e007 b.n 8001b4c + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + 8001b3c: 68fb ldr r3, [r7, #12] + 8001b3e: 2224 movs r2, #36 @ 0x24 + 8001b40: 2100 movs r1, #0 + 8001b42: 5499 strb r1, [r3, r2] + + /* Remain BUSY */ + status = HAL_BUSY; + 8001b44: 2317 movs r3, #23 + 8001b46: 18fb adds r3, r7, r3 + 8001b48: 2202 movs r2, #2 + 8001b4a: 701a strb r2, [r3, #0] + } + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + 8001b4c: 68fb ldr r3, [r7, #12] + 8001b4e: 2224 movs r2, #36 @ 0x24 + 8001b50: 2100 movs r1, #0 + 8001b52: 5499 strb r1, [r3, r2] + + return status; + 8001b54: 2317 movs r3, #23 + 8001b56: 18fb adds r3, r7, r3 + 8001b58: 781b ldrb r3, [r3, #0] +} + 8001b5a: 0018 movs r0, r3 + 8001b5c: 46bd mov sp, r7 + 8001b5e: b006 add sp, #24 + 8001b60: bd80 pop {r7, pc} + ... + +08001b64 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { - 8001358: b580 push {r7, lr} - 800135a: b084 sub sp, #16 - 800135c: af00 add r7, sp, #0 - 800135e: 6078 str r0, [r7, #4] + 8001b64: b580 push {r7, lr} + 8001b66: b084 sub sp, #16 + 8001b68: af00 add r7, sp, #0 + 8001b6a: 6078 str r0, [r7, #4] uint32_t flag_it = DMA1->ISR; - 8001360: 4b55 ldr r3, [pc, #340] @ (80014b8 ) - 8001362: 681b ldr r3, [r3, #0] - 8001364: 60fb str r3, [r7, #12] + 8001b6c: 4b55 ldr r3, [pc, #340] @ (8001cc4 ) + 8001b6e: 681b ldr r3, [r3, #0] + 8001b70: 60fb str r3, [r7, #12] uint32_t source_it = hdma->Instance->CCR; - 8001366: 687b ldr r3, [r7, #4] - 8001368: 681b ldr r3, [r3, #0] - 800136a: 681b ldr r3, [r3, #0] - 800136c: 60bb str r3, [r7, #8] + 8001b72: 687b ldr r3, [r7, #4] + 8001b74: 681b ldr r3, [r3, #0] + 8001b76: 681b ldr r3, [r3, #0] + 8001b78: 60bb str r3, [r7, #8] /* Half Transfer Complete Interrupt management ******************************/ if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_HT) != 0U)) - 800136e: 687b ldr r3, [r7, #4] - 8001370: 6c1b ldr r3, [r3, #64] @ 0x40 - 8001372: 221c movs r2, #28 - 8001374: 4013 ands r3, r2 - 8001376: 2204 movs r2, #4 - 8001378: 409a lsls r2, r3 - 800137a: 0013 movs r3, r2 - 800137c: 68fa ldr r2, [r7, #12] - 800137e: 4013 ands r3, r2 - 8001380: d027 beq.n 80013d2 - 8001382: 68bb ldr r3, [r7, #8] - 8001384: 2204 movs r2, #4 - 8001386: 4013 ands r3, r2 - 8001388: d023 beq.n 80013d2 + 8001b7a: 687b ldr r3, [r7, #4] + 8001b7c: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001b7e: 221c movs r2, #28 + 8001b80: 4013 ands r3, r2 + 8001b82: 2204 movs r2, #4 + 8001b84: 409a lsls r2, r3 + 8001b86: 0013 movs r3, r2 + 8001b88: 68fa ldr r2, [r7, #12] + 8001b8a: 4013 ands r3, r2 + 8001b8c: d027 beq.n 8001bde + 8001b8e: 68bb ldr r3, [r7, #8] + 8001b90: 2204 movs r2, #4 + 8001b92: 4013 ands r3, r2 + 8001b94: d023 beq.n 8001bde { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) - 800138a: 687b ldr r3, [r7, #4] - 800138c: 681b ldr r3, [r3, #0] - 800138e: 681b ldr r3, [r3, #0] - 8001390: 2220 movs r2, #32 - 8001392: 4013 ands r3, r2 - 8001394: d107 bne.n 80013a6 + 8001b96: 687b ldr r3, [r7, #4] + 8001b98: 681b ldr r3, [r3, #0] + 8001b9a: 681b ldr r3, [r3, #0] + 8001b9c: 2220 movs r2, #32 + 8001b9e: 4013 ands r3, r2 + 8001ba0: d107 bne.n 8001bb2 { /* Disable the half transfer interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); - 8001396: 687b ldr r3, [r7, #4] - 8001398: 681b ldr r3, [r3, #0] - 800139a: 681a ldr r2, [r3, #0] - 800139c: 687b ldr r3, [r7, #4] - 800139e: 681b ldr r3, [r3, #0] - 80013a0: 2104 movs r1, #4 - 80013a2: 438a bics r2, r1 - 80013a4: 601a str r2, [r3, #0] + 8001ba2: 687b ldr r3, [r7, #4] + 8001ba4: 681b ldr r3, [r3, #0] + 8001ba6: 681a ldr r2, [r3, #0] + 8001ba8: 687b ldr r3, [r7, #4] + 8001baa: 681b ldr r3, [r3, #0] + 8001bac: 2104 movs r1, #4 + 8001bae: 438a bics r2, r1 + 8001bb0: 601a str r2, [r3, #0] } /* Clear the half transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU))); - 80013a6: 4b44 ldr r3, [pc, #272] @ (80014b8 ) - 80013a8: 6859 ldr r1, [r3, #4] - 80013aa: 687b ldr r3, [r7, #4] - 80013ac: 6c1b ldr r3, [r3, #64] @ 0x40 - 80013ae: 221c movs r2, #28 - 80013b0: 4013 ands r3, r2 - 80013b2: 2204 movs r2, #4 - 80013b4: 409a lsls r2, r3 - 80013b6: 4b40 ldr r3, [pc, #256] @ (80014b8 ) - 80013b8: 430a orrs r2, r1 - 80013ba: 605a str r2, [r3, #4] + 8001bb2: 4b44 ldr r3, [pc, #272] @ (8001cc4 ) + 8001bb4: 6859 ldr r1, [r3, #4] + 8001bb6: 687b ldr r3, [r7, #4] + 8001bb8: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001bba: 221c movs r2, #28 + 8001bbc: 4013 ands r3, r2 + 8001bbe: 2204 movs r2, #4 + 8001bc0: 409a lsls r2, r3 + 8001bc2: 4b40 ldr r3, [pc, #256] @ (8001cc4 ) + 8001bc4: 430a orrs r2, r1 + 8001bc6: 605a str r2, [r3, #4] /* DMA peripheral state is not updated in Half Transfer */ /* but in Transfer Complete case */ if (hdma->XferHalfCpltCallback != NULL) - 80013bc: 687b ldr r3, [r7, #4] - 80013be: 6b1b ldr r3, [r3, #48] @ 0x30 - 80013c0: 2b00 cmp r3, #0 - 80013c2: d100 bne.n 80013c6 - 80013c4: e073 b.n 80014ae + 8001bc8: 687b ldr r3, [r7, #4] + 8001bca: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001bcc: 2b00 cmp r3, #0 + 8001bce: d100 bne.n 8001bd2 + 8001bd0: e073 b.n 8001cba { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); - 80013c6: 687b ldr r3, [r7, #4] - 80013c8: 6b1b ldr r3, [r3, #48] @ 0x30 - 80013ca: 687a ldr r2, [r7, #4] - 80013cc: 0010 movs r0, r2 - 80013ce: 4798 blx r3 + 8001bd2: 687b ldr r3, [r7, #4] + 8001bd4: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001bd6: 687a ldr r2, [r7, #4] + 8001bd8: 0010 movs r0, r2 + 8001bda: 4798 blx r3 if (hdma->XferHalfCpltCallback != NULL) - 80013d0: e06d b.n 80014ae + 8001bdc: e06d b.n 8001cba } } /* Transfer Complete Interrupt management ***********************************/ else if ((0U != (flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU)))) && (0U != (source_it & DMA_IT_TC))) - 80013d2: 687b ldr r3, [r7, #4] - 80013d4: 6c1b ldr r3, [r3, #64] @ 0x40 - 80013d6: 221c movs r2, #28 - 80013d8: 4013 ands r3, r2 - 80013da: 2202 movs r2, #2 - 80013dc: 409a lsls r2, r3 - 80013de: 0013 movs r3, r2 - 80013e0: 68fa ldr r2, [r7, #12] - 80013e2: 4013 ands r3, r2 - 80013e4: d02e beq.n 8001444 - 80013e6: 68bb ldr r3, [r7, #8] - 80013e8: 2202 movs r2, #2 - 80013ea: 4013 ands r3, r2 - 80013ec: d02a beq.n 8001444 + 8001bde: 687b ldr r3, [r7, #4] + 8001be0: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001be2: 221c movs r2, #28 + 8001be4: 4013 ands r3, r2 + 8001be6: 2202 movs r2, #2 + 8001be8: 409a lsls r2, r3 + 8001bea: 0013 movs r3, r2 + 8001bec: 68fa ldr r2, [r7, #12] + 8001bee: 4013 ands r3, r2 + 8001bf0: d02e beq.n 8001c50 + 8001bf2: 68bb ldr r3, [r7, #8] + 8001bf4: 2202 movs r2, #2 + 8001bf6: 4013 ands r3, r2 + 8001bf8: d02a beq.n 8001c50 { if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) - 80013ee: 687b ldr r3, [r7, #4] - 80013f0: 681b ldr r3, [r3, #0] - 80013f2: 681b ldr r3, [r3, #0] - 80013f4: 2220 movs r2, #32 - 80013f6: 4013 ands r3, r2 - 80013f8: d10b bne.n 8001412 + 8001bfa: 687b ldr r3, [r7, #4] + 8001bfc: 681b ldr r3, [r3, #0] + 8001bfe: 681b ldr r3, [r3, #0] + 8001c00: 2220 movs r2, #32 + 8001c02: 4013 ands r3, r2 + 8001c04: d10b bne.n 8001c1e { /* Disable the transfer complete and error interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); - 80013fa: 687b ldr r3, [r7, #4] - 80013fc: 681b ldr r3, [r3, #0] - 80013fe: 681a ldr r2, [r3, #0] - 8001400: 687b ldr r3, [r7, #4] - 8001402: 681b ldr r3, [r3, #0] - 8001404: 210a movs r1, #10 - 8001406: 438a bics r2, r1 - 8001408: 601a str r2, [r3, #0] + 8001c06: 687b ldr r3, [r7, #4] + 8001c08: 681b ldr r3, [r3, #0] + 8001c0a: 681a ldr r2, [r3, #0] + 8001c0c: 687b ldr r3, [r7, #4] + 8001c0e: 681b ldr r3, [r3, #0] + 8001c10: 210a movs r1, #10 + 8001c12: 438a bics r2, r1 + 8001c14: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; - 800140a: 687b ldr r3, [r7, #4] - 800140c: 2225 movs r2, #37 @ 0x25 - 800140e: 2101 movs r1, #1 - 8001410: 5499 strb r1, [r3, r2] + 8001c16: 687b ldr r3, [r7, #4] + 8001c18: 2225 movs r2, #37 @ 0x25 + 8001c1a: 2101 movs r1, #1 + 8001c1c: 5499 strb r1, [r3, r2] } /* Clear the transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU))); - 8001412: 4b29 ldr r3, [pc, #164] @ (80014b8 ) - 8001414: 6859 ldr r1, [r3, #4] - 8001416: 687b ldr r3, [r7, #4] - 8001418: 6c1b ldr r3, [r3, #64] @ 0x40 - 800141a: 221c movs r2, #28 - 800141c: 4013 ands r3, r2 - 800141e: 2202 movs r2, #2 - 8001420: 409a lsls r2, r3 - 8001422: 4b25 ldr r3, [pc, #148] @ (80014b8 ) - 8001424: 430a orrs r2, r1 - 8001426: 605a str r2, [r3, #4] + 8001c1e: 4b29 ldr r3, [pc, #164] @ (8001cc4 ) + 8001c20: 6859 ldr r1, [r3, #4] + 8001c22: 687b ldr r3, [r7, #4] + 8001c24: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001c26: 221c movs r2, #28 + 8001c28: 4013 ands r3, r2 + 8001c2a: 2202 movs r2, #2 + 8001c2c: 409a lsls r2, r3 + 8001c2e: 4b25 ldr r3, [pc, #148] @ (8001cc4 ) + 8001c30: 430a orrs r2, r1 + 8001c32: 605a str r2, [r3, #4] /* Process Unlocked */ __HAL_UNLOCK(hdma); - 8001428: 687b ldr r3, [r7, #4] - 800142a: 2224 movs r2, #36 @ 0x24 - 800142c: 2100 movs r1, #0 - 800142e: 5499 strb r1, [r3, r2] + 8001c34: 687b ldr r3, [r7, #4] + 8001c36: 2224 movs r2, #36 @ 0x24 + 8001c38: 2100 movs r1, #0 + 8001c3a: 5499 strb r1, [r3, r2] if (hdma->XferCpltCallback != NULL) - 8001430: 687b ldr r3, [r7, #4] - 8001432: 6adb ldr r3, [r3, #44] @ 0x2c - 8001434: 2b00 cmp r3, #0 - 8001436: d03a beq.n 80014ae + 8001c3c: 687b ldr r3, [r7, #4] + 8001c3e: 6adb ldr r3, [r3, #44] @ 0x2c + 8001c40: 2b00 cmp r3, #0 + 8001c42: d03a beq.n 8001cba { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); - 8001438: 687b ldr r3, [r7, #4] - 800143a: 6adb ldr r3, [r3, #44] @ 0x2c - 800143c: 687a ldr r2, [r7, #4] - 800143e: 0010 movs r0, r2 - 8001440: 4798 blx r3 + 8001c44: 687b ldr r3, [r7, #4] + 8001c46: 6adb ldr r3, [r3, #44] @ 0x2c + 8001c48: 687a ldr r2, [r7, #4] + 8001c4a: 0010 movs r0, r2 + 8001c4c: 4798 blx r3 if (hdma->XferCpltCallback != NULL) - 8001442: e034 b.n 80014ae + 8001c4e: e034 b.n 8001cba } } /* Transfer Error Interrupt management **************************************/ else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_TE) != 0U)) - 8001444: 687b ldr r3, [r7, #4] - 8001446: 6c1b ldr r3, [r3, #64] @ 0x40 - 8001448: 221c movs r2, #28 - 800144a: 4013 ands r3, r2 - 800144c: 2208 movs r2, #8 - 800144e: 409a lsls r2, r3 - 8001450: 0013 movs r3, r2 - 8001452: 68fa ldr r2, [r7, #12] - 8001454: 4013 ands r3, r2 - 8001456: d02b beq.n 80014b0 - 8001458: 68bb ldr r3, [r7, #8] - 800145a: 2208 movs r2, #8 - 800145c: 4013 ands r3, r2 - 800145e: d027 beq.n 80014b0 + 8001c50: 687b ldr r3, [r7, #4] + 8001c52: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001c54: 221c movs r2, #28 + 8001c56: 4013 ands r3, r2 + 8001c58: 2208 movs r2, #8 + 8001c5a: 409a lsls r2, r3 + 8001c5c: 0013 movs r3, r2 + 8001c5e: 68fa ldr r2, [r7, #12] + 8001c60: 4013 ands r3, r2 + 8001c62: d02b beq.n 8001cbc + 8001c64: 68bb ldr r3, [r7, #8] + 8001c66: 2208 movs r2, #8 + 8001c68: 4013 ands r3, r2 + 8001c6a: d027 beq.n 8001cbc { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Disable ALL DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); - 8001460: 687b ldr r3, [r7, #4] - 8001462: 681b ldr r3, [r3, #0] - 8001464: 681a ldr r2, [r3, #0] - 8001466: 687b ldr r3, [r7, #4] - 8001468: 681b ldr r3, [r3, #0] - 800146a: 210e movs r1, #14 - 800146c: 438a bics r2, r1 - 800146e: 601a str r2, [r3, #0] + 8001c6c: 687b ldr r3, [r7, #4] + 8001c6e: 681b ldr r3, [r3, #0] + 8001c70: 681a ldr r2, [r3, #0] + 8001c72: 687b ldr r3, [r7, #4] + 8001c74: 681b ldr r3, [r3, #0] + 8001c76: 210e movs r1, #14 + 8001c78: 438a bics r2, r1 + 8001c7a: 601a str r2, [r3, #0] /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1cU))); - 8001470: 4b11 ldr r3, [pc, #68] @ (80014b8 ) - 8001472: 6859 ldr r1, [r3, #4] - 8001474: 687b ldr r3, [r7, #4] - 8001476: 6c1b ldr r3, [r3, #64] @ 0x40 - 8001478: 221c movs r2, #28 - 800147a: 4013 ands r3, r2 - 800147c: 2201 movs r2, #1 - 800147e: 409a lsls r2, r3 - 8001480: 4b0d ldr r3, [pc, #52] @ (80014b8 ) - 8001482: 430a orrs r2, r1 - 8001484: 605a str r2, [r3, #4] + 8001c7c: 4b11 ldr r3, [pc, #68] @ (8001cc4 ) + 8001c7e: 6859 ldr r1, [r3, #4] + 8001c80: 687b ldr r3, [r7, #4] + 8001c82: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001c84: 221c movs r2, #28 + 8001c86: 4013 ands r3, r2 + 8001c88: 2201 movs r2, #1 + 8001c8a: 409a lsls r2, r3 + 8001c8c: 4b0d ldr r3, [pc, #52] @ (8001cc4 ) + 8001c8e: 430a orrs r2, r1 + 8001c90: 605a str r2, [r3, #4] /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; - 8001486: 687b ldr r3, [r7, #4] - 8001488: 2201 movs r2, #1 - 800148a: 63da str r2, [r3, #60] @ 0x3c + 8001c92: 687b ldr r3, [r7, #4] + 8001c94: 2201 movs r2, #1 + 8001c96: 63da str r2, [r3, #60] @ 0x3c /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; - 800148c: 687b ldr r3, [r7, #4] - 800148e: 2225 movs r2, #37 @ 0x25 - 8001490: 2101 movs r1, #1 - 8001492: 5499 strb r1, [r3, r2] + 8001c98: 687b ldr r3, [r7, #4] + 8001c9a: 2225 movs r2, #37 @ 0x25 + 8001c9c: 2101 movs r1, #1 + 8001c9e: 5499 strb r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(hdma); - 8001494: 687b ldr r3, [r7, #4] - 8001496: 2224 movs r2, #36 @ 0x24 - 8001498: 2100 movs r1, #0 - 800149a: 5499 strb r1, [r3, r2] + 8001ca0: 687b ldr r3, [r7, #4] + 8001ca2: 2224 movs r2, #36 @ 0x24 + 8001ca4: 2100 movs r1, #0 + 8001ca6: 5499 strb r1, [r3, r2] if (hdma->XferErrorCallback != NULL) - 800149c: 687b ldr r3, [r7, #4] - 800149e: 6b5b ldr r3, [r3, #52] @ 0x34 - 80014a0: 2b00 cmp r3, #0 - 80014a2: d005 beq.n 80014b0 + 8001ca8: 687b ldr r3, [r7, #4] + 8001caa: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001cac: 2b00 cmp r3, #0 + 8001cae: d005 beq.n 8001cbc { /* Transfer error callback */ hdma->XferErrorCallback(hdma); - 80014a4: 687b ldr r3, [r7, #4] - 80014a6: 6b5b ldr r3, [r3, #52] @ 0x34 - 80014a8: 687a ldr r2, [r7, #4] - 80014aa: 0010 movs r0, r2 - 80014ac: 4798 blx r3 + 8001cb0: 687b ldr r3, [r7, #4] + 8001cb2: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001cb4: 687a ldr r2, [r7, #4] + 8001cb6: 0010 movs r0, r2 + 8001cb8: 4798 blx r3 } else { /* Nothing To Do */ } return; - 80014ae: 46c0 nop @ (mov r8, r8) - 80014b0: 46c0 nop @ (mov r8, r8) + 8001cba: 46c0 nop @ (mov r8, r8) + 8001cbc: 46c0 nop @ (mov r8, r8) } - 80014b2: 46bd mov sp, r7 - 80014b4: b004 add sp, #16 - 80014b6: bd80 pop {r7, pc} - 80014b8: 40020000 .word 0x40020000 + 8001cbe: 46bd mov sp, r7 + 8001cc0: b004 add sp, #16 + 8001cc2: bd80 pop {r7, pc} + 8001cc4: 40020000 .word 0x40020000 -080014bc : +08001cc8 : + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + 8001cc8: b580 push {r7, lr} + 8001cca: b084 sub sp, #16 + 8001ccc: af00 add r7, sp, #0 + 8001cce: 60f8 str r0, [r7, #12] + 8001cd0: 60b9 str r1, [r7, #8] + 8001cd2: 607a str r2, [r7, #4] + 8001cd4: 603b str r3, [r7, #0] + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + 8001cd6: 68fb ldr r3, [r7, #12] + 8001cd8: 6c9b ldr r3, [r3, #72] @ 0x48 + 8001cda: 68fa ldr r2, [r7, #12] + 8001cdc: 6cd2 ldr r2, [r2, #76] @ 0x4c + 8001cde: 605a str r2, [r3, #4] + + if (hdma->DMAmuxRequestGen != 0U) + 8001ce0: 68fb ldr r3, [r7, #12] + 8001ce2: 6d1b ldr r3, [r3, #80] @ 0x50 + 8001ce4: 2b00 cmp r3, #0 + 8001ce6: d004 beq.n 8001cf2 + { + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + 8001ce8: 68fb ldr r3, [r7, #12] + 8001cea: 6d5b ldr r3, [r3, #84] @ 0x54 + 8001cec: 68fa ldr r2, [r7, #12] + 8001cee: 6d92 ldr r2, [r2, #88] @ 0x58 + 8001cf0: 605a str r2, [r3, #4] + } + + /* Clear all flags */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1cU))); + 8001cf2: 4b14 ldr r3, [pc, #80] @ (8001d44 ) + 8001cf4: 6859 ldr r1, [r3, #4] + 8001cf6: 68fb ldr r3, [r7, #12] + 8001cf8: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001cfa: 221c movs r2, #28 + 8001cfc: 4013 ands r3, r2 + 8001cfe: 2201 movs r2, #1 + 8001d00: 409a lsls r2, r3 + 8001d02: 4b10 ldr r3, [pc, #64] @ (8001d44 ) + 8001d04: 430a orrs r2, r1 + 8001d06: 605a str r2, [r3, #4] + + /* Configure DMA Channel data length */ + hdma->Instance->CNDTR = DataLength; + 8001d08: 68fb ldr r3, [r7, #12] + 8001d0a: 681b ldr r3, [r3, #0] + 8001d0c: 683a ldr r2, [r7, #0] + 8001d0e: 605a str r2, [r3, #4] + + /* Peripheral to Memory */ + if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + 8001d10: 68fb ldr r3, [r7, #12] + 8001d12: 689b ldr r3, [r3, #8] + 8001d14: 2b10 cmp r3, #16 + 8001d16: d108 bne.n 8001d2a + { + /* Configure DMA Channel destination address */ + hdma->Instance->CPAR = DstAddress; + 8001d18: 68fb ldr r3, [r7, #12] + 8001d1a: 681b ldr r3, [r3, #0] + 8001d1c: 687a ldr r2, [r7, #4] + 8001d1e: 609a str r2, [r3, #8] + + /* Configure DMA Channel source address */ + hdma->Instance->CMAR = SrcAddress; + 8001d20: 68fb ldr r3, [r7, #12] + 8001d22: 681b ldr r3, [r3, #0] + 8001d24: 68ba ldr r2, [r7, #8] + 8001d26: 60da str r2, [r3, #12] + hdma->Instance->CPAR = SrcAddress; + + /* Configure DMA Channel destination address */ + hdma->Instance->CMAR = DstAddress; + } +} + 8001d28: e007 b.n 8001d3a + hdma->Instance->CPAR = SrcAddress; + 8001d2a: 68fb ldr r3, [r7, #12] + 8001d2c: 681b ldr r3, [r3, #0] + 8001d2e: 68ba ldr r2, [r7, #8] + 8001d30: 609a str r2, [r3, #8] + hdma->Instance->CMAR = DstAddress; + 8001d32: 68fb ldr r3, [r7, #12] + 8001d34: 681b ldr r3, [r3, #0] + 8001d36: 687a ldr r2, [r7, #4] + 8001d38: 60da str r2, [r3, #12] +} + 8001d3a: 46c0 nop @ (mov r8, r8) + 8001d3c: 46bd mov sp, r7 + 8001d3e: b004 add sp, #16 + 8001d40: bd80 pop {r7, pc} + 8001d42: 46c0 nop @ (mov r8, r8) + 8001d44: 40020000 .word 0x40020000 + +08001d48 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) { - 80014bc: b580 push {r7, lr} - 80014be: b084 sub sp, #16 - 80014c0: af00 add r7, sp, #0 - 80014c2: 6078 str r0, [r7, #4] + 8001d48: b580 push {r7, lr} + 8001d4a: b084 sub sp, #16 + 8001d4c: af00 add r7, sp, #0 + 8001d4e: 6078 str r0, [r7, #4] uint32_t channel_number; channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U; - 80014c4: 687b ldr r3, [r7, #4] - 80014c6: 681b ldr r3, [r3, #0] - 80014c8: 001a movs r2, r3 - 80014ca: 23ff movs r3, #255 @ 0xff - 80014cc: 4013 ands r3, r2 - 80014ce: 3b08 subs r3, #8 - 80014d0: 2114 movs r1, #20 - 80014d2: 0018 movs r0, r3 - 80014d4: f7fe fe18 bl 8000108 <__udivsi3> - 80014d8: 0003 movs r3, r0 - 80014da: 60fb str r3, [r7, #12] + 8001d50: 687b ldr r3, [r7, #4] + 8001d52: 681b ldr r3, [r3, #0] + 8001d54: 001a movs r2, r3 + 8001d56: 23ff movs r3, #255 @ 0xff + 8001d58: 4013 ands r3, r2 + 8001d5a: 3b08 subs r3, #8 + 8001d5c: 2114 movs r1, #20 + 8001d5e: 0018 movs r0, r3 + 8001d60: f7fe f9d2 bl 8000108 <__udivsi3> + 8001d64: 0003 movs r3, r0 + 8001d66: 60fb str r3, [r7, #12] hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + \ ((hdma->ChannelIndex >> 2U) * \ - 80014dc: 687b ldr r3, [r7, #4] - 80014de: 6c1b ldr r3, [r3, #64] @ 0x40 - 80014e0: 089b lsrs r3, r3, #2 + 8001d68: 687b ldr r3, [r7, #4] + 8001d6a: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001d6c: 089b lsrs r3, r3, #2 hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + \ - 80014e2: 4a0a ldr r2, [pc, #40] @ (800150c ) - 80014e4: 4694 mov ip, r2 - 80014e6: 4463 add r3, ip - 80014e8: 009b lsls r3, r3, #2 - 80014ea: 001a movs r2, r3 - 80014ec: 687b ldr r3, [r7, #4] - 80014ee: 645a str r2, [r3, #68] @ 0x44 + 8001d6e: 4a0a ldr r2, [pc, #40] @ (8001d98 ) + 8001d70: 4694 mov ip, r2 + 8001d72: 4463 add r3, ip + 8001d74: 009b lsls r3, r3, #2 + 8001d76: 001a movs r2, r3 + 8001d78: 687b ldr r3, [r7, #4] + 8001d7a: 645a str r2, [r3, #68] @ 0x44 ((uint32_t)DMAMUX1_Channel1 - \ (uint32_t)DMAMUX1_Channel0))); hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; - 80014f0: 687b ldr r3, [r7, #4] - 80014f2: 4a07 ldr r2, [pc, #28] @ (8001510 ) - 80014f4: 649a str r2, [r3, #72] @ 0x48 + 8001d7c: 687b ldr r3, [r7, #4] + 8001d7e: 4a07 ldr r2, [pc, #28] @ (8001d9c ) + 8001d80: 649a str r2, [r3, #72] @ 0x48 hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1cU); - 80014f6: 68fb ldr r3, [r7, #12] - 80014f8: 221c movs r2, #28 - 80014fa: 4013 ands r3, r2 - 80014fc: 2201 movs r2, #1 - 80014fe: 409a lsls r2, r3 - 8001500: 687b ldr r3, [r7, #4] - 8001502: 64da str r2, [r3, #76] @ 0x4c + 8001d82: 68fb ldr r3, [r7, #12] + 8001d84: 221c movs r2, #28 + 8001d86: 4013 ands r3, r2 + 8001d88: 2201 movs r2, #1 + 8001d8a: 409a lsls r2, r3 + 8001d8c: 687b ldr r3, [r7, #4] + 8001d8e: 64da str r2, [r3, #76] @ 0x4c } - 8001504: 46c0 nop @ (mov r8, r8) - 8001506: 46bd mov sp, r7 - 8001508: b004 add sp, #16 - 800150a: bd80 pop {r7, pc} - 800150c: 10008200 .word 0x10008200 - 8001510: 40020880 .word 0x40020880 + 8001d90: 46c0 nop @ (mov r8, r8) + 8001d92: 46bd mov sp, r7 + 8001d94: b004 add sp, #16 + 8001d96: bd80 pop {r7, pc} + 8001d98: 10008200 .word 0x10008200 + 8001d9c: 40020880 .word 0x40020880 -08001514 : +08001da0 : * the configuration information for the specified DMA Stream. * @retval None */ static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) { - 8001514: b580 push {r7, lr} - 8001516: b084 sub sp, #16 - 8001518: af00 add r7, sp, #0 - 800151a: 6078 str r0, [r7, #4] + 8001da0: b580 push {r7, lr} + 8001da2: b084 sub sp, #16 + 8001da4: af00 add r7, sp, #0 + 8001da6: 6078 str r0, [r7, #4] uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; - 800151c: 687b ldr r3, [r7, #4] - 800151e: 685b ldr r3, [r3, #4] - 8001520: 22ff movs r2, #255 @ 0xff - 8001522: 4013 ands r3, r2 - 8001524: 60fb str r3, [r7, #12] + 8001da8: 687b ldr r3, [r7, #4] + 8001daa: 685b ldr r3, [r3, #4] + 8001dac: 22ff movs r2, #255 @ 0xff + 8001dae: 4013 ands r3, r2 + 8001db0: 60fb str r3, [r7, #12] /* DMA Channels are connected to DMAMUX1 request generator blocks*/ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + \ - 8001526: 68fb ldr r3, [r7, #12] - 8001528: 4a0a ldr r2, [pc, #40] @ (8001554 ) - 800152a: 4694 mov ip, r2 - 800152c: 4463 add r3, ip - 800152e: 009b lsls r3, r3, #2 - 8001530: 001a movs r2, r3 - 8001532: 687b ldr r3, [r7, #4] - 8001534: 651a str r2, [r3, #80] @ 0x50 + 8001db2: 68fb ldr r3, [r7, #12] + 8001db4: 4a0a ldr r2, [pc, #40] @ (8001de0 ) + 8001db6: 4694 mov ip, r2 + 8001db8: 4463 add r3, ip + 8001dba: 009b lsls r3, r3, #2 + 8001dbc: 001a movs r2, r3 + 8001dbe: 687b ldr r3, [r7, #4] + 8001dc0: 651a str r2, [r3, #80] @ 0x50 ((request - 1U) * 4U))); hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; - 8001536: 687b ldr r3, [r7, #4] - 8001538: 4a07 ldr r2, [pc, #28] @ (8001558 ) - 800153a: 655a str r2, [r3, #84] @ 0x54 + 8001dc2: 687b ldr r3, [r7, #4] + 8001dc4: 4a07 ldr r2, [pc, #28] @ (8001de4 ) + 8001dc6: 655a str r2, [r3, #84] @ 0x54 /* here "Request" is either DMA_REQUEST_GENERATOR0 to 4, i.e. <= 4*/ hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U); - 800153c: 68fb ldr r3, [r7, #12] - 800153e: 3b01 subs r3, #1 - 8001540: 2203 movs r2, #3 - 8001542: 4013 ands r3, r2 - 8001544: 2201 movs r2, #1 - 8001546: 409a lsls r2, r3 - 8001548: 687b ldr r3, [r7, #4] - 800154a: 659a str r2, [r3, #88] @ 0x58 + 8001dc8: 68fb ldr r3, [r7, #12] + 8001dca: 3b01 subs r3, #1 + 8001dcc: 2203 movs r2, #3 + 8001dce: 4013 ands r3, r2 + 8001dd0: 2201 movs r2, #1 + 8001dd2: 409a lsls r2, r3 + 8001dd4: 687b ldr r3, [r7, #4] + 8001dd6: 659a str r2, [r3, #88] @ 0x58 } - 800154c: 46c0 nop @ (mov r8, r8) - 800154e: 46bd mov sp, r7 - 8001550: b004 add sp, #16 - 8001552: bd80 pop {r7, pc} - 8001554: 1000823f .word 0x1000823f - 8001558: 40020940 .word 0x40020940 + 8001dd8: 46c0 nop @ (mov r8, r8) + 8001dda: 46bd mov sp, r7 + 8001ddc: b004 add sp, #16 + 8001dde: bd80 pop {r7, pc} + 8001de0: 1000823f .word 0x1000823f + 8001de4: 40020940 .word 0x40020940 -0800155c : +08001de8 : * @param pGPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init) { - 800155c: b580 push {r7, lr} - 800155e: b086 sub sp, #24 - 8001560: af00 add r7, sp, #0 - 8001562: 6078 str r0, [r7, #4] - 8001564: 6039 str r1, [r7, #0] + 8001de8: b580 push {r7, lr} + 8001dea: b086 sub sp, #24 + 8001dec: af00 add r7, sp, #0 + 8001dee: 6078 str r0, [r7, #4] + 8001df0: 6039 str r1, [r7, #0] uint32_t tmp; uint32_t iocurrent; uint32_t position = 0U; - 8001566: 2300 movs r3, #0 - 8001568: 613b str r3, [r7, #16] + 8001df2: 2300 movs r3, #0 + 8001df4: 613b str r3, [r7, #16] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(pGPIO_Init->Pin)); assert_param(IS_GPIO_MODE(pGPIO_Init->Mode)); /* Configure the port pins */ while (((pGPIO_Init->Pin) >> position) != 0U) - 800156a: e153 b.n 8001814 + 8001df6: e153 b.n 80020a0 { /* Get current io position */ iocurrent = (pGPIO_Init->Pin) & (1UL << position); - 800156c: 683b ldr r3, [r7, #0] - 800156e: 681b ldr r3, [r3, #0] - 8001570: 2101 movs r1, #1 - 8001572: 693a ldr r2, [r7, #16] - 8001574: 4091 lsls r1, r2 - 8001576: 000a movs r2, r1 - 8001578: 4013 ands r3, r2 - 800157a: 60fb str r3, [r7, #12] + 8001df8: 683b ldr r3, [r7, #0] + 8001dfa: 681b ldr r3, [r3, #0] + 8001dfc: 2101 movs r1, #1 + 8001dfe: 693a ldr r2, [r7, #16] + 8001e00: 4091 lsls r1, r2 + 8001e02: 000a movs r2, r1 + 8001e04: 4013 ands r3, r2 + 8001e06: 60fb str r3, [r7, #12] if (iocurrent != 0U) - 800157c: 68fb ldr r3, [r7, #12] - 800157e: 2b00 cmp r3, #0 - 8001580: d100 bne.n 8001584 - 8001582: e144 b.n 800180e + 8001e08: 68fb ldr r3, [r7, #12] + 8001e0a: 2b00 cmp r3, #0 + 8001e0c: d100 bne.n 8001e10 + 8001e0e: e144 b.n 800209a { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Alternate function mode selection */ if ((pGPIO_Init->Mode == GPIO_MODE_AF_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_OD)) - 8001584: 683b ldr r3, [r7, #0] - 8001586: 685b ldr r3, [r3, #4] - 8001588: 2b02 cmp r3, #2 - 800158a: d003 beq.n 8001594 - 800158c: 683b ldr r3, [r7, #0] - 800158e: 685b ldr r3, [r3, #4] - 8001590: 2b12 cmp r3, #18 - 8001592: d125 bne.n 80015e0 + 8001e10: 683b ldr r3, [r7, #0] + 8001e12: 685b ldr r3, [r3, #4] + 8001e14: 2b02 cmp r3, #2 + 8001e16: d003 beq.n 8001e20 + 8001e18: 683b ldr r3, [r7, #0] + 8001e1a: 685b ldr r3, [r3, #4] + 8001e1c: 2b12 cmp r3, #18 + 8001e1e: d125 bne.n 8001e6c /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(pGPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ tmp = GPIOx->AFR[position >> 3U]; - 8001594: 693b ldr r3, [r7, #16] - 8001596: 08da lsrs r2, r3, #3 - 8001598: 687b ldr r3, [r7, #4] - 800159a: 3208 adds r2, #8 - 800159c: 0092 lsls r2, r2, #2 - 800159e: 58d3 ldr r3, [r2, r3] - 80015a0: 617b str r3, [r7, #20] + 8001e20: 693b ldr r3, [r7, #16] + 8001e22: 08da lsrs r2, r3, #3 + 8001e24: 687b ldr r3, [r7, #4] + 8001e26: 3208 adds r2, #8 + 8001e28: 0092 lsls r2, r2, #2 + 8001e2a: 58d3 ldr r3, [r2, r3] + 8001e2c: 617b str r3, [r7, #20] tmp &= ~(0xFUL << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)) ; - 80015a2: 693b ldr r3, [r7, #16] - 80015a4: 2207 movs r2, #7 - 80015a6: 4013 ands r3, r2 - 80015a8: 009b lsls r3, r3, #2 - 80015aa: 220f movs r2, #15 - 80015ac: 409a lsls r2, r3 - 80015ae: 0013 movs r3, r2 - 80015b0: 43da mvns r2, r3 - 80015b2: 697b ldr r3, [r7, #20] - 80015b4: 4013 ands r3, r2 - 80015b6: 617b str r3, [r7, #20] + 8001e2e: 693b ldr r3, [r7, #16] + 8001e30: 2207 movs r2, #7 + 8001e32: 4013 ands r3, r2 + 8001e34: 009b lsls r3, r3, #2 + 8001e36: 220f movs r2, #15 + 8001e38: 409a lsls r2, r3 + 8001e3a: 0013 movs r3, r2 + 8001e3c: 43da mvns r2, r3 + 8001e3e: 697b ldr r3, [r7, #20] + 8001e40: 4013 ands r3, r2 + 8001e42: 617b str r3, [r7, #20] tmp |= ((pGPIO_Init->Alternate & 0x0FUL) << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)); - 80015b8: 683b ldr r3, [r7, #0] - 80015ba: 691b ldr r3, [r3, #16] - 80015bc: 220f movs r2, #15 - 80015be: 401a ands r2, r3 - 80015c0: 693b ldr r3, [r7, #16] - 80015c2: 2107 movs r1, #7 - 80015c4: 400b ands r3, r1 - 80015c6: 009b lsls r3, r3, #2 - 80015c8: 409a lsls r2, r3 - 80015ca: 0013 movs r3, r2 - 80015cc: 697a ldr r2, [r7, #20] - 80015ce: 4313 orrs r3, r2 - 80015d0: 617b str r3, [r7, #20] + 8001e44: 683b ldr r3, [r7, #0] + 8001e46: 691b ldr r3, [r3, #16] + 8001e48: 220f movs r2, #15 + 8001e4a: 401a ands r2, r3 + 8001e4c: 693b ldr r3, [r7, #16] + 8001e4e: 2107 movs r1, #7 + 8001e50: 400b ands r3, r1 + 8001e52: 009b lsls r3, r3, #2 + 8001e54: 409a lsls r2, r3 + 8001e56: 0013 movs r3, r2 + 8001e58: 697a ldr r2, [r7, #20] + 8001e5a: 4313 orrs r3, r2 + 8001e5c: 617b str r3, [r7, #20] GPIOx->AFR[position >> 3U] = tmp; - 80015d2: 693b ldr r3, [r7, #16] - 80015d4: 08da lsrs r2, r3, #3 - 80015d6: 687b ldr r3, [r7, #4] - 80015d8: 3208 adds r2, #8 - 80015da: 0092 lsls r2, r2, #2 - 80015dc: 6979 ldr r1, [r7, #20] - 80015de: 50d1 str r1, [r2, r3] + 8001e5e: 693b ldr r3, [r7, #16] + 8001e60: 08da lsrs r2, r3, #3 + 8001e62: 687b ldr r3, [r7, #4] + 8001e64: 3208 adds r2, #8 + 8001e66: 0092 lsls r2, r2, #2 + 8001e68: 6979 ldr r1, [r7, #20] + 8001e6a: 50d1 str r1, [r2, r3] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ tmp = GPIOx->MODER; - 80015e0: 687b ldr r3, [r7, #4] - 80015e2: 681b ldr r3, [r3, #0] - 80015e4: 617b str r3, [r7, #20] + 8001e6c: 687b ldr r3, [r7, #4] + 8001e6e: 681b ldr r3, [r3, #0] + 8001e70: 617b str r3, [r7, #20] tmp &= ~(GPIO_MODER_MODE0 << (position * GPIO_MODER_MODE1_Pos)); - 80015e6: 693b ldr r3, [r7, #16] - 80015e8: 005b lsls r3, r3, #1 - 80015ea: 2203 movs r2, #3 - 80015ec: 409a lsls r2, r3 - 80015ee: 0013 movs r3, r2 - 80015f0: 43da mvns r2, r3 - 80015f2: 697b ldr r3, [r7, #20] - 80015f4: 4013 ands r3, r2 - 80015f6: 617b str r3, [r7, #20] + 8001e72: 693b ldr r3, [r7, #16] + 8001e74: 005b lsls r3, r3, #1 + 8001e76: 2203 movs r2, #3 + 8001e78: 409a lsls r2, r3 + 8001e7a: 0013 movs r3, r2 + 8001e7c: 43da mvns r2, r3 + 8001e7e: 697b ldr r3, [r7, #20] + 8001e80: 4013 ands r3, r2 + 8001e82: 617b str r3, [r7, #20] tmp |= ((pGPIO_Init->Mode & GPIO_MODE) << (position * GPIO_MODER_MODE1_Pos)); - 80015f8: 683b ldr r3, [r7, #0] - 80015fa: 685b ldr r3, [r3, #4] - 80015fc: 2203 movs r2, #3 - 80015fe: 401a ands r2, r3 - 8001600: 693b ldr r3, [r7, #16] - 8001602: 005b lsls r3, r3, #1 - 8001604: 409a lsls r2, r3 - 8001606: 0013 movs r3, r2 - 8001608: 697a ldr r2, [r7, #20] - 800160a: 4313 orrs r3, r2 - 800160c: 617b str r3, [r7, #20] + 8001e84: 683b ldr r3, [r7, #0] + 8001e86: 685b ldr r3, [r3, #4] + 8001e88: 2203 movs r2, #3 + 8001e8a: 401a ands r2, r3 + 8001e8c: 693b ldr r3, [r7, #16] + 8001e8e: 005b lsls r3, r3, #1 + 8001e90: 409a lsls r2, r3 + 8001e92: 0013 movs r3, r2 + 8001e94: 697a ldr r2, [r7, #20] + 8001e96: 4313 orrs r3, r2 + 8001e98: 617b str r3, [r7, #20] GPIOx->MODER = tmp; - 800160e: 687b ldr r3, [r7, #4] - 8001610: 697a ldr r2, [r7, #20] - 8001612: 601a str r2, [r3, #0] + 8001e9a: 687b ldr r3, [r7, #4] + 8001e9c: 697a ldr r2, [r7, #20] + 8001e9e: 601a str r2, [r3, #0] /* In case of Output or Alternate function mode selection */ if ((pGPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_PP) || - 8001614: 683b ldr r3, [r7, #0] - 8001616: 685b ldr r3, [r3, #4] - 8001618: 2b01 cmp r3, #1 - 800161a: d00b beq.n 8001634 - 800161c: 683b ldr r3, [r7, #0] - 800161e: 685b ldr r3, [r3, #4] - 8001620: 2b02 cmp r3, #2 - 8001622: d007 beq.n 8001634 + 8001ea0: 683b ldr r3, [r7, #0] + 8001ea2: 685b ldr r3, [r3, #4] + 8001ea4: 2b01 cmp r3, #1 + 8001ea6: d00b beq.n 8001ec0 + 8001ea8: 683b ldr r3, [r7, #0] + 8001eaa: 685b ldr r3, [r3, #4] + 8001eac: 2b02 cmp r3, #2 + 8001eae: d007 beq.n 8001ec0 (pGPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (pGPIO_Init->Mode == GPIO_MODE_AF_OD)) - 8001624: 683b ldr r3, [r7, #0] - 8001626: 685b ldr r3, [r3, #4] + 8001eb0: 683b ldr r3, [r7, #0] + 8001eb2: 685b ldr r3, [r3, #4] if ((pGPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_PP) || - 8001628: 2b11 cmp r3, #17 - 800162a: d003 beq.n 8001634 + 8001eb4: 2b11 cmp r3, #17 + 8001eb6: d003 beq.n 8001ec0 (pGPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (pGPIO_Init->Mode == GPIO_MODE_AF_OD)) - 800162c: 683b ldr r3, [r7, #0] - 800162e: 685b ldr r3, [r3, #4] - 8001630: 2b12 cmp r3, #18 - 8001632: d130 bne.n 8001696 + 8001eb8: 683b ldr r3, [r7, #0] + 8001eba: 685b ldr r3, [r3, #4] + 8001ebc: 2b12 cmp r3, #18 + 8001ebe: d130 bne.n 8001f22 { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(pGPIO_Init->Speed)); /* Configure the IO Speed */ tmp = GPIOx->OSPEEDR; - 8001634: 687b ldr r3, [r7, #4] - 8001636: 689b ldr r3, [r3, #8] - 8001638: 617b str r3, [r7, #20] + 8001ec0: 687b ldr r3, [r7, #4] + 8001ec2: 689b ldr r3, [r3, #8] + 8001ec4: 617b str r3, [r7, #20] tmp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * GPIO_OSPEEDR_OSPEED1_Pos)); - 800163a: 693b ldr r3, [r7, #16] - 800163c: 005b lsls r3, r3, #1 - 800163e: 2203 movs r2, #3 - 8001640: 409a lsls r2, r3 - 8001642: 0013 movs r3, r2 - 8001644: 43da mvns r2, r3 - 8001646: 697b ldr r3, [r7, #20] - 8001648: 4013 ands r3, r2 - 800164a: 617b str r3, [r7, #20] + 8001ec6: 693b ldr r3, [r7, #16] + 8001ec8: 005b lsls r3, r3, #1 + 8001eca: 2203 movs r2, #3 + 8001ecc: 409a lsls r2, r3 + 8001ece: 0013 movs r3, r2 + 8001ed0: 43da mvns r2, r3 + 8001ed2: 697b ldr r3, [r7, #20] + 8001ed4: 4013 ands r3, r2 + 8001ed6: 617b str r3, [r7, #20] tmp |= (pGPIO_Init->Speed << (position * GPIO_OSPEEDR_OSPEED1_Pos)); - 800164c: 683b ldr r3, [r7, #0] - 800164e: 68da ldr r2, [r3, #12] - 8001650: 693b ldr r3, [r7, #16] - 8001652: 005b lsls r3, r3, #1 - 8001654: 409a lsls r2, r3 - 8001656: 0013 movs r3, r2 - 8001658: 697a ldr r2, [r7, #20] - 800165a: 4313 orrs r3, r2 - 800165c: 617b str r3, [r7, #20] + 8001ed8: 683b ldr r3, [r7, #0] + 8001eda: 68da ldr r2, [r3, #12] + 8001edc: 693b ldr r3, [r7, #16] + 8001ede: 005b lsls r3, r3, #1 + 8001ee0: 409a lsls r2, r3 + 8001ee2: 0013 movs r3, r2 + 8001ee4: 697a ldr r2, [r7, #20] + 8001ee6: 4313 orrs r3, r2 + 8001ee8: 617b str r3, [r7, #20] GPIOx->OSPEEDR = tmp; - 800165e: 687b ldr r3, [r7, #4] - 8001660: 697a ldr r2, [r7, #20] - 8001662: 609a str r2, [r3, #8] + 8001eea: 687b ldr r3, [r7, #4] + 8001eec: 697a ldr r2, [r7, #20] + 8001eee: 609a str r2, [r3, #8] /* Configure the IO Output Type */ tmp = GPIOx->OTYPER; - 8001664: 687b ldr r3, [r7, #4] - 8001666: 685b ldr r3, [r3, #4] - 8001668: 617b str r3, [r7, #20] + 8001ef0: 687b ldr r3, [r7, #4] + 8001ef2: 685b ldr r3, [r3, #4] + 8001ef4: 617b str r3, [r7, #20] tmp &= ~(GPIO_OTYPER_OT0 << position) ; - 800166a: 2201 movs r2, #1 - 800166c: 693b ldr r3, [r7, #16] - 800166e: 409a lsls r2, r3 - 8001670: 0013 movs r3, r2 - 8001672: 43da mvns r2, r3 - 8001674: 697b ldr r3, [r7, #20] - 8001676: 4013 ands r3, r2 - 8001678: 617b str r3, [r7, #20] + 8001ef6: 2201 movs r2, #1 + 8001ef8: 693b ldr r3, [r7, #16] + 8001efa: 409a lsls r2, r3 + 8001efc: 0013 movs r3, r2 + 8001efe: 43da mvns r2, r3 + 8001f00: 697b ldr r3, [r7, #20] + 8001f02: 4013 ands r3, r2 + 8001f04: 617b str r3, [r7, #20] tmp |= (((pGPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position); - 800167a: 683b ldr r3, [r7, #0] - 800167c: 685b ldr r3, [r3, #4] - 800167e: 091b lsrs r3, r3, #4 - 8001680: 2201 movs r2, #1 - 8001682: 401a ands r2, r3 - 8001684: 693b ldr r3, [r7, #16] - 8001686: 409a lsls r2, r3 - 8001688: 0013 movs r3, r2 - 800168a: 697a ldr r2, [r7, #20] - 800168c: 4313 orrs r3, r2 - 800168e: 617b str r3, [r7, #20] + 8001f06: 683b ldr r3, [r7, #0] + 8001f08: 685b ldr r3, [r3, #4] + 8001f0a: 091b lsrs r3, r3, #4 + 8001f0c: 2201 movs r2, #1 + 8001f0e: 401a ands r2, r3 + 8001f10: 693b ldr r3, [r7, #16] + 8001f12: 409a lsls r2, r3 + 8001f14: 0013 movs r3, r2 + 8001f16: 697a ldr r2, [r7, #20] + 8001f18: 4313 orrs r3, r2 + 8001f1a: 617b str r3, [r7, #20] GPIOx->OTYPER = tmp; - 8001690: 687b ldr r3, [r7, #4] - 8001692: 697a ldr r2, [r7, #20] - 8001694: 605a str r2, [r3, #4] + 8001f1c: 687b ldr r3, [r7, #4] + 8001f1e: 697a ldr r2, [r7, #20] + 8001f20: 605a str r2, [r3, #4] } if (pGPIO_Init->Mode != GPIO_MODE_ANALOG) - 8001696: 683b ldr r3, [r7, #0] - 8001698: 685b ldr r3, [r3, #4] - 800169a: 2b03 cmp r3, #3 - 800169c: d017 beq.n 80016ce + 8001f22: 683b ldr r3, [r7, #0] + 8001f24: 685b ldr r3, [r3, #4] + 8001f26: 2b03 cmp r3, #3 + 8001f28: d017 beq.n 8001f5a { /* Check the Pull parameters */ assert_param(IS_GPIO_PULL(pGPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ tmp = GPIOx->PUPDR; - 800169e: 687b ldr r3, [r7, #4] - 80016a0: 68db ldr r3, [r3, #12] - 80016a2: 617b str r3, [r7, #20] + 8001f2a: 687b ldr r3, [r7, #4] + 8001f2c: 68db ldr r3, [r3, #12] + 8001f2e: 617b str r3, [r7, #20] tmp &= ~(GPIO_PUPDR_PUPD0 << (position * GPIO_PUPDR_PUPD1_Pos)); - 80016a4: 693b ldr r3, [r7, #16] - 80016a6: 005b lsls r3, r3, #1 - 80016a8: 2203 movs r2, #3 - 80016aa: 409a lsls r2, r3 - 80016ac: 0013 movs r3, r2 - 80016ae: 43da mvns r2, r3 - 80016b0: 697b ldr r3, [r7, #20] - 80016b2: 4013 ands r3, r2 - 80016b4: 617b str r3, [r7, #20] + 8001f30: 693b ldr r3, [r7, #16] + 8001f32: 005b lsls r3, r3, #1 + 8001f34: 2203 movs r2, #3 + 8001f36: 409a lsls r2, r3 + 8001f38: 0013 movs r3, r2 + 8001f3a: 43da mvns r2, r3 + 8001f3c: 697b ldr r3, [r7, #20] + 8001f3e: 4013 ands r3, r2 + 8001f40: 617b str r3, [r7, #20] tmp |= ((pGPIO_Init->Pull) << (position * GPIO_PUPDR_PUPD1_Pos)); - 80016b6: 683b ldr r3, [r7, #0] - 80016b8: 689a ldr r2, [r3, #8] - 80016ba: 693b ldr r3, [r7, #16] - 80016bc: 005b lsls r3, r3, #1 - 80016be: 409a lsls r2, r3 - 80016c0: 0013 movs r3, r2 - 80016c2: 697a ldr r2, [r7, #20] - 80016c4: 4313 orrs r3, r2 - 80016c6: 617b str r3, [r7, #20] + 8001f42: 683b ldr r3, [r7, #0] + 8001f44: 689a ldr r2, [r3, #8] + 8001f46: 693b ldr r3, [r7, #16] + 8001f48: 005b lsls r3, r3, #1 + 8001f4a: 409a lsls r2, r3 + 8001f4c: 0013 movs r3, r2 + 8001f4e: 697a ldr r2, [r7, #20] + 8001f50: 4313 orrs r3, r2 + 8001f52: 617b str r3, [r7, #20] GPIOx->PUPDR = tmp; - 80016c8: 687b ldr r3, [r7, #4] - 80016ca: 697a ldr r2, [r7, #20] - 80016cc: 60da str r2, [r3, #12] + 8001f54: 687b ldr r3, [r7, #4] + 8001f56: 697a ldr r2, [r7, #20] + 8001f58: 60da str r2, [r3, #12] } /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((pGPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) - 80016ce: 683b ldr r3, [r7, #0] - 80016d0: 685a ldr r2, [r3, #4] - 80016d2: 2380 movs r3, #128 @ 0x80 - 80016d4: 055b lsls r3, r3, #21 - 80016d6: 4013 ands r3, r2 - 80016d8: d100 bne.n 80016dc - 80016da: e098 b.n 800180e + 8001f5a: 683b ldr r3, [r7, #0] + 8001f5c: 685a ldr r2, [r3, #4] + 8001f5e: 2380 movs r3, #128 @ 0x80 + 8001f60: 055b lsls r3, r3, #21 + 8001f62: 4013 ands r3, r2 + 8001f64: d100 bne.n 8001f68 + 8001f66: e098 b.n 800209a { tmp = EXTI->EXTICR[position >> 2U]; - 80016dc: 4a53 ldr r2, [pc, #332] @ (800182c ) - 80016de: 693b ldr r3, [r7, #16] - 80016e0: 089b lsrs r3, r3, #2 - 80016e2: 3318 adds r3, #24 - 80016e4: 009b lsls r3, r3, #2 - 80016e6: 589b ldr r3, [r3, r2] - 80016e8: 617b str r3, [r7, #20] + 8001f68: 4a53 ldr r2, [pc, #332] @ (80020b8 ) + 8001f6a: 693b ldr r3, [r7, #16] + 8001f6c: 089b lsrs r3, r3, #2 + 8001f6e: 3318 adds r3, #24 + 8001f70: 009b lsls r3, r3, #2 + 8001f72: 589b ldr r3, [r3, r2] + 8001f74: 617b str r3, [r7, #20] tmp &= ~((0x0FUL) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos)); - 80016ea: 693b ldr r3, [r7, #16] - 80016ec: 2203 movs r2, #3 - 80016ee: 4013 ands r3, r2 - 80016f0: 00db lsls r3, r3, #3 - 80016f2: 220f movs r2, #15 - 80016f4: 409a lsls r2, r3 - 80016f6: 0013 movs r3, r2 - 80016f8: 43da mvns r2, r3 - 80016fa: 697b ldr r3, [r7, #20] - 80016fc: 4013 ands r3, r2 - 80016fe: 617b str r3, [r7, #20] + 8001f76: 693b ldr r3, [r7, #16] + 8001f78: 2203 movs r2, #3 + 8001f7a: 4013 ands r3, r2 + 8001f7c: 00db lsls r3, r3, #3 + 8001f7e: 220f movs r2, #15 + 8001f80: 409a lsls r2, r3 + 8001f82: 0013 movs r3, r2 + 8001f84: 43da mvns r2, r3 + 8001f86: 697b ldr r3, [r7, #20] + 8001f88: 4013 ands r3, r2 + 8001f8a: 617b str r3, [r7, #20] tmp |= (GPIO_GET_INDEX(GPIOx) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos)); - 8001700: 687a ldr r2, [r7, #4] - 8001702: 23a0 movs r3, #160 @ 0xa0 - 8001704: 05db lsls r3, r3, #23 - 8001706: 429a cmp r2, r3 - 8001708: d019 beq.n 800173e - 800170a: 687b ldr r3, [r7, #4] - 800170c: 4a48 ldr r2, [pc, #288] @ (8001830 ) - 800170e: 4293 cmp r3, r2 - 8001710: d013 beq.n 800173a - 8001712: 687b ldr r3, [r7, #4] - 8001714: 4a47 ldr r2, [pc, #284] @ (8001834 ) - 8001716: 4293 cmp r3, r2 - 8001718: d00d beq.n 8001736 - 800171a: 687b ldr r3, [r7, #4] - 800171c: 4a46 ldr r2, [pc, #280] @ (8001838 ) - 800171e: 4293 cmp r3, r2 - 8001720: d007 beq.n 8001732 - 8001722: 687b ldr r3, [r7, #4] - 8001724: 4a45 ldr r2, [pc, #276] @ (800183c ) - 8001726: 4293 cmp r3, r2 - 8001728: d101 bne.n 800172e - 800172a: 2305 movs r3, #5 - 800172c: e008 b.n 8001740 - 800172e: 2306 movs r3, #6 - 8001730: e006 b.n 8001740 - 8001732: 2303 movs r3, #3 - 8001734: e004 b.n 8001740 - 8001736: 2302 movs r3, #2 - 8001738: e002 b.n 8001740 - 800173a: 2301 movs r3, #1 - 800173c: e000 b.n 8001740 - 800173e: 2300 movs r3, #0 - 8001740: 693a ldr r2, [r7, #16] - 8001742: 2103 movs r1, #3 - 8001744: 400a ands r2, r1 - 8001746: 00d2 lsls r2, r2, #3 - 8001748: 4093 lsls r3, r2 - 800174a: 697a ldr r2, [r7, #20] - 800174c: 4313 orrs r3, r2 - 800174e: 617b str r3, [r7, #20] + 8001f8c: 687a ldr r2, [r7, #4] + 8001f8e: 23a0 movs r3, #160 @ 0xa0 + 8001f90: 05db lsls r3, r3, #23 + 8001f92: 429a cmp r2, r3 + 8001f94: d019 beq.n 8001fca + 8001f96: 687b ldr r3, [r7, #4] + 8001f98: 4a48 ldr r2, [pc, #288] @ (80020bc ) + 8001f9a: 4293 cmp r3, r2 + 8001f9c: d013 beq.n 8001fc6 + 8001f9e: 687b ldr r3, [r7, #4] + 8001fa0: 4a47 ldr r2, [pc, #284] @ (80020c0 ) + 8001fa2: 4293 cmp r3, r2 + 8001fa4: d00d beq.n 8001fc2 + 8001fa6: 687b ldr r3, [r7, #4] + 8001fa8: 4a46 ldr r2, [pc, #280] @ (80020c4 ) + 8001faa: 4293 cmp r3, r2 + 8001fac: d007 beq.n 8001fbe + 8001fae: 687b ldr r3, [r7, #4] + 8001fb0: 4a45 ldr r2, [pc, #276] @ (80020c8 ) + 8001fb2: 4293 cmp r3, r2 + 8001fb4: d101 bne.n 8001fba + 8001fb6: 2305 movs r3, #5 + 8001fb8: e008 b.n 8001fcc + 8001fba: 2306 movs r3, #6 + 8001fbc: e006 b.n 8001fcc + 8001fbe: 2303 movs r3, #3 + 8001fc0: e004 b.n 8001fcc + 8001fc2: 2302 movs r3, #2 + 8001fc4: e002 b.n 8001fcc + 8001fc6: 2301 movs r3, #1 + 8001fc8: e000 b.n 8001fcc + 8001fca: 2300 movs r3, #0 + 8001fcc: 693a ldr r2, [r7, #16] + 8001fce: 2103 movs r1, #3 + 8001fd0: 400a ands r2, r1 + 8001fd2: 00d2 lsls r2, r2, #3 + 8001fd4: 4093 lsls r3, r2 + 8001fd6: 697a ldr r2, [r7, #20] + 8001fd8: 4313 orrs r3, r2 + 8001fda: 617b str r3, [r7, #20] EXTI->EXTICR[position >> 2U] = tmp; - 8001750: 4936 ldr r1, [pc, #216] @ (800182c ) - 8001752: 693b ldr r3, [r7, #16] - 8001754: 089b lsrs r3, r3, #2 - 8001756: 3318 adds r3, #24 - 8001758: 009b lsls r3, r3, #2 - 800175a: 697a ldr r2, [r7, #20] - 800175c: 505a str r2, [r3, r1] + 8001fdc: 4936 ldr r1, [pc, #216] @ (80020b8 ) + 8001fde: 693b ldr r3, [r7, #16] + 8001fe0: 089b lsrs r3, r3, #2 + 8001fe2: 3318 adds r3, #24 + 8001fe4: 009b lsls r3, r3, #2 + 8001fe6: 697a ldr r2, [r7, #20] + 8001fe8: 505a str r2, [r3, r1] /* Clear EXTI line configuration */ tmp = EXTI->IMR1; - 800175e: 4a33 ldr r2, [pc, #204] @ (800182c ) - 8001760: 2380 movs r3, #128 @ 0x80 - 8001762: 58d3 ldr r3, [r2, r3] - 8001764: 617b str r3, [r7, #20] + 8001fea: 4a33 ldr r2, [pc, #204] @ (80020b8 ) + 8001fec: 2380 movs r3, #128 @ 0x80 + 8001fee: 58d3 ldr r3, [r2, r3] + 8001ff0: 617b str r3, [r7, #20] tmp &= ~((uint32_t)iocurrent); - 8001766: 68fb ldr r3, [r7, #12] - 8001768: 43da mvns r2, r3 - 800176a: 697b ldr r3, [r7, #20] - 800176c: 4013 ands r3, r2 - 800176e: 617b str r3, [r7, #20] + 8001ff2: 68fb ldr r3, [r7, #12] + 8001ff4: 43da mvns r2, r3 + 8001ff6: 697b ldr r3, [r7, #20] + 8001ff8: 4013 ands r3, r2 + 8001ffa: 617b str r3, [r7, #20] if ((pGPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) - 8001770: 683b ldr r3, [r7, #0] - 8001772: 685a ldr r2, [r3, #4] - 8001774: 2380 movs r3, #128 @ 0x80 - 8001776: 025b lsls r3, r3, #9 - 8001778: 4013 ands r3, r2 - 800177a: d003 beq.n 8001784 + 8001ffc: 683b ldr r3, [r7, #0] + 8001ffe: 685a ldr r2, [r3, #4] + 8002000: 2380 movs r3, #128 @ 0x80 + 8002002: 025b lsls r3, r3, #9 + 8002004: 4013 ands r3, r2 + 8002006: d003 beq.n 8002010 { tmp |= iocurrent; - 800177c: 697a ldr r2, [r7, #20] - 800177e: 68fb ldr r3, [r7, #12] - 8001780: 4313 orrs r3, r2 - 8001782: 617b str r3, [r7, #20] + 8002008: 697a ldr r2, [r7, #20] + 800200a: 68fb ldr r3, [r7, #12] + 800200c: 4313 orrs r3, r2 + 800200e: 617b str r3, [r7, #20] } EXTI->IMR1 = tmp; - 8001784: 4929 ldr r1, [pc, #164] @ (800182c ) - 8001786: 2280 movs r2, #128 @ 0x80 - 8001788: 697b ldr r3, [r7, #20] - 800178a: 508b str r3, [r1, r2] + 8002010: 4929 ldr r1, [pc, #164] @ (80020b8 ) + 8002012: 2280 movs r2, #128 @ 0x80 + 8002014: 697b ldr r3, [r7, #20] + 8002016: 508b str r3, [r1, r2] tmp = EXTI->EMR1; - 800178c: 4a27 ldr r2, [pc, #156] @ (800182c ) - 800178e: 2384 movs r3, #132 @ 0x84 - 8001790: 58d3 ldr r3, [r2, r3] - 8001792: 617b str r3, [r7, #20] + 8002018: 4a27 ldr r2, [pc, #156] @ (80020b8 ) + 800201a: 2384 movs r3, #132 @ 0x84 + 800201c: 58d3 ldr r3, [r2, r3] + 800201e: 617b str r3, [r7, #20] tmp &= ~((uint32_t)iocurrent); - 8001794: 68fb ldr r3, [r7, #12] - 8001796: 43da mvns r2, r3 - 8001798: 697b ldr r3, [r7, #20] - 800179a: 4013 ands r3, r2 - 800179c: 617b str r3, [r7, #20] + 8002020: 68fb ldr r3, [r7, #12] + 8002022: 43da mvns r2, r3 + 8002024: 697b ldr r3, [r7, #20] + 8002026: 4013 ands r3, r2 + 8002028: 617b str r3, [r7, #20] if ((pGPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) - 800179e: 683b ldr r3, [r7, #0] - 80017a0: 685a ldr r2, [r3, #4] - 80017a2: 2380 movs r3, #128 @ 0x80 - 80017a4: 029b lsls r3, r3, #10 - 80017a6: 4013 ands r3, r2 - 80017a8: d003 beq.n 80017b2 + 800202a: 683b ldr r3, [r7, #0] + 800202c: 685a ldr r2, [r3, #4] + 800202e: 2380 movs r3, #128 @ 0x80 + 8002030: 029b lsls r3, r3, #10 + 8002032: 4013 ands r3, r2 + 8002034: d003 beq.n 800203e { tmp |= iocurrent; - 80017aa: 697a ldr r2, [r7, #20] - 80017ac: 68fb ldr r3, [r7, #12] - 80017ae: 4313 orrs r3, r2 - 80017b0: 617b str r3, [r7, #20] + 8002036: 697a ldr r2, [r7, #20] + 8002038: 68fb ldr r3, [r7, #12] + 800203a: 4313 orrs r3, r2 + 800203c: 617b str r3, [r7, #20] } EXTI->EMR1 = tmp; - 80017b2: 491e ldr r1, [pc, #120] @ (800182c ) - 80017b4: 2284 movs r2, #132 @ 0x84 - 80017b6: 697b ldr r3, [r7, #20] - 80017b8: 508b str r3, [r1, r2] + 800203e: 491e ldr r1, [pc, #120] @ (80020b8 ) + 8002040: 2284 movs r2, #132 @ 0x84 + 8002042: 697b ldr r3, [r7, #20] + 8002044: 508b str r3, [r1, r2] /* Clear Rising Falling edge configuration */ tmp = EXTI->RTSR1; - 80017ba: 4b1c ldr r3, [pc, #112] @ (800182c ) - 80017bc: 681b ldr r3, [r3, #0] - 80017be: 617b str r3, [r7, #20] + 8002046: 4b1c ldr r3, [pc, #112] @ (80020b8 ) + 8002048: 681b ldr r3, [r3, #0] + 800204a: 617b str r3, [r7, #20] tmp &= ~((uint32_t)iocurrent); - 80017c0: 68fb ldr r3, [r7, #12] - 80017c2: 43da mvns r2, r3 - 80017c4: 697b ldr r3, [r7, #20] - 80017c6: 4013 ands r3, r2 - 80017c8: 617b str r3, [r7, #20] + 800204c: 68fb ldr r3, [r7, #12] + 800204e: 43da mvns r2, r3 + 8002050: 697b ldr r3, [r7, #20] + 8002052: 4013 ands r3, r2 + 8002054: 617b str r3, [r7, #20] if ((pGPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) - 80017ca: 683b ldr r3, [r7, #0] - 80017cc: 685a ldr r2, [r3, #4] - 80017ce: 2380 movs r3, #128 @ 0x80 - 80017d0: 035b lsls r3, r3, #13 - 80017d2: 4013 ands r3, r2 - 80017d4: d003 beq.n 80017de + 8002056: 683b ldr r3, [r7, #0] + 8002058: 685a ldr r2, [r3, #4] + 800205a: 2380 movs r3, #128 @ 0x80 + 800205c: 035b lsls r3, r3, #13 + 800205e: 4013 ands r3, r2 + 8002060: d003 beq.n 800206a { tmp |= iocurrent; - 80017d6: 697a ldr r2, [r7, #20] - 80017d8: 68fb ldr r3, [r7, #12] - 80017da: 4313 orrs r3, r2 - 80017dc: 617b str r3, [r7, #20] + 8002062: 697a ldr r2, [r7, #20] + 8002064: 68fb ldr r3, [r7, #12] + 8002066: 4313 orrs r3, r2 + 8002068: 617b str r3, [r7, #20] } EXTI->RTSR1 = tmp; - 80017de: 4b13 ldr r3, [pc, #76] @ (800182c ) - 80017e0: 697a ldr r2, [r7, #20] - 80017e2: 601a str r2, [r3, #0] + 800206a: 4b13 ldr r3, [pc, #76] @ (80020b8 ) + 800206c: 697a ldr r2, [r7, #20] + 800206e: 601a str r2, [r3, #0] tmp = EXTI->FTSR1; - 80017e4: 4b11 ldr r3, [pc, #68] @ (800182c ) - 80017e6: 685b ldr r3, [r3, #4] - 80017e8: 617b str r3, [r7, #20] + 8002070: 4b11 ldr r3, [pc, #68] @ (80020b8 ) + 8002072: 685b ldr r3, [r3, #4] + 8002074: 617b str r3, [r7, #20] tmp &= ~((uint32_t)iocurrent); - 80017ea: 68fb ldr r3, [r7, #12] - 80017ec: 43da mvns r2, r3 - 80017ee: 697b ldr r3, [r7, #20] - 80017f0: 4013 ands r3, r2 - 80017f2: 617b str r3, [r7, #20] + 8002076: 68fb ldr r3, [r7, #12] + 8002078: 43da mvns r2, r3 + 800207a: 697b ldr r3, [r7, #20] + 800207c: 4013 ands r3, r2 + 800207e: 617b str r3, [r7, #20] if ((pGPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) - 80017f4: 683b ldr r3, [r7, #0] - 80017f6: 685a ldr r2, [r3, #4] - 80017f8: 2380 movs r3, #128 @ 0x80 - 80017fa: 039b lsls r3, r3, #14 - 80017fc: 4013 ands r3, r2 - 80017fe: d003 beq.n 8001808 + 8002080: 683b ldr r3, [r7, #0] + 8002082: 685a ldr r2, [r3, #4] + 8002084: 2380 movs r3, #128 @ 0x80 + 8002086: 039b lsls r3, r3, #14 + 8002088: 4013 ands r3, r2 + 800208a: d003 beq.n 8002094 { tmp |= iocurrent; - 8001800: 697a ldr r2, [r7, #20] - 8001802: 68fb ldr r3, [r7, #12] - 8001804: 4313 orrs r3, r2 - 8001806: 617b str r3, [r7, #20] + 800208c: 697a ldr r2, [r7, #20] + 800208e: 68fb ldr r3, [r7, #12] + 8002090: 4313 orrs r3, r2 + 8002092: 617b str r3, [r7, #20] } EXTI->FTSR1 = tmp; - 8001808: 4b08 ldr r3, [pc, #32] @ (800182c ) - 800180a: 697a ldr r2, [r7, #20] - 800180c: 605a str r2, [r3, #4] + 8002094: 4b08 ldr r3, [pc, #32] @ (80020b8 ) + 8002096: 697a ldr r2, [r7, #20] + 8002098: 605a str r2, [r3, #4] } } position++; - 800180e: 693b ldr r3, [r7, #16] - 8001810: 3301 adds r3, #1 - 8001812: 613b str r3, [r7, #16] + 800209a: 693b ldr r3, [r7, #16] + 800209c: 3301 adds r3, #1 + 800209e: 613b str r3, [r7, #16] while (((pGPIO_Init->Pin) >> position) != 0U) - 8001814: 683b ldr r3, [r7, #0] - 8001816: 681a ldr r2, [r3, #0] - 8001818: 693b ldr r3, [r7, #16] - 800181a: 40da lsrs r2, r3 - 800181c: 1e13 subs r3, r2, #0 - 800181e: d000 beq.n 8001822 - 8001820: e6a4 b.n 800156c + 80020a0: 683b ldr r3, [r7, #0] + 80020a2: 681a ldr r2, [r3, #0] + 80020a4: 693b ldr r3, [r7, #16] + 80020a6: 40da lsrs r2, r3 + 80020a8: 1e13 subs r3, r2, #0 + 80020aa: d000 beq.n 80020ae + 80020ac: e6a4 b.n 8001df8 } } - 8001822: 46c0 nop @ (mov r8, r8) - 8001824: 46c0 nop @ (mov r8, r8) - 8001826: 46bd mov sp, r7 - 8001828: b006 add sp, #24 - 800182a: bd80 pop {r7, pc} - 800182c: 40021800 .word 0x40021800 - 8001830: 50000400 .word 0x50000400 - 8001834: 50000800 .word 0x50000800 - 8001838: 50000c00 .word 0x50000c00 - 800183c: 50001400 .word 0x50001400 + 80020ae: 46c0 nop @ (mov r8, r8) + 80020b0: 46c0 nop @ (mov r8, r8) + 80020b2: 46bd mov sp, r7 + 80020b4: b006 add sp, #24 + 80020b6: bd80 pop {r7, pc} + 80020b8: 40021800 .word 0x40021800 + 80020bc: 50000400 .word 0x50000400 + 80020c0: 50000800 .word 0x50000800 + 80020c4: 50000c00 .word 0x50000c00 + 80020c8: 50001400 .word 0x50001400 -08001840 : +080020cc : + * @param GPIO_Pin specifies the port bit to read. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval The input port pin value. + */ +GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + 80020cc: b580 push {r7, lr} + 80020ce: b084 sub sp, #16 + 80020d0: af00 add r7, sp, #0 + 80020d2: 6078 str r0, [r7, #4] + 80020d4: 000a movs r2, r1 + 80020d6: 1cbb adds r3, r7, #2 + 80020d8: 801a strh r2, [r3, #0] + GPIO_PinState bitstatus; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != 0U) + 80020da: 687b ldr r3, [r7, #4] + 80020dc: 691b ldr r3, [r3, #16] + 80020de: 1cba adds r2, r7, #2 + 80020e0: 8812 ldrh r2, [r2, #0] + 80020e2: 4013 ands r3, r2 + 80020e4: d004 beq.n 80020f0 + { + bitstatus = GPIO_PIN_SET; + 80020e6: 230f movs r3, #15 + 80020e8: 18fb adds r3, r7, r3 + 80020ea: 2201 movs r2, #1 + 80020ec: 701a strb r2, [r3, #0] + 80020ee: e003 b.n 80020f8 + } + else + { + bitstatus = GPIO_PIN_RESET; + 80020f0: 230f movs r3, #15 + 80020f2: 18fb adds r3, r7, r3 + 80020f4: 2200 movs r2, #0 + 80020f6: 701a strb r2, [r3, #0] + } + return bitstatus; + 80020f8: 230f movs r3, #15 + 80020fa: 18fb adds r3, r7, r3 + 80020fc: 781b ldrb r3, [r3, #0] +} + 80020fe: 0018 movs r0, r3 + 8002100: 46bd mov sp, r7 + 8002102: b004 add sp, #16 + 8002104: bd80 pop {r7, pc} + +08002106 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { - 8001840: b580 push {r7, lr} - 8001842: b082 sub sp, #8 - 8001844: af00 add r7, sp, #0 - 8001846: 6078 str r0, [r7, #4] - 8001848: 0008 movs r0, r1 - 800184a: 0011 movs r1, r2 - 800184c: 1cbb adds r3, r7, #2 - 800184e: 1c02 adds r2, r0, #0 - 8001850: 801a strh r2, [r3, #0] - 8001852: 1c7b adds r3, r7, #1 - 8001854: 1c0a adds r2, r1, #0 - 8001856: 701a strb r2, [r3, #0] + 8002106: b580 push {r7, lr} + 8002108: b082 sub sp, #8 + 800210a: af00 add r7, sp, #0 + 800210c: 6078 str r0, [r7, #4] + 800210e: 0008 movs r0, r1 + 8002110: 0011 movs r1, r2 + 8002112: 1cbb adds r3, r7, #2 + 8002114: 1c02 adds r2, r0, #0 + 8002116: 801a strh r2, [r3, #0] + 8002118: 1c7b adds r3, r7, #1 + 800211a: 1c0a adds r2, r1, #0 + 800211c: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) - 8001858: 1c7b adds r3, r7, #1 - 800185a: 781b ldrb r3, [r3, #0] - 800185c: 2b00 cmp r3, #0 - 800185e: d004 beq.n 800186a + 800211e: 1c7b adds r3, r7, #1 + 8002120: 781b ldrb r3, [r3, #0] + 8002122: 2b00 cmp r3, #0 + 8002124: d004 beq.n 8002130 { GPIOx->BSRR = (uint32_t)GPIO_Pin; - 8001860: 1cbb adds r3, r7, #2 - 8001862: 881a ldrh r2, [r3, #0] - 8001864: 687b ldr r3, [r7, #4] - 8001866: 619a str r2, [r3, #24] + 8002126: 1cbb adds r3, r7, #2 + 8002128: 881a ldrh r2, [r3, #0] + 800212a: 687b ldr r3, [r7, #4] + 800212c: 619a str r2, [r3, #24] } else { GPIOx->BRR = (uint32_t)GPIO_Pin; } } - 8001868: e003 b.n 8001872 + 800212e: e003 b.n 8002138 GPIOx->BRR = (uint32_t)GPIO_Pin; - 800186a: 1cbb adds r3, r7, #2 - 800186c: 881a ldrh r2, [r3, #0] - 800186e: 687b ldr r3, [r7, #4] - 8001870: 629a str r2, [r3, #40] @ 0x28 + 8002130: 1cbb adds r3, r7, #2 + 8002132: 881a ldrh r2, [r3, #0] + 8002134: 687b ldr r3, [r7, #4] + 8002136: 629a str r2, [r3, #40] @ 0x28 } - 8001872: 46c0 nop @ (mov r8, r8) - 8001874: 46bd mov sp, r7 - 8001876: b002 add sp, #8 - 8001878: bd80 pop {r7, pc} - ... + 8002138: 46c0 nop @ (mov r8, r8) + 800213a: 46bd mov sp, r7 + 800213c: b002 add sp, #8 + 800213e: bd80 pop {r7, pc} -0800187c : +08002140 : * @brief Handle EXTI interrupt request. * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) { - 800187c: b580 push {r7, lr} - 800187e: b082 sub sp, #8 - 8001880: af00 add r7, sp, #0 - 8001882: 0002 movs r2, r0 - 8001884: 1dbb adds r3, r7, #6 - 8001886: 801a strh r2, [r3, #0] + 8002140: b580 push {r7, lr} + 8002142: b082 sub sp, #8 + 8002144: af00 add r7, sp, #0 + 8002146: 0002 movs r2, r0 + 8002148: 1dbb adds r3, r7, #6 + 800214a: 801a strh r2, [r3, #0] /* EXTI line interrupt detected */ if (__HAL_GPIO_EXTI_GET_RISING_IT(GPIO_Pin) != 0U) - 8001888: 4b10 ldr r3, [pc, #64] @ (80018cc ) - 800188a: 68db ldr r3, [r3, #12] - 800188c: 1dba adds r2, r7, #6 - 800188e: 8812 ldrh r2, [r2, #0] - 8001890: 4013 ands r3, r2 - 8001892: d008 beq.n 80018a6 + 800214c: 4b10 ldr r3, [pc, #64] @ (8002190 ) + 800214e: 68db ldr r3, [r3, #12] + 8002150: 1dba adds r2, r7, #6 + 8002152: 8812 ldrh r2, [r2, #0] + 8002154: 4013 ands r3, r2 + 8002156: d008 beq.n 800216a { __HAL_GPIO_EXTI_CLEAR_RISING_IT(GPIO_Pin); - 8001894: 4b0d ldr r3, [pc, #52] @ (80018cc ) - 8001896: 1dba adds r2, r7, #6 - 8001898: 8812 ldrh r2, [r2, #0] - 800189a: 60da str r2, [r3, #12] + 8002158: 4b0d ldr r3, [pc, #52] @ (8002190 ) + 800215a: 1dba adds r2, r7, #6 + 800215c: 8812 ldrh r2, [r2, #0] + 800215e: 60da str r2, [r3, #12] HAL_GPIO_EXTI_Rising_Callback(GPIO_Pin); - 800189c: 1dbb adds r3, r7, #6 - 800189e: 881b ldrh r3, [r3, #0] - 80018a0: 0018 movs r0, r3 - 80018a2: f000 f815 bl 80018d0 + 8002160: 1dbb adds r3, r7, #6 + 8002162: 881b ldrh r3, [r3, #0] + 8002164: 0018 movs r0, r3 + 8002166: f000 f815 bl 8002194 } if (__HAL_GPIO_EXTI_GET_FALLING_IT(GPIO_Pin) != 0U) - 80018a6: 4b09 ldr r3, [pc, #36] @ (80018cc ) - 80018a8: 691b ldr r3, [r3, #16] - 80018aa: 1dba adds r2, r7, #6 - 80018ac: 8812 ldrh r2, [r2, #0] - 80018ae: 4013 ands r3, r2 - 80018b0: d008 beq.n 80018c4 + 800216a: 4b09 ldr r3, [pc, #36] @ (8002190 ) + 800216c: 691b ldr r3, [r3, #16] + 800216e: 1dba adds r2, r7, #6 + 8002170: 8812 ldrh r2, [r2, #0] + 8002172: 4013 ands r3, r2 + 8002174: d008 beq.n 8002188 { __HAL_GPIO_EXTI_CLEAR_FALLING_IT(GPIO_Pin); - 80018b2: 4b06 ldr r3, [pc, #24] @ (80018cc ) - 80018b4: 1dba adds r2, r7, #6 - 80018b6: 8812 ldrh r2, [r2, #0] - 80018b8: 611a str r2, [r3, #16] + 8002176: 4b06 ldr r3, [pc, #24] @ (8002190 ) + 8002178: 1dba adds r2, r7, #6 + 800217a: 8812 ldrh r2, [r2, #0] + 800217c: 611a str r2, [r3, #16] HAL_GPIO_EXTI_Falling_Callback(GPIO_Pin); - 80018ba: 1dbb adds r3, r7, #6 - 80018bc: 881b ldrh r3, [r3, #0] - 80018be: 0018 movs r0, r3 - 80018c0: f000 f810 bl 80018e4 + 800217e: 1dbb adds r3, r7, #6 + 8002180: 881b ldrh r3, [r3, #0] + 8002182: 0018 movs r0, r3 + 8002184: f000 f810 bl 80021a8 } } - 80018c4: 46c0 nop @ (mov r8, r8) - 80018c6: 46bd mov sp, r7 - 80018c8: b002 add sp, #8 - 80018ca: bd80 pop {r7, pc} - 80018cc: 40021800 .word 0x40021800 + 8002188: 46c0 nop @ (mov r8, r8) + 800218a: 46bd mov sp, r7 + 800218c: b002 add sp, #8 + 800218e: bd80 pop {r7, pc} + 8002190: 40021800 .word 0x40021800 -080018d0 : +08002194 : * @brief EXTI line detection callback. * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. * @retval None */ __weak void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin) { - 80018d0: b580 push {r7, lr} - 80018d2: b082 sub sp, #8 - 80018d4: af00 add r7, sp, #0 - 80018d6: 0002 movs r2, r0 - 80018d8: 1dbb adds r3, r7, #6 - 80018da: 801a strh r2, [r3, #0] + 8002194: b580 push {r7, lr} + 8002196: b082 sub sp, #8 + 8002198: af00 add r7, sp, #0 + 800219a: 0002 movs r2, r0 + 800219c: 1dbb adds r3, r7, #6 + 800219e: 801a strh r2, [r3, #0] UNUSED(GPIO_Pin); /* NOTE: This function should not be modified, when the callback is needed, the HAL_GPIO_EXTI_Rising_Callback could be implemented in the user file */ } - 80018dc: 46c0 nop @ (mov r8, r8) - 80018de: 46bd mov sp, r7 - 80018e0: b002 add sp, #8 - 80018e2: bd80 pop {r7, pc} + 80021a0: 46c0 nop @ (mov r8, r8) + 80021a2: 46bd mov sp, r7 + 80021a4: b002 add sp, #8 + 80021a6: bd80 pop {r7, pc} -080018e4 : +080021a8 : * @brief EXTI line detection callback. * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. * @retval None */ __weak void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin) { - 80018e4: b580 push {r7, lr} - 80018e6: b082 sub sp, #8 - 80018e8: af00 add r7, sp, #0 - 80018ea: 0002 movs r2, r0 - 80018ec: 1dbb adds r3, r7, #6 - 80018ee: 801a strh r2, [r3, #0] + 80021a8: b580 push {r7, lr} + 80021aa: b082 sub sp, #8 + 80021ac: af00 add r7, sp, #0 + 80021ae: 0002 movs r2, r0 + 80021b0: 1dbb adds r3, r7, #6 + 80021b2: 801a strh r2, [r3, #0] UNUSED(GPIO_Pin); /* NOTE: This function should not be modified, when the callback is needed, the HAL_GPIO_EXTI_Falling_Callback could be implemented in the user file */ } - 80018f0: 46c0 nop @ (mov r8, r8) - 80018f2: 46bd mov sp, r7 - 80018f4: b002 add sp, #8 - 80018f6: bd80 pop {r7, pc} + 80021b4: 46c0 nop @ (mov r8, r8) + 80021b6: 46bd mov sp, r7 + 80021b8: b002 add sp, #8 + 80021ba: bd80 pop {r7, pc} -080018f8 : +080021bc : must adjust the number of CPU wait states in their application (SystemClock_Config() API) before calling the HAL_RCC_OscConfig() API to update the HSI48 clock division factor. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct) { - 80018f8: b580 push {r7, lr} - 80018fa: b086 sub sp, #24 - 80018fc: af00 add r7, sp, #0 - 80018fe: 6078 str r0, [r7, #4] + 80021bc: b580 push {r7, lr} + 80021be: b086 sub sp, #24 + 80021c0: af00 add r7, sp, #0 + 80021c2: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t temp_sysclksrc; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) - 8001900: 687b ldr r3, [r7, #4] - 8001902: 2b00 cmp r3, #0 - 8001904: d101 bne.n 800190a + 80021c4: 687b ldr r3, [r7, #4] + 80021c6: 2b00 cmp r3, #0 + 80021c8: d101 bne.n 80021ce { return HAL_ERROR; - 8001906: 2301 movs r3, #1 - 8001908: e1d0 b.n 8001cac + 80021ca: 2301 movs r3, #1 + 80021cc: e1d0 b.n 8002570 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) - 800190a: 687b ldr r3, [r7, #4] - 800190c: 681b ldr r3, [r3, #0] - 800190e: 2201 movs r2, #1 - 8001910: 4013 ands r3, r2 - 8001912: d100 bne.n 8001916 - 8001914: e069 b.n 80019ea + 80021ce: 687b ldr r3, [r7, #4] + 80021d0: 681b ldr r3, [r3, #0] + 80021d2: 2201 movs r2, #1 + 80021d4: 4013 ands r3, r2 + 80021d6: d100 bne.n 80021da + 80021d8: e069 b.n 80022ae { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); - 8001916: 4bc8 ldr r3, [pc, #800] @ (8001c38 ) - 8001918: 689b ldr r3, [r3, #8] - 800191a: 2238 movs r2, #56 @ 0x38 - 800191c: 4013 ands r3, r2 - 800191e: 617b str r3, [r7, #20] + 80021da: 4bc8 ldr r3, [pc, #800] @ (80024fc ) + 80021dc: 689b ldr r3, [r3, #8] + 80021de: 2238 movs r2, #56 @ 0x38 + 80021e0: 4013 ands r3, r2 + 80021e2: 617b str r3, [r7, #20] /* When the HSE is used as system clock in these cases it is not allowed to be disabled */ if (temp_sysclksrc == RCC_CFGR_SWS_HSE) - 8001920: 697b ldr r3, [r7, #20] - 8001922: 2b08 cmp r3, #8 - 8001924: d105 bne.n 8001932 + 80021e4: 697b ldr r3, [r7, #20] + 80021e6: 2b08 cmp r3, #8 + 80021e8: d105 bne.n 80021f6 { if (RCC_OscInitStruct->HSEState == RCC_HSE_OFF) - 8001926: 687b ldr r3, [r7, #4] - 8001928: 685b ldr r3, [r3, #4] - 800192a: 2b00 cmp r3, #0 - 800192c: d15d bne.n 80019ea + 80021ea: 687b ldr r3, [r7, #4] + 80021ec: 685b ldr r3, [r3, #4] + 80021ee: 2b00 cmp r3, #0 + 80021f0: d15d bne.n 80022ae { return HAL_ERROR; - 800192e: 2301 movs r3, #1 - 8001930: e1bc b.n 8001cac + 80021f2: 2301 movs r3, #1 + 80021f4: e1bc b.n 8002570 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); - 8001932: 687b ldr r3, [r7, #4] - 8001934: 685a ldr r2, [r3, #4] - 8001936: 2380 movs r3, #128 @ 0x80 - 8001938: 025b lsls r3, r3, #9 - 800193a: 429a cmp r2, r3 - 800193c: d107 bne.n 800194e - 800193e: 4bbe ldr r3, [pc, #760] @ (8001c38 ) - 8001940: 681a ldr r2, [r3, #0] - 8001942: 4bbd ldr r3, [pc, #756] @ (8001c38 ) - 8001944: 2180 movs r1, #128 @ 0x80 - 8001946: 0249 lsls r1, r1, #9 - 8001948: 430a orrs r2, r1 - 800194a: 601a str r2, [r3, #0] - 800194c: e020 b.n 8001990 - 800194e: 687b ldr r3, [r7, #4] - 8001950: 685a ldr r2, [r3, #4] - 8001952: 23a0 movs r3, #160 @ 0xa0 - 8001954: 02db lsls r3, r3, #11 - 8001956: 429a cmp r2, r3 - 8001958: d10e bne.n 8001978 - 800195a: 4bb7 ldr r3, [pc, #732] @ (8001c38 ) - 800195c: 681a ldr r2, [r3, #0] - 800195e: 4bb6 ldr r3, [pc, #728] @ (8001c38 ) - 8001960: 2180 movs r1, #128 @ 0x80 - 8001962: 02c9 lsls r1, r1, #11 - 8001964: 430a orrs r2, r1 - 8001966: 601a str r2, [r3, #0] - 8001968: 4bb3 ldr r3, [pc, #716] @ (8001c38 ) - 800196a: 681a ldr r2, [r3, #0] - 800196c: 4bb2 ldr r3, [pc, #712] @ (8001c38 ) - 800196e: 2180 movs r1, #128 @ 0x80 - 8001970: 0249 lsls r1, r1, #9 - 8001972: 430a orrs r2, r1 - 8001974: 601a str r2, [r3, #0] - 8001976: e00b b.n 8001990 - 8001978: 4baf ldr r3, [pc, #700] @ (8001c38 ) - 800197a: 681a ldr r2, [r3, #0] - 800197c: 4bae ldr r3, [pc, #696] @ (8001c38 ) - 800197e: 49af ldr r1, [pc, #700] @ (8001c3c ) - 8001980: 400a ands r2, r1 - 8001982: 601a str r2, [r3, #0] - 8001984: 4bac ldr r3, [pc, #688] @ (8001c38 ) - 8001986: 681a ldr r2, [r3, #0] - 8001988: 4bab ldr r3, [pc, #684] @ (8001c38 ) - 800198a: 49ad ldr r1, [pc, #692] @ (8001c40 ) - 800198c: 400a ands r2, r1 - 800198e: 601a str r2, [r3, #0] + 80021f6: 687b ldr r3, [r7, #4] + 80021f8: 685a ldr r2, [r3, #4] + 80021fa: 2380 movs r3, #128 @ 0x80 + 80021fc: 025b lsls r3, r3, #9 + 80021fe: 429a cmp r2, r3 + 8002200: d107 bne.n 8002212 + 8002202: 4bbe ldr r3, [pc, #760] @ (80024fc ) + 8002204: 681a ldr r2, [r3, #0] + 8002206: 4bbd ldr r3, [pc, #756] @ (80024fc ) + 8002208: 2180 movs r1, #128 @ 0x80 + 800220a: 0249 lsls r1, r1, #9 + 800220c: 430a orrs r2, r1 + 800220e: 601a str r2, [r3, #0] + 8002210: e020 b.n 8002254 + 8002212: 687b ldr r3, [r7, #4] + 8002214: 685a ldr r2, [r3, #4] + 8002216: 23a0 movs r3, #160 @ 0xa0 + 8002218: 02db lsls r3, r3, #11 + 800221a: 429a cmp r2, r3 + 800221c: d10e bne.n 800223c + 800221e: 4bb7 ldr r3, [pc, #732] @ (80024fc ) + 8002220: 681a ldr r2, [r3, #0] + 8002222: 4bb6 ldr r3, [pc, #728] @ (80024fc ) + 8002224: 2180 movs r1, #128 @ 0x80 + 8002226: 02c9 lsls r1, r1, #11 + 8002228: 430a orrs r2, r1 + 800222a: 601a str r2, [r3, #0] + 800222c: 4bb3 ldr r3, [pc, #716] @ (80024fc ) + 800222e: 681a ldr r2, [r3, #0] + 8002230: 4bb2 ldr r3, [pc, #712] @ (80024fc ) + 8002232: 2180 movs r1, #128 @ 0x80 + 8002234: 0249 lsls r1, r1, #9 + 8002236: 430a orrs r2, r1 + 8002238: 601a str r2, [r3, #0] + 800223a: e00b b.n 8002254 + 800223c: 4baf ldr r3, [pc, #700] @ (80024fc ) + 800223e: 681a ldr r2, [r3, #0] + 8002240: 4bae ldr r3, [pc, #696] @ (80024fc ) + 8002242: 49af ldr r1, [pc, #700] @ (8002500 ) + 8002244: 400a ands r2, r1 + 8002246: 601a str r2, [r3, #0] + 8002248: 4bac ldr r3, [pc, #688] @ (80024fc ) + 800224a: 681a ldr r2, [r3, #0] + 800224c: 4bab ldr r3, [pc, #684] @ (80024fc ) + 800224e: 49ad ldr r1, [pc, #692] @ (8002504 ) + 8002250: 400a ands r2, r1 + 8002252: 601a str r2, [r3, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) - 8001990: 687b ldr r3, [r7, #4] - 8001992: 685b ldr r3, [r3, #4] - 8001994: 2b00 cmp r3, #0 - 8001996: d014 beq.n 80019c2 + 8002254: 687b ldr r3, [r7, #4] + 8002256: 685b ldr r3, [r3, #4] + 8002258: 2b00 cmp r3, #0 + 800225a: d014 beq.n 8002286 { /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8001998: f7ff fb6c bl 8001074 - 800199c: 0003 movs r3, r0 - 800199e: 613b str r3, [r7, #16] + 800225c: f7ff fa6a bl 8001734 + 8002260: 0003 movs r3, r0 + 8002262: 613b str r3, [r7, #16] /* Wait till HSE is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) - 80019a0: e008 b.n 80019b4 + 8002264: e008 b.n 8002278 { if ((HAL_GetTick() - tickstart) > RCC_HSE_TIMEOUT_VALUE) - 80019a2: f7ff fb67 bl 8001074 - 80019a6: 0002 movs r2, r0 - 80019a8: 693b ldr r3, [r7, #16] - 80019aa: 1ad3 subs r3, r2, r3 - 80019ac: 2b64 cmp r3, #100 @ 0x64 - 80019ae: d901 bls.n 80019b4 + 8002266: f7ff fa65 bl 8001734 + 800226a: 0002 movs r2, r0 + 800226c: 693b ldr r3, [r7, #16] + 800226e: 1ad3 subs r3, r2, r3 + 8002270: 2b64 cmp r3, #100 @ 0x64 + 8002272: d901 bls.n 8002278 { return HAL_TIMEOUT; - 80019b0: 2303 movs r3, #3 - 80019b2: e17b b.n 8001cac + 8002274: 2303 movs r3, #3 + 8002276: e17b b.n 8002570 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) - 80019b4: 4ba0 ldr r3, [pc, #640] @ (8001c38 ) - 80019b6: 681a ldr r2, [r3, #0] - 80019b8: 2380 movs r3, #128 @ 0x80 - 80019ba: 029b lsls r3, r3, #10 - 80019bc: 4013 ands r3, r2 - 80019be: d0f0 beq.n 80019a2 - 80019c0: e013 b.n 80019ea + 8002278: 4ba0 ldr r3, [pc, #640] @ (80024fc ) + 800227a: 681a ldr r2, [r3, #0] + 800227c: 2380 movs r3, #128 @ 0x80 + 800227e: 029b lsls r3, r3, #10 + 8002280: 4013 ands r3, r2 + 8002282: d0f0 beq.n 8002266 + 8002284: e013 b.n 80022ae } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); - 80019c2: f7ff fb57 bl 8001074 - 80019c6: 0003 movs r3, r0 - 80019c8: 613b str r3, [r7, #16] + 8002286: f7ff fa55 bl 8001734 + 800228a: 0003 movs r3, r0 + 800228c: 613b str r3, [r7, #16] /* Wait till HSE is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) - 80019ca: e008 b.n 80019de + 800228e: e008 b.n 80022a2 { if ((HAL_GetTick() - tickstart) > RCC_HSE_TIMEOUT_VALUE) - 80019cc: f7ff fb52 bl 8001074 - 80019d0: 0002 movs r2, r0 - 80019d2: 693b ldr r3, [r7, #16] - 80019d4: 1ad3 subs r3, r2, r3 - 80019d6: 2b64 cmp r3, #100 @ 0x64 - 80019d8: d901 bls.n 80019de + 8002290: f7ff fa50 bl 8001734 + 8002294: 0002 movs r2, r0 + 8002296: 693b ldr r3, [r7, #16] + 8002298: 1ad3 subs r3, r2, r3 + 800229a: 2b64 cmp r3, #100 @ 0x64 + 800229c: d901 bls.n 80022a2 { return HAL_TIMEOUT; - 80019da: 2303 movs r3, #3 - 80019dc: e166 b.n 8001cac + 800229e: 2303 movs r3, #3 + 80022a0: e166 b.n 8002570 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) - 80019de: 4b96 ldr r3, [pc, #600] @ (8001c38 ) - 80019e0: 681a ldr r2, [r3, #0] - 80019e2: 2380 movs r3, #128 @ 0x80 - 80019e4: 029b lsls r3, r3, #10 - 80019e6: 4013 ands r3, r2 - 80019e8: d1f0 bne.n 80019cc + 80022a2: 4b96 ldr r3, [pc, #600] @ (80024fc ) + 80022a4: 681a ldr r2, [r3, #0] + 80022a6: 2380 movs r3, #128 @ 0x80 + 80022a8: 029b lsls r3, r3, #10 + 80022aa: 4013 ands r3, r2 + 80022ac: d1f0 bne.n 8002290 } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) - 80019ea: 687b ldr r3, [r7, #4] - 80019ec: 681b ldr r3, [r3, #0] - 80019ee: 2202 movs r2, #2 - 80019f0: 4013 ands r3, r2 - 80019f2: d100 bne.n 80019f6 - 80019f4: e086 b.n 8001b04 + 80022ae: 687b ldr r3, [r7, #4] + 80022b0: 681b ldr r3, [r3, #0] + 80022b2: 2202 movs r2, #2 + 80022b4: 4013 ands r3, r2 + 80022b6: d100 bne.n 80022ba + 80022b8: e086 b.n 80023c8 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); assert_param(IS_RCC_HSIDIV(RCC_OscInitStruct->HSIDiv)); /* Check if HSI48 is used as system clock */ temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); - 80019f6: 4b90 ldr r3, [pc, #576] @ (8001c38 ) - 80019f8: 689b ldr r3, [r3, #8] - 80019fa: 2238 movs r2, #56 @ 0x38 - 80019fc: 4013 ands r3, r2 - 80019fe: 617b str r3, [r7, #20] + 80022ba: 4b90 ldr r3, [pc, #576] @ (80024fc ) + 80022bc: 689b ldr r3, [r3, #8] + 80022be: 2238 movs r2, #56 @ 0x38 + 80022c0: 4013 ands r3, r2 + 80022c2: 617b str r3, [r7, #20] if (temp_sysclksrc == RCC_CFGR_SWS_HSI) - 8001a00: 697b ldr r3, [r7, #20] - 8001a02: 2b00 cmp r3, #0 - 8001a04: d12f bne.n 8001a66 + 80022c4: 697b ldr r3, [r7, #20] + 80022c6: 2b00 cmp r3, #0 + 80022c8: d12f bne.n 800232a { /* When HSI is used as system clock it can not be disabled */ if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF) - 8001a06: 687b ldr r3, [r7, #4] - 8001a08: 68db ldr r3, [r3, #12] - 8001a0a: 2b00 cmp r3, #0 - 8001a0c: d101 bne.n 8001a12 + 80022ca: 687b ldr r3, [r7, #4] + 80022cc: 68db ldr r3, [r3, #12] + 80022ce: 2b00 cmp r3, #0 + 80022d0: d101 bne.n 80022d6 { return HAL_ERROR; - 8001a0e: 2301 movs r3, #1 - 8001a10: e14c b.n 8001cac + 80022d2: 2301 movs r3, #1 + 80022d4: e14c b.n 8002570 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - 8001a12: 4b89 ldr r3, [pc, #548] @ (8001c38 ) - 8001a14: 685b ldr r3, [r3, #4] - 8001a16: 4a8b ldr r2, [pc, #556] @ (8001c44 ) - 8001a18: 4013 ands r3, r2 - 8001a1a: 0019 movs r1, r3 - 8001a1c: 687b ldr r3, [r7, #4] - 8001a1e: 695b ldr r3, [r3, #20] - 8001a20: 021a lsls r2, r3, #8 - 8001a22: 4b85 ldr r3, [pc, #532] @ (8001c38 ) - 8001a24: 430a orrs r2, r1 - 8001a26: 605a str r2, [r3, #4] + 80022d6: 4b89 ldr r3, [pc, #548] @ (80024fc ) + 80022d8: 685b ldr r3, [r3, #4] + 80022da: 4a8b ldr r2, [pc, #556] @ (8002508 ) + 80022dc: 4013 ands r3, r2 + 80022de: 0019 movs r1, r3 + 80022e0: 687b ldr r3, [r7, #4] + 80022e2: 695b ldr r3, [r3, #20] + 80022e4: 021a lsls r2, r3, #8 + 80022e6: 4b85 ldr r3, [pc, #532] @ (80024fc ) + 80022e8: 430a orrs r2, r1 + 80022ea: 605a str r2, [r3, #4] if (temp_sysclksrc == RCC_CFGR_SWS_HSI) - 8001a28: 697b ldr r3, [r7, #20] - 8001a2a: 2b00 cmp r3, #0 - 8001a2c: d112 bne.n 8001a54 + 80022ec: 697b ldr r3, [r7, #20] + 80022ee: 2b00 cmp r3, #0 + 80022f0: d112 bne.n 8002318 { /* Adjust the HSI48 division factor */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv); - 8001a2e: 4b82 ldr r3, [pc, #520] @ (8001c38 ) - 8001a30: 681b ldr r3, [r3, #0] - 8001a32: 4a85 ldr r2, [pc, #532] @ (8001c48 ) - 8001a34: 4013 ands r3, r2 - 8001a36: 0019 movs r1, r3 - 8001a38: 687b ldr r3, [r7, #4] - 8001a3a: 691a ldr r2, [r3, #16] - 8001a3c: 4b7e ldr r3, [pc, #504] @ (8001c38 ) - 8001a3e: 430a orrs r2, r1 - 8001a40: 601a str r2, [r3, #0] + 80022f2: 4b82 ldr r3, [pc, #520] @ (80024fc ) + 80022f4: 681b ldr r3, [r3, #0] + 80022f6: 4a85 ldr r2, [pc, #532] @ (800250c ) + 80022f8: 4013 ands r3, r2 + 80022fa: 0019 movs r1, r3 + 80022fc: 687b ldr r3, [r7, #4] + 80022fe: 691a ldr r2, [r3, #16] + 8002300: 4b7e ldr r3, [pc, #504] @ (80024fc ) + 8002302: 430a orrs r2, r1 + 8002304: 601a str r2, [r3, #0] /* Update the SystemCoreClock global variable with HSISYS value */ SystemCoreClock = (HSI_VALUE / (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos))); - 8001a42: 4b7d ldr r3, [pc, #500] @ (8001c38 ) - 8001a44: 681b ldr r3, [r3, #0] - 8001a46: 0adb lsrs r3, r3, #11 - 8001a48: 2207 movs r2, #7 - 8001a4a: 4013 ands r3, r2 - 8001a4c: 4a7f ldr r2, [pc, #508] @ (8001c4c ) - 8001a4e: 40da lsrs r2, r3 - 8001a50: 4b7f ldr r3, [pc, #508] @ (8001c50 ) - 8001a52: 601a str r2, [r3, #0] + 8002306: 4b7d ldr r3, [pc, #500] @ (80024fc ) + 8002308: 681b ldr r3, [r3, #0] + 800230a: 0adb lsrs r3, r3, #11 + 800230c: 2207 movs r2, #7 + 800230e: 4013 ands r3, r2 + 8002310: 4a7f ldr r2, [pc, #508] @ (8002510 ) + 8002312: 40da lsrs r2, r3 + 8002314: 4b7f ldr r3, [pc, #508] @ (8002514 ) + 8002316: 601a str r2, [r3, #0] } /* Adapt Systick interrupt period */ if (HAL_InitTick(uwTickPrio) != HAL_OK) - 8001a54: 4b7f ldr r3, [pc, #508] @ (8001c54 ) - 8001a56: 681b ldr r3, [r3, #0] - 8001a58: 0018 movs r0, r3 - 8001a5a: f7ff faaf bl 8000fbc - 8001a5e: 1e03 subs r3, r0, #0 - 8001a60: d050 beq.n 8001b04 + 8002318: 4b7f ldr r3, [pc, #508] @ (8002518 ) + 800231a: 681b ldr r3, [r3, #0] + 800231c: 0018 movs r0, r3 + 800231e: f7ff f9ad bl 800167c + 8002322: 1e03 subs r3, r0, #0 + 8002324: d050 beq.n 80023c8 { return HAL_ERROR; - 8001a62: 2301 movs r3, #1 - 8001a64: e122 b.n 8001cac + 8002326: 2301 movs r3, #1 + 8002328: e122 b.n 8002570 } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) - 8001a66: 687b ldr r3, [r7, #4] - 8001a68: 68db ldr r3, [r3, #12] - 8001a6a: 2b00 cmp r3, #0 - 8001a6c: d030 beq.n 8001ad0 + 800232a: 687b ldr r3, [r7, #4] + 800232c: 68db ldr r3, [r3, #12] + 800232e: 2b00 cmp r3, #0 + 8002330: d030 beq.n 8002394 { /* Configure the HSI48 division factor */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv); - 8001a6e: 4b72 ldr r3, [pc, #456] @ (8001c38 ) - 8001a70: 681b ldr r3, [r3, #0] - 8001a72: 4a75 ldr r2, [pc, #468] @ (8001c48 ) - 8001a74: 4013 ands r3, r2 - 8001a76: 0019 movs r1, r3 - 8001a78: 687b ldr r3, [r7, #4] - 8001a7a: 691a ldr r2, [r3, #16] - 8001a7c: 4b6e ldr r3, [pc, #440] @ (8001c38 ) - 8001a7e: 430a orrs r2, r1 - 8001a80: 601a str r2, [r3, #0] + 8002332: 4b72 ldr r3, [pc, #456] @ (80024fc ) + 8002334: 681b ldr r3, [r3, #0] + 8002336: 4a75 ldr r2, [pc, #468] @ (800250c ) + 8002338: 4013 ands r3, r2 + 800233a: 0019 movs r1, r3 + 800233c: 687b ldr r3, [r7, #4] + 800233e: 691a ldr r2, [r3, #16] + 8002340: 4b6e ldr r3, [pc, #440] @ (80024fc ) + 8002342: 430a orrs r2, r1 + 8002344: 601a str r2, [r3, #0] /* Enable the Internal High Speed oscillator (HSI48). */ __HAL_RCC_HSI_ENABLE(); - 8001a82: 4b6d ldr r3, [pc, #436] @ (8001c38 ) - 8001a84: 681a ldr r2, [r3, #0] - 8001a86: 4b6c ldr r3, [pc, #432] @ (8001c38 ) - 8001a88: 2180 movs r1, #128 @ 0x80 - 8001a8a: 0049 lsls r1, r1, #1 - 8001a8c: 430a orrs r2, r1 - 8001a8e: 601a str r2, [r3, #0] + 8002346: 4b6d ldr r3, [pc, #436] @ (80024fc ) + 8002348: 681a ldr r2, [r3, #0] + 800234a: 4b6c ldr r3, [pc, #432] @ (80024fc ) + 800234c: 2180 movs r1, #128 @ 0x80 + 800234e: 0049 lsls r1, r1, #1 + 8002350: 430a orrs r2, r1 + 8002352: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8001a90: f7ff faf0 bl 8001074 - 8001a94: 0003 movs r3, r0 - 8001a96: 613b str r3, [r7, #16] + 8002354: f7ff f9ee bl 8001734 + 8002358: 0003 movs r3, r0 + 800235a: 613b str r3, [r7, #16] /* Wait till HSI is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) - 8001a98: e008 b.n 8001aac + 800235c: e008 b.n 8002370 { if ((HAL_GetTick() - tickstart) > RCC_HSI_TIMEOUT_VALUE) - 8001a9a: f7ff faeb bl 8001074 - 8001a9e: 0002 movs r2, r0 - 8001aa0: 693b ldr r3, [r7, #16] - 8001aa2: 1ad3 subs r3, r2, r3 - 8001aa4: 2b02 cmp r3, #2 - 8001aa6: d901 bls.n 8001aac + 800235e: f7ff f9e9 bl 8001734 + 8002362: 0002 movs r2, r0 + 8002364: 693b ldr r3, [r7, #16] + 8002366: 1ad3 subs r3, r2, r3 + 8002368: 2b02 cmp r3, #2 + 800236a: d901 bls.n 8002370 { return HAL_TIMEOUT; - 8001aa8: 2303 movs r3, #3 - 8001aaa: e0ff b.n 8001cac + 800236c: 2303 movs r3, #3 + 800236e: e0ff b.n 8002570 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) - 8001aac: 4b62 ldr r3, [pc, #392] @ (8001c38 ) - 8001aae: 681a ldr r2, [r3, #0] - 8001ab0: 2380 movs r3, #128 @ 0x80 - 8001ab2: 00db lsls r3, r3, #3 - 8001ab4: 4013 ands r3, r2 - 8001ab6: d0f0 beq.n 8001a9a + 8002370: 4b62 ldr r3, [pc, #392] @ (80024fc ) + 8002372: 681a ldr r2, [r3, #0] + 8002374: 2380 movs r3, #128 @ 0x80 + 8002376: 00db lsls r3, r3, #3 + 8002378: 4013 ands r3, r2 + 800237a: d0f0 beq.n 800235e } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - 8001ab8: 4b5f ldr r3, [pc, #380] @ (8001c38 ) - 8001aba: 685b ldr r3, [r3, #4] - 8001abc: 4a61 ldr r2, [pc, #388] @ (8001c44 ) - 8001abe: 4013 ands r3, r2 - 8001ac0: 0019 movs r1, r3 - 8001ac2: 687b ldr r3, [r7, #4] - 8001ac4: 695b ldr r3, [r3, #20] - 8001ac6: 021a lsls r2, r3, #8 - 8001ac8: 4b5b ldr r3, [pc, #364] @ (8001c38 ) - 8001aca: 430a orrs r2, r1 - 8001acc: 605a str r2, [r3, #4] - 8001ace: e019 b.n 8001b04 + 800237c: 4b5f ldr r3, [pc, #380] @ (80024fc ) + 800237e: 685b ldr r3, [r3, #4] + 8002380: 4a61 ldr r2, [pc, #388] @ (8002508 ) + 8002382: 4013 ands r3, r2 + 8002384: 0019 movs r1, r3 + 8002386: 687b ldr r3, [r7, #4] + 8002388: 695b ldr r3, [r3, #20] + 800238a: 021a lsls r2, r3, #8 + 800238c: 4b5b ldr r3, [pc, #364] @ (80024fc ) + 800238e: 430a orrs r2, r1 + 8002390: 605a str r2, [r3, #4] + 8002392: e019 b.n 80023c8 } else { /* Disable the Internal High Speed oscillator (HSI48). */ __HAL_RCC_HSI_DISABLE(); - 8001ad0: 4b59 ldr r3, [pc, #356] @ (8001c38 ) - 8001ad2: 681a ldr r2, [r3, #0] - 8001ad4: 4b58 ldr r3, [pc, #352] @ (8001c38 ) - 8001ad6: 4960 ldr r1, [pc, #384] @ (8001c58 ) - 8001ad8: 400a ands r2, r1 - 8001ada: 601a str r2, [r3, #0] + 8002394: 4b59 ldr r3, [pc, #356] @ (80024fc ) + 8002396: 681a ldr r2, [r3, #0] + 8002398: 4b58 ldr r3, [pc, #352] @ (80024fc ) + 800239a: 4960 ldr r1, [pc, #384] @ (800251c ) + 800239c: 400a ands r2, r1 + 800239e: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8001adc: f7ff faca bl 8001074 - 8001ae0: 0003 movs r3, r0 - 8001ae2: 613b str r3, [r7, #16] + 80023a0: f7ff f9c8 bl 8001734 + 80023a4: 0003 movs r3, r0 + 80023a6: 613b str r3, [r7, #16] /* Wait till HSI is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) - 8001ae4: e008 b.n 8001af8 + 80023a8: e008 b.n 80023bc { if ((HAL_GetTick() - tickstart) > RCC_HSI_TIMEOUT_VALUE) - 8001ae6: f7ff fac5 bl 8001074 - 8001aea: 0002 movs r2, r0 - 8001aec: 693b ldr r3, [r7, #16] - 8001aee: 1ad3 subs r3, r2, r3 - 8001af0: 2b02 cmp r3, #2 - 8001af2: d901 bls.n 8001af8 + 80023aa: f7ff f9c3 bl 8001734 + 80023ae: 0002 movs r2, r0 + 80023b0: 693b ldr r3, [r7, #16] + 80023b2: 1ad3 subs r3, r2, r3 + 80023b4: 2b02 cmp r3, #2 + 80023b6: d901 bls.n 80023bc { return HAL_TIMEOUT; - 8001af4: 2303 movs r3, #3 - 8001af6: e0d9 b.n 8001cac + 80023b8: 2303 movs r3, #3 + 80023ba: e0d9 b.n 8002570 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) - 8001af8: 4b4f ldr r3, [pc, #316] @ (8001c38 ) - 8001afa: 681a ldr r2, [r3, #0] - 8001afc: 2380 movs r3, #128 @ 0x80 - 8001afe: 00db lsls r3, r3, #3 - 8001b00: 4013 ands r3, r2 - 8001b02: d1f0 bne.n 8001ae6 + 80023bc: 4b4f ldr r3, [pc, #316] @ (80024fc ) + 80023be: 681a ldr r2, [r3, #0] + 80023c0: 2380 movs r3, #128 @ 0x80 + 80023c2: 00db lsls r3, r3, #3 + 80023c4: 4013 ands r3, r2 + 80023c6: d1f0 bne.n 80023aa } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) - 8001b04: 687b ldr r3, [r7, #4] - 8001b06: 681b ldr r3, [r3, #0] - 8001b08: 2208 movs r2, #8 - 8001b0a: 4013 ands r3, r2 - 8001b0c: d042 beq.n 8001b94 + 80023c8: 687b ldr r3, [r7, #4] + 80023ca: 681b ldr r3, [r3, #0] + 80023cc: 2208 movs r2, #8 + 80023ce: 4013 ands r3, r2 + 80023d0: d042 beq.n 8002458 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check if LSI is used as system clock */ if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSI) - 8001b0e: 4b4a ldr r3, [pc, #296] @ (8001c38 ) - 8001b10: 689b ldr r3, [r3, #8] - 8001b12: 2238 movs r2, #56 @ 0x38 - 8001b14: 4013 ands r3, r2 - 8001b16: 2b18 cmp r3, #24 - 8001b18: d105 bne.n 8001b26 + 80023d2: 4b4a ldr r3, [pc, #296] @ (80024fc ) + 80023d4: 689b ldr r3, [r3, #8] + 80023d6: 2238 movs r2, #56 @ 0x38 + 80023d8: 4013 ands r3, r2 + 80023da: 2b18 cmp r3, #24 + 80023dc: d105 bne.n 80023ea { /* When LSI is used as system clock it will not be disabled */ if (RCC_OscInitStruct->LSIState == RCC_LSI_OFF) - 8001b1a: 687b ldr r3, [r7, #4] - 8001b1c: 699b ldr r3, [r3, #24] - 8001b1e: 2b00 cmp r3, #0 - 8001b20: d138 bne.n 8001b94 + 80023de: 687b ldr r3, [r7, #4] + 80023e0: 699b ldr r3, [r3, #24] + 80023e2: 2b00 cmp r3, #0 + 80023e4: d138 bne.n 8002458 { return HAL_ERROR; - 8001b22: 2301 movs r3, #1 - 8001b24: e0c2 b.n 8001cac + 80023e6: 2301 movs r3, #1 + 80023e8: e0c2 b.n 8002570 } } else { /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) - 8001b26: 687b ldr r3, [r7, #4] - 8001b28: 699b ldr r3, [r3, #24] - 8001b2a: 2b00 cmp r3, #0 - 8001b2c: d019 beq.n 8001b62 + 80023ea: 687b ldr r3, [r7, #4] + 80023ec: 699b ldr r3, [r3, #24] + 80023ee: 2b00 cmp r3, #0 + 80023f0: d019 beq.n 8002426 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); - 8001b2e: 4b42 ldr r3, [pc, #264] @ (8001c38 ) - 8001b30: 6e1a ldr r2, [r3, #96] @ 0x60 - 8001b32: 4b41 ldr r3, [pc, #260] @ (8001c38 ) - 8001b34: 2101 movs r1, #1 - 8001b36: 430a orrs r2, r1 - 8001b38: 661a str r2, [r3, #96] @ 0x60 + 80023f2: 4b42 ldr r3, [pc, #264] @ (80024fc ) + 80023f4: 6e1a ldr r2, [r3, #96] @ 0x60 + 80023f6: 4b41 ldr r3, [pc, #260] @ (80024fc ) + 80023f8: 2101 movs r1, #1 + 80023fa: 430a orrs r2, r1 + 80023fc: 661a str r2, [r3, #96] @ 0x60 /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8001b3a: f7ff fa9b bl 8001074 - 8001b3e: 0003 movs r3, r0 - 8001b40: 613b str r3, [r7, #16] + 80023fe: f7ff f999 bl 8001734 + 8002402: 0003 movs r3, r0 + 8002404: 613b str r3, [r7, #16] /* Wait till LSI is ready */ while (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) == 0U) - 8001b42: e008 b.n 8001b56 + 8002406: e008 b.n 800241a { if ((HAL_GetTick() - tickstart) > RCC_LSI_TIMEOUT_VALUE) - 8001b44: f7ff fa96 bl 8001074 - 8001b48: 0002 movs r2, r0 - 8001b4a: 693b ldr r3, [r7, #16] - 8001b4c: 1ad3 subs r3, r2, r3 - 8001b4e: 2b02 cmp r3, #2 - 8001b50: d901 bls.n 8001b56 + 8002408: f7ff f994 bl 8001734 + 800240c: 0002 movs r2, r0 + 800240e: 693b ldr r3, [r7, #16] + 8002410: 1ad3 subs r3, r2, r3 + 8002412: 2b02 cmp r3, #2 + 8002414: d901 bls.n 800241a { return HAL_TIMEOUT; - 8001b52: 2303 movs r3, #3 - 8001b54: e0aa b.n 8001cac + 8002416: 2303 movs r3, #3 + 8002418: e0aa b.n 8002570 while (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) == 0U) - 8001b56: 4b38 ldr r3, [pc, #224] @ (8001c38 ) - 8001b58: 6e1b ldr r3, [r3, #96] @ 0x60 - 8001b5a: 2202 movs r2, #2 - 8001b5c: 4013 ands r3, r2 - 8001b5e: d0f1 beq.n 8001b44 - 8001b60: e018 b.n 8001b94 + 800241a: 4b38 ldr r3, [pc, #224] @ (80024fc ) + 800241c: 6e1b ldr r3, [r3, #96] @ 0x60 + 800241e: 2202 movs r2, #2 + 8002420: 4013 ands r3, r2 + 8002422: d0f1 beq.n 8002408 + 8002424: e018 b.n 8002458 } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); - 8001b62: 4b35 ldr r3, [pc, #212] @ (8001c38 ) - 8001b64: 6e1a ldr r2, [r3, #96] @ 0x60 - 8001b66: 4b34 ldr r3, [pc, #208] @ (8001c38 ) - 8001b68: 2101 movs r1, #1 - 8001b6a: 438a bics r2, r1 - 8001b6c: 661a str r2, [r3, #96] @ 0x60 + 8002426: 4b35 ldr r3, [pc, #212] @ (80024fc ) + 8002428: 6e1a ldr r2, [r3, #96] @ 0x60 + 800242a: 4b34 ldr r3, [pc, #208] @ (80024fc ) + 800242c: 2101 movs r1, #1 + 800242e: 438a bics r2, r1 + 8002430: 661a str r2, [r3, #96] @ 0x60 /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8001b6e: f7ff fa81 bl 8001074 - 8001b72: 0003 movs r3, r0 - 8001b74: 613b str r3, [r7, #16] + 8002432: f7ff f97f bl 8001734 + 8002436: 0003 movs r3, r0 + 8002438: 613b str r3, [r7, #16] /* Wait till LSI is disabled */ while (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) != 0U) - 8001b76: e008 b.n 8001b8a + 800243a: e008 b.n 800244e { if ((HAL_GetTick() - tickstart) > RCC_LSI_TIMEOUT_VALUE) - 8001b78: f7ff fa7c bl 8001074 - 8001b7c: 0002 movs r2, r0 - 8001b7e: 693b ldr r3, [r7, #16] - 8001b80: 1ad3 subs r3, r2, r3 - 8001b82: 2b02 cmp r3, #2 - 8001b84: d901 bls.n 8001b8a + 800243c: f7ff f97a bl 8001734 + 8002440: 0002 movs r2, r0 + 8002442: 693b ldr r3, [r7, #16] + 8002444: 1ad3 subs r3, r2, r3 + 8002446: 2b02 cmp r3, #2 + 8002448: d901 bls.n 800244e { return HAL_TIMEOUT; - 8001b86: 2303 movs r3, #3 - 8001b88: e090 b.n 8001cac + 800244a: 2303 movs r3, #3 + 800244c: e090 b.n 8002570 while (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) != 0U) - 8001b8a: 4b2b ldr r3, [pc, #172] @ (8001c38 ) - 8001b8c: 6e1b ldr r3, [r3, #96] @ 0x60 - 8001b8e: 2202 movs r2, #2 - 8001b90: 4013 ands r3, r2 - 8001b92: d1f1 bne.n 8001b78 + 800244e: 4b2b ldr r3, [pc, #172] @ (80024fc ) + 8002450: 6e1b ldr r3, [r3, #96] @ 0x60 + 8002452: 2202 movs r2, #2 + 8002454: 4013 ands r3, r2 + 8002456: d1f1 bne.n 800243c } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) - 8001b94: 687b ldr r3, [r7, #4] - 8001b96: 681b ldr r3, [r3, #0] - 8001b98: 2204 movs r2, #4 - 8001b9a: 4013 ands r3, r2 - 8001b9c: d100 bne.n 8001ba0 - 8001b9e: e084 b.n 8001caa + 8002458: 687b ldr r3, [r7, #4] + 800245a: 681b ldr r3, [r3, #0] + 800245c: 2204 movs r2, #4 + 800245e: 4013 ands r3, r2 + 8002460: d100 bne.n 8002464 + 8002462: e084 b.n 800256e { FlagStatus pwrclkchanged = RESET; - 8001ba0: 230f movs r3, #15 - 8001ba2: 18fb adds r3, r7, r3 - 8001ba4: 2200 movs r2, #0 - 8001ba6: 701a strb r2, [r3, #0] + 8002464: 230f movs r3, #15 + 8002466: 18fb adds r3, r7, r3 + 8002468: 2200 movs r2, #0 + 800246a: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* When the LSE is used as system clock, it is not allowed disable it */ if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSE) - 8001ba8: 4b23 ldr r3, [pc, #140] @ (8001c38 ) - 8001baa: 689b ldr r3, [r3, #8] - 8001bac: 2238 movs r2, #56 @ 0x38 - 8001bae: 4013 ands r3, r2 - 8001bb0: 2b20 cmp r3, #32 - 8001bb2: d106 bne.n 8001bc2 + 800246c: 4b23 ldr r3, [pc, #140] @ (80024fc ) + 800246e: 689b ldr r3, [r3, #8] + 8002470: 2238 movs r2, #56 @ 0x38 + 8002472: 4013 ands r3, r2 + 8002474: 2b20 cmp r3, #32 + 8002476: d106 bne.n 8002486 { if (RCC_OscInitStruct->LSEState == RCC_LSE_OFF) - 8001bb4: 687b ldr r3, [r7, #4] - 8001bb6: 689b ldr r3, [r3, #8] - 8001bb8: 2b00 cmp r3, #0 - 8001bba: d000 beq.n 8001bbe - 8001bbc: e075 b.n 8001caa + 8002478: 687b ldr r3, [r7, #4] + 800247a: 689b ldr r3, [r3, #8] + 800247c: 2b00 cmp r3, #0 + 800247e: d000 beq.n 8002482 + 8002480: e075 b.n 800256e { return HAL_ERROR; - 8001bbe: 2301 movs r3, #1 - 8001bc0: e074 b.n 8001cac + 8002482: 2301 movs r3, #1 + 8002484: e074 b.n 8002570 } else { /* Update LSE configuration in RTC Domain control register */ /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); - 8001bc2: 687b ldr r3, [r7, #4] - 8001bc4: 689b ldr r3, [r3, #8] - 8001bc6: 2b01 cmp r3, #1 - 8001bc8: d106 bne.n 8001bd8 - 8001bca: 4b1b ldr r3, [pc, #108] @ (8001c38 ) - 8001bcc: 6dda ldr r2, [r3, #92] @ 0x5c - 8001bce: 4b1a ldr r3, [pc, #104] @ (8001c38 ) - 8001bd0: 2101 movs r1, #1 - 8001bd2: 430a orrs r2, r1 - 8001bd4: 65da str r2, [r3, #92] @ 0x5c - 8001bd6: e01c b.n 8001c12 - 8001bd8: 687b ldr r3, [r7, #4] - 8001bda: 689b ldr r3, [r3, #8] - 8001bdc: 2b05 cmp r3, #5 - 8001bde: d10c bne.n 8001bfa - 8001be0: 4b15 ldr r3, [pc, #84] @ (8001c38 ) - 8001be2: 6dda ldr r2, [r3, #92] @ 0x5c - 8001be4: 4b14 ldr r3, [pc, #80] @ (8001c38 ) - 8001be6: 2104 movs r1, #4 - 8001be8: 430a orrs r2, r1 - 8001bea: 65da str r2, [r3, #92] @ 0x5c - 8001bec: 4b12 ldr r3, [pc, #72] @ (8001c38 ) - 8001bee: 6dda ldr r2, [r3, #92] @ 0x5c - 8001bf0: 4b11 ldr r3, [pc, #68] @ (8001c38 ) - 8001bf2: 2101 movs r1, #1 - 8001bf4: 430a orrs r2, r1 - 8001bf6: 65da str r2, [r3, #92] @ 0x5c - 8001bf8: e00b b.n 8001c12 - 8001bfa: 4b0f ldr r3, [pc, #60] @ (8001c38 ) - 8001bfc: 6dda ldr r2, [r3, #92] @ 0x5c - 8001bfe: 4b0e ldr r3, [pc, #56] @ (8001c38 ) - 8001c00: 2101 movs r1, #1 - 8001c02: 438a bics r2, r1 - 8001c04: 65da str r2, [r3, #92] @ 0x5c - 8001c06: 4b0c ldr r3, [pc, #48] @ (8001c38 ) - 8001c08: 6dda ldr r2, [r3, #92] @ 0x5c - 8001c0a: 4b0b ldr r3, [pc, #44] @ (8001c38 ) - 8001c0c: 2104 movs r1, #4 - 8001c0e: 438a bics r2, r1 - 8001c10: 65da str r2, [r3, #92] @ 0x5c + 8002486: 687b ldr r3, [r7, #4] + 8002488: 689b ldr r3, [r3, #8] + 800248a: 2b01 cmp r3, #1 + 800248c: d106 bne.n 800249c + 800248e: 4b1b ldr r3, [pc, #108] @ (80024fc ) + 8002490: 6dda ldr r2, [r3, #92] @ 0x5c + 8002492: 4b1a ldr r3, [pc, #104] @ (80024fc ) + 8002494: 2101 movs r1, #1 + 8002496: 430a orrs r2, r1 + 8002498: 65da str r2, [r3, #92] @ 0x5c + 800249a: e01c b.n 80024d6 + 800249c: 687b ldr r3, [r7, #4] + 800249e: 689b ldr r3, [r3, #8] + 80024a0: 2b05 cmp r3, #5 + 80024a2: d10c bne.n 80024be + 80024a4: 4b15 ldr r3, [pc, #84] @ (80024fc ) + 80024a6: 6dda ldr r2, [r3, #92] @ 0x5c + 80024a8: 4b14 ldr r3, [pc, #80] @ (80024fc ) + 80024aa: 2104 movs r1, #4 + 80024ac: 430a orrs r2, r1 + 80024ae: 65da str r2, [r3, #92] @ 0x5c + 80024b0: 4b12 ldr r3, [pc, #72] @ (80024fc ) + 80024b2: 6dda ldr r2, [r3, #92] @ 0x5c + 80024b4: 4b11 ldr r3, [pc, #68] @ (80024fc ) + 80024b6: 2101 movs r1, #1 + 80024b8: 430a orrs r2, r1 + 80024ba: 65da str r2, [r3, #92] @ 0x5c + 80024bc: e00b b.n 80024d6 + 80024be: 4b0f ldr r3, [pc, #60] @ (80024fc ) + 80024c0: 6dda ldr r2, [r3, #92] @ 0x5c + 80024c2: 4b0e ldr r3, [pc, #56] @ (80024fc ) + 80024c4: 2101 movs r1, #1 + 80024c6: 438a bics r2, r1 + 80024c8: 65da str r2, [r3, #92] @ 0x5c + 80024ca: 4b0c ldr r3, [pc, #48] @ (80024fc ) + 80024cc: 6dda ldr r2, [r3, #92] @ 0x5c + 80024ce: 4b0b ldr r3, [pc, #44] @ (80024fc ) + 80024d0: 2104 movs r1, #4 + 80024d2: 438a bics r2, r1 + 80024d4: 65da str r2, [r3, #92] @ 0x5c /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) - 8001c12: 687b ldr r3, [r7, #4] - 8001c14: 689b ldr r3, [r3, #8] - 8001c16: 2b00 cmp r3, #0 - 8001c18: d028 beq.n 8001c6c + 80024d6: 687b ldr r3, [r7, #4] + 80024d8: 689b ldr r3, [r3, #8] + 80024da: 2b00 cmp r3, #0 + 80024dc: d028 beq.n 8002530 { /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8001c1a: f7ff fa2b bl 8001074 - 8001c1e: 0003 movs r3, r0 - 8001c20: 613b str r3, [r7, #16] + 80024de: f7ff f929 bl 8001734 + 80024e2: 0003 movs r3, r0 + 80024e4: 613b str r3, [r7, #16] /* Wait till LSE is ready */ while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U) - 8001c22: e01d b.n 8001c60 + 80024e6: e01d b.n 8002524 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - 8001c24: f7ff fa26 bl 8001074 - 8001c28: 0002 movs r2, r0 - 8001c2a: 693b ldr r3, [r7, #16] - 8001c2c: 1ad3 subs r3, r2, r3 - 8001c2e: 4a0b ldr r2, [pc, #44] @ (8001c5c ) - 8001c30: 4293 cmp r3, r2 - 8001c32: d915 bls.n 8001c60 + 80024e8: f7ff f924 bl 8001734 + 80024ec: 0002 movs r2, r0 + 80024ee: 693b ldr r3, [r7, #16] + 80024f0: 1ad3 subs r3, r2, r3 + 80024f2: 4a0b ldr r2, [pc, #44] @ (8002520 ) + 80024f4: 4293 cmp r3, r2 + 80024f6: d915 bls.n 8002524 { return HAL_TIMEOUT; - 8001c34: 2303 movs r3, #3 - 8001c36: e039 b.n 8001cac - 8001c38: 40021000 .word 0x40021000 - 8001c3c: fffeffff .word 0xfffeffff - 8001c40: fffbffff .word 0xfffbffff - 8001c44: ffff80ff .word 0xffff80ff - 8001c48: ffffc7ff .word 0xffffc7ff - 8001c4c: 02dc6c00 .word 0x02dc6c00 - 8001c50: 20000000 .word 0x20000000 - 8001c54: 20000004 .word 0x20000004 - 8001c58: fffffeff .word 0xfffffeff - 8001c5c: 00001388 .word 0x00001388 + 80024f8: 2303 movs r3, #3 + 80024fa: e039 b.n 8002570 + 80024fc: 40021000 .word 0x40021000 + 8002500: fffeffff .word 0xfffeffff + 8002504: fffbffff .word 0xfffbffff + 8002508: ffff80ff .word 0xffff80ff + 800250c: ffffc7ff .word 0xffffc7ff + 8002510: 02dc6c00 .word 0x02dc6c00 + 8002514: 20000018 .word 0x20000018 + 8002518: 2000001c .word 0x2000001c + 800251c: fffffeff .word 0xfffffeff + 8002520: 00001388 .word 0x00001388 while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U) - 8001c60: 4b14 ldr r3, [pc, #80] @ (8001cb4 ) - 8001c62: 6ddb ldr r3, [r3, #92] @ 0x5c - 8001c64: 2202 movs r2, #2 - 8001c66: 4013 ands r3, r2 - 8001c68: d0dc beq.n 8001c24 - 8001c6a: e013 b.n 8001c94 + 8002524: 4b14 ldr r3, [pc, #80] @ (8002578 ) + 8002526: 6ddb ldr r3, [r3, #92] @ 0x5c + 8002528: 2202 movs r2, #2 + 800252a: 4013 ands r3, r2 + 800252c: d0dc beq.n 80024e8 + 800252e: e013 b.n 8002558 } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8001c6c: f7ff fa02 bl 8001074 - 8001c70: 0003 movs r3, r0 - 8001c72: 613b str r3, [r7, #16] + 8002530: f7ff f900 bl 8001734 + 8002534: 0003 movs r3, r0 + 8002536: 613b str r3, [r7, #16] /* Wait till LSE is disabled */ while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) != 0U) - 8001c74: e009 b.n 8001c8a + 8002538: e009 b.n 800254e { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - 8001c76: f7ff f9fd bl 8001074 - 8001c7a: 0002 movs r2, r0 - 8001c7c: 693b ldr r3, [r7, #16] - 8001c7e: 1ad3 subs r3, r2, r3 - 8001c80: 4a0d ldr r2, [pc, #52] @ (8001cb8 ) - 8001c82: 4293 cmp r3, r2 - 8001c84: d901 bls.n 8001c8a + 800253a: f7ff f8fb bl 8001734 + 800253e: 0002 movs r2, r0 + 8002540: 693b ldr r3, [r7, #16] + 8002542: 1ad3 subs r3, r2, r3 + 8002544: 4a0d ldr r2, [pc, #52] @ (800257c ) + 8002546: 4293 cmp r3, r2 + 8002548: d901 bls.n 800254e { return HAL_TIMEOUT; - 8001c86: 2303 movs r3, #3 - 8001c88: e010 b.n 8001cac + 800254a: 2303 movs r3, #3 + 800254c: e010 b.n 8002570 while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) != 0U) - 8001c8a: 4b0a ldr r3, [pc, #40] @ (8001cb4 ) - 8001c8c: 6ddb ldr r3, [r3, #92] @ 0x5c - 8001c8e: 2202 movs r2, #2 - 8001c90: 4013 ands r3, r2 - 8001c92: d1f0 bne.n 8001c76 + 800254e: 4b0a ldr r3, [pc, #40] @ (8002578 ) + 8002550: 6ddb ldr r3, [r3, #92] @ 0x5c + 8002552: 2202 movs r2, #2 + 8002554: 4013 ands r3, r2 + 8002556: d1f0 bne.n 800253a } } } /* Restore clock configuration if changed */ if (pwrclkchanged == SET) - 8001c94: 230f movs r3, #15 - 8001c96: 18fb adds r3, r7, r3 - 8001c98: 781b ldrb r3, [r3, #0] - 8001c9a: 2b01 cmp r3, #1 - 8001c9c: d105 bne.n 8001caa + 8002558: 230f movs r3, #15 + 800255a: 18fb adds r3, r7, r3 + 800255c: 781b ldrb r3, [r3, #0] + 800255e: 2b01 cmp r3, #1 + 8002560: d105 bne.n 800256e { __HAL_RCC_PWR_CLK_DISABLE(); - 8001c9e: 4b05 ldr r3, [pc, #20] @ (8001cb4 ) - 8001ca0: 6bda ldr r2, [r3, #60] @ 0x3c - 8001ca2: 4b04 ldr r3, [pc, #16] @ (8001cb4 ) - 8001ca4: 4905 ldr r1, [pc, #20] @ (8001cbc ) - 8001ca6: 400a ands r2, r1 - 8001ca8: 63da str r2, [r3, #60] @ 0x3c + 8002562: 4b05 ldr r3, [pc, #20] @ (8002578 ) + 8002564: 6bda ldr r2, [r3, #60] @ 0x3c + 8002566: 4b04 ldr r3, [pc, #16] @ (8002578 ) + 8002568: 4905 ldr r1, [pc, #20] @ (8002580 ) + 800256a: 400a ands r2, r1 + 800256c: 63da str r2, [r3, #60] @ 0x3c } } } } #endif /* RCC_CR_HSIUSB48ON */ return HAL_OK; - 8001caa: 2300 movs r3, #0 + 800256e: 2300 movs r3, #0 } - 8001cac: 0018 movs r0, r3 - 8001cae: 46bd mov sp, r7 - 8001cb0: b006 add sp, #24 - 8001cb2: bd80 pop {r7, pc} - 8001cb4: 40021000 .word 0x40021000 - 8001cb8: 00001388 .word 0x00001388 - 8001cbc: efffffff .word 0xefffffff + 8002570: 0018 movs r0, r3 + 8002572: 46bd mov sp, r7 + 8002574: b006 add sp, #24 + 8002576: bd80 pop {r7, pc} + 8002578: 40021000 .word 0x40021000 + 800257c: 00001388 .word 0x00001388 + 8002580: efffffff .word 0xefffffff -08001cc0 : +08002584 : * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { - 8001cc0: b580 push {r7, lr} - 8001cc2: b084 sub sp, #16 - 8001cc4: af00 add r7, sp, #0 - 8001cc6: 6078 str r0, [r7, #4] - 8001cc8: 6039 str r1, [r7, #0] + 8002584: b580 push {r7, lr} + 8002586: b084 sub sp, #16 + 8002588: af00 add r7, sp, #0 + 800258a: 6078 str r0, [r7, #4] + 800258c: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) - 8001cca: 687b ldr r3, [r7, #4] - 8001ccc: 2b00 cmp r3, #0 - 8001cce: d101 bne.n 8001cd4 + 800258e: 687b ldr r3, [r7, #4] + 8002590: 2b00 cmp r3, #0 + 8002592: d101 bne.n 8002598 { return HAL_ERROR; - 8001cd0: 2301 movs r3, #1 - 8001cd2: e0e9 b.n 8001ea8 + 8002594: 2301 movs r3, #1 + 8002596: e0e9 b.n 800276c /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the FLASH clock (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) - 8001cd4: 4b76 ldr r3, [pc, #472] @ (8001eb0 ) - 8001cd6: 681b ldr r3, [r3, #0] - 8001cd8: 2207 movs r2, #7 - 8001cda: 4013 ands r3, r2 - 8001cdc: 683a ldr r2, [r7, #0] - 8001cde: 429a cmp r2, r3 - 8001ce0: d91e bls.n 8001d20 + 8002598: 4b76 ldr r3, [pc, #472] @ (8002774 ) + 800259a: 681b ldr r3, [r3, #0] + 800259c: 2207 movs r2, #7 + 800259e: 4013 ands r3, r2 + 80025a0: 683a ldr r2, [r7, #0] + 80025a2: 429a cmp r2, r3 + 80025a4: d91e bls.n 80025e4 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); - 8001ce2: 4b73 ldr r3, [pc, #460] @ (8001eb0 ) - 8001ce4: 681b ldr r3, [r3, #0] - 8001ce6: 2207 movs r2, #7 - 8001ce8: 4393 bics r3, r2 - 8001cea: 0019 movs r1, r3 - 8001cec: 4b70 ldr r3, [pc, #448] @ (8001eb0 ) - 8001cee: 683a ldr r2, [r7, #0] - 8001cf0: 430a orrs r2, r1 - 8001cf2: 601a str r2, [r3, #0] + 80025a6: 4b73 ldr r3, [pc, #460] @ (8002774 ) + 80025a8: 681b ldr r3, [r3, #0] + 80025aa: 2207 movs r2, #7 + 80025ac: 4393 bics r3, r2 + 80025ae: 0019 movs r1, r3 + 80025b0: 4b70 ldr r3, [pc, #448] @ (8002774 ) + 80025b2: 683a ldr r2, [r7, #0] + 80025b4: 430a orrs r2, r1 + 80025b6: 601a str r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by polling the FLASH_ACR register */ tickstart = HAL_GetTick(); - 8001cf4: f7ff f9be bl 8001074 - 8001cf8: 0003 movs r3, r0 - 8001cfa: 60fb str r3, [r7, #12] + 80025b8: f7ff f8bc bl 8001734 + 80025bc: 0003 movs r3, r0 + 80025be: 60fb str r3, [r7, #12] while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) - 8001cfc: e009 b.n 8001d12 + 80025c0: e009 b.n 80025d6 { if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE) - 8001cfe: f7ff f9b9 bl 8001074 - 8001d02: 0002 movs r2, r0 - 8001d04: 68fb ldr r3, [r7, #12] - 8001d06: 1ad3 subs r3, r2, r3 - 8001d08: 4a6a ldr r2, [pc, #424] @ (8001eb4 ) - 8001d0a: 4293 cmp r3, r2 - 8001d0c: d901 bls.n 8001d12 + 80025c2: f7ff f8b7 bl 8001734 + 80025c6: 0002 movs r2, r0 + 80025c8: 68fb ldr r3, [r7, #12] + 80025ca: 1ad3 subs r3, r2, r3 + 80025cc: 4a6a ldr r2, [pc, #424] @ (8002778 ) + 80025ce: 4293 cmp r3, r2 + 80025d0: d901 bls.n 80025d6 { return HAL_TIMEOUT; - 8001d0e: 2303 movs r3, #3 - 8001d10: e0ca b.n 8001ea8 + 80025d2: 2303 movs r3, #3 + 80025d4: e0ca b.n 800276c while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) - 8001d12: 4b67 ldr r3, [pc, #412] @ (8001eb0 ) - 8001d14: 681b ldr r3, [r3, #0] - 8001d16: 2207 movs r2, #7 - 8001d18: 4013 ands r3, r2 - 8001d1a: 683a ldr r2, [r7, #0] - 8001d1c: 429a cmp r2, r3 - 8001d1e: d1ee bne.n 8001cfe + 80025d6: 4b67 ldr r3, [pc, #412] @ (8002774 ) + 80025d8: 681b ldr r3, [r3, #0] + 80025da: 2207 movs r2, #7 + 80025dc: 4013 ands r3, r2 + 80025de: 683a ldr r2, [r7, #0] + 80025e0: 429a cmp r2, r3 + 80025e2: d1ee bne.n 80025c2 } } } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) - 8001d20: 687b ldr r3, [r7, #4] - 8001d22: 681b ldr r3, [r3, #0] - 8001d24: 2202 movs r2, #2 - 8001d26: 4013 ands r3, r2 - 8001d28: d017 beq.n 8001d5a + 80025e4: 687b ldr r3, [r7, #4] + 80025e6: 681b ldr r3, [r3, #0] + 80025e8: 2202 movs r2, #2 + 80025ea: 4013 ands r3, r2 + 80025ec: d017 beq.n 800261e { /* Set the highest APB divider in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - 8001d2a: 687b ldr r3, [r7, #4] - 8001d2c: 681b ldr r3, [r3, #0] - 8001d2e: 2204 movs r2, #4 - 8001d30: 4013 ands r3, r2 - 8001d32: d008 beq.n 8001d46 + 80025ee: 687b ldr r3, [r7, #4] + 80025f0: 681b ldr r3, [r3, #0] + 80025f2: 2204 movs r2, #4 + 80025f4: 4013 ands r3, r2 + 80025f6: d008 beq.n 800260a { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16); - 8001d34: 4b60 ldr r3, [pc, #384] @ (8001eb8 ) - 8001d36: 689b ldr r3, [r3, #8] - 8001d38: 4a60 ldr r2, [pc, #384] @ (8001ebc ) - 8001d3a: 401a ands r2, r3 - 8001d3c: 4b5e ldr r3, [pc, #376] @ (8001eb8 ) - 8001d3e: 21b0 movs r1, #176 @ 0xb0 - 8001d40: 0109 lsls r1, r1, #4 - 8001d42: 430a orrs r2, r1 - 8001d44: 609a str r2, [r3, #8] + 80025f8: 4b60 ldr r3, [pc, #384] @ (800277c ) + 80025fa: 689b ldr r3, [r3, #8] + 80025fc: 4a60 ldr r2, [pc, #384] @ (8002780 ) + 80025fe: 401a ands r2, r3 + 8002600: 4b5e ldr r3, [pc, #376] @ (800277c ) + 8002602: 21b0 movs r1, #176 @ 0xb0 + 8002604: 0109 lsls r1, r1, #4 + 8002606: 430a orrs r2, r1 + 8002608: 609a str r2, [r3, #8] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); - 8001d46: 4b5c ldr r3, [pc, #368] @ (8001eb8 ) - 8001d48: 689b ldr r3, [r3, #8] - 8001d4a: 4a5d ldr r2, [pc, #372] @ (8001ec0 ) - 8001d4c: 4013 ands r3, r2 - 8001d4e: 0019 movs r1, r3 - 8001d50: 687b ldr r3, [r7, #4] - 8001d52: 68da ldr r2, [r3, #12] - 8001d54: 4b58 ldr r3, [pc, #352] @ (8001eb8 ) - 8001d56: 430a orrs r2, r1 - 8001d58: 609a str r2, [r3, #8] + 800260a: 4b5c ldr r3, [pc, #368] @ (800277c ) + 800260c: 689b ldr r3, [r3, #8] + 800260e: 4a5d ldr r2, [pc, #372] @ (8002784 ) + 8002610: 4013 ands r3, r2 + 8002612: 0019 movs r1, r3 + 8002614: 687b ldr r3, [r7, #4] + 8002616: 68da ldr r2, [r3, #12] + 8002618: 4b58 ldr r3, [pc, #352] @ (800277c ) + 800261a: 430a orrs r2, r1 + 800261c: 609a str r2, [r3, #8] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) - 8001d5a: 687b ldr r3, [r7, #4] - 8001d5c: 681b ldr r3, [r3, #0] - 8001d5e: 2201 movs r2, #1 - 8001d60: 4013 ands r3, r2 - 8001d62: d055 beq.n 8001e10 + 800261e: 687b ldr r3, [r7, #4] + 8002620: 681b ldr r3, [r3, #0] + 8002622: 2201 movs r2, #1 + 8002624: 4013 ands r3, r2 + 8002626: d055 beq.n 80026d4 { assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider)); assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); #if defined(RCC_CR_SYSDIV) MODIFY_REG(RCC->CR, RCC_CR_SYSDIV, RCC_ClkInitStruct->SYSCLKDivider); - 8001d64: 4b54 ldr r3, [pc, #336] @ (8001eb8 ) - 8001d66: 681b ldr r3, [r3, #0] - 8001d68: 221c movs r2, #28 - 8001d6a: 4393 bics r3, r2 - 8001d6c: 0019 movs r1, r3 - 8001d6e: 687b ldr r3, [r7, #4] - 8001d70: 689a ldr r2, [r3, #8] - 8001d72: 4b51 ldr r3, [pc, #324] @ (8001eb8 ) - 8001d74: 430a orrs r2, r1 - 8001d76: 601a str r2, [r3, #0] + 8002628: 4b54 ldr r3, [pc, #336] @ (800277c ) + 800262a: 681b ldr r3, [r3, #0] + 800262c: 221c movs r2, #28 + 800262e: 4393 bics r3, r2 + 8002630: 0019 movs r1, r3 + 8002632: 687b ldr r3, [r7, #4] + 8002634: 689a ldr r2, [r3, #8] + 8002636: 4b51 ldr r3, [pc, #324] @ (800277c ) + 8002638: 430a orrs r2, r1 + 800263a: 601a str r2, [r3, #0] #endif /* RCC_CR_SYSDIV */ /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - 8001d78: 687b ldr r3, [r7, #4] - 8001d7a: 685b ldr r3, [r3, #4] - 8001d7c: 2b01 cmp r3, #1 - 8001d7e: d107 bne.n 8001d90 + 800263c: 687b ldr r3, [r7, #4] + 800263e: 685b ldr r3, [r3, #4] + 8002640: 2b01 cmp r3, #1 + 8002642: d107 bne.n 8002654 { /* Check the HSE ready flag */ if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) - 8001d80: 4b4d ldr r3, [pc, #308] @ (8001eb8 ) - 8001d82: 681a ldr r2, [r3, #0] - 8001d84: 2380 movs r3, #128 @ 0x80 - 8001d86: 029b lsls r3, r3, #10 - 8001d88: 4013 ands r3, r2 - 8001d8a: d11f bne.n 8001dcc + 8002644: 4b4d ldr r3, [pc, #308] @ (800277c ) + 8002646: 681a ldr r2, [r3, #0] + 8002648: 2380 movs r3, #128 @ 0x80 + 800264a: 029b lsls r3, r3, #10 + 800264c: 4013 ands r3, r2 + 800264e: d11f bne.n 8002690 { return HAL_ERROR; - 8001d8c: 2301 movs r3, #1 - 8001d8e: e08b b.n 8001ea8 + 8002650: 2301 movs r3, #1 + 8002652: e08b b.n 800276c } } /* HSI is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) - 8001d90: 687b ldr r3, [r7, #4] - 8001d92: 685b ldr r3, [r3, #4] - 8001d94: 2b00 cmp r3, #0 - 8001d96: d107 bne.n 8001da8 + 8002654: 687b ldr r3, [r7, #4] + 8002656: 685b ldr r3, [r3, #4] + 8002658: 2b00 cmp r3, #0 + 800265a: d107 bne.n 800266c { /* Check the HSI ready flag */ if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) - 8001d98: 4b47 ldr r3, [pc, #284] @ (8001eb8 ) - 8001d9a: 681a ldr r2, [r3, #0] - 8001d9c: 2380 movs r3, #128 @ 0x80 - 8001d9e: 00db lsls r3, r3, #3 - 8001da0: 4013 ands r3, r2 - 8001da2: d113 bne.n 8001dcc + 800265c: 4b47 ldr r3, [pc, #284] @ (800277c ) + 800265e: 681a ldr r2, [r3, #0] + 8002660: 2380 movs r3, #128 @ 0x80 + 8002662: 00db lsls r3, r3, #3 + 8002664: 4013 ands r3, r2 + 8002666: d113 bne.n 8002690 { return HAL_ERROR; - 8001da4: 2301 movs r3, #1 - 8001da6: e07f b.n 8001ea8 + 8002668: 2301 movs r3, #1 + 800266a: e07f b.n 800276c return HAL_ERROR; } } #endif /* RCC_HSI48_SUPPORT */ /* LSI is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_LSI) - 8001da8: 687b ldr r3, [r7, #4] - 8001daa: 685b ldr r3, [r3, #4] - 8001dac: 2b03 cmp r3, #3 - 8001dae: d106 bne.n 8001dbe + 800266c: 687b ldr r3, [r7, #4] + 800266e: 685b ldr r3, [r3, #4] + 8002670: 2b03 cmp r3, #3 + 8002672: d106 bne.n 8002682 { /* Check the LSI ready flag */ if (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) == 0U) - 8001db0: 4b41 ldr r3, [pc, #260] @ (8001eb8 ) - 8001db2: 6e1b ldr r3, [r3, #96] @ 0x60 - 8001db4: 2202 movs r2, #2 - 8001db6: 4013 ands r3, r2 - 8001db8: d108 bne.n 8001dcc + 8002674: 4b41 ldr r3, [pc, #260] @ (800277c ) + 8002676: 6e1b ldr r3, [r3, #96] @ 0x60 + 8002678: 2202 movs r2, #2 + 800267a: 4013 ands r3, r2 + 800267c: d108 bne.n 8002690 { return HAL_ERROR; - 8001dba: 2301 movs r3, #1 - 8001dbc: e074 b.n 8001ea8 + 800267e: 2301 movs r3, #1 + 8002680: e074 b.n 800276c } /* LSE is selected as System Clock Source */ else { /* Check the LSE ready flag */ if (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U) - 8001dbe: 4b3e ldr r3, [pc, #248] @ (8001eb8 ) - 8001dc0: 6ddb ldr r3, [r3, #92] @ 0x5c - 8001dc2: 2202 movs r2, #2 - 8001dc4: 4013 ands r3, r2 - 8001dc6: d101 bne.n 8001dcc + 8002682: 4b3e ldr r3, [pc, #248] @ (800277c ) + 8002684: 6ddb ldr r3, [r3, #92] @ 0x5c + 8002686: 2202 movs r2, #2 + 8002688: 4013 ands r3, r2 + 800268a: d101 bne.n 8002690 { return HAL_ERROR; - 8001dc8: 2301 movs r3, #1 - 8001dca: e06d b.n 8001ea8 + 800268c: 2301 movs r3, #1 + 800268e: e06d b.n 800276c } } MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); - 8001dcc: 4b3a ldr r3, [pc, #232] @ (8001eb8 ) - 8001dce: 689b ldr r3, [r3, #8] - 8001dd0: 2207 movs r2, #7 - 8001dd2: 4393 bics r3, r2 - 8001dd4: 0019 movs r1, r3 - 8001dd6: 687b ldr r3, [r7, #4] - 8001dd8: 685a ldr r2, [r3, #4] - 8001dda: 4b37 ldr r3, [pc, #220] @ (8001eb8 ) - 8001ddc: 430a orrs r2, r1 - 8001dde: 609a str r2, [r3, #8] + 8002690: 4b3a ldr r3, [pc, #232] @ (800277c ) + 8002692: 689b ldr r3, [r3, #8] + 8002694: 2207 movs r2, #7 + 8002696: 4393 bics r3, r2 + 8002698: 0019 movs r1, r3 + 800269a: 687b ldr r3, [r7, #4] + 800269c: 685a ldr r2, [r3, #4] + 800269e: 4b37 ldr r3, [pc, #220] @ (800277c ) + 80026a0: 430a orrs r2, r1 + 80026a2: 609a str r2, [r3, #8] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8001de0: f7ff f948 bl 8001074 - 8001de4: 0003 movs r3, r0 - 8001de6: 60fb str r3, [r7, #12] + 80026a4: f7ff f846 bl 8001734 + 80026a8: 0003 movs r3, r0 + 80026aa: 60fb str r3, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) - 8001de8: e009 b.n 8001dfe + 80026ac: e009 b.n 80026c2 { if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE) - 8001dea: f7ff f943 bl 8001074 - 8001dee: 0002 movs r2, r0 - 8001df0: 68fb ldr r3, [r7, #12] - 8001df2: 1ad3 subs r3, r2, r3 - 8001df4: 4a2f ldr r2, [pc, #188] @ (8001eb4 ) - 8001df6: 4293 cmp r3, r2 - 8001df8: d901 bls.n 8001dfe + 80026ae: f7ff f841 bl 8001734 + 80026b2: 0002 movs r2, r0 + 80026b4: 68fb ldr r3, [r7, #12] + 80026b6: 1ad3 subs r3, r2, r3 + 80026b8: 4a2f ldr r2, [pc, #188] @ (8002778 ) + 80026ba: 4293 cmp r3, r2 + 80026bc: d901 bls.n 80026c2 { return HAL_TIMEOUT; - 8001dfa: 2303 movs r3, #3 - 8001dfc: e054 b.n 8001ea8 + 80026be: 2303 movs r3, #3 + 80026c0: e054 b.n 800276c while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) - 8001dfe: 4b2e ldr r3, [pc, #184] @ (8001eb8 ) - 8001e00: 689b ldr r3, [r3, #8] - 8001e02: 2238 movs r2, #56 @ 0x38 - 8001e04: 401a ands r2, r3 - 8001e06: 687b ldr r3, [r7, #4] - 8001e08: 685b ldr r3, [r3, #4] - 8001e0a: 00db lsls r3, r3, #3 - 8001e0c: 429a cmp r2, r3 - 8001e0e: d1ec bne.n 8001dea + 80026c2: 4b2e ldr r3, [pc, #184] @ (800277c ) + 80026c4: 689b ldr r3, [r3, #8] + 80026c6: 2238 movs r2, #56 @ 0x38 + 80026c8: 401a ands r2, r3 + 80026ca: 687b ldr r3, [r7, #4] + 80026cc: 685b ldr r3, [r3, #4] + 80026ce: 00db lsls r3, r3, #3 + 80026d0: 429a cmp r2, r3 + 80026d2: d1ec bne.n 80026ae } } } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) - 8001e10: 4b27 ldr r3, [pc, #156] @ (8001eb0 ) - 8001e12: 681b ldr r3, [r3, #0] - 8001e14: 2207 movs r2, #7 - 8001e16: 4013 ands r3, r2 - 8001e18: 683a ldr r2, [r7, #0] - 8001e1a: 429a cmp r2, r3 - 8001e1c: d21e bcs.n 8001e5c + 80026d4: 4b27 ldr r3, [pc, #156] @ (8002774 ) + 80026d6: 681b ldr r3, [r3, #0] + 80026d8: 2207 movs r2, #7 + 80026da: 4013 ands r3, r2 + 80026dc: 683a ldr r2, [r7, #0] + 80026de: 429a cmp r2, r3 + 80026e0: d21e bcs.n 8002720 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); - 8001e1e: 4b24 ldr r3, [pc, #144] @ (8001eb0 ) - 8001e20: 681b ldr r3, [r3, #0] - 8001e22: 2207 movs r2, #7 - 8001e24: 4393 bics r3, r2 - 8001e26: 0019 movs r1, r3 - 8001e28: 4b21 ldr r3, [pc, #132] @ (8001eb0 ) - 8001e2a: 683a ldr r2, [r7, #0] - 8001e2c: 430a orrs r2, r1 - 8001e2e: 601a str r2, [r3, #0] + 80026e2: 4b24 ldr r3, [pc, #144] @ (8002774 ) + 80026e4: 681b ldr r3, [r3, #0] + 80026e6: 2207 movs r2, #7 + 80026e8: 4393 bics r3, r2 + 80026ea: 0019 movs r1, r3 + 80026ec: 4b21 ldr r3, [pc, #132] @ (8002774 ) + 80026ee: 683a ldr r2, [r7, #0] + 80026f0: 430a orrs r2, r1 + 80026f2: 601a str r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by polling the FLASH_ACR register */ tickstart = HAL_GetTick(); - 8001e30: f7ff f920 bl 8001074 - 8001e34: 0003 movs r3, r0 - 8001e36: 60fb str r3, [r7, #12] + 80026f4: f7ff f81e bl 8001734 + 80026f8: 0003 movs r3, r0 + 80026fa: 60fb str r3, [r7, #12] while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) - 8001e38: e009 b.n 8001e4e + 80026fc: e009 b.n 8002712 { if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE) - 8001e3a: f7ff f91b bl 8001074 - 8001e3e: 0002 movs r2, r0 - 8001e40: 68fb ldr r3, [r7, #12] - 8001e42: 1ad3 subs r3, r2, r3 - 8001e44: 4a1b ldr r2, [pc, #108] @ (8001eb4 ) - 8001e46: 4293 cmp r3, r2 - 8001e48: d901 bls.n 8001e4e + 80026fe: f7ff f819 bl 8001734 + 8002702: 0002 movs r2, r0 + 8002704: 68fb ldr r3, [r7, #12] + 8002706: 1ad3 subs r3, r2, r3 + 8002708: 4a1b ldr r2, [pc, #108] @ (8002778 ) + 800270a: 4293 cmp r3, r2 + 800270c: d901 bls.n 8002712 { return HAL_TIMEOUT; - 8001e4a: 2303 movs r3, #3 - 8001e4c: e02c b.n 8001ea8 + 800270e: 2303 movs r3, #3 + 8002710: e02c b.n 800276c while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) - 8001e4e: 4b18 ldr r3, [pc, #96] @ (8001eb0 ) - 8001e50: 681b ldr r3, [r3, #0] - 8001e52: 2207 movs r2, #7 - 8001e54: 4013 ands r3, r2 - 8001e56: 683a ldr r2, [r7, #0] - 8001e58: 429a cmp r2, r3 - 8001e5a: d1ee bne.n 8001e3a + 8002712: 4b18 ldr r3, [pc, #96] @ (8002774 ) + 8002714: 681b ldr r3, [r3, #0] + 8002716: 2207 movs r2, #7 + 8002718: 4013 ands r3, r2 + 800271a: 683a ldr r2, [r7, #0] + 800271c: 429a cmp r2, r3 + 800271e: d1ee bne.n 80026fe } } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - 8001e5c: 687b ldr r3, [r7, #4] - 8001e5e: 681b ldr r3, [r3, #0] - 8001e60: 2204 movs r2, #4 - 8001e62: 4013 ands r3, r2 - 8001e64: d009 beq.n 8001e7a + 8002720: 687b ldr r3, [r7, #4] + 8002722: 681b ldr r3, [r3, #0] + 8002724: 2204 movs r2, #4 + 8002726: 4013 ands r3, r2 + 8002728: d009 beq.n 800273e { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider); - 8001e66: 4b14 ldr r3, [pc, #80] @ (8001eb8 ) - 8001e68: 689b ldr r3, [r3, #8] - 8001e6a: 4a16 ldr r2, [pc, #88] @ (8001ec4 ) - 8001e6c: 4013 ands r3, r2 - 8001e6e: 0019 movs r1, r3 - 8001e70: 687b ldr r3, [r7, #4] - 8001e72: 691a ldr r2, [r3, #16] - 8001e74: 4b10 ldr r3, [pc, #64] @ (8001eb8 ) - 8001e76: 430a orrs r2, r1 - 8001e78: 609a str r2, [r3, #8] + 800272a: 4b14 ldr r3, [pc, #80] @ (800277c ) + 800272c: 689b ldr r3, [r3, #8] + 800272e: 4a16 ldr r2, [pc, #88] @ (8002788 ) + 8002730: 4013 ands r3, r2 + 8002732: 0019 movs r1, r3 + 8002734: 687b ldr r3, [r7, #4] + 8002736: 691a ldr r2, [r3, #16] + 8002738: 4b10 ldr r3, [pc, #64] @ (800277c ) + 800273a: 430a orrs r2, r1 + 800273c: 609a str r2, [r3, #8] } /* Update the SystemCoreClock global variable */ SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \ - 8001e7a: f000 f82b bl 8001ed4 - 8001e7e: 0001 movs r1, r0 - 8001e80: 4b0d ldr r3, [pc, #52] @ (8001eb8 ) - 8001e82: 689b ldr r3, [r3, #8] + 800273e: f000 f82b bl 8002798 + 8002742: 0001 movs r1, r0 + 8002744: 4b0d ldr r3, [pc, #52] @ (800277c ) + 8002746: 689b ldr r3, [r3, #8] >> RCC_CFGR_HPRE_Pos]) & 0x1FU)); - 8001e84: 0a1b lsrs r3, r3, #8 - 8001e86: 220f movs r2, #15 - 8001e88: 401a ands r2, r3 + 8002748: 0a1b lsrs r3, r3, #8 + 800274a: 220f movs r2, #15 + 800274c: 401a ands r2, r3 SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \ - 8001e8a: 4b0f ldr r3, [pc, #60] @ (8001ec8 ) - 8001e8c: 0092 lsls r2, r2, #2 - 8001e8e: 58d3 ldr r3, [r2, r3] + 800274e: 4b0f ldr r3, [pc, #60] @ (800278c ) + 8002750: 0092 lsls r2, r2, #2 + 8002752: 58d3 ldr r3, [r2, r3] >> RCC_CFGR_HPRE_Pos]) & 0x1FU)); - 8001e90: 221f movs r2, #31 - 8001e92: 4013 ands r3, r2 + 8002754: 221f movs r2, #31 + 8002756: 4013 ands r3, r2 SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \ - 8001e94: 000a movs r2, r1 - 8001e96: 40da lsrs r2, r3 - 8001e98: 4b0c ldr r3, [pc, #48] @ (8001ecc ) - 8001e9a: 601a str r2, [r3, #0] + 8002758: 000a movs r2, r1 + 800275a: 40da lsrs r2, r3 + 800275c: 4b0c ldr r3, [pc, #48] @ (8002790 ) + 800275e: 601a str r2, [r3, #0] /* Configure the source of time base considering new system clocks settings*/ return HAL_InitTick(uwTickPrio); - 8001e9c: 4b0c ldr r3, [pc, #48] @ (8001ed0 ) - 8001e9e: 681b ldr r3, [r3, #0] - 8001ea0: 0018 movs r0, r3 - 8001ea2: f7ff f88b bl 8000fbc - 8001ea6: 0003 movs r3, r0 + 8002760: 4b0c ldr r3, [pc, #48] @ (8002794 ) + 8002762: 681b ldr r3, [r3, #0] + 8002764: 0018 movs r0, r3 + 8002766: f7fe ff89 bl 800167c + 800276a: 0003 movs r3, r0 } - 8001ea8: 0018 movs r0, r3 - 8001eaa: 46bd mov sp, r7 - 8001eac: b004 add sp, #16 - 8001eae: bd80 pop {r7, pc} - 8001eb0: 40022000 .word 0x40022000 - 8001eb4: 00001388 .word 0x00001388 - 8001eb8: 40021000 .word 0x40021000 - 8001ebc: ffff84ff .word 0xffff84ff - 8001ec0: fffff0ff .word 0xfffff0ff - 8001ec4: ffff8fff .word 0xffff8fff - 8001ec8: 08003fac .word 0x08003fac - 8001ecc: 20000000 .word 0x20000000 - 8001ed0: 20000004 .word 0x20000004 + 800276c: 0018 movs r0, r3 + 800276e: 46bd mov sp, r7 + 8002770: b004 add sp, #16 + 8002772: bd80 pop {r7, pc} + 8002774: 40022000 .word 0x40022000 + 8002778: 00001388 .word 0x00001388 + 800277c: 40021000 .word 0x40021000 + 8002780: ffff84ff .word 0xffff84ff + 8002784: fffff0ff .word 0xfffff0ff + 8002788: ffff8fff .word 0xffff8fff + 800278c: 08004dbc .word 0x08004dbc + 8002790: 20000018 .word 0x20000018 + 8002794: 2000001c .word 0x2000001c -08001ed4 : +08002798 : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { - 8001ed4: b580 push {r7, lr} - 8001ed6: b084 sub sp, #16 - 8001ed8: af00 add r7, sp, #0 + 8002798: b580 push {r7, lr} + 800279a: b084 sub sp, #16 + 800279c: af00 add r7, sp, #0 uint32_t hsidiv; uint32_t sysclockfreq; #if defined(RCC_CR_SYSDIV) uint32_t sysclockdiv = (uint32_t)(((RCC->CR & RCC_CR_SYSDIV) >> RCC_CR_SYSDIV_Pos) + 1U); - 8001eda: 4b23 ldr r3, [pc, #140] @ (8001f68 ) - 8001edc: 681b ldr r3, [r3, #0] - 8001ede: 089b lsrs r3, r3, #2 - 8001ee0: 2207 movs r2, #7 - 8001ee2: 4013 ands r3, r2 - 8001ee4: 3301 adds r3, #1 - 8001ee6: 60bb str r3, [r7, #8] + 800279e: 4b23 ldr r3, [pc, #140] @ (800282c ) + 80027a0: 681b ldr r3, [r3, #0] + 80027a2: 089b lsrs r3, r3, #2 + 80027a4: 2207 movs r2, #7 + 80027a6: 4013 ands r3, r2 + 80027a8: 3301 adds r3, #1 + 80027aa: 60bb str r3, [r7, #8] #endif /* RCC_CR_SYSDIV */ if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) - 8001ee8: 4b1f ldr r3, [pc, #124] @ (8001f68 ) - 8001eea: 689b ldr r3, [r3, #8] - 8001eec: 2238 movs r2, #56 @ 0x38 - 8001eee: 4013 ands r3, r2 - 8001ef0: d10f bne.n 8001f12 + 80027ac: 4b1f ldr r3, [pc, #124] @ (800282c ) + 80027ae: 689b ldr r3, [r3, #8] + 80027b0: 2238 movs r2, #56 @ 0x38 + 80027b2: 4013 ands r3, r2 + 80027b4: d10f bne.n 80027d6 { /* HSISYS can be derived for HSI48 */ hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos)); - 8001ef2: 4b1d ldr r3, [pc, #116] @ (8001f68 ) - 8001ef4: 681b ldr r3, [r3, #0] - 8001ef6: 0adb lsrs r3, r3, #11 - 8001ef8: 2207 movs r2, #7 - 8001efa: 4013 ands r3, r2 - 8001efc: 2201 movs r2, #1 - 8001efe: 409a lsls r2, r3 - 8001f00: 0013 movs r3, r2 - 8001f02: 607b str r3, [r7, #4] + 80027b6: 4b1d ldr r3, [pc, #116] @ (800282c ) + 80027b8: 681b ldr r3, [r3, #0] + 80027ba: 0adb lsrs r3, r3, #11 + 80027bc: 2207 movs r2, #7 + 80027be: 4013 ands r3, r2 + 80027c0: 2201 movs r2, #1 + 80027c2: 409a lsls r2, r3 + 80027c4: 0013 movs r3, r2 + 80027c6: 607b str r3, [r7, #4] /* HSI used as system clock source */ sysclockfreq = (HSI_VALUE / hsidiv); - 8001f04: 6879 ldr r1, [r7, #4] - 8001f06: 4819 ldr r0, [pc, #100] @ (8001f6c ) - 8001f08: f7fe f8fe bl 8000108 <__udivsi3> - 8001f0c: 0003 movs r3, r0 - 8001f0e: 60fb str r3, [r7, #12] - 8001f10: e01e b.n 8001f50 + 80027c8: 6879 ldr r1, [r7, #4] + 80027ca: 4819 ldr r0, [pc, #100] @ (8002830 ) + 80027cc: f7fd fc9c bl 8000108 <__udivsi3> + 80027d0: 0003 movs r3, r0 + 80027d2: 60fb str r3, [r7, #12] + 80027d4: e01e b.n 8002814 } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) - 8001f12: 4b15 ldr r3, [pc, #84] @ (8001f68 ) - 8001f14: 689b ldr r3, [r3, #8] - 8001f16: 2238 movs r2, #56 @ 0x38 - 8001f18: 4013 ands r3, r2 - 8001f1a: 2b08 cmp r3, #8 - 8001f1c: d102 bne.n 8001f24 + 80027d6: 4b15 ldr r3, [pc, #84] @ (800282c ) + 80027d8: 689b ldr r3, [r3, #8] + 80027da: 2238 movs r2, #56 @ 0x38 + 80027dc: 4013 ands r3, r2 + 80027de: 2b08 cmp r3, #8 + 80027e0: d102 bne.n 80027e8 { /* HSE used as system clock source */ sysclockfreq = HSE_VALUE; - 8001f1e: 4b14 ldr r3, [pc, #80] @ (8001f70 ) - 8001f20: 60fb str r3, [r7, #12] - 8001f22: e015 b.n 8001f50 + 80027e2: 4b14 ldr r3, [pc, #80] @ (8002834 ) + 80027e4: 60fb str r3, [r7, #12] + 80027e6: e015 b.n 8002814 } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSE) - 8001f24: 4b10 ldr r3, [pc, #64] @ (8001f68 ) - 8001f26: 689b ldr r3, [r3, #8] - 8001f28: 2238 movs r2, #56 @ 0x38 - 8001f2a: 4013 ands r3, r2 - 8001f2c: 2b20 cmp r3, #32 - 8001f2e: d103 bne.n 8001f38 + 80027e8: 4b10 ldr r3, [pc, #64] @ (800282c ) + 80027ea: 689b ldr r3, [r3, #8] + 80027ec: 2238 movs r2, #56 @ 0x38 + 80027ee: 4013 ands r3, r2 + 80027f0: 2b20 cmp r3, #32 + 80027f2: d103 bne.n 80027fc { /* LSE used as system clock source */ sysclockfreq = LSE_VALUE; - 8001f30: 2380 movs r3, #128 @ 0x80 - 8001f32: 021b lsls r3, r3, #8 - 8001f34: 60fb str r3, [r7, #12] - 8001f36: e00b b.n 8001f50 + 80027f4: 2380 movs r3, #128 @ 0x80 + 80027f6: 021b lsls r3, r3, #8 + 80027f8: 60fb str r3, [r7, #12] + 80027fa: e00b b.n 8002814 } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSI) - 8001f38: 4b0b ldr r3, [pc, #44] @ (8001f68 ) - 8001f3a: 689b ldr r3, [r3, #8] - 8001f3c: 2238 movs r2, #56 @ 0x38 - 8001f3e: 4013 ands r3, r2 - 8001f40: 2b18 cmp r3, #24 - 8001f42: d103 bne.n 8001f4c + 80027fc: 4b0b ldr r3, [pc, #44] @ (800282c ) + 80027fe: 689b ldr r3, [r3, #8] + 8002800: 2238 movs r2, #56 @ 0x38 + 8002802: 4013 ands r3, r2 + 8002804: 2b18 cmp r3, #24 + 8002806: d103 bne.n 8002810 { /* LSI used as system clock source */ sysclockfreq = LSI_VALUE; - 8001f44: 23fa movs r3, #250 @ 0xfa - 8001f46: 01db lsls r3, r3, #7 - 8001f48: 60fb str r3, [r7, #12] - 8001f4a: e001 b.n 8001f50 + 8002808: 23fa movs r3, #250 @ 0xfa + 800280a: 01db lsls r3, r3, #7 + 800280c: 60fb str r3, [r7, #12] + 800280e: e001 b.n 8002814 sysclockfreq = HSI48_VALUE; } #endif /* RCC_HSI48_SUPPORT */ else { sysclockfreq = 0U; - 8001f4c: 2300 movs r3, #0 - 8001f4e: 60fb str r3, [r7, #12] + 8002810: 2300 movs r3, #0 + 8002812: 60fb str r3, [r7, #12] } #if defined(RCC_CR_SYSDIV) sysclockfreq = sysclockfreq / sysclockdiv; - 8001f50: 68b9 ldr r1, [r7, #8] - 8001f52: 68f8 ldr r0, [r7, #12] - 8001f54: f7fe f8d8 bl 8000108 <__udivsi3> - 8001f58: 0003 movs r3, r0 - 8001f5a: 60fb str r3, [r7, #12] + 8002814: 68b9 ldr r1, [r7, #8] + 8002816: 68f8 ldr r0, [r7, #12] + 8002818: f7fd fc76 bl 8000108 <__udivsi3> + 800281c: 0003 movs r3, r0 + 800281e: 60fb str r3, [r7, #12] #endif /* RCC_CR_SYSDIV */ return sysclockfreq; - 8001f5c: 68fb ldr r3, [r7, #12] + 8002820: 68fb ldr r3, [r7, #12] } - 8001f5e: 0018 movs r0, r3 - 8001f60: 46bd mov sp, r7 - 8001f62: b004 add sp, #16 - 8001f64: bd80 pop {r7, pc} - 8001f66: 46c0 nop @ (mov r8, r8) - 8001f68: 40021000 .word 0x40021000 - 8001f6c: 02dc6c00 .word 0x02dc6c00 - 8001f70: 007a1200 .word 0x007a1200 + 8002822: 0018 movs r0, r3 + 8002824: 46bd mov sp, r7 + 8002826: b004 add sp, #16 + 8002828: bd80 pop {r7, pc} + 800282a: 46c0 nop @ (mov r8, r8) + 800282c: 40021000 .word 0x40021000 + 8002830: 02dc6c00 .word 0x02dc6c00 + 8002834: 007a1200 .word 0x007a1200 -08001f74 : +08002838 : * * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. * @retval HCLK frequency in Hz */ uint32_t HAL_RCC_GetHCLKFreq(void) { - 8001f74: b580 push {r7, lr} - 8001f76: af00 add r7, sp, #0 + 8002838: b580 push {r7, lr} + 800283a: af00 add r7, sp, #0 SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \ - 8001f78: f7ff ffac bl 8001ed4 - 8001f7c: 0001 movs r1, r0 - 8001f7e: 4b09 ldr r3, [pc, #36] @ (8001fa4 ) - 8001f80: 689b ldr r3, [r3, #8] + 800283c: f7ff ffac bl 8002798 + 8002840: 0001 movs r1, r0 + 8002842: 4b09 ldr r3, [pc, #36] @ (8002868 ) + 8002844: 689b ldr r3, [r3, #8] >> RCC_CFGR_HPRE_Pos]) & 0x1FU)); - 8001f82: 0a1b lsrs r3, r3, #8 - 8001f84: 220f movs r2, #15 - 8001f86: 401a ands r2, r3 + 8002846: 0a1b lsrs r3, r3, #8 + 8002848: 220f movs r2, #15 + 800284a: 401a ands r2, r3 SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \ - 8001f88: 4b07 ldr r3, [pc, #28] @ (8001fa8 ) - 8001f8a: 0092 lsls r2, r2, #2 - 8001f8c: 58d3 ldr r3, [r2, r3] + 800284c: 4b07 ldr r3, [pc, #28] @ (800286c ) + 800284e: 0092 lsls r2, r2, #2 + 8002850: 58d3 ldr r3, [r2, r3] >> RCC_CFGR_HPRE_Pos]) & 0x1FU)); - 8001f8e: 221f movs r2, #31 - 8001f90: 4013 ands r3, r2 + 8002852: 221f movs r2, #31 + 8002854: 4013 ands r3, r2 SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \ - 8001f92: 000a movs r2, r1 - 8001f94: 40da lsrs r2, r3 - 8001f96: 4b05 ldr r3, [pc, #20] @ (8001fac ) - 8001f98: 601a str r2, [r3, #0] + 8002856: 000a movs r2, r1 + 8002858: 40da lsrs r2, r3 + 800285a: 4b05 ldr r3, [pc, #20] @ (8002870 ) + 800285c: 601a str r2, [r3, #0] return SystemCoreClock; - 8001f9a: 4b04 ldr r3, [pc, #16] @ (8001fac ) - 8001f9c: 681b ldr r3, [r3, #0] + 800285e: 4b04 ldr r3, [pc, #16] @ (8002870 ) + 8002860: 681b ldr r3, [r3, #0] } - 8001f9e: 0018 movs r0, r3 - 8001fa0: 46bd mov sp, r7 - 8001fa2: bd80 pop {r7, pc} - 8001fa4: 40021000 .word 0x40021000 - 8001fa8: 08003fac .word 0x08003fac - 8001fac: 20000000 .word 0x20000000 + 8002862: 0018 movs r0, r3 + 8002864: 46bd mov sp, r7 + 8002866: bd80 pop {r7, pc} + 8002868: 40021000 .word 0x40021000 + 800286c: 08004dbc .word 0x08004dbc + 8002870: 20000018 .word 0x20000018 -08001fb0 : +08002874 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency in Hz */ uint32_t HAL_RCC_GetPCLK1Freq(void) { - 8001fb0: b580 push {r7, lr} - 8001fb2: af00 add r7, sp, #0 + 8002874: b580 push {r7, lr} + 8002876: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> ((APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE) >> RCC_CFGR_PPRE_Pos]) & 0x1FU)); - 8001fb4: f7ff ffde bl 8001f74 - 8001fb8: 0001 movs r1, r0 - 8001fba: 4b07 ldr r3, [pc, #28] @ (8001fd8 ) - 8001fbc: 689b ldr r3, [r3, #8] - 8001fbe: 0b1b lsrs r3, r3, #12 - 8001fc0: 2207 movs r2, #7 - 8001fc2: 401a ands r2, r3 - 8001fc4: 4b05 ldr r3, [pc, #20] @ (8001fdc ) - 8001fc6: 0092 lsls r2, r2, #2 - 8001fc8: 58d3 ldr r3, [r2, r3] - 8001fca: 221f movs r2, #31 - 8001fcc: 4013 ands r3, r2 - 8001fce: 40d9 lsrs r1, r3 - 8001fd0: 000b movs r3, r1 + 8002878: f7ff ffde bl 8002838 + 800287c: 0001 movs r1, r0 + 800287e: 4b07 ldr r3, [pc, #28] @ (800289c ) + 8002880: 689b ldr r3, [r3, #8] + 8002882: 0b1b lsrs r3, r3, #12 + 8002884: 2207 movs r2, #7 + 8002886: 401a ands r2, r3 + 8002888: 4b05 ldr r3, [pc, #20] @ (80028a0 ) + 800288a: 0092 lsls r2, r2, #2 + 800288c: 58d3 ldr r3, [r2, r3] + 800288e: 221f movs r2, #31 + 8002890: 4013 ands r3, r2 + 8002892: 40d9 lsrs r1, r3 + 8002894: 000b movs r3, r1 } - 8001fd2: 0018 movs r0, r3 - 8001fd4: 46bd mov sp, r7 - 8001fd6: bd80 pop {r7, pc} - 8001fd8: 40021000 .word 0x40021000 - 8001fdc: 08003fec .word 0x08003fec + 8002896: 0018 movs r0, r3 + 8002898: 46bd mov sp, r7 + 800289a: bd80 pop {r7, pc} + 800289c: 40021000 .word 0x40021000 + 80028a0: 08004dfc .word 0x08004dfc -08001fe0 : +080028a4 : * @note (*) not available on all devices * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *PeriphClkInit) { - 8001fe0: b580 push {r7, lr} - 8001fe2: b086 sub sp, #24 - 8001fe4: af00 add r7, sp, #0 - 8001fe6: 6078 str r0, [r7, #4] + 80028a4: b580 push {r7, lr} + 80028a6: b086 sub sp, #24 + 80028a8: af00 add r7, sp, #0 + 80028aa: 6078 str r0, [r7, #4] uint32_t tmpregister; uint32_t tickstart; HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ - 8001fe8: 2313 movs r3, #19 - 8001fea: 18fb adds r3, r7, r3 - 8001fec: 2200 movs r2, #0 - 8001fee: 701a strb r2, [r3, #0] + 80028ac: 2313 movs r3, #19 + 80028ae: 18fb adds r3, r7, r3 + 80028b0: 2200 movs r2, #0 + 80028b2: 701a strb r2, [r3, #0] HAL_StatusTypeDef status = HAL_OK; /* Final status */ - 8001ff0: 2312 movs r3, #18 - 8001ff2: 18fb adds r3, r7, r3 - 8001ff4: 2200 movs r2, #0 - 8001ff6: 701a strb r2, [r3, #0] + 80028b4: 2312 movs r3, #18 + 80028b6: 18fb adds r3, r7, r3 + 80028b8: 2200 movs r2, #0 + 80028ba: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*-------------------------- RTC clock source configuration ----------------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) - 8001ff8: 687b ldr r3, [r7, #4] - 8001ffa: 681b ldr r3, [r3, #0] - 8001ffc: 2240 movs r2, #64 @ 0x40 - 8001ffe: 4013 ands r3, r2 - 8002000: d100 bne.n 8002004 - 8002002: e079 b.n 80020f8 + 80028bc: 687b ldr r3, [r7, #4] + 80028be: 681b ldr r3, [r3, #0] + 80028c0: 2240 movs r2, #64 @ 0x40 + 80028c2: 4013 ands r3, r2 + 80028c4: d100 bne.n 80028c8 + 80028c6: e079 b.n 80029bc { FlagStatus pwrclkchanged = RESET; - 8002004: 2011 movs r0, #17 - 8002006: 183b adds r3, r7, r0 - 8002008: 2200 movs r2, #0 - 800200a: 701a strb r2, [r3, #0] + 80028c8: 2011 movs r0, #17 + 80028ca: 183b adds r3, r7, r0 + 80028cc: 2200 movs r2, #0 + 80028ce: 701a strb r2, [r3, #0] /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable Power Clock */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) - 800200c: 4b63 ldr r3, [pc, #396] @ (800219c ) - 800200e: 6bda ldr r2, [r3, #60] @ 0x3c - 8002010: 2380 movs r3, #128 @ 0x80 - 8002012: 055b lsls r3, r3, #21 - 8002014: 4013 ands r3, r2 - 8002016: d110 bne.n 800203a + 80028d0: 4b63 ldr r3, [pc, #396] @ (8002a60 ) + 80028d2: 6bda ldr r2, [r3, #60] @ 0x3c + 80028d4: 2380 movs r3, #128 @ 0x80 + 80028d6: 055b lsls r3, r3, #21 + 80028d8: 4013 ands r3, r2 + 80028da: d110 bne.n 80028fe { __HAL_RCC_PWR_CLK_ENABLE(); - 8002018: 4b60 ldr r3, [pc, #384] @ (800219c ) - 800201a: 6bda ldr r2, [r3, #60] @ 0x3c - 800201c: 4b5f ldr r3, [pc, #380] @ (800219c ) - 800201e: 2180 movs r1, #128 @ 0x80 - 8002020: 0549 lsls r1, r1, #21 - 8002022: 430a orrs r2, r1 - 8002024: 63da str r2, [r3, #60] @ 0x3c - 8002026: 4b5d ldr r3, [pc, #372] @ (800219c ) - 8002028: 6bda ldr r2, [r3, #60] @ 0x3c - 800202a: 2380 movs r3, #128 @ 0x80 - 800202c: 055b lsls r3, r3, #21 - 800202e: 4013 ands r3, r2 - 8002030: 60bb str r3, [r7, #8] - 8002032: 68bb ldr r3, [r7, #8] + 80028dc: 4b60 ldr r3, [pc, #384] @ (8002a60 ) + 80028de: 6bda ldr r2, [r3, #60] @ 0x3c + 80028e0: 4b5f ldr r3, [pc, #380] @ (8002a60 ) + 80028e2: 2180 movs r1, #128 @ 0x80 + 80028e4: 0549 lsls r1, r1, #21 + 80028e6: 430a orrs r2, r1 + 80028e8: 63da str r2, [r3, #60] @ 0x3c + 80028ea: 4b5d ldr r3, [pc, #372] @ (8002a60 ) + 80028ec: 6bda ldr r2, [r3, #60] @ 0x3c + 80028ee: 2380 movs r3, #128 @ 0x80 + 80028f0: 055b lsls r3, r3, #21 + 80028f2: 4013 ands r3, r2 + 80028f4: 60bb str r3, [r7, #8] + 80028f6: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; - 8002034: 183b adds r3, r7, r0 - 8002036: 2201 movs r2, #1 - 8002038: 701a strb r2, [r3, #0] + 80028f8: 183b adds r3, r7, r0 + 80028fa: 2201 movs r2, #1 + 80028fc: 701a strb r2, [r3, #0] } /* Reset the RTC domain only if the RTC Clock source selection is modified from default */ tmpregister = READ_BIT(RCC->CSR1, RCC_CSR1_RTCSEL); - 800203a: 4b58 ldr r3, [pc, #352] @ (800219c ) - 800203c: 6dda ldr r2, [r3, #92] @ 0x5c - 800203e: 23c0 movs r3, #192 @ 0xc0 - 8002040: 009b lsls r3, r3, #2 - 8002042: 4013 ands r3, r2 - 8002044: 617b str r3, [r7, #20] + 80028fe: 4b58 ldr r3, [pc, #352] @ (8002a60 ) + 8002900: 6dda ldr r2, [r3, #92] @ 0x5c + 8002902: 23c0 movs r3, #192 @ 0xc0 + 8002904: 009b lsls r3, r3, #2 + 8002906: 4013 ands r3, r2 + 8002908: 617b str r3, [r7, #20] /* Reset the RTC domain only if the RTC Clock source selection is modified */ if ((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection)) - 8002046: 697b ldr r3, [r7, #20] - 8002048: 2b00 cmp r3, #0 - 800204a: d019 beq.n 8002080 - 800204c: 687b ldr r3, [r7, #4] - 800204e: 699b ldr r3, [r3, #24] - 8002050: 697a ldr r2, [r7, #20] - 8002052: 429a cmp r2, r3 - 8002054: d014 beq.n 8002080 + 800290a: 697b ldr r3, [r7, #20] + 800290c: 2b00 cmp r3, #0 + 800290e: d019 beq.n 8002944 + 8002910: 687b ldr r3, [r7, #4] + 8002912: 699b ldr r3, [r3, #24] + 8002914: 697a ldr r2, [r7, #20] + 8002916: 429a cmp r2, r3 + 8002918: d014 beq.n 8002944 { /* Store the content of CSR1 register before the reset of RTC Domain */ tmpregister = READ_BIT(RCC->CSR1, ~(RCC_CSR1_RTCSEL)); - 8002056: 4b51 ldr r3, [pc, #324] @ (800219c ) - 8002058: 6ddb ldr r3, [r3, #92] @ 0x5c - 800205a: 4a51 ldr r2, [pc, #324] @ (80021a0 ) - 800205c: 4013 ands r3, r2 - 800205e: 617b str r3, [r7, #20] + 800291a: 4b51 ldr r3, [pc, #324] @ (8002a60 ) + 800291c: 6ddb ldr r3, [r3, #92] @ 0x5c + 800291e: 4a51 ldr r2, [pc, #324] @ (8002a64 ) + 8002920: 4013 ands r3, r2 + 8002922: 617b str r3, [r7, #20] /* RTC Clock selection can be changed only if the RTC Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); - 8002060: 4b4e ldr r3, [pc, #312] @ (800219c ) - 8002062: 6dda ldr r2, [r3, #92] @ 0x5c - 8002064: 4b4d ldr r3, [pc, #308] @ (800219c ) - 8002066: 2180 movs r1, #128 @ 0x80 - 8002068: 0249 lsls r1, r1, #9 - 800206a: 430a orrs r2, r1 - 800206c: 65da str r2, [r3, #92] @ 0x5c + 8002924: 4b4e ldr r3, [pc, #312] @ (8002a60 ) + 8002926: 6dda ldr r2, [r3, #92] @ 0x5c + 8002928: 4b4d ldr r3, [pc, #308] @ (8002a60 ) + 800292a: 2180 movs r1, #128 @ 0x80 + 800292c: 0249 lsls r1, r1, #9 + 800292e: 430a orrs r2, r1 + 8002930: 65da str r2, [r3, #92] @ 0x5c __HAL_RCC_BACKUPRESET_RELEASE(); - 800206e: 4b4b ldr r3, [pc, #300] @ (800219c ) - 8002070: 6dda ldr r2, [r3, #92] @ 0x5c - 8002072: 4b4a ldr r3, [pc, #296] @ (800219c ) - 8002074: 494b ldr r1, [pc, #300] @ (80021a4 ) - 8002076: 400a ands r2, r1 - 8002078: 65da str r2, [r3, #92] @ 0x5c + 8002932: 4b4b ldr r3, [pc, #300] @ (8002a60 ) + 8002934: 6dda ldr r2, [r3, #92] @ 0x5c + 8002936: 4b4a ldr r3, [pc, #296] @ (8002a60 ) + 8002938: 494b ldr r1, [pc, #300] @ (8002a68 ) + 800293a: 400a ands r2, r1 + 800293c: 65da str r2, [r3, #92] @ 0x5c /* Restore the Content of CSR1 register */ RCC->CSR1 = tmpregister; - 800207a: 4b48 ldr r3, [pc, #288] @ (800219c ) - 800207c: 697a ldr r2, [r7, #20] - 800207e: 65da str r2, [r3, #92] @ 0x5c + 800293e: 4b48 ldr r3, [pc, #288] @ (8002a60 ) + 8002940: 697a ldr r2, [r7, #20] + 8002942: 65da str r2, [r3, #92] @ 0x5c } /* Wait for LSE reactivation if LSE was enable prior to RTC Domain reset */ if (HAL_IS_BIT_SET(tmpregister, RCC_CSR1_LSEON)) - 8002080: 697b ldr r3, [r7, #20] - 8002082: 2201 movs r2, #1 - 8002084: 4013 ands r3, r2 - 8002086: d016 beq.n 80020b6 + 8002944: 697b ldr r3, [r7, #20] + 8002946: 2201 movs r2, #1 + 8002948: 4013 ands r3, r2 + 800294a: d016 beq.n 800297a { /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8002088: f7fe fff4 bl 8001074 - 800208c: 0003 movs r3, r0 - 800208e: 60fb str r3, [r7, #12] + 800294c: f7fe fef2 bl 8001734 + 8002950: 0003 movs r3, r0 + 8002952: 60fb str r3, [r7, #12] /* Wait till LSE is ready */ while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U) - 8002090: e00c b.n 80020ac + 8002954: e00c b.n 8002970 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - 8002092: f7fe ffef bl 8001074 - 8002096: 0002 movs r2, r0 - 8002098: 68fb ldr r3, [r7, #12] - 800209a: 1ad3 subs r3, r2, r3 - 800209c: 4a42 ldr r2, [pc, #264] @ (80021a8 ) - 800209e: 4293 cmp r3, r2 - 80020a0: d904 bls.n 80020ac + 8002956: f7fe feed bl 8001734 + 800295a: 0002 movs r2, r0 + 800295c: 68fb ldr r3, [r7, #12] + 800295e: 1ad3 subs r3, r2, r3 + 8002960: 4a42 ldr r2, [pc, #264] @ (8002a6c ) + 8002962: 4293 cmp r3, r2 + 8002964: d904 bls.n 8002970 { ret = HAL_TIMEOUT; - 80020a2: 2313 movs r3, #19 - 80020a4: 18fb adds r3, r7, r3 - 80020a6: 2203 movs r2, #3 - 80020a8: 701a strb r2, [r3, #0] + 8002966: 2313 movs r3, #19 + 8002968: 18fb adds r3, r7, r3 + 800296a: 2203 movs r2, #3 + 800296c: 701a strb r2, [r3, #0] break; - 80020aa: e004 b.n 80020b6 + 800296e: e004 b.n 800297a while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U) - 80020ac: 4b3b ldr r3, [pc, #236] @ (800219c ) - 80020ae: 6ddb ldr r3, [r3, #92] @ 0x5c - 80020b0: 2202 movs r2, #2 - 80020b2: 4013 ands r3, r2 - 80020b4: d0ed beq.n 8002092 + 8002970: 4b3b ldr r3, [pc, #236] @ (8002a60 ) + 8002972: 6ddb ldr r3, [r3, #92] @ 0x5c + 8002974: 2202 movs r2, #2 + 8002976: 4013 ands r3, r2 + 8002978: d0ed beq.n 8002956 } } } if (ret == HAL_OK) - 80020b6: 2313 movs r3, #19 - 80020b8: 18fb adds r3, r7, r3 - 80020ba: 781b ldrb r3, [r3, #0] - 80020bc: 2b00 cmp r3, #0 - 80020be: d10a bne.n 80020d6 + 800297a: 2313 movs r3, #19 + 800297c: 18fb adds r3, r7, r3 + 800297e: 781b ldrb r3, [r3, #0] + 8002980: 2b00 cmp r3, #0 + 8002982: d10a bne.n 800299a { /* Apply new RTC clock source selection */ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); - 80020c0: 4b36 ldr r3, [pc, #216] @ (800219c ) - 80020c2: 6ddb ldr r3, [r3, #92] @ 0x5c - 80020c4: 4a36 ldr r2, [pc, #216] @ (80021a0 ) - 80020c6: 4013 ands r3, r2 - 80020c8: 0019 movs r1, r3 - 80020ca: 687b ldr r3, [r7, #4] - 80020cc: 699a ldr r2, [r3, #24] - 80020ce: 4b33 ldr r3, [pc, #204] @ (800219c ) - 80020d0: 430a orrs r2, r1 - 80020d2: 65da str r2, [r3, #92] @ 0x5c - 80020d4: e005 b.n 80020e2 + 8002984: 4b36 ldr r3, [pc, #216] @ (8002a60 ) + 8002986: 6ddb ldr r3, [r3, #92] @ 0x5c + 8002988: 4a36 ldr r2, [pc, #216] @ (8002a64 ) + 800298a: 4013 ands r3, r2 + 800298c: 0019 movs r1, r3 + 800298e: 687b ldr r3, [r7, #4] + 8002990: 699a ldr r2, [r3, #24] + 8002992: 4b33 ldr r3, [pc, #204] @ (8002a60 ) + 8002994: 430a orrs r2, r1 + 8002996: 65da str r2, [r3, #92] @ 0x5c + 8002998: e005 b.n 80029a6 } else { /* set overall return value */ status = ret; - 80020d6: 2312 movs r3, #18 - 80020d8: 18fb adds r3, r7, r3 - 80020da: 2213 movs r2, #19 - 80020dc: 18ba adds r2, r7, r2 - 80020de: 7812 ldrb r2, [r2, #0] - 80020e0: 701a strb r2, [r3, #0] + 800299a: 2312 movs r3, #18 + 800299c: 18fb adds r3, r7, r3 + 800299e: 2213 movs r2, #19 + 80029a0: 18ba adds r2, r7, r2 + 80029a2: 7812 ldrb r2, [r2, #0] + 80029a4: 701a strb r2, [r3, #0] } /* Restore clock configuration if changed */ if (pwrclkchanged == SET) - 80020e2: 2311 movs r3, #17 - 80020e4: 18fb adds r3, r7, r3 - 80020e6: 781b ldrb r3, [r3, #0] - 80020e8: 2b01 cmp r3, #1 - 80020ea: d105 bne.n 80020f8 + 80029a6: 2311 movs r3, #17 + 80029a8: 18fb adds r3, r7, r3 + 80029aa: 781b ldrb r3, [r3, #0] + 80029ac: 2b01 cmp r3, #1 + 80029ae: d105 bne.n 80029bc { __HAL_RCC_PWR_CLK_DISABLE(); - 80020ec: 4b2b ldr r3, [pc, #172] @ (800219c ) - 80020ee: 6bda ldr r2, [r3, #60] @ 0x3c - 80020f0: 4b2a ldr r3, [pc, #168] @ (800219c ) - 80020f2: 492e ldr r1, [pc, #184] @ (80021ac ) - 80020f4: 400a ands r2, r1 - 80020f6: 63da str r2, [r3, #60] @ 0x3c + 80029b0: 4b2b ldr r3, [pc, #172] @ (8002a60 ) + 80029b2: 6bda ldr r2, [r3, #60] @ 0x3c + 80029b4: 4b2a ldr r3, [pc, #168] @ (8002a60 ) + 80029b6: 492e ldr r1, [pc, #184] @ (8002a70 ) + 80029b8: 400a ands r2, r1 + 80029ba: 63da str r2, [r3, #60] @ 0x3c } } /*-------------------------- USART1 clock source configuration -------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) - 80020f8: 687b ldr r3, [r7, #4] - 80020fa: 681b ldr r3, [r3, #0] - 80020fc: 2201 movs r2, #1 - 80020fe: 4013 ands r3, r2 - 8002100: d009 beq.n 8002116 + 80029bc: 687b ldr r3, [r7, #4] + 80029be: 681b ldr r3, [r3, #0] + 80029c0: 2201 movs r2, #1 + 80029c2: 4013 ands r3, r2 + 80029c4: d009 beq.n 80029da { /* Check the parameters */ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); /* Configure the USART1 clock source */ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); - 8002102: 4b26 ldr r3, [pc, #152] @ (800219c ) - 8002104: 6d5b ldr r3, [r3, #84] @ 0x54 - 8002106: 2203 movs r2, #3 - 8002108: 4393 bics r3, r2 - 800210a: 0019 movs r1, r3 - 800210c: 687b ldr r3, [r7, #4] - 800210e: 689a ldr r2, [r3, #8] - 8002110: 4b22 ldr r3, [pc, #136] @ (800219c ) - 8002112: 430a orrs r2, r1 - 8002114: 655a str r2, [r3, #84] @ 0x54 + 80029c6: 4b26 ldr r3, [pc, #152] @ (8002a60 ) + 80029c8: 6d5b ldr r3, [r3, #84] @ 0x54 + 80029ca: 2203 movs r2, #3 + 80029cc: 4393 bics r3, r2 + 80029ce: 0019 movs r1, r3 + 80029d0: 687b ldr r3, [r7, #4] + 80029d2: 689a ldr r2, [r3, #8] + 80029d4: 4b22 ldr r3, [pc, #136] @ (8002a60 ) + 80029d6: 430a orrs r2, r1 + 80029d8: 655a str r2, [r3, #84] @ 0x54 } /*-------------------------- I2C1 clock source configuration ---------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) - 8002116: 687b ldr r3, [r7, #4] - 8002118: 681b ldr r3, [r3, #0] - 800211a: 2202 movs r2, #2 - 800211c: 4013 ands r3, r2 - 800211e: d009 beq.n 8002134 + 80029da: 687b ldr r3, [r7, #4] + 80029dc: 681b ldr r3, [r3, #0] + 80029de: 2202 movs r2, #2 + 80029e0: 4013 ands r3, r2 + 80029e2: d009 beq.n 80029f8 { /* Check the parameters */ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); /* Configure the I2C1 clock source */ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); - 8002120: 4b1e ldr r3, [pc, #120] @ (800219c ) - 8002122: 6d5b ldr r3, [r3, #84] @ 0x54 - 8002124: 4a22 ldr r2, [pc, #136] @ (80021b0 ) - 8002126: 4013 ands r3, r2 - 8002128: 0019 movs r1, r3 - 800212a: 687b ldr r3, [r7, #4] - 800212c: 68da ldr r2, [r3, #12] - 800212e: 4b1b ldr r3, [pc, #108] @ (800219c ) - 8002130: 430a orrs r2, r1 - 8002132: 655a str r2, [r3, #84] @ 0x54 + 80029e4: 4b1e ldr r3, [pc, #120] @ (8002a60 ) + 80029e6: 6d5b ldr r3, [r3, #84] @ 0x54 + 80029e8: 4a22 ldr r2, [pc, #136] @ (8002a74 ) + 80029ea: 4013 ands r3, r2 + 80029ec: 0019 movs r1, r3 + 80029ee: 687b ldr r3, [r7, #4] + 80029f0: 68da ldr r2, [r3, #12] + 80029f2: 4b1b ldr r3, [pc, #108] @ (8002a60 ) + 80029f4: 430a orrs r2, r1 + 80029f6: 655a str r2, [r3, #84] @ 0x54 } /*-------------------------- ADC clock source configuration ----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) - 8002134: 687b ldr r3, [r7, #4] - 8002136: 681b ldr r3, [r3, #0] - 8002138: 2220 movs r2, #32 - 800213a: 4013 ands r3, r2 - 800213c: d008 beq.n 8002150 + 80029f8: 687b ldr r3, [r7, #4] + 80029fa: 681b ldr r3, [r3, #0] + 80029fc: 2220 movs r2, #32 + 80029fe: 4013 ands r3, r2 + 8002a00: d008 beq.n 8002a14 { /* Check the parameters */ assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection)); /* Configure the ADC interface clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); - 800213e: 4b17 ldr r3, [pc, #92] @ (800219c ) - 8002140: 6d5b ldr r3, [r3, #84] @ 0x54 - 8002142: 009b lsls r3, r3, #2 - 8002144: 0899 lsrs r1, r3, #2 - 8002146: 687b ldr r3, [r7, #4] - 8002148: 695a ldr r2, [r3, #20] - 800214a: 4b14 ldr r3, [pc, #80] @ (800219c ) - 800214c: 430a orrs r2, r1 - 800214e: 655a str r2, [r3, #84] @ 0x54 + 8002a02: 4b17 ldr r3, [pc, #92] @ (8002a60 ) + 8002a04: 6d5b ldr r3, [r3, #84] @ 0x54 + 8002a06: 009b lsls r3, r3, #2 + 8002a08: 0899 lsrs r1, r3, #2 + 8002a0a: 687b ldr r3, [r7, #4] + 8002a0c: 695a ldr r2, [r3, #20] + 8002a0e: 4b14 ldr r3, [pc, #80] @ (8002a60 ) + 8002a10: 430a orrs r2, r1 + 8002a12: 655a str r2, [r3, #84] @ 0x54 __HAL_RCC_FDCAN1_CONFIG(PeriphClkInit->Fdcan1ClockSelection); } #endif /* FDCAN1 */ /*-------------------------- I2S1 clock source configuration ---------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) - 8002150: 687b ldr r3, [r7, #4] - 8002152: 681b ldr r3, [r3, #0] - 8002154: 2204 movs r2, #4 - 8002156: 4013 ands r3, r2 - 8002158: d009 beq.n 800216e + 8002a14: 687b ldr r3, [r7, #4] + 8002a16: 681b ldr r3, [r3, #0] + 8002a18: 2204 movs r2, #4 + 8002a1a: 4013 ands r3, r2 + 8002a1c: d009 beq.n 8002a32 { /* Check the parameters */ assert_param(IS_RCC_I2S1CLKSOURCE(PeriphClkInit->I2s1ClockSelection)); /* Configure the I2S1 clock source */ __HAL_RCC_I2S1_CONFIG(PeriphClkInit->I2s1ClockSelection); - 800215a: 4b10 ldr r3, [pc, #64] @ (800219c ) - 800215c: 6d5b ldr r3, [r3, #84] @ 0x54 - 800215e: 4a15 ldr r2, [pc, #84] @ (80021b4 ) - 8002160: 4013 ands r3, r2 - 8002162: 0019 movs r1, r3 - 8002164: 687b ldr r3, [r7, #4] - 8002166: 691a ldr r2, [r3, #16] - 8002168: 4b0c ldr r3, [pc, #48] @ (800219c ) - 800216a: 430a orrs r2, r1 - 800216c: 655a str r2, [r3, #84] @ 0x54 + 8002a1e: 4b10 ldr r3, [pc, #64] @ (8002a60 ) + 8002a20: 6d5b ldr r3, [r3, #84] @ 0x54 + 8002a22: 4a15 ldr r2, [pc, #84] @ (8002a78 ) + 8002a24: 4013 ands r3, r2 + 8002a26: 0019 movs r1, r3 + 8002a28: 687b ldr r3, [r7, #4] + 8002a2a: 691a ldr r2, [r3, #16] + 8002a2c: 4b0c ldr r3, [pc, #48] @ (8002a60 ) + 8002a2e: 430a orrs r2, r1 + 8002a30: 655a str r2, [r3, #84] @ 0x54 } /*------------------------------------ HSI Kernel clock source configuration --------------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HSIKER) == RCC_PERIPHCLK_HSIKER) - 800216e: 687b ldr r3, [r7, #4] - 8002170: 681b ldr r3, [r3, #0] - 8002172: 2280 movs r2, #128 @ 0x80 - 8002174: 4013 ands r3, r2 - 8002176: d009 beq.n 800218c + 8002a32: 687b ldr r3, [r7, #4] + 8002a34: 681b ldr r3, [r3, #0] + 8002a36: 2280 movs r2, #128 @ 0x80 + 8002a38: 4013 ands r3, r2 + 8002a3a: d009 beq.n 8002a50 { /* Check the parameters */ assert_param(IS_RCC_HSIKERDIV(PeriphClkInit->HSIKerClockDivider)); /* Configure the HSI Kernel clock source Divider */ __HAL_RCC_HSIKER_CONFIG(PeriphClkInit->HSIKerClockDivider); - 8002178: 4b08 ldr r3, [pc, #32] @ (800219c ) - 800217a: 681b ldr r3, [r3, #0] - 800217c: 22e0 movs r2, #224 @ 0xe0 - 800217e: 4393 bics r3, r2 - 8002180: 0019 movs r1, r3 - 8002182: 687b ldr r3, [r7, #4] - 8002184: 685a ldr r2, [r3, #4] - 8002186: 4b05 ldr r3, [pc, #20] @ (800219c ) - 8002188: 430a orrs r2, r1 - 800218a: 601a str r2, [r3, #0] + 8002a3c: 4b08 ldr r3, [pc, #32] @ (8002a60 ) + 8002a3e: 681b ldr r3, [r3, #0] + 8002a40: 22e0 movs r2, #224 @ 0xe0 + 8002a42: 4393 bics r3, r2 + 8002a44: 0019 movs r1, r3 + 8002a46: 687b ldr r3, [r7, #4] + 8002a48: 685a ldr r2, [r3, #4] + 8002a4a: 4b05 ldr r3, [pc, #20] @ (8002a60 ) + 8002a4c: 430a orrs r2, r1 + 8002a4e: 601a str r2, [r3, #0] } return status; - 800218c: 2312 movs r3, #18 - 800218e: 18fb adds r3, r7, r3 - 8002190: 781b ldrb r3, [r3, #0] + 8002a50: 2312 movs r3, #18 + 8002a52: 18fb adds r3, r7, r3 + 8002a54: 781b ldrb r3, [r3, #0] } - 8002192: 0018 movs r0, r3 - 8002194: 46bd mov sp, r7 - 8002196: b006 add sp, #24 - 8002198: bd80 pop {r7, pc} - 800219a: 46c0 nop @ (mov r8, r8) - 800219c: 40021000 .word 0x40021000 - 80021a0: fffffcff .word 0xfffffcff - 80021a4: fffeffff .word 0xfffeffff - 80021a8: 00001388 .word 0x00001388 - 80021ac: efffffff .word 0xefffffff - 80021b0: ffffcfff .word 0xffffcfff - 80021b4: ffff3fff .word 0xffff3fff + 8002a56: 0018 movs r0, r3 + 8002a58: 46bd mov sp, r7 + 8002a5a: b006 add sp, #24 + 8002a5c: bd80 pop {r7, pc} + 8002a5e: 46c0 nop @ (mov r8, r8) + 8002a60: 40021000 .word 0x40021000 + 8002a64: fffffcff .word 0xfffffcff + 8002a68: fffeffff .word 0xfffeffff + 8002a6c: 00001388 .word 0x00001388 + 8002a70: efffffff .word 0xefffffff + 8002a74: ffffcfff .word 0xffffcfff + 8002a78: ffff3fff .word 0xffff3fff -080021b8 : +08002a7c : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { - 80021b8: b580 push {r7, lr} - 80021ba: b082 sub sp, #8 - 80021bc: af00 add r7, sp, #0 - 80021be: 6078 str r0, [r7, #4] + 8002a7c: b580 push {r7, lr} + 8002a7e: b082 sub sp, #8 + 8002a80: af00 add r7, sp, #0 + 8002a82: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) - 80021c0: 687b ldr r3, [r7, #4] - 80021c2: 2b00 cmp r3, #0 - 80021c4: d101 bne.n 80021ca + 8002a84: 687b ldr r3, [r7, #4] + 8002a86: 2b00 cmp r3, #0 + 8002a88: d101 bne.n 8002a8e { return HAL_ERROR; - 80021c6: 2301 movs r3, #1 - 80021c8: e04a b.n 8002260 + 8002a8a: 2301 movs r3, #1 + 8002a8c: e04a b.n 8002b24 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) - 80021ca: 687b ldr r3, [r7, #4] - 80021cc: 223d movs r2, #61 @ 0x3d - 80021ce: 5c9b ldrb r3, [r3, r2] - 80021d0: b2db uxtb r3, r3 - 80021d2: 2b00 cmp r3, #0 - 80021d4: d107 bne.n 80021e6 + 8002a8e: 687b ldr r3, [r7, #4] + 8002a90: 223d movs r2, #61 @ 0x3d + 8002a92: 5c9b ldrb r3, [r3, r2] + 8002a94: b2db uxtb r3, r3 + 8002a96: 2b00 cmp r3, #0 + 8002a98: d107 bne.n 8002aaa { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; - 80021d6: 687b ldr r3, [r7, #4] - 80021d8: 223c movs r2, #60 @ 0x3c - 80021da: 2100 movs r1, #0 - 80021dc: 5499 strb r1, [r3, r2] + 8002a9a: 687b ldr r3, [r7, #4] + 8002a9c: 223c movs r2, #60 @ 0x3c + 8002a9e: 2100 movs r1, #0 + 8002aa0: 5499 strb r1, [r3, r2] } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); - 80021de: 687b ldr r3, [r7, #4] - 80021e0: 0018 movs r0, r3 - 80021e2: f7fe fc91 bl 8000b08 + 8002aa2: 687b ldr r3, [r7, #4] + 8002aa4: 0018 movs r0, r3 + 8002aa6: f7fe fb29 bl 80010fc #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; - 80021e6: 687b ldr r3, [r7, #4] - 80021e8: 223d movs r2, #61 @ 0x3d - 80021ea: 2102 movs r1, #2 - 80021ec: 5499 strb r1, [r3, r2] + 8002aaa: 687b ldr r3, [r7, #4] + 8002aac: 223d movs r2, #61 @ 0x3d + 8002aae: 2102 movs r1, #2 + 8002ab0: 5499 strb r1, [r3, r2] /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); - 80021ee: 687b ldr r3, [r7, #4] - 80021f0: 681a ldr r2, [r3, #0] - 80021f2: 687b ldr r3, [r7, #4] - 80021f4: 3304 adds r3, #4 - 80021f6: 0019 movs r1, r3 - 80021f8: 0010 movs r0, r2 - 80021fa: f000 fc3b bl 8002a74 + 8002ab2: 687b ldr r3, [r7, #4] + 8002ab4: 681a ldr r2, [r3, #0] + 8002ab6: 687b ldr r3, [r7, #4] + 8002ab8: 3304 adds r3, #4 + 8002aba: 0019 movs r1, r3 + 8002abc: 0010 movs r0, r2 + 8002abe: f000 fc3b bl 8003338 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - 80021fe: 687b ldr r3, [r7, #4] - 8002200: 2248 movs r2, #72 @ 0x48 - 8002202: 2101 movs r1, #1 - 8002204: 5499 strb r1, [r3, r2] + 8002ac2: 687b ldr r3, [r7, #4] + 8002ac4: 2248 movs r2, #72 @ 0x48 + 8002ac6: 2101 movs r1, #1 + 8002ac8: 5499 strb r1, [r3, r2] /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - 8002206: 687b ldr r3, [r7, #4] - 8002208: 223e movs r2, #62 @ 0x3e - 800220a: 2101 movs r1, #1 - 800220c: 5499 strb r1, [r3, r2] - 800220e: 687b ldr r3, [r7, #4] - 8002210: 223f movs r2, #63 @ 0x3f - 8002212: 2101 movs r1, #1 - 8002214: 5499 strb r1, [r3, r2] - 8002216: 687b ldr r3, [r7, #4] - 8002218: 2240 movs r2, #64 @ 0x40 - 800221a: 2101 movs r1, #1 - 800221c: 5499 strb r1, [r3, r2] - 800221e: 687b ldr r3, [r7, #4] - 8002220: 2241 movs r2, #65 @ 0x41 - 8002222: 2101 movs r1, #1 - 8002224: 5499 strb r1, [r3, r2] - 8002226: 687b ldr r3, [r7, #4] - 8002228: 2242 movs r2, #66 @ 0x42 - 800222a: 2101 movs r1, #1 - 800222c: 5499 strb r1, [r3, r2] - 800222e: 687b ldr r3, [r7, #4] - 8002230: 2243 movs r2, #67 @ 0x43 - 8002232: 2101 movs r1, #1 - 8002234: 5499 strb r1, [r3, r2] + 8002aca: 687b ldr r3, [r7, #4] + 8002acc: 223e movs r2, #62 @ 0x3e + 8002ace: 2101 movs r1, #1 + 8002ad0: 5499 strb r1, [r3, r2] + 8002ad2: 687b ldr r3, [r7, #4] + 8002ad4: 223f movs r2, #63 @ 0x3f + 8002ad6: 2101 movs r1, #1 + 8002ad8: 5499 strb r1, [r3, r2] + 8002ada: 687b ldr r3, [r7, #4] + 8002adc: 2240 movs r2, #64 @ 0x40 + 8002ade: 2101 movs r1, #1 + 8002ae0: 5499 strb r1, [r3, r2] + 8002ae2: 687b ldr r3, [r7, #4] + 8002ae4: 2241 movs r2, #65 @ 0x41 + 8002ae6: 2101 movs r1, #1 + 8002ae8: 5499 strb r1, [r3, r2] + 8002aea: 687b ldr r3, [r7, #4] + 8002aec: 2242 movs r2, #66 @ 0x42 + 8002aee: 2101 movs r1, #1 + 8002af0: 5499 strb r1, [r3, r2] + 8002af2: 687b ldr r3, [r7, #4] + 8002af4: 2243 movs r2, #67 @ 0x43 + 8002af6: 2101 movs r1, #1 + 8002af8: 5499 strb r1, [r3, r2] TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - 8002236: 687b ldr r3, [r7, #4] - 8002238: 2244 movs r2, #68 @ 0x44 - 800223a: 2101 movs r1, #1 - 800223c: 5499 strb r1, [r3, r2] - 800223e: 687b ldr r3, [r7, #4] - 8002240: 2245 movs r2, #69 @ 0x45 - 8002242: 2101 movs r1, #1 - 8002244: 5499 strb r1, [r3, r2] - 8002246: 687b ldr r3, [r7, #4] - 8002248: 2246 movs r2, #70 @ 0x46 - 800224a: 2101 movs r1, #1 - 800224c: 5499 strb r1, [r3, r2] - 800224e: 687b ldr r3, [r7, #4] - 8002250: 2247 movs r2, #71 @ 0x47 - 8002252: 2101 movs r1, #1 - 8002254: 5499 strb r1, [r3, r2] + 8002afa: 687b ldr r3, [r7, #4] + 8002afc: 2244 movs r2, #68 @ 0x44 + 8002afe: 2101 movs r1, #1 + 8002b00: 5499 strb r1, [r3, r2] + 8002b02: 687b ldr r3, [r7, #4] + 8002b04: 2245 movs r2, #69 @ 0x45 + 8002b06: 2101 movs r1, #1 + 8002b08: 5499 strb r1, [r3, r2] + 8002b0a: 687b ldr r3, [r7, #4] + 8002b0c: 2246 movs r2, #70 @ 0x46 + 8002b0e: 2101 movs r1, #1 + 8002b10: 5499 strb r1, [r3, r2] + 8002b12: 687b ldr r3, [r7, #4] + 8002b14: 2247 movs r2, #71 @ 0x47 + 8002b16: 2101 movs r1, #1 + 8002b18: 5499 strb r1, [r3, r2] /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; - 8002256: 687b ldr r3, [r7, #4] - 8002258: 223d movs r2, #61 @ 0x3d - 800225a: 2101 movs r1, #1 - 800225c: 5499 strb r1, [r3, r2] + 8002b1a: 687b ldr r3, [r7, #4] + 8002b1c: 223d movs r2, #61 @ 0x3d + 8002b1e: 2101 movs r1, #1 + 8002b20: 5499 strb r1, [r3, r2] return HAL_OK; - 800225e: 2300 movs r3, #0 + 8002b22: 2300 movs r3, #0 } - 8002260: 0018 movs r0, r3 - 8002262: 46bd mov sp, r7 - 8002264: b002 add sp, #8 - 8002266: bd80 pop {r7, pc} + 8002b24: 0018 movs r0, r3 + 8002b26: 46bd mov sp, r7 + 8002b28: b002 add sp, #8 + 8002b2a: bd80 pop {r7, pc} -08002268 : +08002b2c : * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { - 8002268: b580 push {r7, lr} - 800226a: b082 sub sp, #8 - 800226c: af00 add r7, sp, #0 - 800226e: 6078 str r0, [r7, #4] + 8002b2c: b580 push {r7, lr} + 8002b2e: b082 sub sp, #8 + 8002b30: af00 add r7, sp, #0 + 8002b32: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) - 8002270: 687b ldr r3, [r7, #4] - 8002272: 2b00 cmp r3, #0 - 8002274: d101 bne.n 800227a + 8002b34: 687b ldr r3, [r7, #4] + 8002b36: 2b00 cmp r3, #0 + 8002b38: d101 bne.n 8002b3e { return HAL_ERROR; - 8002276: 2301 movs r3, #1 - 8002278: e04a b.n 8002310 + 8002b3a: 2301 movs r3, #1 + 8002b3c: e04a b.n 8002bd4 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) - 800227a: 687b ldr r3, [r7, #4] - 800227c: 223d movs r2, #61 @ 0x3d - 800227e: 5c9b ldrb r3, [r3, r2] - 8002280: b2db uxtb r3, r3 - 8002282: 2b00 cmp r3, #0 - 8002284: d107 bne.n 8002296 + 8002b3e: 687b ldr r3, [r7, #4] + 8002b40: 223d movs r2, #61 @ 0x3d + 8002b42: 5c9b ldrb r3, [r3, r2] + 8002b44: b2db uxtb r3, r3 + 8002b46: 2b00 cmp r3, #0 + 8002b48: d107 bne.n 8002b5a { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; - 8002286: 687b ldr r3, [r7, #4] - 8002288: 223c movs r2, #60 @ 0x3c - 800228a: 2100 movs r1, #0 - 800228c: 5499 strb r1, [r3, r2] + 8002b4a: 687b ldr r3, [r7, #4] + 8002b4c: 223c movs r2, #60 @ 0x3c + 8002b4e: 2100 movs r1, #0 + 8002b50: 5499 strb r1, [r3, r2] } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->PWM_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); - 800228e: 687b ldr r3, [r7, #4] - 8002290: 0018 movs r0, r3 - 8002292: f000 f841 bl 8002318 + 8002b52: 687b ldr r3, [r7, #4] + 8002b54: 0018 movs r0, r3 + 8002b56: f000 f841 bl 8002bdc #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; - 8002296: 687b ldr r3, [r7, #4] - 8002298: 223d movs r2, #61 @ 0x3d - 800229a: 2102 movs r1, #2 - 800229c: 5499 strb r1, [r3, r2] + 8002b5a: 687b ldr r3, [r7, #4] + 8002b5c: 223d movs r2, #61 @ 0x3d + 8002b5e: 2102 movs r1, #2 + 8002b60: 5499 strb r1, [r3, r2] /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); - 800229e: 687b ldr r3, [r7, #4] - 80022a0: 681a ldr r2, [r3, #0] - 80022a2: 687b ldr r3, [r7, #4] - 80022a4: 3304 adds r3, #4 - 80022a6: 0019 movs r1, r3 - 80022a8: 0010 movs r0, r2 - 80022aa: f000 fbe3 bl 8002a74 + 8002b62: 687b ldr r3, [r7, #4] + 8002b64: 681a ldr r2, [r3, #0] + 8002b66: 687b ldr r3, [r7, #4] + 8002b68: 3304 adds r3, #4 + 8002b6a: 0019 movs r1, r3 + 8002b6c: 0010 movs r0, r2 + 8002b6e: f000 fbe3 bl 8003338 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - 80022ae: 687b ldr r3, [r7, #4] - 80022b0: 2248 movs r2, #72 @ 0x48 - 80022b2: 2101 movs r1, #1 - 80022b4: 5499 strb r1, [r3, r2] + 8002b72: 687b ldr r3, [r7, #4] + 8002b74: 2248 movs r2, #72 @ 0x48 + 8002b76: 2101 movs r1, #1 + 8002b78: 5499 strb r1, [r3, r2] /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - 80022b6: 687b ldr r3, [r7, #4] - 80022b8: 223e movs r2, #62 @ 0x3e - 80022ba: 2101 movs r1, #1 - 80022bc: 5499 strb r1, [r3, r2] - 80022be: 687b ldr r3, [r7, #4] - 80022c0: 223f movs r2, #63 @ 0x3f - 80022c2: 2101 movs r1, #1 - 80022c4: 5499 strb r1, [r3, r2] - 80022c6: 687b ldr r3, [r7, #4] - 80022c8: 2240 movs r2, #64 @ 0x40 - 80022ca: 2101 movs r1, #1 - 80022cc: 5499 strb r1, [r3, r2] - 80022ce: 687b ldr r3, [r7, #4] - 80022d0: 2241 movs r2, #65 @ 0x41 - 80022d2: 2101 movs r1, #1 - 80022d4: 5499 strb r1, [r3, r2] - 80022d6: 687b ldr r3, [r7, #4] - 80022d8: 2242 movs r2, #66 @ 0x42 - 80022da: 2101 movs r1, #1 - 80022dc: 5499 strb r1, [r3, r2] - 80022de: 687b ldr r3, [r7, #4] - 80022e0: 2243 movs r2, #67 @ 0x43 - 80022e2: 2101 movs r1, #1 - 80022e4: 5499 strb r1, [r3, r2] + 8002b7a: 687b ldr r3, [r7, #4] + 8002b7c: 223e movs r2, #62 @ 0x3e + 8002b7e: 2101 movs r1, #1 + 8002b80: 5499 strb r1, [r3, r2] + 8002b82: 687b ldr r3, [r7, #4] + 8002b84: 223f movs r2, #63 @ 0x3f + 8002b86: 2101 movs r1, #1 + 8002b88: 5499 strb r1, [r3, r2] + 8002b8a: 687b ldr r3, [r7, #4] + 8002b8c: 2240 movs r2, #64 @ 0x40 + 8002b8e: 2101 movs r1, #1 + 8002b90: 5499 strb r1, [r3, r2] + 8002b92: 687b ldr r3, [r7, #4] + 8002b94: 2241 movs r2, #65 @ 0x41 + 8002b96: 2101 movs r1, #1 + 8002b98: 5499 strb r1, [r3, r2] + 8002b9a: 687b ldr r3, [r7, #4] + 8002b9c: 2242 movs r2, #66 @ 0x42 + 8002b9e: 2101 movs r1, #1 + 8002ba0: 5499 strb r1, [r3, r2] + 8002ba2: 687b ldr r3, [r7, #4] + 8002ba4: 2243 movs r2, #67 @ 0x43 + 8002ba6: 2101 movs r1, #1 + 8002ba8: 5499 strb r1, [r3, r2] TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - 80022e6: 687b ldr r3, [r7, #4] - 80022e8: 2244 movs r2, #68 @ 0x44 - 80022ea: 2101 movs r1, #1 - 80022ec: 5499 strb r1, [r3, r2] - 80022ee: 687b ldr r3, [r7, #4] - 80022f0: 2245 movs r2, #69 @ 0x45 - 80022f2: 2101 movs r1, #1 - 80022f4: 5499 strb r1, [r3, r2] - 80022f6: 687b ldr r3, [r7, #4] - 80022f8: 2246 movs r2, #70 @ 0x46 - 80022fa: 2101 movs r1, #1 - 80022fc: 5499 strb r1, [r3, r2] - 80022fe: 687b ldr r3, [r7, #4] - 8002300: 2247 movs r2, #71 @ 0x47 - 8002302: 2101 movs r1, #1 - 8002304: 5499 strb r1, [r3, r2] + 8002baa: 687b ldr r3, [r7, #4] + 8002bac: 2244 movs r2, #68 @ 0x44 + 8002bae: 2101 movs r1, #1 + 8002bb0: 5499 strb r1, [r3, r2] + 8002bb2: 687b ldr r3, [r7, #4] + 8002bb4: 2245 movs r2, #69 @ 0x45 + 8002bb6: 2101 movs r1, #1 + 8002bb8: 5499 strb r1, [r3, r2] + 8002bba: 687b ldr r3, [r7, #4] + 8002bbc: 2246 movs r2, #70 @ 0x46 + 8002bbe: 2101 movs r1, #1 + 8002bc0: 5499 strb r1, [r3, r2] + 8002bc2: 687b ldr r3, [r7, #4] + 8002bc4: 2247 movs r2, #71 @ 0x47 + 8002bc6: 2101 movs r1, #1 + 8002bc8: 5499 strb r1, [r3, r2] /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; - 8002306: 687b ldr r3, [r7, #4] - 8002308: 223d movs r2, #61 @ 0x3d - 800230a: 2101 movs r1, #1 - 800230c: 5499 strb r1, [r3, r2] + 8002bca: 687b ldr r3, [r7, #4] + 8002bcc: 223d movs r2, #61 @ 0x3d + 8002bce: 2101 movs r1, #1 + 8002bd0: 5499 strb r1, [r3, r2] return HAL_OK; - 800230e: 2300 movs r3, #0 + 8002bd2: 2300 movs r3, #0 } - 8002310: 0018 movs r0, r3 - 8002312: 46bd mov sp, r7 - 8002314: b002 add sp, #8 - 8002316: bd80 pop {r7, pc} + 8002bd4: 0018 movs r0, r3 + 8002bd6: 46bd mov sp, r7 + 8002bd8: b002 add sp, #8 + 8002bda: bd80 pop {r7, pc} -08002318 : +08002bdc : * @brief Initializes the TIM PWM MSP. * @param htim TIM PWM handle * @retval None */ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) { - 8002318: b580 push {r7, lr} - 800231a: b082 sub sp, #8 - 800231c: af00 add r7, sp, #0 - 800231e: 6078 str r0, [r7, #4] + 8002bdc: b580 push {r7, lr} + 8002bde: b082 sub sp, #8 + 8002be0: af00 add r7, sp, #0 + 8002be2: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_MspInit could be implemented in the user file */ } - 8002320: 46c0 nop @ (mov r8, r8) - 8002322: 46bd mov sp, r7 - 8002324: b002 add sp, #8 - 8002326: bd80 pop {r7, pc} + 8002be4: 46c0 nop @ (mov r8, r8) + 8002be6: 46bd mov sp, r7 + 8002be8: b002 add sp, #8 + 8002bea: bd80 pop {r7, pc} -08002328 : +08002bec : * @param htim TIM Encoder Interface handle * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig) { - 8002328: b580 push {r7, lr} - 800232a: b086 sub sp, #24 - 800232c: af00 add r7, sp, #0 - 800232e: 6078 str r0, [r7, #4] - 8002330: 6039 str r1, [r7, #0] + 8002bec: b580 push {r7, lr} + 8002bee: b086 sub sp, #24 + 8002bf0: af00 add r7, sp, #0 + 8002bf2: 6078 str r0, [r7, #4] + 8002bf4: 6039 str r1, [r7, #0] uint32_t tmpsmcr; uint32_t tmpccmr1; uint32_t tmpccer; /* Check the TIM handle allocation */ if (htim == NULL) - 8002332: 687b ldr r3, [r7, #4] - 8002334: 2b00 cmp r3, #0 - 8002336: d101 bne.n 800233c + 8002bf6: 687b ldr r3, [r7, #4] + 8002bf8: 2b00 cmp r3, #0 + 8002bfa: d101 bne.n 8002c00 { return HAL_ERROR; - 8002338: 2301 movs r3, #1 - 800233a: e090 b.n 800245e + 8002bfc: 2301 movs r3, #1 + 8002bfe: e090 b.n 8002d22 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); if (htim->State == HAL_TIM_STATE_RESET) - 800233c: 687b ldr r3, [r7, #4] - 800233e: 223d movs r2, #61 @ 0x3d - 8002340: 5c9b ldrb r3, [r3, r2] - 8002342: b2db uxtb r3, r3 - 8002344: 2b00 cmp r3, #0 - 8002346: d107 bne.n 8002358 + 8002c00: 687b ldr r3, [r7, #4] + 8002c02: 223d movs r2, #61 @ 0x3d + 8002c04: 5c9b ldrb r3, [r3, r2] + 8002c06: b2db uxtb r3, r3 + 8002c08: 2b00 cmp r3, #0 + 8002c0a: d107 bne.n 8002c1c { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; - 8002348: 687b ldr r3, [r7, #4] - 800234a: 223c movs r2, #60 @ 0x3c - 800234c: 2100 movs r1, #0 - 800234e: 5499 strb r1, [r3, r2] + 8002c0c: 687b ldr r3, [r7, #4] + 8002c0e: 223c movs r2, #60 @ 0x3c + 8002c10: 2100 movs r1, #0 + 8002c12: 5499 strb r1, [r3, r2] } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Encoder_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_Encoder_MspInit(htim); - 8002350: 687b ldr r3, [r7, #4] - 8002352: 0018 movs r0, r3 - 8002354: f7fe fc34 bl 8000bc0 + 8002c14: 687b ldr r3, [r7, #4] + 8002c16: 0018 movs r0, r3 + 8002c18: f7fe faea bl 80011f0 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; - 8002358: 687b ldr r3, [r7, #4] - 800235a: 223d movs r2, #61 @ 0x3d - 800235c: 2102 movs r1, #2 - 800235e: 5499 strb r1, [r3, r2] + 8002c1c: 687b ldr r3, [r7, #4] + 8002c1e: 223d movs r2, #61 @ 0x3d + 8002c20: 2102 movs r1, #2 + 8002c22: 5499 strb r1, [r3, r2] /* Reset the SMS and ECE bits */ htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); - 8002360: 687b ldr r3, [r7, #4] - 8002362: 681b ldr r3, [r3, #0] - 8002364: 689a ldr r2, [r3, #8] - 8002366: 687b ldr r3, [r7, #4] - 8002368: 681b ldr r3, [r3, #0] - 800236a: 493f ldr r1, [pc, #252] @ (8002468 ) - 800236c: 400a ands r2, r1 - 800236e: 609a str r2, [r3, #8] + 8002c24: 687b ldr r3, [r7, #4] + 8002c26: 681b ldr r3, [r3, #0] + 8002c28: 689a ldr r2, [r3, #8] + 8002c2a: 687b ldr r3, [r7, #4] + 8002c2c: 681b ldr r3, [r3, #0] + 8002c2e: 493f ldr r1, [pc, #252] @ (8002d2c ) + 8002c30: 400a ands r2, r1 + 8002c32: 609a str r2, [r3, #8] /* Configure the Time base in the Encoder Mode */ TIM_Base_SetConfig(htim->Instance, &htim->Init); - 8002370: 687b ldr r3, [r7, #4] - 8002372: 681a ldr r2, [r3, #0] - 8002374: 687b ldr r3, [r7, #4] - 8002376: 3304 adds r3, #4 - 8002378: 0019 movs r1, r3 - 800237a: 0010 movs r0, r2 - 800237c: f000 fb7a bl 8002a74 + 8002c34: 687b ldr r3, [r7, #4] + 8002c36: 681a ldr r2, [r3, #0] + 8002c38: 687b ldr r3, [r7, #4] + 8002c3a: 3304 adds r3, #4 + 8002c3c: 0019 movs r1, r3 + 8002c3e: 0010 movs r0, r2 + 8002c40: f000 fb7a bl 8003338 /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; - 8002380: 687b ldr r3, [r7, #4] - 8002382: 681b ldr r3, [r3, #0] - 8002384: 689b ldr r3, [r3, #8] - 8002386: 617b str r3, [r7, #20] + 8002c44: 687b ldr r3, [r7, #4] + 8002c46: 681b ldr r3, [r3, #0] + 8002c48: 689b ldr r3, [r3, #8] + 8002c4a: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmr1 = htim->Instance->CCMR1; - 8002388: 687b ldr r3, [r7, #4] - 800238a: 681b ldr r3, [r3, #0] - 800238c: 699b ldr r3, [r3, #24] - 800238e: 613b str r3, [r7, #16] + 8002c4c: 687b ldr r3, [r7, #4] + 8002c4e: 681b ldr r3, [r3, #0] + 8002c50: 699b ldr r3, [r3, #24] + 8002c52: 613b str r3, [r7, #16] /* Get the TIMx CCER register value */ tmpccer = htim->Instance->CCER; - 8002390: 687b ldr r3, [r7, #4] - 8002392: 681b ldr r3, [r3, #0] - 8002394: 6a1b ldr r3, [r3, #32] - 8002396: 60fb str r3, [r7, #12] + 8002c54: 687b ldr r3, [r7, #4] + 8002c56: 681b ldr r3, [r3, #0] + 8002c58: 6a1b ldr r3, [r3, #32] + 8002c5a: 60fb str r3, [r7, #12] /* Set the encoder Mode */ tmpsmcr |= sConfig->EncoderMode; - 8002398: 683b ldr r3, [r7, #0] - 800239a: 681b ldr r3, [r3, #0] - 800239c: 697a ldr r2, [r7, #20] - 800239e: 4313 orrs r3, r2 - 80023a0: 617b str r3, [r7, #20] + 8002c5c: 683b ldr r3, [r7, #0] + 8002c5e: 681b ldr r3, [r3, #0] + 8002c60: 697a ldr r2, [r7, #20] + 8002c62: 4313 orrs r3, r2 + 8002c64: 617b str r3, [r7, #20] /* Select the Capture Compare 1 and the Capture Compare 2 as input */ tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); - 80023a2: 693b ldr r3, [r7, #16] - 80023a4: 4a31 ldr r2, [pc, #196] @ (800246c ) - 80023a6: 4013 ands r3, r2 - 80023a8: 613b str r3, [r7, #16] + 8002c66: 693b ldr r3, [r7, #16] + 8002c68: 4a31 ldr r2, [pc, #196] @ (8002d30 ) + 8002c6a: 4013 ands r3, r2 + 8002c6c: 613b str r3, [r7, #16] tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); - 80023aa: 683b ldr r3, [r7, #0] - 80023ac: 689a ldr r2, [r3, #8] - 80023ae: 683b ldr r3, [r7, #0] - 80023b0: 699b ldr r3, [r3, #24] - 80023b2: 021b lsls r3, r3, #8 - 80023b4: 4313 orrs r3, r2 - 80023b6: 693a ldr r2, [r7, #16] - 80023b8: 4313 orrs r3, r2 - 80023ba: 613b str r3, [r7, #16] + 8002c6e: 683b ldr r3, [r7, #0] + 8002c70: 689a ldr r2, [r3, #8] + 8002c72: 683b ldr r3, [r7, #0] + 8002c74: 699b ldr r3, [r3, #24] + 8002c76: 021b lsls r3, r3, #8 + 8002c78: 4313 orrs r3, r2 + 8002c7a: 693a ldr r2, [r7, #16] + 8002c7c: 4313 orrs r3, r2 + 8002c7e: 613b str r3, [r7, #16] /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); - 80023bc: 693b ldr r3, [r7, #16] - 80023be: 4a2c ldr r2, [pc, #176] @ (8002470 ) - 80023c0: 4013 ands r3, r2 - 80023c2: 613b str r3, [r7, #16] + 8002c80: 693b ldr r3, [r7, #16] + 8002c82: 4a2c ldr r2, [pc, #176] @ (8002d34 ) + 8002c84: 4013 ands r3, r2 + 8002c86: 613b str r3, [r7, #16] tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); - 80023c4: 693b ldr r3, [r7, #16] - 80023c6: 4a2b ldr r2, [pc, #172] @ (8002474 ) - 80023c8: 4013 ands r3, r2 - 80023ca: 613b str r3, [r7, #16] + 8002c88: 693b ldr r3, [r7, #16] + 8002c8a: 4a2b ldr r2, [pc, #172] @ (8002d38 ) + 8002c8c: 4013 ands r3, r2 + 8002c8e: 613b str r3, [r7, #16] tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); - 80023cc: 683b ldr r3, [r7, #0] - 80023ce: 68da ldr r2, [r3, #12] - 80023d0: 683b ldr r3, [r7, #0] - 80023d2: 69db ldr r3, [r3, #28] - 80023d4: 021b lsls r3, r3, #8 - 80023d6: 4313 orrs r3, r2 - 80023d8: 693a ldr r2, [r7, #16] - 80023da: 4313 orrs r3, r2 - 80023dc: 613b str r3, [r7, #16] + 8002c90: 683b ldr r3, [r7, #0] + 8002c92: 68da ldr r2, [r3, #12] + 8002c94: 683b ldr r3, [r7, #0] + 8002c96: 69db ldr r3, [r3, #28] + 8002c98: 021b lsls r3, r3, #8 + 8002c9a: 4313 orrs r3, r2 + 8002c9c: 693a ldr r2, [r7, #16] + 8002c9e: 4313 orrs r3, r2 + 8002ca0: 613b str r3, [r7, #16] tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); - 80023de: 683b ldr r3, [r7, #0] - 80023e0: 691b ldr r3, [r3, #16] - 80023e2: 011a lsls r2, r3, #4 - 80023e4: 683b ldr r3, [r7, #0] - 80023e6: 6a1b ldr r3, [r3, #32] - 80023e8: 031b lsls r3, r3, #12 - 80023ea: 4313 orrs r3, r2 - 80023ec: 693a ldr r2, [r7, #16] - 80023ee: 4313 orrs r3, r2 - 80023f0: 613b str r3, [r7, #16] + 8002ca2: 683b ldr r3, [r7, #0] + 8002ca4: 691b ldr r3, [r3, #16] + 8002ca6: 011a lsls r2, r3, #4 + 8002ca8: 683b ldr r3, [r7, #0] + 8002caa: 6a1b ldr r3, [r3, #32] + 8002cac: 031b lsls r3, r3, #12 + 8002cae: 4313 orrs r3, r2 + 8002cb0: 693a ldr r2, [r7, #16] + 8002cb2: 4313 orrs r3, r2 + 8002cb4: 613b str r3, [r7, #16] /* Set the TI1 and the TI2 Polarities */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); - 80023f2: 68fb ldr r3, [r7, #12] - 80023f4: 2222 movs r2, #34 @ 0x22 - 80023f6: 4393 bics r3, r2 - 80023f8: 60fb str r3, [r7, #12] + 8002cb6: 68fb ldr r3, [r7, #12] + 8002cb8: 2222 movs r2, #34 @ 0x22 + 8002cba: 4393 bics r3, r2 + 8002cbc: 60fb str r3, [r7, #12] tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); - 80023fa: 68fb ldr r3, [r7, #12] - 80023fc: 2288 movs r2, #136 @ 0x88 - 80023fe: 4393 bics r3, r2 - 8002400: 60fb str r3, [r7, #12] + 8002cbe: 68fb ldr r3, [r7, #12] + 8002cc0: 2288 movs r2, #136 @ 0x88 + 8002cc2: 4393 bics r3, r2 + 8002cc4: 60fb str r3, [r7, #12] tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); - 8002402: 683b ldr r3, [r7, #0] - 8002404: 685a ldr r2, [r3, #4] - 8002406: 683b ldr r3, [r7, #0] - 8002408: 695b ldr r3, [r3, #20] - 800240a: 011b lsls r3, r3, #4 - 800240c: 4313 orrs r3, r2 - 800240e: 68fa ldr r2, [r7, #12] - 8002410: 4313 orrs r3, r2 - 8002412: 60fb str r3, [r7, #12] + 8002cc6: 683b ldr r3, [r7, #0] + 8002cc8: 685a ldr r2, [r3, #4] + 8002cca: 683b ldr r3, [r7, #0] + 8002ccc: 695b ldr r3, [r3, #20] + 8002cce: 011b lsls r3, r3, #4 + 8002cd0: 4313 orrs r3, r2 + 8002cd2: 68fa ldr r2, [r7, #12] + 8002cd4: 4313 orrs r3, r2 + 8002cd6: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; - 8002414: 687b ldr r3, [r7, #4] - 8002416: 681b ldr r3, [r3, #0] - 8002418: 697a ldr r2, [r7, #20] - 800241a: 609a str r2, [r3, #8] + 8002cd8: 687b ldr r3, [r7, #4] + 8002cda: 681b ldr r3, [r3, #0] + 8002cdc: 697a ldr r2, [r7, #20] + 8002cde: 609a str r2, [r3, #8] /* Write to TIMx CCMR1 */ htim->Instance->CCMR1 = tmpccmr1; - 800241c: 687b ldr r3, [r7, #4] - 800241e: 681b ldr r3, [r3, #0] - 8002420: 693a ldr r2, [r7, #16] - 8002422: 619a str r2, [r3, #24] + 8002ce0: 687b ldr r3, [r7, #4] + 8002ce2: 681b ldr r3, [r3, #0] + 8002ce4: 693a ldr r2, [r7, #16] + 8002ce6: 619a str r2, [r3, #24] /* Write to TIMx CCER */ htim->Instance->CCER = tmpccer; - 8002424: 687b ldr r3, [r7, #4] - 8002426: 681b ldr r3, [r3, #0] - 8002428: 68fa ldr r2, [r7, #12] - 800242a: 621a str r2, [r3, #32] + 8002ce8: 687b ldr r3, [r7, #4] + 8002cea: 681b ldr r3, [r3, #0] + 8002cec: 68fa ldr r2, [r7, #12] + 8002cee: 621a str r2, [r3, #32] /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - 800242c: 687b ldr r3, [r7, #4] - 800242e: 2248 movs r2, #72 @ 0x48 - 8002430: 2101 movs r1, #1 - 8002432: 5499 strb r1, [r3, r2] + 8002cf0: 687b ldr r3, [r7, #4] + 8002cf2: 2248 movs r2, #72 @ 0x48 + 8002cf4: 2101 movs r1, #1 + 8002cf6: 5499 strb r1, [r3, r2] /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - 8002434: 687b ldr r3, [r7, #4] - 8002436: 223e movs r2, #62 @ 0x3e - 8002438: 2101 movs r1, #1 - 800243a: 5499 strb r1, [r3, r2] + 8002cf8: 687b ldr r3, [r7, #4] + 8002cfa: 223e movs r2, #62 @ 0x3e + 8002cfc: 2101 movs r1, #1 + 8002cfe: 5499 strb r1, [r3, r2] TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - 800243c: 687b ldr r3, [r7, #4] - 800243e: 223f movs r2, #63 @ 0x3f - 8002440: 2101 movs r1, #1 - 8002442: 5499 strb r1, [r3, r2] + 8002d00: 687b ldr r3, [r7, #4] + 8002d02: 223f movs r2, #63 @ 0x3f + 8002d04: 2101 movs r1, #1 + 8002d06: 5499 strb r1, [r3, r2] TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - 8002444: 687b ldr r3, [r7, #4] - 8002446: 2244 movs r2, #68 @ 0x44 - 8002448: 2101 movs r1, #1 - 800244a: 5499 strb r1, [r3, r2] + 8002d08: 687b ldr r3, [r7, #4] + 8002d0a: 2244 movs r2, #68 @ 0x44 + 8002d0c: 2101 movs r1, #1 + 8002d0e: 5499 strb r1, [r3, r2] TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - 800244c: 687b ldr r3, [r7, #4] - 800244e: 2245 movs r2, #69 @ 0x45 - 8002450: 2101 movs r1, #1 - 8002452: 5499 strb r1, [r3, r2] + 8002d10: 687b ldr r3, [r7, #4] + 8002d12: 2245 movs r2, #69 @ 0x45 + 8002d14: 2101 movs r1, #1 + 8002d16: 5499 strb r1, [r3, r2] /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; - 8002454: 687b ldr r3, [r7, #4] - 8002456: 223d movs r2, #61 @ 0x3d - 8002458: 2101 movs r1, #1 - 800245a: 5499 strb r1, [r3, r2] + 8002d18: 687b ldr r3, [r7, #4] + 8002d1a: 223d movs r2, #61 @ 0x3d + 8002d1c: 2101 movs r1, #1 + 8002d1e: 5499 strb r1, [r3, r2] return HAL_OK; - 800245c: 2300 movs r3, #0 + 8002d20: 2300 movs r3, #0 } - 800245e: 0018 movs r0, r3 - 8002460: 46bd mov sp, r7 - 8002462: b006 add sp, #24 - 8002464: bd80 pop {r7, pc} - 8002466: 46c0 nop @ (mov r8, r8) - 8002468: fffebff8 .word 0xfffebff8 - 800246c: fffffcfc .word 0xfffffcfc - 8002470: fffff3f3 .word 0xfffff3f3 - 8002474: ffff0f0f .word 0xffff0f0f + 8002d22: 0018 movs r0, r3 + 8002d24: 46bd mov sp, r7 + 8002d26: b006 add sp, #24 + 8002d28: bd80 pop {r7, pc} + 8002d2a: 46c0 nop @ (mov r8, r8) + 8002d2c: fffebff8 .word 0xfffebff8 + 8002d30: fffffcfc .word 0xfffffcfc + 8002d34: fffff3f3 .word 0xfffff3f3 + 8002d38: ffff0f0f .word 0xffff0f0f -08002478 : +08002d3c : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { - 8002478: b580 push {r7, lr} - 800247a: b084 sub sp, #16 - 800247c: af00 add r7, sp, #0 - 800247e: 6078 str r0, [r7, #4] + 8002d3c: b580 push {r7, lr} + 8002d3e: b084 sub sp, #16 + 8002d40: af00 add r7, sp, #0 + 8002d42: 6078 str r0, [r7, #4] uint32_t itsource = htim->Instance->DIER; - 8002480: 687b ldr r3, [r7, #4] - 8002482: 681b ldr r3, [r3, #0] - 8002484: 68db ldr r3, [r3, #12] - 8002486: 60fb str r3, [r7, #12] + 8002d44: 687b ldr r3, [r7, #4] + 8002d46: 681b ldr r3, [r3, #0] + 8002d48: 68db ldr r3, [r3, #12] + 8002d4a: 60fb str r3, [r7, #12] uint32_t itflag = htim->Instance->SR; - 8002488: 687b ldr r3, [r7, #4] - 800248a: 681b ldr r3, [r3, #0] - 800248c: 691b ldr r3, [r3, #16] - 800248e: 60bb str r3, [r7, #8] + 8002d4c: 687b ldr r3, [r7, #4] + 8002d4e: 681b ldr r3, [r3, #0] + 8002d50: 691b ldr r3, [r3, #16] + 8002d52: 60bb str r3, [r7, #8] /* Capture compare 1 event */ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) - 8002490: 68bb ldr r3, [r7, #8] - 8002492: 2202 movs r2, #2 - 8002494: 4013 ands r3, r2 - 8002496: d021 beq.n 80024dc + 8002d54: 68bb ldr r3, [r7, #8] + 8002d56: 2202 movs r2, #2 + 8002d58: 4013 ands r3, r2 + 8002d5a: d021 beq.n 8002da0 { if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) - 8002498: 68fb ldr r3, [r7, #12] - 800249a: 2202 movs r2, #2 - 800249c: 4013 ands r3, r2 - 800249e: d01d beq.n 80024dc + 8002d5c: 68fb ldr r3, [r7, #12] + 8002d5e: 2202 movs r2, #2 + 8002d60: 4013 ands r3, r2 + 8002d62: d01d beq.n 8002da0 { { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); - 80024a0: 687b ldr r3, [r7, #4] - 80024a2: 681b ldr r3, [r3, #0] - 80024a4: 2203 movs r2, #3 - 80024a6: 4252 negs r2, r2 - 80024a8: 611a str r2, [r3, #16] + 8002d64: 687b ldr r3, [r7, #4] + 8002d66: 681b ldr r3, [r3, #0] + 8002d68: 2203 movs r2, #3 + 8002d6a: 4252 negs r2, r2 + 8002d6c: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - 80024aa: 687b ldr r3, [r7, #4] - 80024ac: 2201 movs r2, #1 - 80024ae: 771a strb r2, [r3, #28] + 8002d6e: 687b ldr r3, [r7, #4] + 8002d70: 2201 movs r2, #1 + 8002d72: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) - 80024b0: 687b ldr r3, [r7, #4] - 80024b2: 681b ldr r3, [r3, #0] - 80024b4: 699b ldr r3, [r3, #24] - 80024b6: 2203 movs r2, #3 - 80024b8: 4013 ands r3, r2 - 80024ba: d004 beq.n 80024c6 + 8002d74: 687b ldr r3, [r7, #4] + 8002d76: 681b ldr r3, [r3, #0] + 8002d78: 699b ldr r3, [r3, #24] + 8002d7a: 2203 movs r2, #3 + 8002d7c: 4013 ands r3, r2 + 8002d7e: d004 beq.n 8002d8a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); - 80024bc: 687b ldr r3, [r7, #4] - 80024be: 0018 movs r0, r3 - 80024c0: f000 fac0 bl 8002a44 - 80024c4: e007 b.n 80024d6 + 8002d80: 687b ldr r3, [r7, #4] + 8002d82: 0018 movs r0, r3 + 8002d84: f000 fac0 bl 8003308 + 8002d88: e007 b.n 8002d9a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); - 80024c6: 687b ldr r3, [r7, #4] - 80024c8: 0018 movs r0, r3 - 80024ca: f000 fab3 bl 8002a34 + 8002d8a: 687b ldr r3, [r7, #4] + 8002d8c: 0018 movs r0, r3 + 8002d8e: f000 fab3 bl 80032f8 HAL_TIM_PWM_PulseFinishedCallback(htim); - 80024ce: 687b ldr r3, [r7, #4] - 80024d0: 0018 movs r0, r3 - 80024d2: f000 fabf bl 8002a54 + 8002d92: 687b ldr r3, [r7, #4] + 8002d94: 0018 movs r0, r3 + 8002d96: f000 fabf bl 8003318 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - 80024d6: 687b ldr r3, [r7, #4] - 80024d8: 2200 movs r2, #0 - 80024da: 771a strb r2, [r3, #28] + 8002d9a: 687b ldr r3, [r7, #4] + 8002d9c: 2200 movs r2, #0 + 8002d9e: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) - 80024dc: 68bb ldr r3, [r7, #8] - 80024de: 2204 movs r2, #4 - 80024e0: 4013 ands r3, r2 - 80024e2: d022 beq.n 800252a + 8002da0: 68bb ldr r3, [r7, #8] + 8002da2: 2204 movs r2, #4 + 8002da4: 4013 ands r3, r2 + 8002da6: d022 beq.n 8002dee { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) - 80024e4: 68fb ldr r3, [r7, #12] - 80024e6: 2204 movs r2, #4 - 80024e8: 4013 ands r3, r2 - 80024ea: d01e beq.n 800252a + 8002da8: 68fb ldr r3, [r7, #12] + 8002daa: 2204 movs r2, #4 + 8002dac: 4013 ands r3, r2 + 8002dae: d01e beq.n 8002dee { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); - 80024ec: 687b ldr r3, [r7, #4] - 80024ee: 681b ldr r3, [r3, #0] - 80024f0: 2205 movs r2, #5 - 80024f2: 4252 negs r2, r2 - 80024f4: 611a str r2, [r3, #16] + 8002db0: 687b ldr r3, [r7, #4] + 8002db2: 681b ldr r3, [r3, #0] + 8002db4: 2205 movs r2, #5 + 8002db6: 4252 negs r2, r2 + 8002db8: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - 80024f6: 687b ldr r3, [r7, #4] - 80024f8: 2202 movs r2, #2 - 80024fa: 771a strb r2, [r3, #28] + 8002dba: 687b ldr r3, [r7, #4] + 8002dbc: 2202 movs r2, #2 + 8002dbe: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) - 80024fc: 687b ldr r3, [r7, #4] - 80024fe: 681b ldr r3, [r3, #0] - 8002500: 699a ldr r2, [r3, #24] - 8002502: 23c0 movs r3, #192 @ 0xc0 - 8002504: 009b lsls r3, r3, #2 - 8002506: 4013 ands r3, r2 - 8002508: d004 beq.n 8002514 + 8002dc0: 687b ldr r3, [r7, #4] + 8002dc2: 681b ldr r3, [r3, #0] + 8002dc4: 699a ldr r2, [r3, #24] + 8002dc6: 23c0 movs r3, #192 @ 0xc0 + 8002dc8: 009b lsls r3, r3, #2 + 8002dca: 4013 ands r3, r2 + 8002dcc: d004 beq.n 8002dd8 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); - 800250a: 687b ldr r3, [r7, #4] - 800250c: 0018 movs r0, r3 - 800250e: f000 fa99 bl 8002a44 - 8002512: e007 b.n 8002524 + 8002dce: 687b ldr r3, [r7, #4] + 8002dd0: 0018 movs r0, r3 + 8002dd2: f000 fa99 bl 8003308 + 8002dd6: e007 b.n 8002de8 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); - 8002514: 687b ldr r3, [r7, #4] - 8002516: 0018 movs r0, r3 - 8002518: f000 fa8c bl 8002a34 + 8002dd8: 687b ldr r3, [r7, #4] + 8002dda: 0018 movs r0, r3 + 8002ddc: f000 fa8c bl 80032f8 HAL_TIM_PWM_PulseFinishedCallback(htim); - 800251c: 687b ldr r3, [r7, #4] - 800251e: 0018 movs r0, r3 - 8002520: f000 fa98 bl 8002a54 + 8002de0: 687b ldr r3, [r7, #4] + 8002de2: 0018 movs r0, r3 + 8002de4: f000 fa98 bl 8003318 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - 8002524: 687b ldr r3, [r7, #4] - 8002526: 2200 movs r2, #0 - 8002528: 771a strb r2, [r3, #28] + 8002de8: 687b ldr r3, [r7, #4] + 8002dea: 2200 movs r2, #0 + 8002dec: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) - 800252a: 68bb ldr r3, [r7, #8] - 800252c: 2208 movs r2, #8 - 800252e: 4013 ands r3, r2 - 8002530: d021 beq.n 8002576 + 8002dee: 68bb ldr r3, [r7, #8] + 8002df0: 2208 movs r2, #8 + 8002df2: 4013 ands r3, r2 + 8002df4: d021 beq.n 8002e3a { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) - 8002532: 68fb ldr r3, [r7, #12] - 8002534: 2208 movs r2, #8 - 8002536: 4013 ands r3, r2 - 8002538: d01d beq.n 8002576 + 8002df6: 68fb ldr r3, [r7, #12] + 8002df8: 2208 movs r2, #8 + 8002dfa: 4013 ands r3, r2 + 8002dfc: d01d beq.n 8002e3a { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); - 800253a: 687b ldr r3, [r7, #4] - 800253c: 681b ldr r3, [r3, #0] - 800253e: 2209 movs r2, #9 - 8002540: 4252 negs r2, r2 - 8002542: 611a str r2, [r3, #16] + 8002dfe: 687b ldr r3, [r7, #4] + 8002e00: 681b ldr r3, [r3, #0] + 8002e02: 2209 movs r2, #9 + 8002e04: 4252 negs r2, r2 + 8002e06: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - 8002544: 687b ldr r3, [r7, #4] - 8002546: 2204 movs r2, #4 - 8002548: 771a strb r2, [r3, #28] + 8002e08: 687b ldr r3, [r7, #4] + 8002e0a: 2204 movs r2, #4 + 8002e0c: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) - 800254a: 687b ldr r3, [r7, #4] - 800254c: 681b ldr r3, [r3, #0] - 800254e: 69db ldr r3, [r3, #28] - 8002550: 2203 movs r2, #3 - 8002552: 4013 ands r3, r2 - 8002554: d004 beq.n 8002560 + 8002e0e: 687b ldr r3, [r7, #4] + 8002e10: 681b ldr r3, [r3, #0] + 8002e12: 69db ldr r3, [r3, #28] + 8002e14: 2203 movs r2, #3 + 8002e16: 4013 ands r3, r2 + 8002e18: d004 beq.n 8002e24 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); - 8002556: 687b ldr r3, [r7, #4] - 8002558: 0018 movs r0, r3 - 800255a: f000 fa73 bl 8002a44 - 800255e: e007 b.n 8002570 + 8002e1a: 687b ldr r3, [r7, #4] + 8002e1c: 0018 movs r0, r3 + 8002e1e: f000 fa73 bl 8003308 + 8002e22: e007 b.n 8002e34 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); - 8002560: 687b ldr r3, [r7, #4] - 8002562: 0018 movs r0, r3 - 8002564: f000 fa66 bl 8002a34 + 8002e24: 687b ldr r3, [r7, #4] + 8002e26: 0018 movs r0, r3 + 8002e28: f000 fa66 bl 80032f8 HAL_TIM_PWM_PulseFinishedCallback(htim); - 8002568: 687b ldr r3, [r7, #4] - 800256a: 0018 movs r0, r3 - 800256c: f000 fa72 bl 8002a54 + 8002e2c: 687b ldr r3, [r7, #4] + 8002e2e: 0018 movs r0, r3 + 8002e30: f000 fa72 bl 8003318 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - 8002570: 687b ldr r3, [r7, #4] - 8002572: 2200 movs r2, #0 - 8002574: 771a strb r2, [r3, #28] + 8002e34: 687b ldr r3, [r7, #4] + 8002e36: 2200 movs r2, #0 + 8002e38: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) - 8002576: 68bb ldr r3, [r7, #8] - 8002578: 2210 movs r2, #16 - 800257a: 4013 ands r3, r2 - 800257c: d022 beq.n 80025c4 + 8002e3a: 68bb ldr r3, [r7, #8] + 8002e3c: 2210 movs r2, #16 + 8002e3e: 4013 ands r3, r2 + 8002e40: d022 beq.n 8002e88 { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) - 800257e: 68fb ldr r3, [r7, #12] - 8002580: 2210 movs r2, #16 - 8002582: 4013 ands r3, r2 - 8002584: d01e beq.n 80025c4 + 8002e42: 68fb ldr r3, [r7, #12] + 8002e44: 2210 movs r2, #16 + 8002e46: 4013 ands r3, r2 + 8002e48: d01e beq.n 8002e88 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); - 8002586: 687b ldr r3, [r7, #4] - 8002588: 681b ldr r3, [r3, #0] - 800258a: 2211 movs r2, #17 - 800258c: 4252 negs r2, r2 - 800258e: 611a str r2, [r3, #16] + 8002e4a: 687b ldr r3, [r7, #4] + 8002e4c: 681b ldr r3, [r3, #0] + 8002e4e: 2211 movs r2, #17 + 8002e50: 4252 negs r2, r2 + 8002e52: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - 8002590: 687b ldr r3, [r7, #4] - 8002592: 2208 movs r2, #8 - 8002594: 771a strb r2, [r3, #28] + 8002e54: 687b ldr r3, [r7, #4] + 8002e56: 2208 movs r2, #8 + 8002e58: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) - 8002596: 687b ldr r3, [r7, #4] - 8002598: 681b ldr r3, [r3, #0] - 800259a: 69da ldr r2, [r3, #28] - 800259c: 23c0 movs r3, #192 @ 0xc0 - 800259e: 009b lsls r3, r3, #2 - 80025a0: 4013 ands r3, r2 - 80025a2: d004 beq.n 80025ae + 8002e5a: 687b ldr r3, [r7, #4] + 8002e5c: 681b ldr r3, [r3, #0] + 8002e5e: 69da ldr r2, [r3, #28] + 8002e60: 23c0 movs r3, #192 @ 0xc0 + 8002e62: 009b lsls r3, r3, #2 + 8002e64: 4013 ands r3, r2 + 8002e66: d004 beq.n 8002e72 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); - 80025a4: 687b ldr r3, [r7, #4] - 80025a6: 0018 movs r0, r3 - 80025a8: f000 fa4c bl 8002a44 - 80025ac: e007 b.n 80025be + 8002e68: 687b ldr r3, [r7, #4] + 8002e6a: 0018 movs r0, r3 + 8002e6c: f000 fa4c bl 8003308 + 8002e70: e007 b.n 8002e82 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); - 80025ae: 687b ldr r3, [r7, #4] - 80025b0: 0018 movs r0, r3 - 80025b2: f000 fa3f bl 8002a34 + 8002e72: 687b ldr r3, [r7, #4] + 8002e74: 0018 movs r0, r3 + 8002e76: f000 fa3f bl 80032f8 HAL_TIM_PWM_PulseFinishedCallback(htim); - 80025b6: 687b ldr r3, [r7, #4] - 80025b8: 0018 movs r0, r3 - 80025ba: f000 fa4b bl 8002a54 + 8002e7a: 687b ldr r3, [r7, #4] + 8002e7c: 0018 movs r0, r3 + 8002e7e: f000 fa4b bl 8003318 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - 80025be: 687b ldr r3, [r7, #4] - 80025c0: 2200 movs r2, #0 - 80025c2: 771a strb r2, [r3, #28] + 8002e82: 687b ldr r3, [r7, #4] + 8002e84: 2200 movs r2, #0 + 8002e86: 771a strb r2, [r3, #28] } } /* TIM Update event */ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) - 80025c4: 68bb ldr r3, [r7, #8] - 80025c6: 2201 movs r2, #1 - 80025c8: 4013 ands r3, r2 - 80025ca: d00c beq.n 80025e6 + 8002e88: 68bb ldr r3, [r7, #8] + 8002e8a: 2201 movs r2, #1 + 8002e8c: 4013 ands r3, r2 + 8002e8e: d00c beq.n 8002eaa { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) - 80025cc: 68fb ldr r3, [r7, #12] - 80025ce: 2201 movs r2, #1 - 80025d0: 4013 ands r3, r2 - 80025d2: d008 beq.n 80025e6 + 8002e90: 68fb ldr r3, [r7, #12] + 8002e92: 2201 movs r2, #1 + 8002e94: 4013 ands r3, r2 + 8002e96: d008 beq.n 8002eaa { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); - 80025d4: 687b ldr r3, [r7, #4] - 80025d6: 681b ldr r3, [r3, #0] - 80025d8: 2202 movs r2, #2 - 80025da: 4252 negs r2, r2 - 80025dc: 611a str r2, [r3, #16] + 8002e98: 687b ldr r3, [r7, #4] + 8002e9a: 681b ldr r3, [r3, #0] + 8002e9c: 2202 movs r2, #2 + 8002e9e: 4252 negs r2, r2 + 8002ea0: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); - 80025de: 687b ldr r3, [r7, #4] - 80025e0: 0018 movs r0, r3 - 80025e2: f7fe fa5f bl 8000aa4 + 8002ea2: 687b ldr r3, [r7, #4] + 8002ea4: 0018 movs r0, r3 + 8002ea6: f7fe f81b bl 8000ee0 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ - 80025e6: 68bb ldr r3, [r7, #8] - 80025e8: 2280 movs r2, #128 @ 0x80 - 80025ea: 4013 ands r3, r2 - 80025ec: d104 bne.n 80025f8 + 8002eaa: 68bb ldr r3, [r7, #8] + 8002eac: 2280 movs r2, #128 @ 0x80 + 8002eae: 4013 ands r3, r2 + 8002eb0: d104 bne.n 8002ebc ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK))) - 80025ee: 68ba ldr r2, [r7, #8] - 80025f0: 2380 movs r3, #128 @ 0x80 - 80025f2: 019b lsls r3, r3, #6 - 80025f4: 4013 ands r3, r2 + 8002eb2: 68ba ldr r2, [r7, #8] + 8002eb4: 2380 movs r3, #128 @ 0x80 + 8002eb6: 019b lsls r3, r3, #6 + 8002eb8: 4013 ands r3, r2 if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ - 80025f6: d00b beq.n 8002610 + 8002eba: d00b beq.n 8002ed4 { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) - 80025f8: 68fb ldr r3, [r7, #12] - 80025fa: 2280 movs r2, #128 @ 0x80 - 80025fc: 4013 ands r3, r2 - 80025fe: d007 beq.n 8002610 + 8002ebc: 68fb ldr r3, [r7, #12] + 8002ebe: 2280 movs r2, #128 @ 0x80 + 8002ec0: 4013 ands r3, r2 + 8002ec2: d007 beq.n 8002ed4 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK); - 8002600: 687b ldr r3, [r7, #4] - 8002602: 681b ldr r3, [r3, #0] - 8002604: 4a1e ldr r2, [pc, #120] @ (8002680 ) - 8002606: 611a str r2, [r3, #16] + 8002ec4: 687b ldr r3, [r7, #4] + 8002ec6: 681b ldr r3, [r3, #0] + 8002ec8: 4a1e ldr r2, [pc, #120] @ (8002f44 ) + 8002eca: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); - 8002608: 687b ldr r3, [r7, #4] - 800260a: 0018 movs r0, r3 - 800260c: f000 fef2 bl 80033f4 + 8002ecc: 687b ldr r3, [r7, #4] + 8002ece: 0018 movs r0, r3 + 8002ed0: f000 fef2 bl 8003cb8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break2 input event */ if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) - 8002610: 68ba ldr r2, [r7, #8] - 8002612: 2380 movs r3, #128 @ 0x80 - 8002614: 005b lsls r3, r3, #1 - 8002616: 4013 ands r3, r2 - 8002618: d00b beq.n 8002632 + 8002ed4: 68ba ldr r2, [r7, #8] + 8002ed6: 2380 movs r3, #128 @ 0x80 + 8002ed8: 005b lsls r3, r3, #1 + 8002eda: 4013 ands r3, r2 + 8002edc: d00b beq.n 8002ef6 { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) - 800261a: 68fb ldr r3, [r7, #12] - 800261c: 2280 movs r2, #128 @ 0x80 - 800261e: 4013 ands r3, r2 - 8002620: d007 beq.n 8002632 + 8002ede: 68fb ldr r3, [r7, #12] + 8002ee0: 2280 movs r2, #128 @ 0x80 + 8002ee2: 4013 ands r3, r2 + 8002ee4: d007 beq.n 8002ef6 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); - 8002622: 687b ldr r3, [r7, #4] - 8002624: 681b ldr r3, [r3, #0] - 8002626: 4a17 ldr r2, [pc, #92] @ (8002684 ) - 8002628: 611a str r2, [r3, #16] + 8002ee6: 687b ldr r3, [r7, #4] + 8002ee8: 681b ldr r3, [r3, #0] + 8002eea: 4a17 ldr r2, [pc, #92] @ (8002f48 ) + 8002eec: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->Break2Callback(htim); #else HAL_TIMEx_Break2Callback(htim); - 800262a: 687b ldr r3, [r7, #4] - 800262c: 0018 movs r0, r3 - 800262e: f000 fee9 bl 8003404 + 8002eee: 687b ldr r3, [r7, #4] + 8002ef0: 0018 movs r0, r3 + 8002ef2: f000 fee9 bl 8003cc8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) - 8002632: 68bb ldr r3, [r7, #8] - 8002634: 2240 movs r2, #64 @ 0x40 - 8002636: 4013 ands r3, r2 - 8002638: d00c beq.n 8002654 + 8002ef6: 68bb ldr r3, [r7, #8] + 8002ef8: 2240 movs r2, #64 @ 0x40 + 8002efa: 4013 ands r3, r2 + 8002efc: d00c beq.n 8002f18 { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) - 800263a: 68fb ldr r3, [r7, #12] - 800263c: 2240 movs r2, #64 @ 0x40 - 800263e: 4013 ands r3, r2 - 8002640: d008 beq.n 8002654 + 8002efe: 68fb ldr r3, [r7, #12] + 8002f00: 2240 movs r2, #64 @ 0x40 + 8002f02: 4013 ands r3, r2 + 8002f04: d008 beq.n 8002f18 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); - 8002642: 687b ldr r3, [r7, #4] - 8002644: 681b ldr r3, [r3, #0] - 8002646: 2241 movs r2, #65 @ 0x41 - 8002648: 4252 negs r2, r2 - 800264a: 611a str r2, [r3, #16] + 8002f06: 687b ldr r3, [r7, #4] + 8002f08: 681b ldr r3, [r3, #0] + 8002f0a: 2241 movs r2, #65 @ 0x41 + 8002f0c: 4252 negs r2, r2 + 8002f0e: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); - 800264c: 687b ldr r3, [r7, #4] - 800264e: 0018 movs r0, r3 - 8002650: f000 fa08 bl 8002a64 + 8002f10: 687b ldr r3, [r7, #4] + 8002f12: 0018 movs r0, r3 + 8002f14: f000 fa08 bl 8003328 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) - 8002654: 68bb ldr r3, [r7, #8] - 8002656: 2220 movs r2, #32 - 8002658: 4013 ands r3, r2 - 800265a: d00c beq.n 8002676 + 8002f18: 68bb ldr r3, [r7, #8] + 8002f1a: 2220 movs r2, #32 + 8002f1c: 4013 ands r3, r2 + 8002f1e: d00c beq.n 8002f3a { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) - 800265c: 68fb ldr r3, [r7, #12] - 800265e: 2220 movs r2, #32 - 8002660: 4013 ands r3, r2 - 8002662: d008 beq.n 8002676 + 8002f20: 68fb ldr r3, [r7, #12] + 8002f22: 2220 movs r2, #32 + 8002f24: 4013 ands r3, r2 + 8002f26: d008 beq.n 8002f3a { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); - 8002664: 687b ldr r3, [r7, #4] - 8002666: 681b ldr r3, [r3, #0] - 8002668: 2221 movs r2, #33 @ 0x21 - 800266a: 4252 negs r2, r2 - 800266c: 611a str r2, [r3, #16] + 8002f28: 687b ldr r3, [r7, #4] + 8002f2a: 681b ldr r3, [r3, #0] + 8002f2c: 2221 movs r2, #33 @ 0x21 + 8002f2e: 4252 negs r2, r2 + 8002f30: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); - 800266e: 687b ldr r3, [r7, #4] - 8002670: 0018 movs r0, r3 - 8002672: f000 feb7 bl 80033e4 + 8002f32: 687b ldr r3, [r7, #4] + 8002f34: 0018 movs r0, r3 + 8002f36: f000 feb7 bl 8003ca8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } - 8002676: 46c0 nop @ (mov r8, r8) - 8002678: 46bd mov sp, r7 - 800267a: b004 add sp, #16 - 800267c: bd80 pop {r7, pc} - 800267e: 46c0 nop @ (mov r8, r8) - 8002680: ffffdf7f .word 0xffffdf7f - 8002684: fffffeff .word 0xfffffeff + 8002f3a: 46c0 nop @ (mov r8, r8) + 8002f3c: 46bd mov sp, r7 + 8002f3e: b004 add sp, #16 + 8002f40: bd80 pop {r7, pc} + 8002f42: 46c0 nop @ (mov r8, r8) + 8002f44: ffffdf7f .word 0xffffdf7f + 8002f48: fffffeff .word 0xfffffeff -08002688 : +08002f4c : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { - 8002688: b580 push {r7, lr} - 800268a: b086 sub sp, #24 - 800268c: af00 add r7, sp, #0 - 800268e: 60f8 str r0, [r7, #12] - 8002690: 60b9 str r1, [r7, #8] - 8002692: 607a str r2, [r7, #4] + 8002f4c: b580 push {r7, lr} + 8002f4e: b086 sub sp, #24 + 8002f50: af00 add r7, sp, #0 + 8002f52: 60f8 str r0, [r7, #12] + 8002f54: 60b9 str r1, [r7, #8] + 8002f56: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; - 8002694: 2317 movs r3, #23 - 8002696: 18fb adds r3, r7, r3 - 8002698: 2200 movs r2, #0 - 800269a: 701a strb r2, [r3, #0] + 8002f58: 2317 movs r3, #23 + 8002f5a: 18fb adds r3, r7, r3 + 8002f5c: 2200 movs r2, #0 + 8002f5e: 701a strb r2, [r3, #0] assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); /* Process Locked */ __HAL_LOCK(htim); - 800269c: 68fb ldr r3, [r7, #12] - 800269e: 223c movs r2, #60 @ 0x3c - 80026a0: 5c9b ldrb r3, [r3, r2] - 80026a2: 2b01 cmp r3, #1 - 80026a4: d101 bne.n 80026aa - 80026a6: 2302 movs r3, #2 - 80026a8: e0e5 b.n 8002876 - 80026aa: 68fb ldr r3, [r7, #12] - 80026ac: 223c movs r2, #60 @ 0x3c - 80026ae: 2101 movs r1, #1 - 80026b0: 5499 strb r1, [r3, r2] + 8002f60: 68fb ldr r3, [r7, #12] + 8002f62: 223c movs r2, #60 @ 0x3c + 8002f64: 5c9b ldrb r3, [r3, r2] + 8002f66: 2b01 cmp r3, #1 + 8002f68: d101 bne.n 8002f6e + 8002f6a: 2302 movs r3, #2 + 8002f6c: e0e5 b.n 800313a + 8002f6e: 68fb ldr r3, [r7, #12] + 8002f70: 223c movs r2, #60 @ 0x3c + 8002f72: 2101 movs r1, #1 + 8002f74: 5499 strb r1, [r3, r2] switch (Channel) - 80026b2: 687b ldr r3, [r7, #4] - 80026b4: 2b14 cmp r3, #20 - 80026b6: d900 bls.n 80026ba - 80026b8: e0d1 b.n 800285e - 80026ba: 687b ldr r3, [r7, #4] - 80026bc: 009a lsls r2, r3, #2 - 80026be: 4b70 ldr r3, [pc, #448] @ (8002880 ) - 80026c0: 18d3 adds r3, r2, r3 - 80026c2: 681b ldr r3, [r3, #0] - 80026c4: 469f mov pc, r3 + 8002f76: 687b ldr r3, [r7, #4] + 8002f78: 2b14 cmp r3, #20 + 8002f7a: d900 bls.n 8002f7e + 8002f7c: e0d1 b.n 8003122 + 8002f7e: 687b ldr r3, [r7, #4] + 8002f80: 009a lsls r2, r3, #2 + 8002f82: 4b70 ldr r3, [pc, #448] @ (8003144 ) + 8002f84: 18d3 adds r3, r2, r3 + 8002f86: 681b ldr r3, [r3, #0] + 8002f88: 469f mov pc, r3 { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the Channel 1 in PWM mode */ TIM_OC1_SetConfig(htim->Instance, sConfig); - 80026c6: 68fb ldr r3, [r7, #12] - 80026c8: 681b ldr r3, [r3, #0] - 80026ca: 68ba ldr r2, [r7, #8] - 80026cc: 0011 movs r1, r2 - 80026ce: 0018 movs r0, r3 - 80026d0: f000 fa4c bl 8002b6c + 8002f8a: 68fb ldr r3, [r7, #12] + 8002f8c: 681b ldr r3, [r3, #0] + 8002f8e: 68ba ldr r2, [r7, #8] + 8002f90: 0011 movs r1, r2 + 8002f92: 0018 movs r0, r3 + 8002f94: f000 fa4c bl 8003430 /* Set the Preload enable bit for channel1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; - 80026d4: 68fb ldr r3, [r7, #12] - 80026d6: 681b ldr r3, [r3, #0] - 80026d8: 699a ldr r2, [r3, #24] - 80026da: 68fb ldr r3, [r7, #12] - 80026dc: 681b ldr r3, [r3, #0] - 80026de: 2108 movs r1, #8 - 80026e0: 430a orrs r2, r1 - 80026e2: 619a str r2, [r3, #24] + 8002f98: 68fb ldr r3, [r7, #12] + 8002f9a: 681b ldr r3, [r3, #0] + 8002f9c: 699a ldr r2, [r3, #24] + 8002f9e: 68fb ldr r3, [r7, #12] + 8002fa0: 681b ldr r3, [r3, #0] + 8002fa2: 2108 movs r1, #8 + 8002fa4: 430a orrs r2, r1 + 8002fa6: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; - 80026e4: 68fb ldr r3, [r7, #12] - 80026e6: 681b ldr r3, [r3, #0] - 80026e8: 699a ldr r2, [r3, #24] - 80026ea: 68fb ldr r3, [r7, #12] - 80026ec: 681b ldr r3, [r3, #0] - 80026ee: 2104 movs r1, #4 - 80026f0: 438a bics r2, r1 - 80026f2: 619a str r2, [r3, #24] + 8002fa8: 68fb ldr r3, [r7, #12] + 8002faa: 681b ldr r3, [r3, #0] + 8002fac: 699a ldr r2, [r3, #24] + 8002fae: 68fb ldr r3, [r7, #12] + 8002fb0: 681b ldr r3, [r3, #0] + 8002fb2: 2104 movs r1, #4 + 8002fb4: 438a bics r2, r1 + 8002fb6: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode; - 80026f4: 68fb ldr r3, [r7, #12] - 80026f6: 681b ldr r3, [r3, #0] - 80026f8: 6999 ldr r1, [r3, #24] - 80026fa: 68bb ldr r3, [r7, #8] - 80026fc: 691a ldr r2, [r3, #16] - 80026fe: 68fb ldr r3, [r7, #12] - 8002700: 681b ldr r3, [r3, #0] - 8002702: 430a orrs r2, r1 - 8002704: 619a str r2, [r3, #24] + 8002fb8: 68fb ldr r3, [r7, #12] + 8002fba: 681b ldr r3, [r3, #0] + 8002fbc: 6999 ldr r1, [r3, #24] + 8002fbe: 68bb ldr r3, [r7, #8] + 8002fc0: 691a ldr r2, [r3, #16] + 8002fc2: 68fb ldr r3, [r7, #12] + 8002fc4: 681b ldr r3, [r3, #0] + 8002fc6: 430a orrs r2, r1 + 8002fc8: 619a str r2, [r3, #24] break; - 8002706: e0af b.n 8002868 + 8002fca: e0af b.n 800312c { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the Channel 2 in PWM mode */ TIM_OC2_SetConfig(htim->Instance, sConfig); - 8002708: 68fb ldr r3, [r7, #12] - 800270a: 681b ldr r3, [r3, #0] - 800270c: 68ba ldr r2, [r7, #8] - 800270e: 0011 movs r1, r2 - 8002710: 0018 movs r0, r3 - 8002712: f000 faab bl 8002c6c + 8002fcc: 68fb ldr r3, [r7, #12] + 8002fce: 681b ldr r3, [r3, #0] + 8002fd0: 68ba ldr r2, [r7, #8] + 8002fd2: 0011 movs r1, r2 + 8002fd4: 0018 movs r0, r3 + 8002fd6: f000 faab bl 8003530 /* Set the Preload enable bit for channel2 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; - 8002716: 68fb ldr r3, [r7, #12] - 8002718: 681b ldr r3, [r3, #0] - 800271a: 699a ldr r2, [r3, #24] - 800271c: 68fb ldr r3, [r7, #12] - 800271e: 681b ldr r3, [r3, #0] - 8002720: 2180 movs r1, #128 @ 0x80 - 8002722: 0109 lsls r1, r1, #4 - 8002724: 430a orrs r2, r1 - 8002726: 619a str r2, [r3, #24] + 8002fda: 68fb ldr r3, [r7, #12] + 8002fdc: 681b ldr r3, [r3, #0] + 8002fde: 699a ldr r2, [r3, #24] + 8002fe0: 68fb ldr r3, [r7, #12] + 8002fe2: 681b ldr r3, [r3, #0] + 8002fe4: 2180 movs r1, #128 @ 0x80 + 8002fe6: 0109 lsls r1, r1, #4 + 8002fe8: 430a orrs r2, r1 + 8002fea: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; - 8002728: 68fb ldr r3, [r7, #12] - 800272a: 681b ldr r3, [r3, #0] - 800272c: 699a ldr r2, [r3, #24] - 800272e: 68fb ldr r3, [r7, #12] - 8002730: 681b ldr r3, [r3, #0] - 8002732: 4954 ldr r1, [pc, #336] @ (8002884 ) - 8002734: 400a ands r2, r1 - 8002736: 619a str r2, [r3, #24] + 8002fec: 68fb ldr r3, [r7, #12] + 8002fee: 681b ldr r3, [r3, #0] + 8002ff0: 699a ldr r2, [r3, #24] + 8002ff2: 68fb ldr r3, [r7, #12] + 8002ff4: 681b ldr r3, [r3, #0] + 8002ff6: 4954 ldr r1, [pc, #336] @ (8003148 ) + 8002ff8: 400a ands r2, r1 + 8002ffa: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; - 8002738: 68fb ldr r3, [r7, #12] - 800273a: 681b ldr r3, [r3, #0] - 800273c: 6999 ldr r1, [r3, #24] - 800273e: 68bb ldr r3, [r7, #8] - 8002740: 691b ldr r3, [r3, #16] - 8002742: 021a lsls r2, r3, #8 - 8002744: 68fb ldr r3, [r7, #12] - 8002746: 681b ldr r3, [r3, #0] - 8002748: 430a orrs r2, r1 - 800274a: 619a str r2, [r3, #24] + 8002ffc: 68fb ldr r3, [r7, #12] + 8002ffe: 681b ldr r3, [r3, #0] + 8003000: 6999 ldr r1, [r3, #24] + 8003002: 68bb ldr r3, [r7, #8] + 8003004: 691b ldr r3, [r3, #16] + 8003006: 021a lsls r2, r3, #8 + 8003008: 68fb ldr r3, [r7, #12] + 800300a: 681b ldr r3, [r3, #0] + 800300c: 430a orrs r2, r1 + 800300e: 619a str r2, [r3, #24] break; - 800274c: e08c b.n 8002868 + 8003010: e08c b.n 800312c { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the Channel 3 in PWM mode */ TIM_OC3_SetConfig(htim->Instance, sConfig); - 800274e: 68fb ldr r3, [r7, #12] - 8002750: 681b ldr r3, [r3, #0] - 8002752: 68ba ldr r2, [r7, #8] - 8002754: 0011 movs r1, r2 - 8002756: 0018 movs r0, r3 - 8002758: f000 fb06 bl 8002d68 + 8003012: 68fb ldr r3, [r7, #12] + 8003014: 681b ldr r3, [r3, #0] + 8003016: 68ba ldr r2, [r7, #8] + 8003018: 0011 movs r1, r2 + 800301a: 0018 movs r0, r3 + 800301c: f000 fb06 bl 800362c /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; - 800275c: 68fb ldr r3, [r7, #12] - 800275e: 681b ldr r3, [r3, #0] - 8002760: 69da ldr r2, [r3, #28] - 8002762: 68fb ldr r3, [r7, #12] - 8002764: 681b ldr r3, [r3, #0] - 8002766: 2108 movs r1, #8 - 8002768: 430a orrs r2, r1 - 800276a: 61da str r2, [r3, #28] + 8003020: 68fb ldr r3, [r7, #12] + 8003022: 681b ldr r3, [r3, #0] + 8003024: 69da ldr r2, [r3, #28] + 8003026: 68fb ldr r3, [r7, #12] + 8003028: 681b ldr r3, [r3, #0] + 800302a: 2108 movs r1, #8 + 800302c: 430a orrs r2, r1 + 800302e: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; - 800276c: 68fb ldr r3, [r7, #12] - 800276e: 681b ldr r3, [r3, #0] - 8002770: 69da ldr r2, [r3, #28] - 8002772: 68fb ldr r3, [r7, #12] - 8002774: 681b ldr r3, [r3, #0] - 8002776: 2104 movs r1, #4 - 8002778: 438a bics r2, r1 - 800277a: 61da str r2, [r3, #28] + 8003030: 68fb ldr r3, [r7, #12] + 8003032: 681b ldr r3, [r3, #0] + 8003034: 69da ldr r2, [r3, #28] + 8003036: 68fb ldr r3, [r7, #12] + 8003038: 681b ldr r3, [r3, #0] + 800303a: 2104 movs r1, #4 + 800303c: 438a bics r2, r1 + 800303e: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode; - 800277c: 68fb ldr r3, [r7, #12] - 800277e: 681b ldr r3, [r3, #0] - 8002780: 69d9 ldr r1, [r3, #28] - 8002782: 68bb ldr r3, [r7, #8] - 8002784: 691a ldr r2, [r3, #16] - 8002786: 68fb ldr r3, [r7, #12] - 8002788: 681b ldr r3, [r3, #0] - 800278a: 430a orrs r2, r1 - 800278c: 61da str r2, [r3, #28] + 8003040: 68fb ldr r3, [r7, #12] + 8003042: 681b ldr r3, [r3, #0] + 8003044: 69d9 ldr r1, [r3, #28] + 8003046: 68bb ldr r3, [r7, #8] + 8003048: 691a ldr r2, [r3, #16] + 800304a: 68fb ldr r3, [r7, #12] + 800304c: 681b ldr r3, [r3, #0] + 800304e: 430a orrs r2, r1 + 8003050: 61da str r2, [r3, #28] break; - 800278e: e06b b.n 8002868 + 8003052: e06b b.n 800312c { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the Channel 4 in PWM mode */ TIM_OC4_SetConfig(htim->Instance, sConfig); - 8002790: 68fb ldr r3, [r7, #12] - 8002792: 681b ldr r3, [r3, #0] - 8002794: 68ba ldr r2, [r7, #8] - 8002796: 0011 movs r1, r2 - 8002798: 0018 movs r0, r3 - 800279a: f000 fb67 bl 8002e6c + 8003054: 68fb ldr r3, [r7, #12] + 8003056: 681b ldr r3, [r3, #0] + 8003058: 68ba ldr r2, [r7, #8] + 800305a: 0011 movs r1, r2 + 800305c: 0018 movs r0, r3 + 800305e: f000 fb67 bl 8003730 /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; - 800279e: 68fb ldr r3, [r7, #12] - 80027a0: 681b ldr r3, [r3, #0] - 80027a2: 69da ldr r2, [r3, #28] - 80027a4: 68fb ldr r3, [r7, #12] - 80027a6: 681b ldr r3, [r3, #0] - 80027a8: 2180 movs r1, #128 @ 0x80 - 80027aa: 0109 lsls r1, r1, #4 - 80027ac: 430a orrs r2, r1 - 80027ae: 61da str r2, [r3, #28] + 8003062: 68fb ldr r3, [r7, #12] + 8003064: 681b ldr r3, [r3, #0] + 8003066: 69da ldr r2, [r3, #28] + 8003068: 68fb ldr r3, [r7, #12] + 800306a: 681b ldr r3, [r3, #0] + 800306c: 2180 movs r1, #128 @ 0x80 + 800306e: 0109 lsls r1, r1, #4 + 8003070: 430a orrs r2, r1 + 8003072: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; - 80027b0: 68fb ldr r3, [r7, #12] - 80027b2: 681b ldr r3, [r3, #0] - 80027b4: 69da ldr r2, [r3, #28] - 80027b6: 68fb ldr r3, [r7, #12] - 80027b8: 681b ldr r3, [r3, #0] - 80027ba: 4932 ldr r1, [pc, #200] @ (8002884 ) - 80027bc: 400a ands r2, r1 - 80027be: 61da str r2, [r3, #28] + 8003074: 68fb ldr r3, [r7, #12] + 8003076: 681b ldr r3, [r3, #0] + 8003078: 69da ldr r2, [r3, #28] + 800307a: 68fb ldr r3, [r7, #12] + 800307c: 681b ldr r3, [r3, #0] + 800307e: 4932 ldr r1, [pc, #200] @ (8003148 ) + 8003080: 400a ands r2, r1 + 8003082: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; - 80027c0: 68fb ldr r3, [r7, #12] - 80027c2: 681b ldr r3, [r3, #0] - 80027c4: 69d9 ldr r1, [r3, #28] - 80027c6: 68bb ldr r3, [r7, #8] - 80027c8: 691b ldr r3, [r3, #16] - 80027ca: 021a lsls r2, r3, #8 - 80027cc: 68fb ldr r3, [r7, #12] - 80027ce: 681b ldr r3, [r3, #0] - 80027d0: 430a orrs r2, r1 - 80027d2: 61da str r2, [r3, #28] + 8003084: 68fb ldr r3, [r7, #12] + 8003086: 681b ldr r3, [r3, #0] + 8003088: 69d9 ldr r1, [r3, #28] + 800308a: 68bb ldr r3, [r7, #8] + 800308c: 691b ldr r3, [r3, #16] + 800308e: 021a lsls r2, r3, #8 + 8003090: 68fb ldr r3, [r7, #12] + 8003092: 681b ldr r3, [r3, #0] + 8003094: 430a orrs r2, r1 + 8003096: 61da str r2, [r3, #28] break; - 80027d4: e048 b.n 8002868 + 8003098: e048 b.n 800312c { /* Check the parameters */ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); /* Configure the Channel 5 in PWM mode */ TIM_OC5_SetConfig(htim->Instance, sConfig); - 80027d6: 68fb ldr r3, [r7, #12] - 80027d8: 681b ldr r3, [r3, #0] - 80027da: 68ba ldr r2, [r7, #8] - 80027dc: 0011 movs r1, r2 - 80027de: 0018 movs r0, r3 - 80027e0: f000 fba8 bl 8002f34 + 800309a: 68fb ldr r3, [r7, #12] + 800309c: 681b ldr r3, [r3, #0] + 800309e: 68ba ldr r2, [r7, #8] + 80030a0: 0011 movs r1, r2 + 80030a2: 0018 movs r0, r3 + 80030a4: f000 fba8 bl 80037f8 /* Set the Preload enable bit for channel5*/ htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; - 80027e4: 68fb ldr r3, [r7, #12] - 80027e6: 681b ldr r3, [r3, #0] - 80027e8: 6d5a ldr r2, [r3, #84] @ 0x54 - 80027ea: 68fb ldr r3, [r7, #12] - 80027ec: 681b ldr r3, [r3, #0] - 80027ee: 2108 movs r1, #8 - 80027f0: 430a orrs r2, r1 - 80027f2: 655a str r2, [r3, #84] @ 0x54 + 80030a8: 68fb ldr r3, [r7, #12] + 80030aa: 681b ldr r3, [r3, #0] + 80030ac: 6d5a ldr r2, [r3, #84] @ 0x54 + 80030ae: 68fb ldr r3, [r7, #12] + 80030b0: 681b ldr r3, [r3, #0] + 80030b2: 2108 movs r1, #8 + 80030b4: 430a orrs r2, r1 + 80030b6: 655a str r2, [r3, #84] @ 0x54 /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; - 80027f4: 68fb ldr r3, [r7, #12] - 80027f6: 681b ldr r3, [r3, #0] - 80027f8: 6d5a ldr r2, [r3, #84] @ 0x54 - 80027fa: 68fb ldr r3, [r7, #12] - 80027fc: 681b ldr r3, [r3, #0] - 80027fe: 2104 movs r1, #4 - 8002800: 438a bics r2, r1 - 8002802: 655a str r2, [r3, #84] @ 0x54 + 80030b8: 68fb ldr r3, [r7, #12] + 80030ba: 681b ldr r3, [r3, #0] + 80030bc: 6d5a ldr r2, [r3, #84] @ 0x54 + 80030be: 68fb ldr r3, [r7, #12] + 80030c0: 681b ldr r3, [r3, #0] + 80030c2: 2104 movs r1, #4 + 80030c4: 438a bics r2, r1 + 80030c6: 655a str r2, [r3, #84] @ 0x54 htim->Instance->CCMR3 |= sConfig->OCFastMode; - 8002804: 68fb ldr r3, [r7, #12] - 8002806: 681b ldr r3, [r3, #0] - 8002808: 6d59 ldr r1, [r3, #84] @ 0x54 - 800280a: 68bb ldr r3, [r7, #8] - 800280c: 691a ldr r2, [r3, #16] - 800280e: 68fb ldr r3, [r7, #12] - 8002810: 681b ldr r3, [r3, #0] - 8002812: 430a orrs r2, r1 - 8002814: 655a str r2, [r3, #84] @ 0x54 + 80030c8: 68fb ldr r3, [r7, #12] + 80030ca: 681b ldr r3, [r3, #0] + 80030cc: 6d59 ldr r1, [r3, #84] @ 0x54 + 80030ce: 68bb ldr r3, [r7, #8] + 80030d0: 691a ldr r2, [r3, #16] + 80030d2: 68fb ldr r3, [r7, #12] + 80030d4: 681b ldr r3, [r3, #0] + 80030d6: 430a orrs r2, r1 + 80030d8: 655a str r2, [r3, #84] @ 0x54 break; - 8002816: e027 b.n 8002868 + 80030da: e027 b.n 800312c { /* Check the parameters */ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); /* Configure the Channel 6 in PWM mode */ TIM_OC6_SetConfig(htim->Instance, sConfig); - 8002818: 68fb ldr r3, [r7, #12] - 800281a: 681b ldr r3, [r3, #0] - 800281c: 68ba ldr r2, [r7, #8] - 800281e: 0011 movs r1, r2 - 8002820: 0018 movs r0, r3 - 8002822: f000 fbe1 bl 8002fe8 + 80030dc: 68fb ldr r3, [r7, #12] + 80030de: 681b ldr r3, [r3, #0] + 80030e0: 68ba ldr r2, [r7, #8] + 80030e2: 0011 movs r1, r2 + 80030e4: 0018 movs r0, r3 + 80030e6: f000 fbe1 bl 80038ac /* Set the Preload enable bit for channel6 */ htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; - 8002826: 68fb ldr r3, [r7, #12] - 8002828: 681b ldr r3, [r3, #0] - 800282a: 6d5a ldr r2, [r3, #84] @ 0x54 - 800282c: 68fb ldr r3, [r7, #12] - 800282e: 681b ldr r3, [r3, #0] - 8002830: 2180 movs r1, #128 @ 0x80 - 8002832: 0109 lsls r1, r1, #4 - 8002834: 430a orrs r2, r1 - 8002836: 655a str r2, [r3, #84] @ 0x54 + 80030ea: 68fb ldr r3, [r7, #12] + 80030ec: 681b ldr r3, [r3, #0] + 80030ee: 6d5a ldr r2, [r3, #84] @ 0x54 + 80030f0: 68fb ldr r3, [r7, #12] + 80030f2: 681b ldr r3, [r3, #0] + 80030f4: 2180 movs r1, #128 @ 0x80 + 80030f6: 0109 lsls r1, r1, #4 + 80030f8: 430a orrs r2, r1 + 80030fa: 655a str r2, [r3, #84] @ 0x54 /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; - 8002838: 68fb ldr r3, [r7, #12] - 800283a: 681b ldr r3, [r3, #0] - 800283c: 6d5a ldr r2, [r3, #84] @ 0x54 - 800283e: 68fb ldr r3, [r7, #12] - 8002840: 681b ldr r3, [r3, #0] - 8002842: 4910 ldr r1, [pc, #64] @ (8002884 ) - 8002844: 400a ands r2, r1 - 8002846: 655a str r2, [r3, #84] @ 0x54 + 80030fc: 68fb ldr r3, [r7, #12] + 80030fe: 681b ldr r3, [r3, #0] + 8003100: 6d5a ldr r2, [r3, #84] @ 0x54 + 8003102: 68fb ldr r3, [r7, #12] + 8003104: 681b ldr r3, [r3, #0] + 8003106: 4910 ldr r1, [pc, #64] @ (8003148 ) + 8003108: 400a ands r2, r1 + 800310a: 655a str r2, [r3, #84] @ 0x54 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; - 8002848: 68fb ldr r3, [r7, #12] - 800284a: 681b ldr r3, [r3, #0] - 800284c: 6d59 ldr r1, [r3, #84] @ 0x54 - 800284e: 68bb ldr r3, [r7, #8] - 8002850: 691b ldr r3, [r3, #16] - 8002852: 021a lsls r2, r3, #8 - 8002854: 68fb ldr r3, [r7, #12] - 8002856: 681b ldr r3, [r3, #0] - 8002858: 430a orrs r2, r1 - 800285a: 655a str r2, [r3, #84] @ 0x54 + 800310c: 68fb ldr r3, [r7, #12] + 800310e: 681b ldr r3, [r3, #0] + 8003110: 6d59 ldr r1, [r3, #84] @ 0x54 + 8003112: 68bb ldr r3, [r7, #8] + 8003114: 691b ldr r3, [r3, #16] + 8003116: 021a lsls r2, r3, #8 + 8003118: 68fb ldr r3, [r7, #12] + 800311a: 681b ldr r3, [r3, #0] + 800311c: 430a orrs r2, r1 + 800311e: 655a str r2, [r3, #84] @ 0x54 break; - 800285c: e004 b.n 8002868 + 8003120: e004 b.n 800312c } default: status = HAL_ERROR; - 800285e: 2317 movs r3, #23 - 8002860: 18fb adds r3, r7, r3 - 8002862: 2201 movs r2, #1 - 8002864: 701a strb r2, [r3, #0] + 8003122: 2317 movs r3, #23 + 8003124: 18fb adds r3, r7, r3 + 8003126: 2201 movs r2, #1 + 8003128: 701a strb r2, [r3, #0] break; - 8002866: 46c0 nop @ (mov r8, r8) + 800312a: 46c0 nop @ (mov r8, r8) } __HAL_UNLOCK(htim); - 8002868: 68fb ldr r3, [r7, #12] - 800286a: 223c movs r2, #60 @ 0x3c - 800286c: 2100 movs r1, #0 - 800286e: 5499 strb r1, [r3, r2] + 800312c: 68fb ldr r3, [r7, #12] + 800312e: 223c movs r2, #60 @ 0x3c + 8003130: 2100 movs r1, #0 + 8003132: 5499 strb r1, [r3, r2] return status; - 8002870: 2317 movs r3, #23 - 8002872: 18fb adds r3, r7, r3 - 8002874: 781b ldrb r3, [r3, #0] + 8003134: 2317 movs r3, #23 + 8003136: 18fb adds r3, r7, r3 + 8003138: 781b ldrb r3, [r3, #0] } - 8002876: 0018 movs r0, r3 - 8002878: 46bd mov sp, r7 - 800287a: b006 add sp, #24 - 800287c: bd80 pop {r7, pc} - 800287e: 46c0 nop @ (mov r8, r8) - 8002880: 0800400c .word 0x0800400c - 8002884: fffffbff .word 0xfffffbff + 800313a: 0018 movs r0, r3 + 800313c: 46bd mov sp, r7 + 800313e: b006 add sp, #24 + 8003140: bd80 pop {r7, pc} + 8003142: 46c0 nop @ (mov r8, r8) + 8003144: 08004e1c .word 0x08004e1c + 8003148: fffffbff .word 0xfffffbff -08002888 : +0800314c : * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) { - 8002888: b580 push {r7, lr} - 800288a: b084 sub sp, #16 - 800288c: af00 add r7, sp, #0 - 800288e: 6078 str r0, [r7, #4] - 8002890: 6039 str r1, [r7, #0] + 800314c: b580 push {r7, lr} + 800314e: b084 sub sp, #16 + 8003150: af00 add r7, sp, #0 + 8003152: 6078 str r0, [r7, #4] + 8003154: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; - 8002892: 230f movs r3, #15 - 8002894: 18fb adds r3, r7, r3 - 8002896: 2200 movs r2, #0 - 8002898: 701a strb r2, [r3, #0] + 8003156: 230f movs r3, #15 + 8003158: 18fb adds r3, r7, r3 + 800315a: 2200 movs r2, #0 + 800315c: 701a strb r2, [r3, #0] uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); - 800289a: 687b ldr r3, [r7, #4] - 800289c: 223c movs r2, #60 @ 0x3c - 800289e: 5c9b ldrb r3, [r3, r2] - 80028a0: 2b01 cmp r3, #1 - 80028a2: d101 bne.n 80028a8 - 80028a4: 2302 movs r3, #2 - 80028a6: e0bc b.n 8002a22 - 80028a8: 687b ldr r3, [r7, #4] - 80028aa: 223c movs r2, #60 @ 0x3c - 80028ac: 2101 movs r1, #1 - 80028ae: 5499 strb r1, [r3, r2] + 800315e: 687b ldr r3, [r7, #4] + 8003160: 223c movs r2, #60 @ 0x3c + 8003162: 5c9b ldrb r3, [r3, r2] + 8003164: 2b01 cmp r3, #1 + 8003166: d101 bne.n 800316c + 8003168: 2302 movs r3, #2 + 800316a: e0bc b.n 80032e6 + 800316c: 687b ldr r3, [r7, #4] + 800316e: 223c movs r2, #60 @ 0x3c + 8003170: 2101 movs r1, #1 + 8003172: 5499 strb r1, [r3, r2] htim->State = HAL_TIM_STATE_BUSY; - 80028b0: 687b ldr r3, [r7, #4] - 80028b2: 223d movs r2, #61 @ 0x3d - 80028b4: 2102 movs r1, #2 - 80028b6: 5499 strb r1, [r3, r2] + 8003174: 687b ldr r3, [r7, #4] + 8003176: 223d movs r2, #61 @ 0x3d + 8003178: 2102 movs r1, #2 + 800317a: 5499 strb r1, [r3, r2] /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; - 80028b8: 687b ldr r3, [r7, #4] - 80028ba: 681b ldr r3, [r3, #0] - 80028bc: 689b ldr r3, [r3, #8] - 80028be: 60bb str r3, [r7, #8] + 800317c: 687b ldr r3, [r7, #4] + 800317e: 681b ldr r3, [r3, #0] + 8003180: 689b ldr r3, [r3, #8] + 8003182: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); - 80028c0: 68bb ldr r3, [r7, #8] - 80028c2: 4a5a ldr r2, [pc, #360] @ (8002a2c ) - 80028c4: 4013 ands r3, r2 - 80028c6: 60bb str r3, [r7, #8] + 8003184: 68bb ldr r3, [r7, #8] + 8003186: 4a5a ldr r2, [pc, #360] @ (80032f0 ) + 8003188: 4013 ands r3, r2 + 800318a: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); - 80028c8: 68bb ldr r3, [r7, #8] - 80028ca: 4a59 ldr r2, [pc, #356] @ (8002a30 ) - 80028cc: 4013 ands r3, r2 - 80028ce: 60bb str r3, [r7, #8] + 800318c: 68bb ldr r3, [r7, #8] + 800318e: 4a59 ldr r2, [pc, #356] @ (80032f4 ) + 8003190: 4013 ands r3, r2 + 8003192: 60bb str r3, [r7, #8] htim->Instance->SMCR = tmpsmcr; - 80028d0: 687b ldr r3, [r7, #4] - 80028d2: 681b ldr r3, [r3, #0] - 80028d4: 68ba ldr r2, [r7, #8] - 80028d6: 609a str r2, [r3, #8] + 8003194: 687b ldr r3, [r7, #4] + 8003196: 681b ldr r3, [r3, #0] + 8003198: 68ba ldr r2, [r7, #8] + 800319a: 609a str r2, [r3, #8] switch (sClockSourceConfig->ClockSource) - 80028d8: 683b ldr r3, [r7, #0] - 80028da: 681b ldr r3, [r3, #0] - 80028dc: 2280 movs r2, #128 @ 0x80 - 80028de: 0192 lsls r2, r2, #6 - 80028e0: 4293 cmp r3, r2 - 80028e2: d040 beq.n 8002966 - 80028e4: 2280 movs r2, #128 @ 0x80 - 80028e6: 0192 lsls r2, r2, #6 - 80028e8: 4293 cmp r3, r2 - 80028ea: d900 bls.n 80028ee - 80028ec: e088 b.n 8002a00 - 80028ee: 2280 movs r2, #128 @ 0x80 - 80028f0: 0152 lsls r2, r2, #5 - 80028f2: 4293 cmp r3, r2 - 80028f4: d100 bne.n 80028f8 - 80028f6: e088 b.n 8002a0a - 80028f8: 2280 movs r2, #128 @ 0x80 - 80028fa: 0152 lsls r2, r2, #5 - 80028fc: 4293 cmp r3, r2 - 80028fe: d900 bls.n 8002902 - 8002900: e07e b.n 8002a00 - 8002902: 2b70 cmp r3, #112 @ 0x70 - 8002904: d018 beq.n 8002938 - 8002906: d900 bls.n 800290a - 8002908: e07a b.n 8002a00 - 800290a: 2b60 cmp r3, #96 @ 0x60 - 800290c: d04f beq.n 80029ae - 800290e: d900 bls.n 8002912 - 8002910: e076 b.n 8002a00 - 8002912: 2b50 cmp r3, #80 @ 0x50 - 8002914: d03b beq.n 800298e - 8002916: d900 bls.n 800291a - 8002918: e072 b.n 8002a00 - 800291a: 2b40 cmp r3, #64 @ 0x40 - 800291c: d057 beq.n 80029ce - 800291e: d900 bls.n 8002922 - 8002920: e06e b.n 8002a00 - 8002922: 2b30 cmp r3, #48 @ 0x30 - 8002924: d063 beq.n 80029ee - 8002926: d86b bhi.n 8002a00 - 8002928: 2b20 cmp r3, #32 - 800292a: d060 beq.n 80029ee - 800292c: d868 bhi.n 8002a00 - 800292e: 2b00 cmp r3, #0 - 8002930: d05d beq.n 80029ee - 8002932: 2b10 cmp r3, #16 - 8002934: d05b beq.n 80029ee - 8002936: e063 b.n 8002a00 + 800319c: 683b ldr r3, [r7, #0] + 800319e: 681b ldr r3, [r3, #0] + 80031a0: 2280 movs r2, #128 @ 0x80 + 80031a2: 0192 lsls r2, r2, #6 + 80031a4: 4293 cmp r3, r2 + 80031a6: d040 beq.n 800322a + 80031a8: 2280 movs r2, #128 @ 0x80 + 80031aa: 0192 lsls r2, r2, #6 + 80031ac: 4293 cmp r3, r2 + 80031ae: d900 bls.n 80031b2 + 80031b0: e088 b.n 80032c4 + 80031b2: 2280 movs r2, #128 @ 0x80 + 80031b4: 0152 lsls r2, r2, #5 + 80031b6: 4293 cmp r3, r2 + 80031b8: d100 bne.n 80031bc + 80031ba: e088 b.n 80032ce + 80031bc: 2280 movs r2, #128 @ 0x80 + 80031be: 0152 lsls r2, r2, #5 + 80031c0: 4293 cmp r3, r2 + 80031c2: d900 bls.n 80031c6 + 80031c4: e07e b.n 80032c4 + 80031c6: 2b70 cmp r3, #112 @ 0x70 + 80031c8: d018 beq.n 80031fc + 80031ca: d900 bls.n 80031ce + 80031cc: e07a b.n 80032c4 + 80031ce: 2b60 cmp r3, #96 @ 0x60 + 80031d0: d04f beq.n 8003272 + 80031d2: d900 bls.n 80031d6 + 80031d4: e076 b.n 80032c4 + 80031d6: 2b50 cmp r3, #80 @ 0x50 + 80031d8: d03b beq.n 8003252 + 80031da: d900 bls.n 80031de + 80031dc: e072 b.n 80032c4 + 80031de: 2b40 cmp r3, #64 @ 0x40 + 80031e0: d057 beq.n 8003292 + 80031e2: d900 bls.n 80031e6 + 80031e4: e06e b.n 80032c4 + 80031e6: 2b30 cmp r3, #48 @ 0x30 + 80031e8: d063 beq.n 80032b2 + 80031ea: d86b bhi.n 80032c4 + 80031ec: 2b20 cmp r3, #32 + 80031ee: d060 beq.n 80032b2 + 80031f0: d868 bhi.n 80032c4 + 80031f2: 2b00 cmp r3, #0 + 80031f4: d05d beq.n 80032b2 + 80031f6: 2b10 cmp r3, #16 + 80031f8: d05b beq.n 80032b2 + 80031fa: e063 b.n 80032c4 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, - 8002938: 687b ldr r3, [r7, #4] - 800293a: 6818 ldr r0, [r3, #0] + 80031fc: 687b ldr r3, [r7, #4] + 80031fe: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, - 800293c: 683b ldr r3, [r7, #0] - 800293e: 6899 ldr r1, [r3, #8] + 8003200: 683b ldr r3, [r7, #0] + 8003202: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, - 8002940: 683b ldr r3, [r7, #0] - 8002942: 685a ldr r2, [r3, #4] + 8003204: 683b ldr r3, [r7, #0] + 8003206: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); - 8002944: 683b ldr r3, [r7, #0] - 8002946: 68db ldr r3, [r3, #12] + 8003208: 683b ldr r3, [r7, #0] + 800320a: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, - 8002948: f000 fc28 bl 800319c + 800320c: f000 fc28 bl 8003a60 /* Select the External clock mode1 and the ETRF trigger */ tmpsmcr = htim->Instance->SMCR; - 800294c: 687b ldr r3, [r7, #4] - 800294e: 681b ldr r3, [r3, #0] - 8002950: 689b ldr r3, [r3, #8] - 8002952: 60bb str r3, [r7, #8] + 8003210: 687b ldr r3, [r7, #4] + 8003212: 681b ldr r3, [r3, #0] + 8003214: 689b ldr r3, [r3, #8] + 8003216: 60bb str r3, [r7, #8] tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); - 8002954: 68bb ldr r3, [r7, #8] - 8002956: 2277 movs r2, #119 @ 0x77 - 8002958: 4313 orrs r3, r2 - 800295a: 60bb str r3, [r7, #8] + 8003218: 68bb ldr r3, [r7, #8] + 800321a: 2277 movs r2, #119 @ 0x77 + 800321c: 4313 orrs r3, r2 + 800321e: 60bb str r3, [r7, #8] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; - 800295c: 687b ldr r3, [r7, #4] - 800295e: 681b ldr r3, [r3, #0] - 8002960: 68ba ldr r2, [r7, #8] - 8002962: 609a str r2, [r3, #8] + 8003220: 687b ldr r3, [r7, #4] + 8003222: 681b ldr r3, [r3, #0] + 8003224: 68ba ldr r2, [r7, #8] + 8003226: 609a str r2, [r3, #8] break; - 8002964: e052 b.n 8002a0c + 8003228: e052 b.n 80032d0 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, - 8002966: 687b ldr r3, [r7, #4] - 8002968: 6818 ldr r0, [r3, #0] + 800322a: 687b ldr r3, [r7, #4] + 800322c: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, - 800296a: 683b ldr r3, [r7, #0] - 800296c: 6899 ldr r1, [r3, #8] + 800322e: 683b ldr r3, [r7, #0] + 8003230: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, - 800296e: 683b ldr r3, [r7, #0] - 8002970: 685a ldr r2, [r3, #4] + 8003232: 683b ldr r3, [r7, #0] + 8003234: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); - 8002972: 683b ldr r3, [r7, #0] - 8002974: 68db ldr r3, [r3, #12] + 8003236: 683b ldr r3, [r7, #0] + 8003238: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, - 8002976: f000 fc11 bl 800319c + 800323a: f000 fc11 bl 8003a60 /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; - 800297a: 687b ldr r3, [r7, #4] - 800297c: 681b ldr r3, [r3, #0] - 800297e: 689a ldr r2, [r3, #8] - 8002980: 687b ldr r3, [r7, #4] - 8002982: 681b ldr r3, [r3, #0] - 8002984: 2180 movs r1, #128 @ 0x80 - 8002986: 01c9 lsls r1, r1, #7 - 8002988: 430a orrs r2, r1 - 800298a: 609a str r2, [r3, #8] + 800323e: 687b ldr r3, [r7, #4] + 8003240: 681b ldr r3, [r3, #0] + 8003242: 689a ldr r2, [r3, #8] + 8003244: 687b ldr r3, [r7, #4] + 8003246: 681b ldr r3, [r3, #0] + 8003248: 2180 movs r1, #128 @ 0x80 + 800324a: 01c9 lsls r1, r1, #7 + 800324c: 430a orrs r2, r1 + 800324e: 609a str r2, [r3, #8] break; - 800298c: e03e b.n 8002a0c + 8003250: e03e b.n 80032d0 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, - 800298e: 687b ldr r3, [r7, #4] - 8002990: 6818 ldr r0, [r3, #0] + 8003252: 687b ldr r3, [r7, #4] + 8003254: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, - 8002992: 683b ldr r3, [r7, #0] - 8002994: 6859 ldr r1, [r3, #4] + 8003256: 683b ldr r3, [r7, #0] + 8003258: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); - 8002996: 683b ldr r3, [r7, #0] - 8002998: 68db ldr r3, [r3, #12] + 800325a: 683b ldr r3, [r7, #0] + 800325c: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, - 800299a: 001a movs r2, r3 - 800299c: f000 fb82 bl 80030a4 + 800325e: 001a movs r2, r3 + 8003260: f000 fb82 bl 8003968 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); - 80029a0: 687b ldr r3, [r7, #4] - 80029a2: 681b ldr r3, [r3, #0] - 80029a4: 2150 movs r1, #80 @ 0x50 - 80029a6: 0018 movs r0, r3 - 80029a8: f000 fbdc bl 8003164 + 8003264: 687b ldr r3, [r7, #4] + 8003266: 681b ldr r3, [r3, #0] + 8003268: 2150 movs r1, #80 @ 0x50 + 800326a: 0018 movs r0, r3 + 800326c: f000 fbdc bl 8003a28 break; - 80029ac: e02e b.n 8002a0c + 8003270: e02e b.n 80032d0 /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI2_ConfigInputStage(htim->Instance, - 80029ae: 687b ldr r3, [r7, #4] - 80029b0: 6818 ldr r0, [r3, #0] + 8003272: 687b ldr r3, [r7, #4] + 8003274: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, - 80029b2: 683b ldr r3, [r7, #0] - 80029b4: 6859 ldr r1, [r3, #4] + 8003276: 683b ldr r3, [r7, #0] + 8003278: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); - 80029b6: 683b ldr r3, [r7, #0] - 80029b8: 68db ldr r3, [r3, #12] + 800327a: 683b ldr r3, [r7, #0] + 800327c: 68db ldr r3, [r3, #12] TIM_TI2_ConfigInputStage(htim->Instance, - 80029ba: 001a movs r2, r3 - 80029bc: f000 fba0 bl 8003100 + 800327e: 001a movs r2, r3 + 8003280: f000 fba0 bl 80039c4 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); - 80029c0: 687b ldr r3, [r7, #4] - 80029c2: 681b ldr r3, [r3, #0] - 80029c4: 2160 movs r1, #96 @ 0x60 - 80029c6: 0018 movs r0, r3 - 80029c8: f000 fbcc bl 8003164 + 8003284: 687b ldr r3, [r7, #4] + 8003286: 681b ldr r3, [r3, #0] + 8003288: 2160 movs r1, #96 @ 0x60 + 800328a: 0018 movs r0, r3 + 800328c: f000 fbcc bl 8003a28 break; - 80029cc: e01e b.n 8002a0c + 8003290: e01e b.n 80032d0 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, - 80029ce: 687b ldr r3, [r7, #4] - 80029d0: 6818 ldr r0, [r3, #0] + 8003292: 687b ldr r3, [r7, #4] + 8003294: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, - 80029d2: 683b ldr r3, [r7, #0] - 80029d4: 6859 ldr r1, [r3, #4] + 8003296: 683b ldr r3, [r7, #0] + 8003298: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); - 80029d6: 683b ldr r3, [r7, #0] - 80029d8: 68db ldr r3, [r3, #12] + 800329a: 683b ldr r3, [r7, #0] + 800329c: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, - 80029da: 001a movs r2, r3 - 80029dc: f000 fb62 bl 80030a4 + 800329e: 001a movs r2, r3 + 80032a0: f000 fb62 bl 8003968 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); - 80029e0: 687b ldr r3, [r7, #4] - 80029e2: 681b ldr r3, [r3, #0] - 80029e4: 2140 movs r1, #64 @ 0x40 - 80029e6: 0018 movs r0, r3 - 80029e8: f000 fbbc bl 8003164 + 80032a4: 687b ldr r3, [r7, #4] + 80032a6: 681b ldr r3, [r3, #0] + 80032a8: 2140 movs r1, #64 @ 0x40 + 80032aa: 0018 movs r0, r3 + 80032ac: f000 fbbc bl 8003a28 break; - 80029ec: e00e b.n 8002a0c + 80032b0: e00e b.n 80032d0 case TIM_CLOCKSOURCE_ITR3: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); - 80029ee: 687b ldr r3, [r7, #4] - 80029f0: 681a ldr r2, [r3, #0] - 80029f2: 683b ldr r3, [r7, #0] - 80029f4: 681b ldr r3, [r3, #0] - 80029f6: 0019 movs r1, r3 - 80029f8: 0010 movs r0, r2 - 80029fa: f000 fbb3 bl 8003164 + 80032b2: 687b ldr r3, [r7, #4] + 80032b4: 681a ldr r2, [r3, #0] + 80032b6: 683b ldr r3, [r7, #0] + 80032b8: 681b ldr r3, [r3, #0] + 80032ba: 0019 movs r1, r3 + 80032bc: 0010 movs r0, r2 + 80032be: f000 fbb3 bl 8003a28 break; - 80029fe: e005 b.n 8002a0c + 80032c2: e005 b.n 80032d0 } default: status = HAL_ERROR; - 8002a00: 230f movs r3, #15 - 8002a02: 18fb adds r3, r7, r3 - 8002a04: 2201 movs r2, #1 - 8002a06: 701a strb r2, [r3, #0] + 80032c4: 230f movs r3, #15 + 80032c6: 18fb adds r3, r7, r3 + 80032c8: 2201 movs r2, #1 + 80032ca: 701a strb r2, [r3, #0] break; - 8002a08: e000 b.n 8002a0c + 80032cc: e000 b.n 80032d0 break; - 8002a0a: 46c0 nop @ (mov r8, r8) + 80032ce: 46c0 nop @ (mov r8, r8) } htim->State = HAL_TIM_STATE_READY; - 8002a0c: 687b ldr r3, [r7, #4] - 8002a0e: 223d movs r2, #61 @ 0x3d - 8002a10: 2101 movs r1, #1 - 8002a12: 5499 strb r1, [r3, r2] + 80032d0: 687b ldr r3, [r7, #4] + 80032d2: 223d movs r2, #61 @ 0x3d + 80032d4: 2101 movs r1, #1 + 80032d6: 5499 strb r1, [r3, r2] __HAL_UNLOCK(htim); - 8002a14: 687b ldr r3, [r7, #4] - 8002a16: 223c movs r2, #60 @ 0x3c - 8002a18: 2100 movs r1, #0 - 8002a1a: 5499 strb r1, [r3, r2] + 80032d8: 687b ldr r3, [r7, #4] + 80032da: 223c movs r2, #60 @ 0x3c + 80032dc: 2100 movs r1, #0 + 80032de: 5499 strb r1, [r3, r2] return status; - 8002a1c: 230f movs r3, #15 - 8002a1e: 18fb adds r3, r7, r3 - 8002a20: 781b ldrb r3, [r3, #0] + 80032e0: 230f movs r3, #15 + 80032e2: 18fb adds r3, r7, r3 + 80032e4: 781b ldrb r3, [r3, #0] } - 8002a22: 0018 movs r0, r3 - 8002a24: 46bd mov sp, r7 - 8002a26: b004 add sp, #16 - 8002a28: bd80 pop {r7, pc} - 8002a2a: 46c0 nop @ (mov r8, r8) - 8002a2c: ffceff88 .word 0xffceff88 - 8002a30: ffff00ff .word 0xffff00ff + 80032e6: 0018 movs r0, r3 + 80032e8: 46bd mov sp, r7 + 80032ea: b004 add sp, #16 + 80032ec: bd80 pop {r7, pc} + 80032ee: 46c0 nop @ (mov r8, r8) + 80032f0: ffceff88 .word 0xffceff88 + 80032f4: ffff00ff .word 0xffff00ff -08002a34 : +080032f8 : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { - 8002a34: b580 push {r7, lr} - 8002a36: b082 sub sp, #8 - 8002a38: af00 add r7, sp, #0 - 8002a3a: 6078 str r0, [r7, #4] + 80032f8: b580 push {r7, lr} + 80032fa: b082 sub sp, #8 + 80032fc: af00 add r7, sp, #0 + 80032fe: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } - 8002a3c: 46c0 nop @ (mov r8, r8) - 8002a3e: 46bd mov sp, r7 - 8002a40: b002 add sp, #8 - 8002a42: bd80 pop {r7, pc} + 8003300: 46c0 nop @ (mov r8, r8) + 8003302: 46bd mov sp, r7 + 8003304: b002 add sp, #8 + 8003306: bd80 pop {r7, pc} -08002a44 : +08003308 : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { - 8002a44: b580 push {r7, lr} - 8002a46: b082 sub sp, #8 - 8002a48: af00 add r7, sp, #0 - 8002a4a: 6078 str r0, [r7, #4] + 8003308: b580 push {r7, lr} + 800330a: b082 sub sp, #8 + 800330c: af00 add r7, sp, #0 + 800330e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } - 8002a4c: 46c0 nop @ (mov r8, r8) - 8002a4e: 46bd mov sp, r7 - 8002a50: b002 add sp, #8 - 8002a52: bd80 pop {r7, pc} + 8003310: 46c0 nop @ (mov r8, r8) + 8003312: 46bd mov sp, r7 + 8003314: b002 add sp, #8 + 8003316: bd80 pop {r7, pc} -08002a54 : +08003318 : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { - 8002a54: b580 push {r7, lr} - 8002a56: b082 sub sp, #8 - 8002a58: af00 add r7, sp, #0 - 8002a5a: 6078 str r0, [r7, #4] + 8003318: b580 push {r7, lr} + 800331a: b082 sub sp, #8 + 800331c: af00 add r7, sp, #0 + 800331e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } - 8002a5c: 46c0 nop @ (mov r8, r8) - 8002a5e: 46bd mov sp, r7 - 8002a60: b002 add sp, #8 - 8002a62: bd80 pop {r7, pc} + 8003320: 46c0 nop @ (mov r8, r8) + 8003322: 46bd mov sp, r7 + 8003324: b002 add sp, #8 + 8003326: bd80 pop {r7, pc} -08002a64 : +08003328 : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { - 8002a64: b580 push {r7, lr} - 8002a66: b082 sub sp, #8 - 8002a68: af00 add r7, sp, #0 - 8002a6a: 6078 str r0, [r7, #4] + 8003328: b580 push {r7, lr} + 800332a: b082 sub sp, #8 + 800332c: af00 add r7, sp, #0 + 800332e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } - 8002a6c: 46c0 nop @ (mov r8, r8) - 8002a6e: 46bd mov sp, r7 - 8002a70: b002 add sp, #8 - 8002a72: bd80 pop {r7, pc} + 8003330: 46c0 nop @ (mov r8, r8) + 8003332: 46bd mov sp, r7 + 8003334: b002 add sp, #8 + 8003336: bd80 pop {r7, pc} -08002a74 : +08003338 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { - 8002a74: b580 push {r7, lr} - 8002a76: b084 sub sp, #16 - 8002a78: af00 add r7, sp, #0 - 8002a7a: 6078 str r0, [r7, #4] - 8002a7c: 6039 str r1, [r7, #0] + 8003338: b580 push {r7, lr} + 800333a: b084 sub sp, #16 + 800333c: af00 add r7, sp, #0 + 800333e: 6078 str r0, [r7, #4] + 8003340: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; - 8002a7e: 687b ldr r3, [r7, #4] - 8002a80: 681b ldr r3, [r3, #0] - 8002a82: 60fb str r3, [r7, #12] + 8003342: 687b ldr r3, [r7, #4] + 8003344: 681b ldr r3, [r3, #0] + 8003346: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) - 8002a84: 687b ldr r3, [r7, #4] - 8002a86: 4a33 ldr r2, [pc, #204] @ (8002b54 ) - 8002a88: 4293 cmp r3, r2 - 8002a8a: d008 beq.n 8002a9e - 8002a8c: 687a ldr r2, [r7, #4] - 8002a8e: 2380 movs r3, #128 @ 0x80 - 8002a90: 05db lsls r3, r3, #23 - 8002a92: 429a cmp r2, r3 - 8002a94: d003 beq.n 8002a9e - 8002a96: 687b ldr r3, [r7, #4] - 8002a98: 4a2f ldr r2, [pc, #188] @ (8002b58 ) - 8002a9a: 4293 cmp r3, r2 - 8002a9c: d108 bne.n 8002ab0 + 8003348: 687b ldr r3, [r7, #4] + 800334a: 4a33 ldr r2, [pc, #204] @ (8003418 ) + 800334c: 4293 cmp r3, r2 + 800334e: d008 beq.n 8003362 + 8003350: 687a ldr r2, [r7, #4] + 8003352: 2380 movs r3, #128 @ 0x80 + 8003354: 05db lsls r3, r3, #23 + 8003356: 429a cmp r2, r3 + 8003358: d003 beq.n 8003362 + 800335a: 687b ldr r3, [r7, #4] + 800335c: 4a2f ldr r2, [pc, #188] @ (800341c ) + 800335e: 4293 cmp r3, r2 + 8003360: d108 bne.n 8003374 { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); - 8002a9e: 68fb ldr r3, [r7, #12] - 8002aa0: 2270 movs r2, #112 @ 0x70 - 8002aa2: 4393 bics r3, r2 - 8002aa4: 60fb str r3, [r7, #12] + 8003362: 68fb ldr r3, [r7, #12] + 8003364: 2270 movs r2, #112 @ 0x70 + 8003366: 4393 bics r3, r2 + 8003368: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; - 8002aa6: 683b ldr r3, [r7, #0] - 8002aa8: 685b ldr r3, [r3, #4] - 8002aaa: 68fa ldr r2, [r7, #12] - 8002aac: 4313 orrs r3, r2 - 8002aae: 60fb str r3, [r7, #12] + 800336a: 683b ldr r3, [r7, #0] + 800336c: 685b ldr r3, [r3, #4] + 800336e: 68fa ldr r2, [r7, #12] + 8003370: 4313 orrs r3, r2 + 8003372: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) - 8002ab0: 687b ldr r3, [r7, #4] - 8002ab2: 4a28 ldr r2, [pc, #160] @ (8002b54 ) - 8002ab4: 4293 cmp r3, r2 - 8002ab6: d014 beq.n 8002ae2 - 8002ab8: 687a ldr r2, [r7, #4] - 8002aba: 2380 movs r3, #128 @ 0x80 - 8002abc: 05db lsls r3, r3, #23 - 8002abe: 429a cmp r2, r3 - 8002ac0: d00f beq.n 8002ae2 - 8002ac2: 687b ldr r3, [r7, #4] - 8002ac4: 4a24 ldr r2, [pc, #144] @ (8002b58 ) - 8002ac6: 4293 cmp r3, r2 - 8002ac8: d00b beq.n 8002ae2 - 8002aca: 687b ldr r3, [r7, #4] - 8002acc: 4a23 ldr r2, [pc, #140] @ (8002b5c ) - 8002ace: 4293 cmp r3, r2 - 8002ad0: d007 beq.n 8002ae2 - 8002ad2: 687b ldr r3, [r7, #4] - 8002ad4: 4a22 ldr r2, [pc, #136] @ (8002b60 ) - 8002ad6: 4293 cmp r3, r2 - 8002ad8: d003 beq.n 8002ae2 - 8002ada: 687b ldr r3, [r7, #4] - 8002adc: 4a21 ldr r2, [pc, #132] @ (8002b64 ) - 8002ade: 4293 cmp r3, r2 - 8002ae0: d108 bne.n 8002af4 + 8003374: 687b ldr r3, [r7, #4] + 8003376: 4a28 ldr r2, [pc, #160] @ (8003418 ) + 8003378: 4293 cmp r3, r2 + 800337a: d014 beq.n 80033a6 + 800337c: 687a ldr r2, [r7, #4] + 800337e: 2380 movs r3, #128 @ 0x80 + 8003380: 05db lsls r3, r3, #23 + 8003382: 429a cmp r2, r3 + 8003384: d00f beq.n 80033a6 + 8003386: 687b ldr r3, [r7, #4] + 8003388: 4a24 ldr r2, [pc, #144] @ (800341c ) + 800338a: 4293 cmp r3, r2 + 800338c: d00b beq.n 80033a6 + 800338e: 687b ldr r3, [r7, #4] + 8003390: 4a23 ldr r2, [pc, #140] @ (8003420 ) + 8003392: 4293 cmp r3, r2 + 8003394: d007 beq.n 80033a6 + 8003396: 687b ldr r3, [r7, #4] + 8003398: 4a22 ldr r2, [pc, #136] @ (8003424 ) + 800339a: 4293 cmp r3, r2 + 800339c: d003 beq.n 80033a6 + 800339e: 687b ldr r3, [r7, #4] + 80033a0: 4a21 ldr r2, [pc, #132] @ (8003428 ) + 80033a2: 4293 cmp r3, r2 + 80033a4: d108 bne.n 80033b8 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; - 8002ae2: 68fb ldr r3, [r7, #12] - 8002ae4: 4a20 ldr r2, [pc, #128] @ (8002b68 ) - 8002ae6: 4013 ands r3, r2 - 8002ae8: 60fb str r3, [r7, #12] + 80033a6: 68fb ldr r3, [r7, #12] + 80033a8: 4a20 ldr r2, [pc, #128] @ (800342c ) + 80033aa: 4013 ands r3, r2 + 80033ac: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; - 8002aea: 683b ldr r3, [r7, #0] - 8002aec: 68db ldr r3, [r3, #12] - 8002aee: 68fa ldr r2, [r7, #12] - 8002af0: 4313 orrs r3, r2 - 8002af2: 60fb str r3, [r7, #12] + 80033ae: 683b ldr r3, [r7, #0] + 80033b0: 68db ldr r3, [r3, #12] + 80033b2: 68fa ldr r2, [r7, #12] + 80033b4: 4313 orrs r3, r2 + 80033b6: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); - 8002af4: 68fb ldr r3, [r7, #12] - 8002af6: 2280 movs r2, #128 @ 0x80 - 8002af8: 4393 bics r3, r2 - 8002afa: 001a movs r2, r3 - 8002afc: 683b ldr r3, [r7, #0] - 8002afe: 695b ldr r3, [r3, #20] - 8002b00: 4313 orrs r3, r2 - 8002b02: 60fb str r3, [r7, #12] + 80033b8: 68fb ldr r3, [r7, #12] + 80033ba: 2280 movs r2, #128 @ 0x80 + 80033bc: 4393 bics r3, r2 + 80033be: 001a movs r2, r3 + 80033c0: 683b ldr r3, [r7, #0] + 80033c2: 695b ldr r3, [r3, #20] + 80033c4: 4313 orrs r3, r2 + 80033c6: 60fb str r3, [r7, #12] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; - 8002b04: 683b ldr r3, [r7, #0] - 8002b06: 689a ldr r2, [r3, #8] - 8002b08: 687b ldr r3, [r7, #4] - 8002b0a: 62da str r2, [r3, #44] @ 0x2c + 80033c8: 683b ldr r3, [r7, #0] + 80033ca: 689a ldr r2, [r3, #8] + 80033cc: 687b ldr r3, [r7, #4] + 80033ce: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; - 8002b0c: 683b ldr r3, [r7, #0] - 8002b0e: 681a ldr r2, [r3, #0] - 8002b10: 687b ldr r3, [r7, #4] - 8002b12: 629a str r2, [r3, #40] @ 0x28 + 80033d0: 683b ldr r3, [r7, #0] + 80033d2: 681a ldr r2, [r3, #0] + 80033d4: 687b ldr r3, [r7, #4] + 80033d6: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) - 8002b14: 687b ldr r3, [r7, #4] - 8002b16: 4a0f ldr r2, [pc, #60] @ (8002b54 ) - 8002b18: 4293 cmp r3, r2 - 8002b1a: d007 beq.n 8002b2c - 8002b1c: 687b ldr r3, [r7, #4] - 8002b1e: 4a10 ldr r2, [pc, #64] @ (8002b60 ) - 8002b20: 4293 cmp r3, r2 - 8002b22: d003 beq.n 8002b2c - 8002b24: 687b ldr r3, [r7, #4] - 8002b26: 4a0f ldr r2, [pc, #60] @ (8002b64 ) - 8002b28: 4293 cmp r3, r2 - 8002b2a: d103 bne.n 8002b34 + 80033d8: 687b ldr r3, [r7, #4] + 80033da: 4a0f ldr r2, [pc, #60] @ (8003418 ) + 80033dc: 4293 cmp r3, r2 + 80033de: d007 beq.n 80033f0 + 80033e0: 687b ldr r3, [r7, #4] + 80033e2: 4a10 ldr r2, [pc, #64] @ (8003424 ) + 80033e4: 4293 cmp r3, r2 + 80033e6: d003 beq.n 80033f0 + 80033e8: 687b ldr r3, [r7, #4] + 80033ea: 4a0f ldr r2, [pc, #60] @ (8003428 ) + 80033ec: 4293 cmp r3, r2 + 80033ee: d103 bne.n 80033f8 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; - 8002b2c: 683b ldr r3, [r7, #0] - 8002b2e: 691a ldr r2, [r3, #16] - 8002b30: 687b ldr r3, [r7, #4] - 8002b32: 631a str r2, [r3, #48] @ 0x30 + 80033f0: 683b ldr r3, [r7, #0] + 80033f2: 691a ldr r2, [r3, #16] + 80033f4: 687b ldr r3, [r7, #4] + 80033f6: 631a str r2, [r3, #48] @ 0x30 } /* Disable Update Event (UEV) with Update Generation (UG) by changing Update Request Source (URS) to avoid Update flag (UIF) */ SET_BIT(TIMx->CR1, TIM_CR1_URS); - 8002b34: 687b ldr r3, [r7, #4] - 8002b36: 681b ldr r3, [r3, #0] - 8002b38: 2204 movs r2, #4 - 8002b3a: 431a orrs r2, r3 - 8002b3c: 687b ldr r3, [r7, #4] - 8002b3e: 601a str r2, [r3, #0] + 80033f8: 687b ldr r3, [r7, #4] + 80033fa: 681b ldr r3, [r3, #0] + 80033fc: 2204 movs r2, #4 + 80033fe: 431a orrs r2, r3 + 8003400: 687b ldr r3, [r7, #4] + 8003402: 601a str r2, [r3, #0] /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; - 8002b40: 687b ldr r3, [r7, #4] - 8002b42: 2201 movs r2, #1 - 8002b44: 615a str r2, [r3, #20] + 8003404: 687b ldr r3, [r7, #4] + 8003406: 2201 movs r2, #1 + 8003408: 615a str r2, [r3, #20] TIMx->CR1 = tmpcr1; - 8002b46: 687b ldr r3, [r7, #4] - 8002b48: 68fa ldr r2, [r7, #12] - 8002b4a: 601a str r2, [r3, #0] + 800340a: 687b ldr r3, [r7, #4] + 800340c: 68fa ldr r2, [r7, #12] + 800340e: 601a str r2, [r3, #0] } - 8002b4c: 46c0 nop @ (mov r8, r8) - 8002b4e: 46bd mov sp, r7 - 8002b50: b004 add sp, #16 - 8002b52: bd80 pop {r7, pc} - 8002b54: 40012c00 .word 0x40012c00 - 8002b58: 40000400 .word 0x40000400 - 8002b5c: 40002000 .word 0x40002000 - 8002b60: 40014400 .word 0x40014400 - 8002b64: 40014800 .word 0x40014800 - 8002b68: fffffcff .word 0xfffffcff + 8003410: 46c0 nop @ (mov r8, r8) + 8003412: 46bd mov sp, r7 + 8003414: b004 add sp, #16 + 8003416: bd80 pop {r7, pc} + 8003418: 40012c00 .word 0x40012c00 + 800341c: 40000400 .word 0x40000400 + 8003420: 40002000 .word 0x40002000 + 8003424: 40014400 .word 0x40014400 + 8003428: 40014800 .word 0x40014800 + 800342c: fffffcff .word 0xfffffcff -08002b6c : +08003430 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { - 8002b6c: b580 push {r7, lr} - 8002b6e: b086 sub sp, #24 - 8002b70: af00 add r7, sp, #0 - 8002b72: 6078 str r0, [r7, #4] - 8002b74: 6039 str r1, [r7, #0] + 8003430: b580 push {r7, lr} + 8003432: b086 sub sp, #24 + 8003434: af00 add r7, sp, #0 + 8003436: 6078 str r0, [r7, #4] + 8003438: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; - 8002b76: 687b ldr r3, [r7, #4] - 8002b78: 6a1b ldr r3, [r3, #32] - 8002b7a: 617b str r3, [r7, #20] + 800343a: 687b ldr r3, [r7, #4] + 800343c: 6a1b ldr r3, [r3, #32] + 800343e: 617b str r3, [r7, #20] /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; - 8002b7c: 687b ldr r3, [r7, #4] - 8002b7e: 6a1b ldr r3, [r3, #32] - 8002b80: 2201 movs r2, #1 - 8002b82: 4393 bics r3, r2 - 8002b84: 001a movs r2, r3 - 8002b86: 687b ldr r3, [r7, #4] - 8002b88: 621a str r2, [r3, #32] + 8003440: 687b ldr r3, [r7, #4] + 8003442: 6a1b ldr r3, [r3, #32] + 8003444: 2201 movs r2, #1 + 8003446: 4393 bics r3, r2 + 8003448: 001a movs r2, r3 + 800344a: 687b ldr r3, [r7, #4] + 800344c: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; - 8002b8a: 687b ldr r3, [r7, #4] - 8002b8c: 685b ldr r3, [r3, #4] - 8002b8e: 613b str r3, [r7, #16] + 800344e: 687b ldr r3, [r7, #4] + 8003450: 685b ldr r3, [r3, #4] + 8003452: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; - 8002b90: 687b ldr r3, [r7, #4] - 8002b92: 699b ldr r3, [r3, #24] - 8002b94: 60fb str r3, [r7, #12] + 8003454: 687b ldr r3, [r7, #4] + 8003456: 699b ldr r3, [r3, #24] + 8003458: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; - 8002b96: 68fb ldr r3, [r7, #12] - 8002b98: 4a2e ldr r2, [pc, #184] @ (8002c54 ) - 8002b9a: 4013 ands r3, r2 - 8002b9c: 60fb str r3, [r7, #12] + 800345a: 68fb ldr r3, [r7, #12] + 800345c: 4a2e ldr r2, [pc, #184] @ (8003518 ) + 800345e: 4013 ands r3, r2 + 8003460: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC1S; - 8002b9e: 68fb ldr r3, [r7, #12] - 8002ba0: 2203 movs r2, #3 - 8002ba2: 4393 bics r3, r2 - 8002ba4: 60fb str r3, [r7, #12] + 8003462: 68fb ldr r3, [r7, #12] + 8003464: 2203 movs r2, #3 + 8003466: 4393 bics r3, r2 + 8003468: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; - 8002ba6: 683b ldr r3, [r7, #0] - 8002ba8: 681b ldr r3, [r3, #0] - 8002baa: 68fa ldr r2, [r7, #12] - 8002bac: 4313 orrs r3, r2 - 8002bae: 60fb str r3, [r7, #12] + 800346a: 683b ldr r3, [r7, #0] + 800346c: 681b ldr r3, [r3, #0] + 800346e: 68fa ldr r2, [r7, #12] + 8003470: 4313 orrs r3, r2 + 8003472: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; - 8002bb0: 697b ldr r3, [r7, #20] - 8002bb2: 2202 movs r2, #2 - 8002bb4: 4393 bics r3, r2 - 8002bb6: 617b str r3, [r7, #20] + 8003474: 697b ldr r3, [r7, #20] + 8003476: 2202 movs r2, #2 + 8003478: 4393 bics r3, r2 + 800347a: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; - 8002bb8: 683b ldr r3, [r7, #0] - 8002bba: 689b ldr r3, [r3, #8] - 8002bbc: 697a ldr r2, [r7, #20] - 8002bbe: 4313 orrs r3, r2 - 8002bc0: 617b str r3, [r7, #20] + 800347c: 683b ldr r3, [r7, #0] + 800347e: 689b ldr r3, [r3, #8] + 8003480: 697a ldr r2, [r7, #20] + 8003482: 4313 orrs r3, r2 + 8003484: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) - 8002bc2: 687b ldr r3, [r7, #4] - 8002bc4: 4a24 ldr r2, [pc, #144] @ (8002c58 ) - 8002bc6: 4293 cmp r3, r2 - 8002bc8: d007 beq.n 8002bda - 8002bca: 687b ldr r3, [r7, #4] - 8002bcc: 4a23 ldr r2, [pc, #140] @ (8002c5c ) - 8002bce: 4293 cmp r3, r2 - 8002bd0: d003 beq.n 8002bda - 8002bd2: 687b ldr r3, [r7, #4] - 8002bd4: 4a22 ldr r2, [pc, #136] @ (8002c60 ) - 8002bd6: 4293 cmp r3, r2 - 8002bd8: d10c bne.n 8002bf4 + 8003486: 687b ldr r3, [r7, #4] + 8003488: 4a24 ldr r2, [pc, #144] @ (800351c ) + 800348a: 4293 cmp r3, r2 + 800348c: d007 beq.n 800349e + 800348e: 687b ldr r3, [r7, #4] + 8003490: 4a23 ldr r2, [pc, #140] @ (8003520 ) + 8003492: 4293 cmp r3, r2 + 8003494: d003 beq.n 800349e + 8003496: 687b ldr r3, [r7, #4] + 8003498: 4a22 ldr r2, [pc, #136] @ (8003524 ) + 800349a: 4293 cmp r3, r2 + 800349c: d10c bne.n 80034b8 { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; - 8002bda: 697b ldr r3, [r7, #20] - 8002bdc: 2208 movs r2, #8 - 8002bde: 4393 bics r3, r2 - 8002be0: 617b str r3, [r7, #20] + 800349e: 697b ldr r3, [r7, #20] + 80034a0: 2208 movs r2, #8 + 80034a2: 4393 bics r3, r2 + 80034a4: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; - 8002be2: 683b ldr r3, [r7, #0] - 8002be4: 68db ldr r3, [r3, #12] - 8002be6: 697a ldr r2, [r7, #20] - 8002be8: 4313 orrs r3, r2 - 8002bea: 617b str r3, [r7, #20] + 80034a6: 683b ldr r3, [r7, #0] + 80034a8: 68db ldr r3, [r3, #12] + 80034aa: 697a ldr r2, [r7, #20] + 80034ac: 4313 orrs r3, r2 + 80034ae: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; - 8002bec: 697b ldr r3, [r7, #20] - 8002bee: 2204 movs r2, #4 - 8002bf0: 4393 bics r3, r2 - 8002bf2: 617b str r3, [r7, #20] + 80034b0: 697b ldr r3, [r7, #20] + 80034b2: 2204 movs r2, #4 + 80034b4: 4393 bics r3, r2 + 80034b6: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) - 8002bf4: 687b ldr r3, [r7, #4] - 8002bf6: 4a18 ldr r2, [pc, #96] @ (8002c58 ) - 8002bf8: 4293 cmp r3, r2 - 8002bfa: d007 beq.n 8002c0c - 8002bfc: 687b ldr r3, [r7, #4] - 8002bfe: 4a17 ldr r2, [pc, #92] @ (8002c5c ) - 8002c00: 4293 cmp r3, r2 - 8002c02: d003 beq.n 8002c0c - 8002c04: 687b ldr r3, [r7, #4] - 8002c06: 4a16 ldr r2, [pc, #88] @ (8002c60 ) - 8002c08: 4293 cmp r3, r2 - 8002c0a: d111 bne.n 8002c30 + 80034b8: 687b ldr r3, [r7, #4] + 80034ba: 4a18 ldr r2, [pc, #96] @ (800351c ) + 80034bc: 4293 cmp r3, r2 + 80034be: d007 beq.n 80034d0 + 80034c0: 687b ldr r3, [r7, #4] + 80034c2: 4a17 ldr r2, [pc, #92] @ (8003520 ) + 80034c4: 4293 cmp r3, r2 + 80034c6: d003 beq.n 80034d0 + 80034c8: 687b ldr r3, [r7, #4] + 80034ca: 4a16 ldr r2, [pc, #88] @ (8003524 ) + 80034cc: 4293 cmp r3, r2 + 80034ce: d111 bne.n 80034f4 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; - 8002c0c: 693b ldr r3, [r7, #16] - 8002c0e: 4a15 ldr r2, [pc, #84] @ (8002c64 ) - 8002c10: 4013 ands r3, r2 - 8002c12: 613b str r3, [r7, #16] + 80034d0: 693b ldr r3, [r7, #16] + 80034d2: 4a15 ldr r2, [pc, #84] @ (8003528 ) + 80034d4: 4013 ands r3, r2 + 80034d6: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS1N; - 8002c14: 693b ldr r3, [r7, #16] - 8002c16: 4a14 ldr r2, [pc, #80] @ (8002c68 ) - 8002c18: 4013 ands r3, r2 - 8002c1a: 613b str r3, [r7, #16] + 80034d8: 693b ldr r3, [r7, #16] + 80034da: 4a14 ldr r2, [pc, #80] @ (800352c ) + 80034dc: 4013 ands r3, r2 + 80034de: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; - 8002c1c: 683b ldr r3, [r7, #0] - 8002c1e: 695b ldr r3, [r3, #20] - 8002c20: 693a ldr r2, [r7, #16] - 8002c22: 4313 orrs r3, r2 - 8002c24: 613b str r3, [r7, #16] + 80034e0: 683b ldr r3, [r7, #0] + 80034e2: 695b ldr r3, [r3, #20] + 80034e4: 693a ldr r2, [r7, #16] + 80034e6: 4313 orrs r3, r2 + 80034e8: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; - 8002c26: 683b ldr r3, [r7, #0] - 8002c28: 699b ldr r3, [r3, #24] - 8002c2a: 693a ldr r2, [r7, #16] - 8002c2c: 4313 orrs r3, r2 - 8002c2e: 613b str r3, [r7, #16] + 80034ea: 683b ldr r3, [r7, #0] + 80034ec: 699b ldr r3, [r3, #24] + 80034ee: 693a ldr r2, [r7, #16] + 80034f0: 4313 orrs r3, r2 + 80034f2: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; - 8002c30: 687b ldr r3, [r7, #4] - 8002c32: 693a ldr r2, [r7, #16] - 8002c34: 605a str r2, [r3, #4] + 80034f4: 687b ldr r3, [r7, #4] + 80034f6: 693a ldr r2, [r7, #16] + 80034f8: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; - 8002c36: 687b ldr r3, [r7, #4] - 8002c38: 68fa ldr r2, [r7, #12] - 8002c3a: 619a str r2, [r3, #24] + 80034fa: 687b ldr r3, [r7, #4] + 80034fc: 68fa ldr r2, [r7, #12] + 80034fe: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; - 8002c3c: 683b ldr r3, [r7, #0] - 8002c3e: 685a ldr r2, [r3, #4] - 8002c40: 687b ldr r3, [r7, #4] - 8002c42: 635a str r2, [r3, #52] @ 0x34 + 8003500: 683b ldr r3, [r7, #0] + 8003502: 685a ldr r2, [r3, #4] + 8003504: 687b ldr r3, [r7, #4] + 8003506: 635a str r2, [r3, #52] @ 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; - 8002c44: 687b ldr r3, [r7, #4] - 8002c46: 697a ldr r2, [r7, #20] - 8002c48: 621a str r2, [r3, #32] + 8003508: 687b ldr r3, [r7, #4] + 800350a: 697a ldr r2, [r7, #20] + 800350c: 621a str r2, [r3, #32] } - 8002c4a: 46c0 nop @ (mov r8, r8) - 8002c4c: 46bd mov sp, r7 - 8002c4e: b006 add sp, #24 - 8002c50: bd80 pop {r7, pc} - 8002c52: 46c0 nop @ (mov r8, r8) - 8002c54: fffeff8f .word 0xfffeff8f - 8002c58: 40012c00 .word 0x40012c00 - 8002c5c: 40014400 .word 0x40014400 - 8002c60: 40014800 .word 0x40014800 - 8002c64: fffffeff .word 0xfffffeff - 8002c68: fffffdff .word 0xfffffdff + 800350e: 46c0 nop @ (mov r8, r8) + 8003510: 46bd mov sp, r7 + 8003512: b006 add sp, #24 + 8003514: bd80 pop {r7, pc} + 8003516: 46c0 nop @ (mov r8, r8) + 8003518: fffeff8f .word 0xfffeff8f + 800351c: 40012c00 .word 0x40012c00 + 8003520: 40014400 .word 0x40014400 + 8003524: 40014800 .word 0x40014800 + 8003528: fffffeff .word 0xfffffeff + 800352c: fffffdff .word 0xfffffdff -08002c6c : +08003530 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { - 8002c6c: b580 push {r7, lr} - 8002c6e: b086 sub sp, #24 - 8002c70: af00 add r7, sp, #0 - 8002c72: 6078 str r0, [r7, #4] - 8002c74: 6039 str r1, [r7, #0] + 8003530: b580 push {r7, lr} + 8003532: b086 sub sp, #24 + 8003534: af00 add r7, sp, #0 + 8003536: 6078 str r0, [r7, #4] + 8003538: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; - 8002c76: 687b ldr r3, [r7, #4] - 8002c78: 6a1b ldr r3, [r3, #32] - 8002c7a: 617b str r3, [r7, #20] + 800353a: 687b ldr r3, [r7, #4] + 800353c: 6a1b ldr r3, [r3, #32] + 800353e: 617b str r3, [r7, #20] /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; - 8002c7c: 687b ldr r3, [r7, #4] - 8002c7e: 6a1b ldr r3, [r3, #32] - 8002c80: 2210 movs r2, #16 - 8002c82: 4393 bics r3, r2 - 8002c84: 001a movs r2, r3 - 8002c86: 687b ldr r3, [r7, #4] - 8002c88: 621a str r2, [r3, #32] + 8003540: 687b ldr r3, [r7, #4] + 8003542: 6a1b ldr r3, [r3, #32] + 8003544: 2210 movs r2, #16 + 8003546: 4393 bics r3, r2 + 8003548: 001a movs r2, r3 + 800354a: 687b ldr r3, [r7, #4] + 800354c: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; - 8002c8a: 687b ldr r3, [r7, #4] - 8002c8c: 685b ldr r3, [r3, #4] - 8002c8e: 613b str r3, [r7, #16] + 800354e: 687b ldr r3, [r7, #4] + 8003550: 685b ldr r3, [r3, #4] + 8003552: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; - 8002c90: 687b ldr r3, [r7, #4] - 8002c92: 699b ldr r3, [r3, #24] - 8002c94: 60fb str r3, [r7, #12] + 8003554: 687b ldr r3, [r7, #4] + 8003556: 699b ldr r3, [r3, #24] + 8003558: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; - 8002c96: 68fb ldr r3, [r7, #12] - 8002c98: 4a2c ldr r2, [pc, #176] @ (8002d4c ) - 8002c9a: 4013 ands r3, r2 - 8002c9c: 60fb str r3, [r7, #12] + 800355a: 68fb ldr r3, [r7, #12] + 800355c: 4a2c ldr r2, [pc, #176] @ (8003610 ) + 800355e: 4013 ands r3, r2 + 8003560: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC2S; - 8002c9e: 68fb ldr r3, [r7, #12] - 8002ca0: 4a2b ldr r2, [pc, #172] @ (8002d50 ) - 8002ca2: 4013 ands r3, r2 - 8002ca4: 60fb str r3, [r7, #12] + 8003562: 68fb ldr r3, [r7, #12] + 8003564: 4a2b ldr r2, [pc, #172] @ (8003614 ) + 8003566: 4013 ands r3, r2 + 8003568: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); - 8002ca6: 683b ldr r3, [r7, #0] - 8002ca8: 681b ldr r3, [r3, #0] - 8002caa: 021b lsls r3, r3, #8 - 8002cac: 68fa ldr r2, [r7, #12] - 8002cae: 4313 orrs r3, r2 - 8002cb0: 60fb str r3, [r7, #12] + 800356a: 683b ldr r3, [r7, #0] + 800356c: 681b ldr r3, [r3, #0] + 800356e: 021b lsls r3, r3, #8 + 8003570: 68fa ldr r2, [r7, #12] + 8003572: 4313 orrs r3, r2 + 8003574: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; - 8002cb2: 697b ldr r3, [r7, #20] - 8002cb4: 2220 movs r2, #32 - 8002cb6: 4393 bics r3, r2 - 8002cb8: 617b str r3, [r7, #20] + 8003576: 697b ldr r3, [r7, #20] + 8003578: 2220 movs r2, #32 + 800357a: 4393 bics r3, r2 + 800357c: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); - 8002cba: 683b ldr r3, [r7, #0] - 8002cbc: 689b ldr r3, [r3, #8] - 8002cbe: 011b lsls r3, r3, #4 - 8002cc0: 697a ldr r2, [r7, #20] - 8002cc2: 4313 orrs r3, r2 - 8002cc4: 617b str r3, [r7, #20] + 800357e: 683b ldr r3, [r7, #0] + 8003580: 689b ldr r3, [r3, #8] + 8003582: 011b lsls r3, r3, #4 + 8003584: 697a ldr r2, [r7, #20] + 8003586: 4313 orrs r3, r2 + 8003588: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) - 8002cc6: 687b ldr r3, [r7, #4] - 8002cc8: 4a22 ldr r2, [pc, #136] @ (8002d54 ) - 8002cca: 4293 cmp r3, r2 - 8002ccc: d10d bne.n 8002cea + 800358a: 687b ldr r3, [r7, #4] + 800358c: 4a22 ldr r2, [pc, #136] @ (8003618 ) + 800358e: 4293 cmp r3, r2 + 8003590: d10d bne.n 80035ae { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; - 8002cce: 697b ldr r3, [r7, #20] - 8002cd0: 2280 movs r2, #128 @ 0x80 - 8002cd2: 4393 bics r3, r2 - 8002cd4: 617b str r3, [r7, #20] + 8003592: 697b ldr r3, [r7, #20] + 8003594: 2280 movs r2, #128 @ 0x80 + 8003596: 4393 bics r3, r2 + 8003598: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); - 8002cd6: 683b ldr r3, [r7, #0] - 8002cd8: 68db ldr r3, [r3, #12] - 8002cda: 011b lsls r3, r3, #4 - 8002cdc: 697a ldr r2, [r7, #20] - 8002cde: 4313 orrs r3, r2 - 8002ce0: 617b str r3, [r7, #20] + 800359a: 683b ldr r3, [r7, #0] + 800359c: 68db ldr r3, [r3, #12] + 800359e: 011b lsls r3, r3, #4 + 80035a0: 697a ldr r2, [r7, #20] + 80035a2: 4313 orrs r3, r2 + 80035a4: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; - 8002ce2: 697b ldr r3, [r7, #20] - 8002ce4: 2240 movs r2, #64 @ 0x40 - 8002ce6: 4393 bics r3, r2 - 8002ce8: 617b str r3, [r7, #20] + 80035a6: 697b ldr r3, [r7, #20] + 80035a8: 2240 movs r2, #64 @ 0x40 + 80035aa: 4393 bics r3, r2 + 80035ac: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) - 8002cea: 687b ldr r3, [r7, #4] - 8002cec: 4a19 ldr r2, [pc, #100] @ (8002d54 ) - 8002cee: 4293 cmp r3, r2 - 8002cf0: d007 beq.n 8002d02 - 8002cf2: 687b ldr r3, [r7, #4] - 8002cf4: 4a18 ldr r2, [pc, #96] @ (8002d58 ) - 8002cf6: 4293 cmp r3, r2 - 8002cf8: d003 beq.n 8002d02 - 8002cfa: 687b ldr r3, [r7, #4] - 8002cfc: 4a17 ldr r2, [pc, #92] @ (8002d5c ) - 8002cfe: 4293 cmp r3, r2 - 8002d00: d113 bne.n 8002d2a + 80035ae: 687b ldr r3, [r7, #4] + 80035b0: 4a19 ldr r2, [pc, #100] @ (8003618 ) + 80035b2: 4293 cmp r3, r2 + 80035b4: d007 beq.n 80035c6 + 80035b6: 687b ldr r3, [r7, #4] + 80035b8: 4a18 ldr r2, [pc, #96] @ (800361c ) + 80035ba: 4293 cmp r3, r2 + 80035bc: d003 beq.n 80035c6 + 80035be: 687b ldr r3, [r7, #4] + 80035c0: 4a17 ldr r2, [pc, #92] @ (8003620 ) + 80035c2: 4293 cmp r3, r2 + 80035c4: d113 bne.n 80035ee /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; - 8002d02: 693b ldr r3, [r7, #16] - 8002d04: 4a16 ldr r2, [pc, #88] @ (8002d60 ) - 8002d06: 4013 ands r3, r2 - 8002d08: 613b str r3, [r7, #16] + 80035c6: 693b ldr r3, [r7, #16] + 80035c8: 4a16 ldr r2, [pc, #88] @ (8003624 ) + 80035ca: 4013 ands r3, r2 + 80035cc: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS2N; - 8002d0a: 693b ldr r3, [r7, #16] - 8002d0c: 4a15 ldr r2, [pc, #84] @ (8002d64 ) - 8002d0e: 4013 ands r3, r2 - 8002d10: 613b str r3, [r7, #16] + 80035ce: 693b ldr r3, [r7, #16] + 80035d0: 4a15 ldr r2, [pc, #84] @ (8003628 ) + 80035d2: 4013 ands r3, r2 + 80035d4: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); - 8002d12: 683b ldr r3, [r7, #0] - 8002d14: 695b ldr r3, [r3, #20] - 8002d16: 009b lsls r3, r3, #2 - 8002d18: 693a ldr r2, [r7, #16] - 8002d1a: 4313 orrs r3, r2 - 8002d1c: 613b str r3, [r7, #16] + 80035d6: 683b ldr r3, [r7, #0] + 80035d8: 695b ldr r3, [r3, #20] + 80035da: 009b lsls r3, r3, #2 + 80035dc: 693a ldr r2, [r7, #16] + 80035de: 4313 orrs r3, r2 + 80035e0: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); - 8002d1e: 683b ldr r3, [r7, #0] - 8002d20: 699b ldr r3, [r3, #24] - 8002d22: 009b lsls r3, r3, #2 - 8002d24: 693a ldr r2, [r7, #16] - 8002d26: 4313 orrs r3, r2 - 8002d28: 613b str r3, [r7, #16] + 80035e2: 683b ldr r3, [r7, #0] + 80035e4: 699b ldr r3, [r3, #24] + 80035e6: 009b lsls r3, r3, #2 + 80035e8: 693a ldr r2, [r7, #16] + 80035ea: 4313 orrs r3, r2 + 80035ec: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; - 8002d2a: 687b ldr r3, [r7, #4] - 8002d2c: 693a ldr r2, [r7, #16] - 8002d2e: 605a str r2, [r3, #4] + 80035ee: 687b ldr r3, [r7, #4] + 80035f0: 693a ldr r2, [r7, #16] + 80035f2: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; - 8002d30: 687b ldr r3, [r7, #4] - 8002d32: 68fa ldr r2, [r7, #12] - 8002d34: 619a str r2, [r3, #24] + 80035f4: 687b ldr r3, [r7, #4] + 80035f6: 68fa ldr r2, [r7, #12] + 80035f8: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; - 8002d36: 683b ldr r3, [r7, #0] - 8002d38: 685a ldr r2, [r3, #4] - 8002d3a: 687b ldr r3, [r7, #4] - 8002d3c: 639a str r2, [r3, #56] @ 0x38 + 80035fa: 683b ldr r3, [r7, #0] + 80035fc: 685a ldr r2, [r3, #4] + 80035fe: 687b ldr r3, [r7, #4] + 8003600: 639a str r2, [r3, #56] @ 0x38 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; - 8002d3e: 687b ldr r3, [r7, #4] - 8002d40: 697a ldr r2, [r7, #20] - 8002d42: 621a str r2, [r3, #32] + 8003602: 687b ldr r3, [r7, #4] + 8003604: 697a ldr r2, [r7, #20] + 8003606: 621a str r2, [r3, #32] } - 8002d44: 46c0 nop @ (mov r8, r8) - 8002d46: 46bd mov sp, r7 - 8002d48: b006 add sp, #24 - 8002d4a: bd80 pop {r7, pc} - 8002d4c: feff8fff .word 0xfeff8fff - 8002d50: fffffcff .word 0xfffffcff - 8002d54: 40012c00 .word 0x40012c00 - 8002d58: 40014400 .word 0x40014400 - 8002d5c: 40014800 .word 0x40014800 - 8002d60: fffffbff .word 0xfffffbff - 8002d64: fffff7ff .word 0xfffff7ff + 8003608: 46c0 nop @ (mov r8, r8) + 800360a: 46bd mov sp, r7 + 800360c: b006 add sp, #24 + 800360e: bd80 pop {r7, pc} + 8003610: feff8fff .word 0xfeff8fff + 8003614: fffffcff .word 0xfffffcff + 8003618: 40012c00 .word 0x40012c00 + 800361c: 40014400 .word 0x40014400 + 8003620: 40014800 .word 0x40014800 + 8003624: fffffbff .word 0xfffffbff + 8003628: fffff7ff .word 0xfffff7ff -08002d68 : +0800362c : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { - 8002d68: b580 push {r7, lr} - 8002d6a: b086 sub sp, #24 - 8002d6c: af00 add r7, sp, #0 - 8002d6e: 6078 str r0, [r7, #4] - 8002d70: 6039 str r1, [r7, #0] + 800362c: b580 push {r7, lr} + 800362e: b086 sub sp, #24 + 8003630: af00 add r7, sp, #0 + 8003632: 6078 str r0, [r7, #4] + 8003634: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; - 8002d72: 687b ldr r3, [r7, #4] - 8002d74: 6a1b ldr r3, [r3, #32] - 8002d76: 617b str r3, [r7, #20] + 8003636: 687b ldr r3, [r7, #4] + 8003638: 6a1b ldr r3, [r3, #32] + 800363a: 617b str r3, [r7, #20] /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; - 8002d78: 687b ldr r3, [r7, #4] - 8002d7a: 6a1b ldr r3, [r3, #32] - 8002d7c: 4a31 ldr r2, [pc, #196] @ (8002e44 ) - 8002d7e: 401a ands r2, r3 - 8002d80: 687b ldr r3, [r7, #4] - 8002d82: 621a str r2, [r3, #32] + 800363c: 687b ldr r3, [r7, #4] + 800363e: 6a1b ldr r3, [r3, #32] + 8003640: 4a31 ldr r2, [pc, #196] @ (8003708 ) + 8003642: 401a ands r2, r3 + 8003644: 687b ldr r3, [r7, #4] + 8003646: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; - 8002d84: 687b ldr r3, [r7, #4] - 8002d86: 685b ldr r3, [r3, #4] - 8002d88: 613b str r3, [r7, #16] + 8003648: 687b ldr r3, [r7, #4] + 800364a: 685b ldr r3, [r3, #4] + 800364c: 613b str r3, [r7, #16] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; - 8002d8a: 687b ldr r3, [r7, #4] - 8002d8c: 69db ldr r3, [r3, #28] - 8002d8e: 60fb str r3, [r7, #12] + 800364e: 687b ldr r3, [r7, #4] + 8003650: 69db ldr r3, [r3, #28] + 8003652: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; - 8002d90: 68fb ldr r3, [r7, #12] - 8002d92: 4a2d ldr r2, [pc, #180] @ (8002e48 ) - 8002d94: 4013 ands r3, r2 - 8002d96: 60fb str r3, [r7, #12] + 8003654: 68fb ldr r3, [r7, #12] + 8003656: 4a2d ldr r2, [pc, #180] @ (800370c ) + 8003658: 4013 ands r3, r2 + 800365a: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC3S; - 8002d98: 68fb ldr r3, [r7, #12] - 8002d9a: 2203 movs r2, #3 - 8002d9c: 4393 bics r3, r2 - 8002d9e: 60fb str r3, [r7, #12] + 800365c: 68fb ldr r3, [r7, #12] + 800365e: 2203 movs r2, #3 + 8003660: 4393 bics r3, r2 + 8003662: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; - 8002da0: 683b ldr r3, [r7, #0] - 8002da2: 681b ldr r3, [r3, #0] - 8002da4: 68fa ldr r2, [r7, #12] - 8002da6: 4313 orrs r3, r2 - 8002da8: 60fb str r3, [r7, #12] + 8003664: 683b ldr r3, [r7, #0] + 8003666: 681b ldr r3, [r3, #0] + 8003668: 68fa ldr r2, [r7, #12] + 800366a: 4313 orrs r3, r2 + 800366c: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; - 8002daa: 697b ldr r3, [r7, #20] - 8002dac: 4a27 ldr r2, [pc, #156] @ (8002e4c ) - 8002dae: 4013 ands r3, r2 - 8002db0: 617b str r3, [r7, #20] + 800366e: 697b ldr r3, [r7, #20] + 8003670: 4a27 ldr r2, [pc, #156] @ (8003710 ) + 8003672: 4013 ands r3, r2 + 8003674: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); - 8002db2: 683b ldr r3, [r7, #0] - 8002db4: 689b ldr r3, [r3, #8] - 8002db6: 021b lsls r3, r3, #8 - 8002db8: 697a ldr r2, [r7, #20] - 8002dba: 4313 orrs r3, r2 - 8002dbc: 617b str r3, [r7, #20] + 8003676: 683b ldr r3, [r7, #0] + 8003678: 689b ldr r3, [r3, #8] + 800367a: 021b lsls r3, r3, #8 + 800367c: 697a ldr r2, [r7, #20] + 800367e: 4313 orrs r3, r2 + 8003680: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) - 8002dbe: 687b ldr r3, [r7, #4] - 8002dc0: 4a23 ldr r2, [pc, #140] @ (8002e50 ) - 8002dc2: 4293 cmp r3, r2 - 8002dc4: d10d bne.n 8002de2 + 8003682: 687b ldr r3, [r7, #4] + 8003684: 4a23 ldr r2, [pc, #140] @ (8003714 ) + 8003686: 4293 cmp r3, r2 + 8003688: d10d bne.n 80036a6 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; - 8002dc6: 697b ldr r3, [r7, #20] - 8002dc8: 4a22 ldr r2, [pc, #136] @ (8002e54 ) - 8002dca: 4013 ands r3, r2 - 8002dcc: 617b str r3, [r7, #20] + 800368a: 697b ldr r3, [r7, #20] + 800368c: 4a22 ldr r2, [pc, #136] @ (8003718 ) + 800368e: 4013 ands r3, r2 + 8003690: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); - 8002dce: 683b ldr r3, [r7, #0] - 8002dd0: 68db ldr r3, [r3, #12] - 8002dd2: 021b lsls r3, r3, #8 - 8002dd4: 697a ldr r2, [r7, #20] - 8002dd6: 4313 orrs r3, r2 - 8002dd8: 617b str r3, [r7, #20] + 8003692: 683b ldr r3, [r7, #0] + 8003694: 68db ldr r3, [r3, #12] + 8003696: 021b lsls r3, r3, #8 + 8003698: 697a ldr r2, [r7, #20] + 800369a: 4313 orrs r3, r2 + 800369c: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; - 8002dda: 697b ldr r3, [r7, #20] - 8002ddc: 4a1e ldr r2, [pc, #120] @ (8002e58 ) - 8002dde: 4013 ands r3, r2 - 8002de0: 617b str r3, [r7, #20] + 800369e: 697b ldr r3, [r7, #20] + 80036a0: 4a1e ldr r2, [pc, #120] @ (800371c ) + 80036a2: 4013 ands r3, r2 + 80036a4: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) - 8002de2: 687b ldr r3, [r7, #4] - 8002de4: 4a1a ldr r2, [pc, #104] @ (8002e50 ) - 8002de6: 4293 cmp r3, r2 - 8002de8: d007 beq.n 8002dfa - 8002dea: 687b ldr r3, [r7, #4] - 8002dec: 4a1b ldr r2, [pc, #108] @ (8002e5c ) - 8002dee: 4293 cmp r3, r2 - 8002df0: d003 beq.n 8002dfa - 8002df2: 687b ldr r3, [r7, #4] - 8002df4: 4a1a ldr r2, [pc, #104] @ (8002e60 ) - 8002df6: 4293 cmp r3, r2 - 8002df8: d113 bne.n 8002e22 + 80036a6: 687b ldr r3, [r7, #4] + 80036a8: 4a1a ldr r2, [pc, #104] @ (8003714 ) + 80036aa: 4293 cmp r3, r2 + 80036ac: d007 beq.n 80036be + 80036ae: 687b ldr r3, [r7, #4] + 80036b0: 4a1b ldr r2, [pc, #108] @ (8003720 ) + 80036b2: 4293 cmp r3, r2 + 80036b4: d003 beq.n 80036be + 80036b6: 687b ldr r3, [r7, #4] + 80036b8: 4a1a ldr r2, [pc, #104] @ (8003724 ) + 80036ba: 4293 cmp r3, r2 + 80036bc: d113 bne.n 80036e6 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; - 8002dfa: 693b ldr r3, [r7, #16] - 8002dfc: 4a19 ldr r2, [pc, #100] @ (8002e64 ) - 8002dfe: 4013 ands r3, r2 - 8002e00: 613b str r3, [r7, #16] + 80036be: 693b ldr r3, [r7, #16] + 80036c0: 4a19 ldr r2, [pc, #100] @ (8003728 ) + 80036c2: 4013 ands r3, r2 + 80036c4: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS3N; - 8002e02: 693b ldr r3, [r7, #16] - 8002e04: 4a18 ldr r2, [pc, #96] @ (8002e68 ) - 8002e06: 4013 ands r3, r2 - 8002e08: 613b str r3, [r7, #16] + 80036c6: 693b ldr r3, [r7, #16] + 80036c8: 4a18 ldr r2, [pc, #96] @ (800372c ) + 80036ca: 4013 ands r3, r2 + 80036cc: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); - 8002e0a: 683b ldr r3, [r7, #0] - 8002e0c: 695b ldr r3, [r3, #20] - 8002e0e: 011b lsls r3, r3, #4 - 8002e10: 693a ldr r2, [r7, #16] - 8002e12: 4313 orrs r3, r2 - 8002e14: 613b str r3, [r7, #16] + 80036ce: 683b ldr r3, [r7, #0] + 80036d0: 695b ldr r3, [r3, #20] + 80036d2: 011b lsls r3, r3, #4 + 80036d4: 693a ldr r2, [r7, #16] + 80036d6: 4313 orrs r3, r2 + 80036d8: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); - 8002e16: 683b ldr r3, [r7, #0] - 8002e18: 699b ldr r3, [r3, #24] - 8002e1a: 011b lsls r3, r3, #4 - 8002e1c: 693a ldr r2, [r7, #16] - 8002e1e: 4313 orrs r3, r2 - 8002e20: 613b str r3, [r7, #16] + 80036da: 683b ldr r3, [r7, #0] + 80036dc: 699b ldr r3, [r3, #24] + 80036de: 011b lsls r3, r3, #4 + 80036e0: 693a ldr r2, [r7, #16] + 80036e2: 4313 orrs r3, r2 + 80036e4: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; - 8002e22: 687b ldr r3, [r7, #4] - 8002e24: 693a ldr r2, [r7, #16] - 8002e26: 605a str r2, [r3, #4] + 80036e6: 687b ldr r3, [r7, #4] + 80036e8: 693a ldr r2, [r7, #16] + 80036ea: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; - 8002e28: 687b ldr r3, [r7, #4] - 8002e2a: 68fa ldr r2, [r7, #12] - 8002e2c: 61da str r2, [r3, #28] + 80036ec: 687b ldr r3, [r7, #4] + 80036ee: 68fa ldr r2, [r7, #12] + 80036f0: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; - 8002e2e: 683b ldr r3, [r7, #0] - 8002e30: 685a ldr r2, [r3, #4] - 8002e32: 687b ldr r3, [r7, #4] - 8002e34: 63da str r2, [r3, #60] @ 0x3c + 80036f2: 683b ldr r3, [r7, #0] + 80036f4: 685a ldr r2, [r3, #4] + 80036f6: 687b ldr r3, [r7, #4] + 80036f8: 63da str r2, [r3, #60] @ 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; - 8002e36: 687b ldr r3, [r7, #4] - 8002e38: 697a ldr r2, [r7, #20] - 8002e3a: 621a str r2, [r3, #32] + 80036fa: 687b ldr r3, [r7, #4] + 80036fc: 697a ldr r2, [r7, #20] + 80036fe: 621a str r2, [r3, #32] } - 8002e3c: 46c0 nop @ (mov r8, r8) - 8002e3e: 46bd mov sp, r7 - 8002e40: b006 add sp, #24 - 8002e42: bd80 pop {r7, pc} - 8002e44: fffffeff .word 0xfffffeff - 8002e48: fffeff8f .word 0xfffeff8f - 8002e4c: fffffdff .word 0xfffffdff - 8002e50: 40012c00 .word 0x40012c00 - 8002e54: fffff7ff .word 0xfffff7ff - 8002e58: fffffbff .word 0xfffffbff - 8002e5c: 40014400 .word 0x40014400 - 8002e60: 40014800 .word 0x40014800 - 8002e64: ffffefff .word 0xffffefff - 8002e68: ffffdfff .word 0xffffdfff + 8003700: 46c0 nop @ (mov r8, r8) + 8003702: 46bd mov sp, r7 + 8003704: b006 add sp, #24 + 8003706: bd80 pop {r7, pc} + 8003708: fffffeff .word 0xfffffeff + 800370c: fffeff8f .word 0xfffeff8f + 8003710: fffffdff .word 0xfffffdff + 8003714: 40012c00 .word 0x40012c00 + 8003718: fffff7ff .word 0xfffff7ff + 800371c: fffffbff .word 0xfffffbff + 8003720: 40014400 .word 0x40014400 + 8003724: 40014800 .word 0x40014800 + 8003728: ffffefff .word 0xffffefff + 800372c: ffffdfff .word 0xffffdfff -08002e6c : +08003730 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { - 8002e6c: b580 push {r7, lr} - 8002e6e: b086 sub sp, #24 - 8002e70: af00 add r7, sp, #0 - 8002e72: 6078 str r0, [r7, #4] - 8002e74: 6039 str r1, [r7, #0] + 8003730: b580 push {r7, lr} + 8003732: b086 sub sp, #24 + 8003734: af00 add r7, sp, #0 + 8003736: 6078 str r0, [r7, #4] + 8003738: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; - 8002e76: 687b ldr r3, [r7, #4] - 8002e78: 6a1b ldr r3, [r3, #32] - 8002e7a: 613b str r3, [r7, #16] + 800373a: 687b ldr r3, [r7, #4] + 800373c: 6a1b ldr r3, [r3, #32] + 800373e: 613b str r3, [r7, #16] /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; - 8002e7c: 687b ldr r3, [r7, #4] - 8002e7e: 6a1b ldr r3, [r3, #32] - 8002e80: 4a24 ldr r2, [pc, #144] @ (8002f14 ) - 8002e82: 401a ands r2, r3 - 8002e84: 687b ldr r3, [r7, #4] - 8002e86: 621a str r2, [r3, #32] + 8003740: 687b ldr r3, [r7, #4] + 8003742: 6a1b ldr r3, [r3, #32] + 8003744: 4a24 ldr r2, [pc, #144] @ (80037d8 ) + 8003746: 401a ands r2, r3 + 8003748: 687b ldr r3, [r7, #4] + 800374a: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; - 8002e88: 687b ldr r3, [r7, #4] - 8002e8a: 685b ldr r3, [r3, #4] - 8002e8c: 617b str r3, [r7, #20] + 800374c: 687b ldr r3, [r7, #4] + 800374e: 685b ldr r3, [r3, #4] + 8003750: 617b str r3, [r7, #20] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; - 8002e8e: 687b ldr r3, [r7, #4] - 8002e90: 69db ldr r3, [r3, #28] - 8002e92: 60fb str r3, [r7, #12] + 8003752: 687b ldr r3, [r7, #4] + 8003754: 69db ldr r3, [r3, #28] + 8003756: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; - 8002e94: 68fb ldr r3, [r7, #12] - 8002e96: 4a20 ldr r2, [pc, #128] @ (8002f18 ) - 8002e98: 4013 ands r3, r2 - 8002e9a: 60fb str r3, [r7, #12] + 8003758: 68fb ldr r3, [r7, #12] + 800375a: 4a20 ldr r2, [pc, #128] @ (80037dc ) + 800375c: 4013 ands r3, r2 + 800375e: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC4S; - 8002e9c: 68fb ldr r3, [r7, #12] - 8002e9e: 4a1f ldr r2, [pc, #124] @ (8002f1c ) - 8002ea0: 4013 ands r3, r2 - 8002ea2: 60fb str r3, [r7, #12] + 8003760: 68fb ldr r3, [r7, #12] + 8003762: 4a1f ldr r2, [pc, #124] @ (80037e0 ) + 8003764: 4013 ands r3, r2 + 8003766: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); - 8002ea4: 683b ldr r3, [r7, #0] - 8002ea6: 681b ldr r3, [r3, #0] - 8002ea8: 021b lsls r3, r3, #8 - 8002eaa: 68fa ldr r2, [r7, #12] - 8002eac: 4313 orrs r3, r2 - 8002eae: 60fb str r3, [r7, #12] + 8003768: 683b ldr r3, [r7, #0] + 800376a: 681b ldr r3, [r3, #0] + 800376c: 021b lsls r3, r3, #8 + 800376e: 68fa ldr r2, [r7, #12] + 8003770: 4313 orrs r3, r2 + 8003772: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; - 8002eb0: 693b ldr r3, [r7, #16] - 8002eb2: 4a1b ldr r2, [pc, #108] @ (8002f20 ) - 8002eb4: 4013 ands r3, r2 - 8002eb6: 613b str r3, [r7, #16] + 8003774: 693b ldr r3, [r7, #16] + 8003776: 4a1b ldr r2, [pc, #108] @ (80037e4 ) + 8003778: 4013 ands r3, r2 + 800377a: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); - 8002eb8: 683b ldr r3, [r7, #0] - 8002eba: 689b ldr r3, [r3, #8] - 8002ebc: 031b lsls r3, r3, #12 - 8002ebe: 693a ldr r2, [r7, #16] - 8002ec0: 4313 orrs r3, r2 - 8002ec2: 613b str r3, [r7, #16] + 800377c: 683b ldr r3, [r7, #0] + 800377e: 689b ldr r3, [r3, #8] + 8003780: 031b lsls r3, r3, #12 + 8003782: 693a ldr r2, [r7, #16] + 8003784: 4313 orrs r3, r2 + 8003786: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) - 8002ec4: 687b ldr r3, [r7, #4] - 8002ec6: 4a17 ldr r2, [pc, #92] @ (8002f24 ) - 8002ec8: 4293 cmp r3, r2 - 8002eca: d007 beq.n 8002edc - 8002ecc: 687b ldr r3, [r7, #4] - 8002ece: 4a16 ldr r2, [pc, #88] @ (8002f28 ) - 8002ed0: 4293 cmp r3, r2 - 8002ed2: d003 beq.n 8002edc - 8002ed4: 687b ldr r3, [r7, #4] - 8002ed6: 4a15 ldr r2, [pc, #84] @ (8002f2c ) - 8002ed8: 4293 cmp r3, r2 - 8002eda: d109 bne.n 8002ef0 + 8003788: 687b ldr r3, [r7, #4] + 800378a: 4a17 ldr r2, [pc, #92] @ (80037e8 ) + 800378c: 4293 cmp r3, r2 + 800378e: d007 beq.n 80037a0 + 8003790: 687b ldr r3, [r7, #4] + 8003792: 4a16 ldr r2, [pc, #88] @ (80037ec ) + 8003794: 4293 cmp r3, r2 + 8003796: d003 beq.n 80037a0 + 8003798: 687b ldr r3, [r7, #4] + 800379a: 4a15 ldr r2, [pc, #84] @ (80037f0 ) + 800379c: 4293 cmp r3, r2 + 800379e: d109 bne.n 80037b4 { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; - 8002edc: 697b ldr r3, [r7, #20] - 8002ede: 4a14 ldr r2, [pc, #80] @ (8002f30 ) - 8002ee0: 4013 ands r3, r2 - 8002ee2: 617b str r3, [r7, #20] + 80037a0: 697b ldr r3, [r7, #20] + 80037a2: 4a14 ldr r2, [pc, #80] @ (80037f4 ) + 80037a4: 4013 ands r3, r2 + 80037a6: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); - 8002ee4: 683b ldr r3, [r7, #0] - 8002ee6: 695b ldr r3, [r3, #20] - 8002ee8: 019b lsls r3, r3, #6 - 8002eea: 697a ldr r2, [r7, #20] - 8002eec: 4313 orrs r3, r2 - 8002eee: 617b str r3, [r7, #20] + 80037a8: 683b ldr r3, [r7, #0] + 80037aa: 695b ldr r3, [r3, #20] + 80037ac: 019b lsls r3, r3, #6 + 80037ae: 697a ldr r2, [r7, #20] + 80037b0: 4313 orrs r3, r2 + 80037b2: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; - 8002ef0: 687b ldr r3, [r7, #4] - 8002ef2: 697a ldr r2, [r7, #20] - 8002ef4: 605a str r2, [r3, #4] + 80037b4: 687b ldr r3, [r7, #4] + 80037b6: 697a ldr r2, [r7, #20] + 80037b8: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; - 8002ef6: 687b ldr r3, [r7, #4] - 8002ef8: 68fa ldr r2, [r7, #12] - 8002efa: 61da str r2, [r3, #28] + 80037ba: 687b ldr r3, [r7, #4] + 80037bc: 68fa ldr r2, [r7, #12] + 80037be: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; - 8002efc: 683b ldr r3, [r7, #0] - 8002efe: 685a ldr r2, [r3, #4] - 8002f00: 687b ldr r3, [r7, #4] - 8002f02: 641a str r2, [r3, #64] @ 0x40 + 80037c0: 683b ldr r3, [r7, #0] + 80037c2: 685a ldr r2, [r3, #4] + 80037c4: 687b ldr r3, [r7, #4] + 80037c6: 641a str r2, [r3, #64] @ 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; - 8002f04: 687b ldr r3, [r7, #4] - 8002f06: 693a ldr r2, [r7, #16] - 8002f08: 621a str r2, [r3, #32] + 80037c8: 687b ldr r3, [r7, #4] + 80037ca: 693a ldr r2, [r7, #16] + 80037cc: 621a str r2, [r3, #32] } - 8002f0a: 46c0 nop @ (mov r8, r8) - 8002f0c: 46bd mov sp, r7 - 8002f0e: b006 add sp, #24 - 8002f10: bd80 pop {r7, pc} - 8002f12: 46c0 nop @ (mov r8, r8) - 8002f14: ffffefff .word 0xffffefff - 8002f18: feff8fff .word 0xfeff8fff - 8002f1c: fffffcff .word 0xfffffcff - 8002f20: ffffdfff .word 0xffffdfff - 8002f24: 40012c00 .word 0x40012c00 - 8002f28: 40014400 .word 0x40014400 - 8002f2c: 40014800 .word 0x40014800 - 8002f30: ffffbfff .word 0xffffbfff + 80037ce: 46c0 nop @ (mov r8, r8) + 80037d0: 46bd mov sp, r7 + 80037d2: b006 add sp, #24 + 80037d4: bd80 pop {r7, pc} + 80037d6: 46c0 nop @ (mov r8, r8) + 80037d8: ffffefff .word 0xffffefff + 80037dc: feff8fff .word 0xfeff8fff + 80037e0: fffffcff .word 0xfffffcff + 80037e4: ffffdfff .word 0xffffdfff + 80037e8: 40012c00 .word 0x40012c00 + 80037ec: 40014400 .word 0x40014400 + 80037f0: 40014800 .word 0x40014800 + 80037f4: ffffbfff .word 0xffffbfff -08002f34 : +080037f8 : * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { - 8002f34: b580 push {r7, lr} - 8002f36: b086 sub sp, #24 - 8002f38: af00 add r7, sp, #0 - 8002f3a: 6078 str r0, [r7, #4] - 8002f3c: 6039 str r1, [r7, #0] + 80037f8: b580 push {r7, lr} + 80037fa: b086 sub sp, #24 + 80037fc: af00 add r7, sp, #0 + 80037fe: 6078 str r0, [r7, #4] + 8003800: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; - 8002f3e: 687b ldr r3, [r7, #4] - 8002f40: 6a1b ldr r3, [r3, #32] - 8002f42: 613b str r3, [r7, #16] + 8003802: 687b ldr r3, [r7, #4] + 8003804: 6a1b ldr r3, [r3, #32] + 8003806: 613b str r3, [r7, #16] /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC5E; - 8002f44: 687b ldr r3, [r7, #4] - 8002f46: 6a1b ldr r3, [r3, #32] - 8002f48: 4a21 ldr r2, [pc, #132] @ (8002fd0 ) - 8002f4a: 401a ands r2, r3 - 8002f4c: 687b ldr r3, [r7, #4] - 8002f4e: 621a str r2, [r3, #32] + 8003808: 687b ldr r3, [r7, #4] + 800380a: 6a1b ldr r3, [r3, #32] + 800380c: 4a21 ldr r2, [pc, #132] @ (8003894 ) + 800380e: 401a ands r2, r3 + 8003810: 687b ldr r3, [r7, #4] + 8003812: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; - 8002f50: 687b ldr r3, [r7, #4] - 8002f52: 685b ldr r3, [r3, #4] - 8002f54: 617b str r3, [r7, #20] + 8003814: 687b ldr r3, [r7, #4] + 8003816: 685b ldr r3, [r3, #4] + 8003818: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR3; - 8002f56: 687b ldr r3, [r7, #4] - 8002f58: 6d5b ldr r3, [r3, #84] @ 0x54 - 8002f5a: 60fb str r3, [r7, #12] + 800381a: 687b ldr r3, [r7, #4] + 800381c: 6d5b ldr r3, [r3, #84] @ 0x54 + 800381e: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC5M); - 8002f5c: 68fb ldr r3, [r7, #12] - 8002f5e: 4a1d ldr r2, [pc, #116] @ (8002fd4 ) - 8002f60: 4013 ands r3, r2 - 8002f62: 60fb str r3, [r7, #12] + 8003820: 68fb ldr r3, [r7, #12] + 8003822: 4a1d ldr r2, [pc, #116] @ (8003898 ) + 8003824: 4013 ands r3, r2 + 8003826: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; - 8002f64: 683b ldr r3, [r7, #0] - 8002f66: 681b ldr r3, [r3, #0] - 8002f68: 68fa ldr r2, [r7, #12] - 8002f6a: 4313 orrs r3, r2 - 8002f6c: 60fb str r3, [r7, #12] + 8003828: 683b ldr r3, [r7, #0] + 800382a: 681b ldr r3, [r3, #0] + 800382c: 68fa ldr r2, [r7, #12] + 800382e: 4313 orrs r3, r2 + 8003830: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC5P; - 8002f6e: 693b ldr r3, [r7, #16] - 8002f70: 4a19 ldr r2, [pc, #100] @ (8002fd8 ) - 8002f72: 4013 ands r3, r2 - 8002f74: 613b str r3, [r7, #16] + 8003832: 693b ldr r3, [r7, #16] + 8003834: 4a19 ldr r2, [pc, #100] @ (800389c ) + 8003836: 4013 ands r3, r2 + 8003838: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 16U); - 8002f76: 683b ldr r3, [r7, #0] - 8002f78: 689b ldr r3, [r3, #8] - 8002f7a: 041b lsls r3, r3, #16 - 8002f7c: 693a ldr r2, [r7, #16] - 8002f7e: 4313 orrs r3, r2 - 8002f80: 613b str r3, [r7, #16] + 800383a: 683b ldr r3, [r7, #0] + 800383c: 689b ldr r3, [r3, #8] + 800383e: 041b lsls r3, r3, #16 + 8003840: 693a ldr r2, [r7, #16] + 8003842: 4313 orrs r3, r2 + 8003844: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) - 8002f82: 687b ldr r3, [r7, #4] - 8002f84: 4a15 ldr r2, [pc, #84] @ (8002fdc ) - 8002f86: 4293 cmp r3, r2 - 8002f88: d007 beq.n 8002f9a - 8002f8a: 687b ldr r3, [r7, #4] - 8002f8c: 4a14 ldr r2, [pc, #80] @ (8002fe0 ) - 8002f8e: 4293 cmp r3, r2 - 8002f90: d003 beq.n 8002f9a - 8002f92: 687b ldr r3, [r7, #4] - 8002f94: 4a13 ldr r2, [pc, #76] @ (8002fe4 ) - 8002f96: 4293 cmp r3, r2 - 8002f98: d109 bne.n 8002fae + 8003846: 687b ldr r3, [r7, #4] + 8003848: 4a15 ldr r2, [pc, #84] @ (80038a0 ) + 800384a: 4293 cmp r3, r2 + 800384c: d007 beq.n 800385e + 800384e: 687b ldr r3, [r7, #4] + 8003850: 4a14 ldr r2, [pc, #80] @ (80038a4 ) + 8003852: 4293 cmp r3, r2 + 8003854: d003 beq.n 800385e + 8003856: 687b ldr r3, [r7, #4] + 8003858: 4a13 ldr r2, [pc, #76] @ (80038a8 ) + 800385a: 4293 cmp r3, r2 + 800385c: d109 bne.n 8003872 { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS5; - 8002f9a: 697b ldr r3, [r7, #20] - 8002f9c: 4a0c ldr r2, [pc, #48] @ (8002fd0 ) - 8002f9e: 4013 ands r3, r2 - 8002fa0: 617b str r3, [r7, #20] + 800385e: 697b ldr r3, [r7, #20] + 8003860: 4a0c ldr r2, [pc, #48] @ (8003894 ) + 8003862: 4013 ands r3, r2 + 8003864: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 8U); - 8002fa2: 683b ldr r3, [r7, #0] - 8002fa4: 695b ldr r3, [r3, #20] - 8002fa6: 021b lsls r3, r3, #8 - 8002fa8: 697a ldr r2, [r7, #20] - 8002faa: 4313 orrs r3, r2 - 8002fac: 617b str r3, [r7, #20] + 8003866: 683b ldr r3, [r7, #0] + 8003868: 695b ldr r3, [r3, #20] + 800386a: 021b lsls r3, r3, #8 + 800386c: 697a ldr r2, [r7, #20] + 800386e: 4313 orrs r3, r2 + 8003870: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; - 8002fae: 687b ldr r3, [r7, #4] - 8002fb0: 697a ldr r2, [r7, #20] - 8002fb2: 605a str r2, [r3, #4] + 8003872: 687b ldr r3, [r7, #4] + 8003874: 697a ldr r2, [r7, #20] + 8003876: 605a str r2, [r3, #4] /* Write to TIMx CCMR3 */ TIMx->CCMR3 = tmpccmrx; - 8002fb4: 687b ldr r3, [r7, #4] - 8002fb6: 68fa ldr r2, [r7, #12] - 8002fb8: 655a str r2, [r3, #84] @ 0x54 + 8003878: 687b ldr r3, [r7, #4] + 800387a: 68fa ldr r2, [r7, #12] + 800387c: 655a str r2, [r3, #84] @ 0x54 /* Set the Capture Compare Register value */ TIMx->CCR5 = OC_Config->Pulse; - 8002fba: 683b ldr r3, [r7, #0] - 8002fbc: 685a ldr r2, [r3, #4] - 8002fbe: 687b ldr r3, [r7, #4] - 8002fc0: 659a str r2, [r3, #88] @ 0x58 + 800387e: 683b ldr r3, [r7, #0] + 8003880: 685a ldr r2, [r3, #4] + 8003882: 687b ldr r3, [r7, #4] + 8003884: 659a str r2, [r3, #88] @ 0x58 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; - 8002fc2: 687b ldr r3, [r7, #4] - 8002fc4: 693a ldr r2, [r7, #16] - 8002fc6: 621a str r2, [r3, #32] + 8003886: 687b ldr r3, [r7, #4] + 8003888: 693a ldr r2, [r7, #16] + 800388a: 621a str r2, [r3, #32] } - 8002fc8: 46c0 nop @ (mov r8, r8) - 8002fca: 46bd mov sp, r7 - 8002fcc: b006 add sp, #24 - 8002fce: bd80 pop {r7, pc} - 8002fd0: fffeffff .word 0xfffeffff - 8002fd4: fffeff8f .word 0xfffeff8f - 8002fd8: fffdffff .word 0xfffdffff - 8002fdc: 40012c00 .word 0x40012c00 - 8002fe0: 40014400 .word 0x40014400 - 8002fe4: 40014800 .word 0x40014800 + 800388c: 46c0 nop @ (mov r8, r8) + 800388e: 46bd mov sp, r7 + 8003890: b006 add sp, #24 + 8003892: bd80 pop {r7, pc} + 8003894: fffeffff .word 0xfffeffff + 8003898: fffeff8f .word 0xfffeff8f + 800389c: fffdffff .word 0xfffdffff + 80038a0: 40012c00 .word 0x40012c00 + 80038a4: 40014400 .word 0x40014400 + 80038a8: 40014800 .word 0x40014800 -08002fe8 : +080038ac : * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { - 8002fe8: b580 push {r7, lr} - 8002fea: b086 sub sp, #24 - 8002fec: af00 add r7, sp, #0 - 8002fee: 6078 str r0, [r7, #4] - 8002ff0: 6039 str r1, [r7, #0] + 80038ac: b580 push {r7, lr} + 80038ae: b086 sub sp, #24 + 80038b0: af00 add r7, sp, #0 + 80038b2: 6078 str r0, [r7, #4] + 80038b4: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; - 8002ff2: 687b ldr r3, [r7, #4] - 8002ff4: 6a1b ldr r3, [r3, #32] - 8002ff6: 613b str r3, [r7, #16] + 80038b6: 687b ldr r3, [r7, #4] + 80038b8: 6a1b ldr r3, [r3, #32] + 80038ba: 613b str r3, [r7, #16] /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC6E; - 8002ff8: 687b ldr r3, [r7, #4] - 8002ffa: 6a1b ldr r3, [r3, #32] - 8002ffc: 4a22 ldr r2, [pc, #136] @ (8003088 ) - 8002ffe: 401a ands r2, r3 - 8003000: 687b ldr r3, [r7, #4] - 8003002: 621a str r2, [r3, #32] + 80038bc: 687b ldr r3, [r7, #4] + 80038be: 6a1b ldr r3, [r3, #32] + 80038c0: 4a22 ldr r2, [pc, #136] @ (800394c ) + 80038c2: 401a ands r2, r3 + 80038c4: 687b ldr r3, [r7, #4] + 80038c6: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; - 8003004: 687b ldr r3, [r7, #4] - 8003006: 685b ldr r3, [r3, #4] - 8003008: 617b str r3, [r7, #20] + 80038c8: 687b ldr r3, [r7, #4] + 80038ca: 685b ldr r3, [r3, #4] + 80038cc: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR3; - 800300a: 687b ldr r3, [r7, #4] - 800300c: 6d5b ldr r3, [r3, #84] @ 0x54 - 800300e: 60fb str r3, [r7, #12] + 80038ce: 687b ldr r3, [r7, #4] + 80038d0: 6d5b ldr r3, [r3, #84] @ 0x54 + 80038d2: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC6M); - 8003010: 68fb ldr r3, [r7, #12] - 8003012: 4a1e ldr r2, [pc, #120] @ (800308c ) - 8003014: 4013 ands r3, r2 - 8003016: 60fb str r3, [r7, #12] + 80038d4: 68fb ldr r3, [r7, #12] + 80038d6: 4a1e ldr r2, [pc, #120] @ (8003950 ) + 80038d8: 4013 ands r3, r2 + 80038da: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); - 8003018: 683b ldr r3, [r7, #0] - 800301a: 681b ldr r3, [r3, #0] - 800301c: 021b lsls r3, r3, #8 - 800301e: 68fa ldr r2, [r7, #12] - 8003020: 4313 orrs r3, r2 - 8003022: 60fb str r3, [r7, #12] + 80038dc: 683b ldr r3, [r7, #0] + 80038de: 681b ldr r3, [r3, #0] + 80038e0: 021b lsls r3, r3, #8 + 80038e2: 68fa ldr r2, [r7, #12] + 80038e4: 4313 orrs r3, r2 + 80038e6: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= (uint32_t)~TIM_CCER_CC6P; - 8003024: 693b ldr r3, [r7, #16] - 8003026: 4a1a ldr r2, [pc, #104] @ (8003090 ) - 8003028: 4013 ands r3, r2 - 800302a: 613b str r3, [r7, #16] + 80038e8: 693b ldr r3, [r7, #16] + 80038ea: 4a1a ldr r2, [pc, #104] @ (8003954 ) + 80038ec: 4013 ands r3, r2 + 80038ee: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 20U); - 800302c: 683b ldr r3, [r7, #0] - 800302e: 689b ldr r3, [r3, #8] - 8003030: 051b lsls r3, r3, #20 - 8003032: 693a ldr r2, [r7, #16] - 8003034: 4313 orrs r3, r2 - 8003036: 613b str r3, [r7, #16] + 80038f0: 683b ldr r3, [r7, #0] + 80038f2: 689b ldr r3, [r3, #8] + 80038f4: 051b lsls r3, r3, #20 + 80038f6: 693a ldr r2, [r7, #16] + 80038f8: 4313 orrs r3, r2 + 80038fa: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) - 8003038: 687b ldr r3, [r7, #4] - 800303a: 4a16 ldr r2, [pc, #88] @ (8003094 ) - 800303c: 4293 cmp r3, r2 - 800303e: d007 beq.n 8003050 - 8003040: 687b ldr r3, [r7, #4] - 8003042: 4a15 ldr r2, [pc, #84] @ (8003098 ) - 8003044: 4293 cmp r3, r2 - 8003046: d003 beq.n 8003050 - 8003048: 687b ldr r3, [r7, #4] - 800304a: 4a14 ldr r2, [pc, #80] @ (800309c ) - 800304c: 4293 cmp r3, r2 - 800304e: d109 bne.n 8003064 + 80038fc: 687b ldr r3, [r7, #4] + 80038fe: 4a16 ldr r2, [pc, #88] @ (8003958 ) + 8003900: 4293 cmp r3, r2 + 8003902: d007 beq.n 8003914 + 8003904: 687b ldr r3, [r7, #4] + 8003906: 4a15 ldr r2, [pc, #84] @ (800395c ) + 8003908: 4293 cmp r3, r2 + 800390a: d003 beq.n 8003914 + 800390c: 687b ldr r3, [r7, #4] + 800390e: 4a14 ldr r2, [pc, #80] @ (8003960 ) + 8003910: 4293 cmp r3, r2 + 8003912: d109 bne.n 8003928 { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS6; - 8003050: 697b ldr r3, [r7, #20] - 8003052: 4a13 ldr r2, [pc, #76] @ (80030a0 ) - 8003054: 4013 ands r3, r2 - 8003056: 617b str r3, [r7, #20] + 8003914: 697b ldr r3, [r7, #20] + 8003916: 4a13 ldr r2, [pc, #76] @ (8003964 ) + 8003918: 4013 ands r3, r2 + 800391a: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 10U); - 8003058: 683b ldr r3, [r7, #0] - 800305a: 695b ldr r3, [r3, #20] - 800305c: 029b lsls r3, r3, #10 - 800305e: 697a ldr r2, [r7, #20] - 8003060: 4313 orrs r3, r2 - 8003062: 617b str r3, [r7, #20] + 800391c: 683b ldr r3, [r7, #0] + 800391e: 695b ldr r3, [r3, #20] + 8003920: 029b lsls r3, r3, #10 + 8003922: 697a ldr r2, [r7, #20] + 8003924: 4313 orrs r3, r2 + 8003926: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; - 8003064: 687b ldr r3, [r7, #4] - 8003066: 697a ldr r2, [r7, #20] - 8003068: 605a str r2, [r3, #4] + 8003928: 687b ldr r3, [r7, #4] + 800392a: 697a ldr r2, [r7, #20] + 800392c: 605a str r2, [r3, #4] /* Write to TIMx CCMR3 */ TIMx->CCMR3 = tmpccmrx; - 800306a: 687b ldr r3, [r7, #4] - 800306c: 68fa ldr r2, [r7, #12] - 800306e: 655a str r2, [r3, #84] @ 0x54 + 800392e: 687b ldr r3, [r7, #4] + 8003930: 68fa ldr r2, [r7, #12] + 8003932: 655a str r2, [r3, #84] @ 0x54 /* Set the Capture Compare Register value */ TIMx->CCR6 = OC_Config->Pulse; - 8003070: 683b ldr r3, [r7, #0] - 8003072: 685a ldr r2, [r3, #4] - 8003074: 687b ldr r3, [r7, #4] - 8003076: 65da str r2, [r3, #92] @ 0x5c + 8003934: 683b ldr r3, [r7, #0] + 8003936: 685a ldr r2, [r3, #4] + 8003938: 687b ldr r3, [r7, #4] + 800393a: 65da str r2, [r3, #92] @ 0x5c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; - 8003078: 687b ldr r3, [r7, #4] - 800307a: 693a ldr r2, [r7, #16] - 800307c: 621a str r2, [r3, #32] + 800393c: 687b ldr r3, [r7, #4] + 800393e: 693a ldr r2, [r7, #16] + 8003940: 621a str r2, [r3, #32] } - 800307e: 46c0 nop @ (mov r8, r8) - 8003080: 46bd mov sp, r7 - 8003082: b006 add sp, #24 - 8003084: bd80 pop {r7, pc} - 8003086: 46c0 nop @ (mov r8, r8) - 8003088: ffefffff .word 0xffefffff - 800308c: feff8fff .word 0xfeff8fff - 8003090: ffdfffff .word 0xffdfffff - 8003094: 40012c00 .word 0x40012c00 - 8003098: 40014400 .word 0x40014400 - 800309c: 40014800 .word 0x40014800 - 80030a0: fffbffff .word 0xfffbffff + 8003942: 46c0 nop @ (mov r8, r8) + 8003944: 46bd mov sp, r7 + 8003946: b006 add sp, #24 + 8003948: bd80 pop {r7, pc} + 800394a: 46c0 nop @ (mov r8, r8) + 800394c: ffefffff .word 0xffefffff + 8003950: feff8fff .word 0xfeff8fff + 8003954: ffdfffff .word 0xffdfffff + 8003958: 40012c00 .word 0x40012c00 + 800395c: 40014400 .word 0x40014400 + 8003960: 40014800 .word 0x40014800 + 8003964: fffbffff .word 0xfffbffff -080030a4 : +08003968 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { - 80030a4: b580 push {r7, lr} - 80030a6: b086 sub sp, #24 - 80030a8: af00 add r7, sp, #0 - 80030aa: 60f8 str r0, [r7, #12] - 80030ac: 60b9 str r1, [r7, #8] - 80030ae: 607a str r2, [r7, #4] + 8003968: b580 push {r7, lr} + 800396a: b086 sub sp, #24 + 800396c: af00 add r7, sp, #0 + 800396e: 60f8 str r0, [r7, #12] + 8003970: 60b9 str r1, [r7, #8] + 8003972: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; - 80030b0: 68fb ldr r3, [r7, #12] - 80030b2: 6a1b ldr r3, [r3, #32] - 80030b4: 617b str r3, [r7, #20] + 8003974: 68fb ldr r3, [r7, #12] + 8003976: 6a1b ldr r3, [r3, #32] + 8003978: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC1E; - 80030b6: 68fb ldr r3, [r7, #12] - 80030b8: 6a1b ldr r3, [r3, #32] - 80030ba: 2201 movs r2, #1 - 80030bc: 4393 bics r3, r2 - 80030be: 001a movs r2, r3 - 80030c0: 68fb ldr r3, [r7, #12] - 80030c2: 621a str r2, [r3, #32] + 800397a: 68fb ldr r3, [r7, #12] + 800397c: 6a1b ldr r3, [r3, #32] + 800397e: 2201 movs r2, #1 + 8003980: 4393 bics r3, r2 + 8003982: 001a movs r2, r3 + 8003984: 68fb ldr r3, [r7, #12] + 8003986: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; - 80030c4: 68fb ldr r3, [r7, #12] - 80030c6: 699b ldr r3, [r3, #24] - 80030c8: 613b str r3, [r7, #16] + 8003988: 68fb ldr r3, [r7, #12] + 800398a: 699b ldr r3, [r3, #24] + 800398c: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; - 80030ca: 693b ldr r3, [r7, #16] - 80030cc: 22f0 movs r2, #240 @ 0xf0 - 80030ce: 4393 bics r3, r2 - 80030d0: 613b str r3, [r7, #16] + 800398e: 693b ldr r3, [r7, #16] + 8003990: 22f0 movs r2, #240 @ 0xf0 + 8003992: 4393 bics r3, r2 + 8003994: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 4U); - 80030d2: 687b ldr r3, [r7, #4] - 80030d4: 011b lsls r3, r3, #4 - 80030d6: 693a ldr r2, [r7, #16] - 80030d8: 4313 orrs r3, r2 - 80030da: 613b str r3, [r7, #16] + 8003996: 687b ldr r3, [r7, #4] + 8003998: 011b lsls r3, r3, #4 + 800399a: 693a ldr r2, [r7, #16] + 800399c: 4313 orrs r3, r2 + 800399e: 613b str r3, [r7, #16] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); - 80030dc: 697b ldr r3, [r7, #20] - 80030de: 220a movs r2, #10 - 80030e0: 4393 bics r3, r2 - 80030e2: 617b str r3, [r7, #20] + 80039a0: 697b ldr r3, [r7, #20] + 80039a2: 220a movs r2, #10 + 80039a4: 4393 bics r3, r2 + 80039a6: 617b str r3, [r7, #20] tmpccer |= TIM_ICPolarity; - 80030e4: 697a ldr r2, [r7, #20] - 80030e6: 68bb ldr r3, [r7, #8] - 80030e8: 4313 orrs r3, r2 - 80030ea: 617b str r3, [r7, #20] + 80039a8: 697a ldr r2, [r7, #20] + 80039aa: 68bb ldr r3, [r7, #8] + 80039ac: 4313 orrs r3, r2 + 80039ae: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; - 80030ec: 68fb ldr r3, [r7, #12] - 80030ee: 693a ldr r2, [r7, #16] - 80030f0: 619a str r2, [r3, #24] + 80039b0: 68fb ldr r3, [r7, #12] + 80039b2: 693a ldr r2, [r7, #16] + 80039b4: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; - 80030f2: 68fb ldr r3, [r7, #12] - 80030f4: 697a ldr r2, [r7, #20] - 80030f6: 621a str r2, [r3, #32] + 80039b6: 68fb ldr r3, [r7, #12] + 80039b8: 697a ldr r2, [r7, #20] + 80039ba: 621a str r2, [r3, #32] } - 80030f8: 46c0 nop @ (mov r8, r8) - 80030fa: 46bd mov sp, r7 - 80030fc: b006 add sp, #24 - 80030fe: bd80 pop {r7, pc} + 80039bc: 46c0 nop @ (mov r8, r8) + 80039be: 46bd mov sp, r7 + 80039c0: b006 add sp, #24 + 80039c2: bd80 pop {r7, pc} -08003100 : +080039c4 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { - 8003100: b580 push {r7, lr} - 8003102: b086 sub sp, #24 - 8003104: af00 add r7, sp, #0 - 8003106: 60f8 str r0, [r7, #12] - 8003108: 60b9 str r1, [r7, #8] - 800310a: 607a str r2, [r7, #4] + 80039c4: b580 push {r7, lr} + 80039c6: b086 sub sp, #24 + 80039c8: af00 add r7, sp, #0 + 80039ca: 60f8 str r0, [r7, #12] + 80039cc: 60b9 str r1, [r7, #8] + 80039ce: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ tmpccer = TIMx->CCER; - 800310c: 68fb ldr r3, [r7, #12] - 800310e: 6a1b ldr r3, [r3, #32] - 8003110: 617b str r3, [r7, #20] + 80039d0: 68fb ldr r3, [r7, #12] + 80039d2: 6a1b ldr r3, [r3, #32] + 80039d4: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC2E; - 8003112: 68fb ldr r3, [r7, #12] - 8003114: 6a1b ldr r3, [r3, #32] - 8003116: 2210 movs r2, #16 - 8003118: 4393 bics r3, r2 - 800311a: 001a movs r2, r3 - 800311c: 68fb ldr r3, [r7, #12] - 800311e: 621a str r2, [r3, #32] + 80039d6: 68fb ldr r3, [r7, #12] + 80039d8: 6a1b ldr r3, [r3, #32] + 80039da: 2210 movs r2, #16 + 80039dc: 4393 bics r3, r2 + 80039de: 001a movs r2, r3 + 80039e0: 68fb ldr r3, [r7, #12] + 80039e2: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; - 8003120: 68fb ldr r3, [r7, #12] - 8003122: 699b ldr r3, [r3, #24] - 8003124: 613b str r3, [r7, #16] + 80039e4: 68fb ldr r3, [r7, #12] + 80039e6: 699b ldr r3, [r3, #24] + 80039e8: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; - 8003126: 693b ldr r3, [r7, #16] - 8003128: 4a0d ldr r2, [pc, #52] @ (8003160 ) - 800312a: 4013 ands r3, r2 - 800312c: 613b str r3, [r7, #16] + 80039ea: 693b ldr r3, [r7, #16] + 80039ec: 4a0d ldr r2, [pc, #52] @ (8003a24 ) + 80039ee: 4013 ands r3, r2 + 80039f0: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 12U); - 800312e: 687b ldr r3, [r7, #4] - 8003130: 031b lsls r3, r3, #12 - 8003132: 693a ldr r2, [r7, #16] - 8003134: 4313 orrs r3, r2 - 8003136: 613b str r3, [r7, #16] + 80039f2: 687b ldr r3, [r7, #4] + 80039f4: 031b lsls r3, r3, #12 + 80039f6: 693a ldr r2, [r7, #16] + 80039f8: 4313 orrs r3, r2 + 80039fa: 613b str r3, [r7, #16] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - 8003138: 697b ldr r3, [r7, #20] - 800313a: 22a0 movs r2, #160 @ 0xa0 - 800313c: 4393 bics r3, r2 - 800313e: 617b str r3, [r7, #20] + 80039fc: 697b ldr r3, [r7, #20] + 80039fe: 22a0 movs r2, #160 @ 0xa0 + 8003a00: 4393 bics r3, r2 + 8003a02: 617b str r3, [r7, #20] tmpccer |= (TIM_ICPolarity << 4U); - 8003140: 68bb ldr r3, [r7, #8] - 8003142: 011b lsls r3, r3, #4 - 8003144: 697a ldr r2, [r7, #20] - 8003146: 4313 orrs r3, r2 - 8003148: 617b str r3, [r7, #20] + 8003a04: 68bb ldr r3, [r7, #8] + 8003a06: 011b lsls r3, r3, #4 + 8003a08: 697a ldr r2, [r7, #20] + 8003a0a: 4313 orrs r3, r2 + 8003a0c: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; - 800314a: 68fb ldr r3, [r7, #12] - 800314c: 693a ldr r2, [r7, #16] - 800314e: 619a str r2, [r3, #24] + 8003a0e: 68fb ldr r3, [r7, #12] + 8003a10: 693a ldr r2, [r7, #16] + 8003a12: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; - 8003150: 68fb ldr r3, [r7, #12] - 8003152: 697a ldr r2, [r7, #20] - 8003154: 621a str r2, [r3, #32] + 8003a14: 68fb ldr r3, [r7, #12] + 8003a16: 697a ldr r2, [r7, #20] + 8003a18: 621a str r2, [r3, #32] } - 8003156: 46c0 nop @ (mov r8, r8) - 8003158: 46bd mov sp, r7 - 800315a: b006 add sp, #24 - 800315c: bd80 pop {r7, pc} - 800315e: 46c0 nop @ (mov r8, r8) - 8003160: ffff0fff .word 0xffff0fff + 8003a1a: 46c0 nop @ (mov r8, r8) + 8003a1c: 46bd mov sp, r7 + 8003a1e: b006 add sp, #24 + 8003a20: bd80 pop {r7, pc} + 8003a22: 46c0 nop @ (mov r8, r8) + 8003a24: ffff0fff .word 0xffff0fff -08003164 : +08003a28 : * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 * @arg TIM_TS_ETRF: External Trigger input * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { - 8003164: b580 push {r7, lr} - 8003166: b084 sub sp, #16 - 8003168: af00 add r7, sp, #0 - 800316a: 6078 str r0, [r7, #4] - 800316c: 6039 str r1, [r7, #0] + 8003a28: b580 push {r7, lr} + 8003a2a: b084 sub sp, #16 + 8003a2c: af00 add r7, sp, #0 + 8003a2e: 6078 str r0, [r7, #4] + 8003a30: 6039 str r1, [r7, #0] uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; - 800316e: 687b ldr r3, [r7, #4] - 8003170: 689b ldr r3, [r3, #8] - 8003172: 60fb str r3, [r7, #12] + 8003a32: 687b ldr r3, [r7, #4] + 8003a34: 689b ldr r3, [r3, #8] + 8003a36: 60fb str r3, [r7, #12] /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; - 8003174: 68fb ldr r3, [r7, #12] - 8003176: 4a08 ldr r2, [pc, #32] @ (8003198 ) - 8003178: 4013 ands r3, r2 - 800317a: 60fb str r3, [r7, #12] + 8003a38: 68fb ldr r3, [r7, #12] + 8003a3a: 4a08 ldr r2, [pc, #32] @ (8003a5c ) + 8003a3c: 4013 ands r3, r2 + 8003a3e: 60fb str r3, [r7, #12] /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); - 800317c: 683a ldr r2, [r7, #0] - 800317e: 68fb ldr r3, [r7, #12] - 8003180: 4313 orrs r3, r2 - 8003182: 2207 movs r2, #7 - 8003184: 4313 orrs r3, r2 - 8003186: 60fb str r3, [r7, #12] + 8003a40: 683a ldr r2, [r7, #0] + 8003a42: 68fb ldr r3, [r7, #12] + 8003a44: 4313 orrs r3, r2 + 8003a46: 2207 movs r2, #7 + 8003a48: 4313 orrs r3, r2 + 8003a4a: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; - 8003188: 687b ldr r3, [r7, #4] - 800318a: 68fa ldr r2, [r7, #12] - 800318c: 609a str r2, [r3, #8] + 8003a4c: 687b ldr r3, [r7, #4] + 8003a4e: 68fa ldr r2, [r7, #12] + 8003a50: 609a str r2, [r3, #8] } - 800318e: 46c0 nop @ (mov r8, r8) - 8003190: 46bd mov sp, r7 - 8003192: b004 add sp, #16 - 8003194: bd80 pop {r7, pc} - 8003196: 46c0 nop @ (mov r8, r8) - 8003198: ffcfff8f .word 0xffcfff8f + 8003a52: 46c0 nop @ (mov r8, r8) + 8003a54: 46bd mov sp, r7 + 8003a56: b004 add sp, #16 + 8003a58: bd80 pop {r7, pc} + 8003a5a: 46c0 nop @ (mov r8, r8) + 8003a5c: ffcfff8f .word 0xffcfff8f -0800319c : +08003a60 : * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { - 800319c: b580 push {r7, lr} - 800319e: b086 sub sp, #24 - 80031a0: af00 add r7, sp, #0 - 80031a2: 60f8 str r0, [r7, #12] - 80031a4: 60b9 str r1, [r7, #8] - 80031a6: 607a str r2, [r7, #4] - 80031a8: 603b str r3, [r7, #0] + 8003a60: b580 push {r7, lr} + 8003a62: b086 sub sp, #24 + 8003a64: af00 add r7, sp, #0 + 8003a66: 60f8 str r0, [r7, #12] + 8003a68: 60b9 str r1, [r7, #8] + 8003a6a: 607a str r2, [r7, #4] + 8003a6c: 603b str r3, [r7, #0] uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; - 80031aa: 68fb ldr r3, [r7, #12] - 80031ac: 689b ldr r3, [r3, #8] - 80031ae: 617b str r3, [r7, #20] + 8003a6e: 68fb ldr r3, [r7, #12] + 8003a70: 689b ldr r3, [r3, #8] + 8003a72: 617b str r3, [r7, #20] /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); - 80031b0: 697b ldr r3, [r7, #20] - 80031b2: 4a09 ldr r2, [pc, #36] @ (80031d8 ) - 80031b4: 4013 ands r3, r2 - 80031b6: 617b str r3, [r7, #20] + 8003a74: 697b ldr r3, [r7, #20] + 8003a76: 4a09 ldr r2, [pc, #36] @ (8003a9c ) + 8003a78: 4013 ands r3, r2 + 8003a7a: 617b str r3, [r7, #20] /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); - 80031b8: 683b ldr r3, [r7, #0] - 80031ba: 021a lsls r2, r3, #8 - 80031bc: 687b ldr r3, [r7, #4] - 80031be: 431a orrs r2, r3 - 80031c0: 68bb ldr r3, [r7, #8] - 80031c2: 4313 orrs r3, r2 - 80031c4: 697a ldr r2, [r7, #20] - 80031c6: 4313 orrs r3, r2 - 80031c8: 617b str r3, [r7, #20] + 8003a7c: 683b ldr r3, [r7, #0] + 8003a7e: 021a lsls r2, r3, #8 + 8003a80: 687b ldr r3, [r7, #4] + 8003a82: 431a orrs r2, r3 + 8003a84: 68bb ldr r3, [r7, #8] + 8003a86: 4313 orrs r3, r2 + 8003a88: 697a ldr r2, [r7, #20] + 8003a8a: 4313 orrs r3, r2 + 8003a8c: 617b str r3, [r7, #20] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; - 80031ca: 68fb ldr r3, [r7, #12] - 80031cc: 697a ldr r2, [r7, #20] - 80031ce: 609a str r2, [r3, #8] + 8003a8e: 68fb ldr r3, [r7, #12] + 8003a90: 697a ldr r2, [r7, #20] + 8003a92: 609a str r2, [r3, #8] } - 80031d0: 46c0 nop @ (mov r8, r8) - 80031d2: 46bd mov sp, r7 - 80031d4: b006 add sp, #24 - 80031d6: bd80 pop {r7, pc} - 80031d8: ffff00ff .word 0xffff00ff + 8003a94: 46c0 nop @ (mov r8, r8) + 8003a96: 46bd mov sp, r7 + 8003a98: b006 add sp, #24 + 8003a9a: bd80 pop {r7, pc} + 8003a9c: ffff00ff .word 0xffff00ff -080031dc : +08003aa0 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { - 80031dc: b580 push {r7, lr} - 80031de: b084 sub sp, #16 - 80031e0: af00 add r7, sp, #0 - 80031e2: 6078 str r0, [r7, #4] - 80031e4: 6039 str r1, [r7, #0] + 8003aa0: b580 push {r7, lr} + 8003aa2: b084 sub sp, #16 + 8003aa4: af00 add r7, sp, #0 + 8003aa6: 6078 str r0, [r7, #4] + 8003aa8: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); - 80031e6: 687b ldr r3, [r7, #4] - 80031e8: 223c movs r2, #60 @ 0x3c - 80031ea: 5c9b ldrb r3, [r3, r2] - 80031ec: 2b01 cmp r3, #1 - 80031ee: d101 bne.n 80031f4 - 80031f0: 2302 movs r3, #2 - 80031f2: e050 b.n 8003296 - 80031f4: 687b ldr r3, [r7, #4] - 80031f6: 223c movs r2, #60 @ 0x3c - 80031f8: 2101 movs r1, #1 - 80031fa: 5499 strb r1, [r3, r2] + 8003aaa: 687b ldr r3, [r7, #4] + 8003aac: 223c movs r2, #60 @ 0x3c + 8003aae: 5c9b ldrb r3, [r3, r2] + 8003ab0: 2b01 cmp r3, #1 + 8003ab2: d101 bne.n 8003ab8 + 8003ab4: 2302 movs r3, #2 + 8003ab6: e050 b.n 8003b5a + 8003ab8: 687b ldr r3, [r7, #4] + 8003aba: 223c movs r2, #60 @ 0x3c + 8003abc: 2101 movs r1, #1 + 8003abe: 5499 strb r1, [r3, r2] /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; - 80031fc: 687b ldr r3, [r7, #4] - 80031fe: 223d movs r2, #61 @ 0x3d - 8003200: 2102 movs r1, #2 - 8003202: 5499 strb r1, [r3, r2] + 8003ac0: 687b ldr r3, [r7, #4] + 8003ac2: 223d movs r2, #61 @ 0x3d + 8003ac4: 2102 movs r1, #2 + 8003ac6: 5499 strb r1, [r3, r2] /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; - 8003204: 687b ldr r3, [r7, #4] - 8003206: 681b ldr r3, [r3, #0] - 8003208: 685b ldr r3, [r3, #4] - 800320a: 60fb str r3, [r7, #12] + 8003ac8: 687b ldr r3, [r7, #4] + 8003aca: 681b ldr r3, [r3, #0] + 8003acc: 685b ldr r3, [r3, #4] + 8003ace: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; - 800320c: 687b ldr r3, [r7, #4] - 800320e: 681b ldr r3, [r3, #0] - 8003210: 689b ldr r3, [r3, #8] - 8003212: 60bb str r3, [r7, #8] + 8003ad0: 687b ldr r3, [r7, #4] + 8003ad2: 681b ldr r3, [r3, #0] + 8003ad4: 689b ldr r3, [r3, #8] + 8003ad6: 60bb str r3, [r7, #8] /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) - 8003214: 687b ldr r3, [r7, #4] - 8003216: 681b ldr r3, [r3, #0] - 8003218: 4a21 ldr r2, [pc, #132] @ (80032a0 ) - 800321a: 4293 cmp r3, r2 - 800321c: d108 bne.n 8003230 + 8003ad8: 687b ldr r3, [r7, #4] + 8003ada: 681b ldr r3, [r3, #0] + 8003adc: 4a21 ldr r2, [pc, #132] @ (8003b64 ) + 8003ade: 4293 cmp r3, r2 + 8003ae0: d108 bne.n 8003af4 { /* Check the parameters */ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); /* Clear the MMS2 bits */ tmpcr2 &= ~TIM_CR2_MMS2; - 800321e: 68fb ldr r3, [r7, #12] - 8003220: 4a20 ldr r2, [pc, #128] @ (80032a4 ) - 8003222: 4013 ands r3, r2 - 8003224: 60fb str r3, [r7, #12] + 8003ae2: 68fb ldr r3, [r7, #12] + 8003ae4: 4a20 ldr r2, [pc, #128] @ (8003b68 ) + 8003ae6: 4013 ands r3, r2 + 8003ae8: 60fb str r3, [r7, #12] /* Select the TRGO2 source*/ tmpcr2 |= sMasterConfig->MasterOutputTrigger2; - 8003226: 683b ldr r3, [r7, #0] - 8003228: 685b ldr r3, [r3, #4] - 800322a: 68fa ldr r2, [r7, #12] - 800322c: 4313 orrs r3, r2 - 800322e: 60fb str r3, [r7, #12] + 8003aea: 683b ldr r3, [r7, #0] + 8003aec: 685b ldr r3, [r3, #4] + 8003aee: 68fa ldr r2, [r7, #12] + 8003af0: 4313 orrs r3, r2 + 8003af2: 60fb str r3, [r7, #12] } /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; - 8003230: 68fb ldr r3, [r7, #12] - 8003232: 2270 movs r2, #112 @ 0x70 - 8003234: 4393 bics r3, r2 - 8003236: 60fb str r3, [r7, #12] + 8003af4: 68fb ldr r3, [r7, #12] + 8003af6: 2270 movs r2, #112 @ 0x70 + 8003af8: 4393 bics r3, r2 + 8003afa: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; - 8003238: 683b ldr r3, [r7, #0] - 800323a: 681b ldr r3, [r3, #0] - 800323c: 68fa ldr r2, [r7, #12] - 800323e: 4313 orrs r3, r2 - 8003240: 60fb str r3, [r7, #12] + 8003afc: 683b ldr r3, [r7, #0] + 8003afe: 681b ldr r3, [r3, #0] + 8003b00: 68fa ldr r2, [r7, #12] + 8003b02: 4313 orrs r3, r2 + 8003b04: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; - 8003242: 687b ldr r3, [r7, #4] - 8003244: 681b ldr r3, [r3, #0] - 8003246: 68fa ldr r2, [r7, #12] - 8003248: 605a str r2, [r3, #4] + 8003b06: 687b ldr r3, [r7, #4] + 8003b08: 681b ldr r3, [r3, #0] + 8003b0a: 68fa ldr r2, [r7, #12] + 8003b0c: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - 800324a: 687b ldr r3, [r7, #4] - 800324c: 681b ldr r3, [r3, #0] - 800324e: 4a14 ldr r2, [pc, #80] @ (80032a0 ) - 8003250: 4293 cmp r3, r2 - 8003252: d00a beq.n 800326a - 8003254: 687b ldr r3, [r7, #4] - 8003256: 681a ldr r2, [r3, #0] - 8003258: 2380 movs r3, #128 @ 0x80 - 800325a: 05db lsls r3, r3, #23 - 800325c: 429a cmp r2, r3 - 800325e: d004 beq.n 800326a - 8003260: 687b ldr r3, [r7, #4] - 8003262: 681b ldr r3, [r3, #0] - 8003264: 4a10 ldr r2, [pc, #64] @ (80032a8 ) - 8003266: 4293 cmp r3, r2 - 8003268: d10c bne.n 8003284 + 8003b0e: 687b ldr r3, [r7, #4] + 8003b10: 681b ldr r3, [r3, #0] + 8003b12: 4a14 ldr r2, [pc, #80] @ (8003b64 ) + 8003b14: 4293 cmp r3, r2 + 8003b16: d00a beq.n 8003b2e + 8003b18: 687b ldr r3, [r7, #4] + 8003b1a: 681a ldr r2, [r3, #0] + 8003b1c: 2380 movs r3, #128 @ 0x80 + 8003b1e: 05db lsls r3, r3, #23 + 8003b20: 429a cmp r2, r3 + 8003b22: d004 beq.n 8003b2e + 8003b24: 687b ldr r3, [r7, #4] + 8003b26: 681b ldr r3, [r3, #0] + 8003b28: 4a10 ldr r2, [pc, #64] @ (8003b6c ) + 8003b2a: 4293 cmp r3, r2 + 8003b2c: d10c bne.n 8003b48 { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; - 800326a: 68bb ldr r3, [r7, #8] - 800326c: 2280 movs r2, #128 @ 0x80 - 800326e: 4393 bics r3, r2 - 8003270: 60bb str r3, [r7, #8] + 8003b2e: 68bb ldr r3, [r7, #8] + 8003b30: 2280 movs r2, #128 @ 0x80 + 8003b32: 4393 bics r3, r2 + 8003b34: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; - 8003272: 683b ldr r3, [r7, #0] - 8003274: 689b ldr r3, [r3, #8] - 8003276: 68ba ldr r2, [r7, #8] - 8003278: 4313 orrs r3, r2 - 800327a: 60bb str r3, [r7, #8] + 8003b36: 683b ldr r3, [r7, #0] + 8003b38: 689b ldr r3, [r3, #8] + 8003b3a: 68ba ldr r2, [r7, #8] + 8003b3c: 4313 orrs r3, r2 + 8003b3e: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; - 800327c: 687b ldr r3, [r7, #4] - 800327e: 681b ldr r3, [r3, #0] - 8003280: 68ba ldr r2, [r7, #8] - 8003282: 609a str r2, [r3, #8] + 8003b40: 687b ldr r3, [r7, #4] + 8003b42: 681b ldr r3, [r3, #0] + 8003b44: 68ba ldr r2, [r7, #8] + 8003b46: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; - 8003284: 687b ldr r3, [r7, #4] - 8003286: 223d movs r2, #61 @ 0x3d - 8003288: 2101 movs r1, #1 - 800328a: 5499 strb r1, [r3, r2] + 8003b48: 687b ldr r3, [r7, #4] + 8003b4a: 223d movs r2, #61 @ 0x3d + 8003b4c: 2101 movs r1, #1 + 8003b4e: 5499 strb r1, [r3, r2] __HAL_UNLOCK(htim); - 800328c: 687b ldr r3, [r7, #4] - 800328e: 223c movs r2, #60 @ 0x3c - 8003290: 2100 movs r1, #0 - 8003292: 5499 strb r1, [r3, r2] + 8003b50: 687b ldr r3, [r7, #4] + 8003b52: 223c movs r2, #60 @ 0x3c + 8003b54: 2100 movs r1, #0 + 8003b56: 5499 strb r1, [r3, r2] return HAL_OK; - 8003294: 2300 movs r3, #0 + 8003b58: 2300 movs r3, #0 } - 8003296: 0018 movs r0, r3 - 8003298: 46bd mov sp, r7 - 800329a: b004 add sp, #16 - 800329c: bd80 pop {r7, pc} - 800329e: 46c0 nop @ (mov r8, r8) - 80032a0: 40012c00 .word 0x40012c00 - 80032a4: ff0fffff .word 0xff0fffff - 80032a8: 40000400 .word 0x40000400 + 8003b5a: 0018 movs r0, r3 + 8003b5c: 46bd mov sp, r7 + 8003b5e: b004 add sp, #16 + 8003b60: bd80 pop {r7, pc} + 8003b62: 46c0 nop @ (mov r8, r8) + 8003b64: 40012c00 .word 0x40012c00 + 8003b68: ff0fffff .word 0xff0fffff + 8003b6c: 40000400 .word 0x40000400 -080032ac : +08003b70 : * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) { - 80032ac: b580 push {r7, lr} - 80032ae: b084 sub sp, #16 - 80032b0: af00 add r7, sp, #0 - 80032b2: 6078 str r0, [r7, #4] - 80032b4: 6039 str r1, [r7, #0] + 8003b70: b580 push {r7, lr} + 8003b72: b084 sub sp, #16 + 8003b74: af00 add r7, sp, #0 + 8003b76: 6078 str r0, [r7, #4] + 8003b78: 6039 str r1, [r7, #0] /* Keep this variable initialized to 0 as it is used to configure BDTR register */ uint32_t tmpbdtr = 0U; - 80032b6: 2300 movs r3, #0 - 80032b8: 60fb str r3, [r7, #12] + 8003b7a: 2300 movs r3, #0 + 8003b7c: 60fb str r3, [r7, #12] assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); /* Check input state */ __HAL_LOCK(htim); - 80032ba: 687b ldr r3, [r7, #4] - 80032bc: 223c movs r2, #60 @ 0x3c - 80032be: 5c9b ldrb r3, [r3, r2] - 80032c0: 2b01 cmp r3, #1 - 80032c2: d101 bne.n 80032c8 - 80032c4: 2302 movs r3, #2 - 80032c6: e06f b.n 80033a8 - 80032c8: 687b ldr r3, [r7, #4] - 80032ca: 223c movs r2, #60 @ 0x3c - 80032cc: 2101 movs r1, #1 - 80032ce: 5499 strb r1, [r3, r2] + 8003b7e: 687b ldr r3, [r7, #4] + 8003b80: 223c movs r2, #60 @ 0x3c + 8003b82: 5c9b ldrb r3, [r3, r2] + 8003b84: 2b01 cmp r3, #1 + 8003b86: d101 bne.n 8003b8c + 8003b88: 2302 movs r3, #2 + 8003b8a: e06f b.n 8003c6c + 8003b8c: 687b ldr r3, [r7, #4] + 8003b8e: 223c movs r2, #60 @ 0x3c + 8003b90: 2101 movs r1, #1 + 8003b92: 5499 strb r1, [r3, r2] /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ /* Set the BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); - 80032d0: 68fb ldr r3, [r7, #12] - 80032d2: 22ff movs r2, #255 @ 0xff - 80032d4: 4393 bics r3, r2 - 80032d6: 001a movs r2, r3 - 80032d8: 683b ldr r3, [r7, #0] - 80032da: 68db ldr r3, [r3, #12] - 80032dc: 4313 orrs r3, r2 - 80032de: 60fb str r3, [r7, #12] + 8003b94: 68fb ldr r3, [r7, #12] + 8003b96: 22ff movs r2, #255 @ 0xff + 8003b98: 4393 bics r3, r2 + 8003b9a: 001a movs r2, r3 + 8003b9c: 683b ldr r3, [r7, #0] + 8003b9e: 68db ldr r3, [r3, #12] + 8003ba0: 4313 orrs r3, r2 + 8003ba2: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); - 80032e0: 68fb ldr r3, [r7, #12] - 80032e2: 4a33 ldr r2, [pc, #204] @ (80033b0 ) - 80032e4: 401a ands r2, r3 - 80032e6: 683b ldr r3, [r7, #0] - 80032e8: 689b ldr r3, [r3, #8] - 80032ea: 4313 orrs r3, r2 - 80032ec: 60fb str r3, [r7, #12] + 8003ba4: 68fb ldr r3, [r7, #12] + 8003ba6: 4a33 ldr r2, [pc, #204] @ (8003c74 ) + 8003ba8: 401a ands r2, r3 + 8003baa: 683b ldr r3, [r7, #0] + 8003bac: 689b ldr r3, [r3, #8] + 8003bae: 4313 orrs r3, r2 + 8003bb0: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); - 80032ee: 68fb ldr r3, [r7, #12] - 80032f0: 4a30 ldr r2, [pc, #192] @ (80033b4 ) - 80032f2: 401a ands r2, r3 - 80032f4: 683b ldr r3, [r7, #0] - 80032f6: 685b ldr r3, [r3, #4] - 80032f8: 4313 orrs r3, r2 - 80032fa: 60fb str r3, [r7, #12] + 8003bb2: 68fb ldr r3, [r7, #12] + 8003bb4: 4a30 ldr r2, [pc, #192] @ (8003c78 ) + 8003bb6: 401a ands r2, r3 + 8003bb8: 683b ldr r3, [r7, #0] + 8003bba: 685b ldr r3, [r3, #4] + 8003bbc: 4313 orrs r3, r2 + 8003bbe: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); - 80032fc: 68fb ldr r3, [r7, #12] - 80032fe: 4a2e ldr r2, [pc, #184] @ (80033b8 ) - 8003300: 401a ands r2, r3 - 8003302: 683b ldr r3, [r7, #0] - 8003304: 681b ldr r3, [r3, #0] - 8003306: 4313 orrs r3, r2 - 8003308: 60fb str r3, [r7, #12] + 8003bc0: 68fb ldr r3, [r7, #12] + 8003bc2: 4a2e ldr r2, [pc, #184] @ (8003c7c ) + 8003bc4: 401a ands r2, r3 + 8003bc6: 683b ldr r3, [r7, #0] + 8003bc8: 681b ldr r3, [r3, #0] + 8003bca: 4313 orrs r3, r2 + 8003bcc: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); - 800330a: 68fb ldr r3, [r7, #12] - 800330c: 4a2b ldr r2, [pc, #172] @ (80033bc ) - 800330e: 401a ands r2, r3 - 8003310: 683b ldr r3, [r7, #0] - 8003312: 691b ldr r3, [r3, #16] - 8003314: 4313 orrs r3, r2 - 8003316: 60fb str r3, [r7, #12] + 8003bce: 68fb ldr r3, [r7, #12] + 8003bd0: 4a2b ldr r2, [pc, #172] @ (8003c80 ) + 8003bd2: 401a ands r2, r3 + 8003bd4: 683b ldr r3, [r7, #0] + 8003bd6: 691b ldr r3, [r3, #16] + 8003bd8: 4313 orrs r3, r2 + 8003bda: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); - 8003318: 68fb ldr r3, [r7, #12] - 800331a: 4a29 ldr r2, [pc, #164] @ (80033c0 ) - 800331c: 401a ands r2, r3 - 800331e: 683b ldr r3, [r7, #0] - 8003320: 695b ldr r3, [r3, #20] - 8003322: 4313 orrs r3, r2 - 8003324: 60fb str r3, [r7, #12] + 8003bdc: 68fb ldr r3, [r7, #12] + 8003bde: 4a29 ldr r2, [pc, #164] @ (8003c84 ) + 8003be0: 401a ands r2, r3 + 8003be2: 683b ldr r3, [r7, #0] + 8003be4: 695b ldr r3, [r3, #20] + 8003be6: 4313 orrs r3, r2 + 8003be8: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); - 8003326: 68fb ldr r3, [r7, #12] - 8003328: 4a26 ldr r2, [pc, #152] @ (80033c4 ) - 800332a: 401a ands r2, r3 - 800332c: 683b ldr r3, [r7, #0] - 800332e: 6b1b ldr r3, [r3, #48] @ 0x30 - 8003330: 4313 orrs r3, r2 - 8003332: 60fb str r3, [r7, #12] + 8003bea: 68fb ldr r3, [r7, #12] + 8003bec: 4a26 ldr r2, [pc, #152] @ (8003c88 ) + 8003bee: 401a ands r2, r3 + 8003bf0: 683b ldr r3, [r7, #0] + 8003bf2: 6b1b ldr r3, [r3, #48] @ 0x30 + 8003bf4: 4313 orrs r3, r2 + 8003bf6: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); - 8003334: 68fb ldr r3, [r7, #12] - 8003336: 4a24 ldr r2, [pc, #144] @ (80033c8 ) - 8003338: 401a ands r2, r3 - 800333a: 683b ldr r3, [r7, #0] - 800333c: 699b ldr r3, [r3, #24] - 800333e: 041b lsls r3, r3, #16 - 8003340: 4313 orrs r3, r2 - 8003342: 60fb str r3, [r7, #12] + 8003bf8: 68fb ldr r3, [r7, #12] + 8003bfa: 4a24 ldr r2, [pc, #144] @ (8003c8c ) + 8003bfc: 401a ands r2, r3 + 8003bfe: 683b ldr r3, [r7, #0] + 8003c00: 699b ldr r3, [r3, #24] + 8003c02: 041b lsls r3, r3, #16 + 8003c04: 4313 orrs r3, r2 + 8003c06: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); - 8003344: 68fb ldr r3, [r7, #12] - 8003346: 4a21 ldr r2, [pc, #132] @ (80033cc ) - 8003348: 401a ands r2, r3 - 800334a: 683b ldr r3, [r7, #0] - 800334c: 69db ldr r3, [r3, #28] - 800334e: 4313 orrs r3, r2 - 8003350: 60fb str r3, [r7, #12] + 8003c08: 68fb ldr r3, [r7, #12] + 8003c0a: 4a21 ldr r2, [pc, #132] @ (8003c90 ) + 8003c0c: 401a ands r2, r3 + 8003c0e: 683b ldr r3, [r7, #0] + 8003c10: 69db ldr r3, [r3, #28] + 8003c12: 4313 orrs r3, r2 + 8003c14: 60fb str r3, [r7, #12] if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) - 8003352: 687b ldr r3, [r7, #4] - 8003354: 681b ldr r3, [r3, #0] - 8003356: 4a1e ldr r2, [pc, #120] @ (80033d0 ) - 8003358: 4293 cmp r3, r2 - 800335a: d11c bne.n 8003396 + 8003c16: 687b ldr r3, [r7, #4] + 8003c18: 681b ldr r3, [r3, #0] + 8003c1a: 4a1e ldr r2, [pc, #120] @ (8003c94 ) + 8003c1c: 4293 cmp r3, r2 + 8003c1e: d11c bne.n 8003c5a assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); /* Set the BREAK2 input related BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); - 800335c: 68fb ldr r3, [r7, #12] - 800335e: 4a1d ldr r2, [pc, #116] @ (80033d4 ) - 8003360: 401a ands r2, r3 - 8003362: 683b ldr r3, [r7, #0] - 8003364: 6a9b ldr r3, [r3, #40] @ 0x28 - 8003366: 051b lsls r3, r3, #20 - 8003368: 4313 orrs r3, r2 - 800336a: 60fb str r3, [r7, #12] + 8003c20: 68fb ldr r3, [r7, #12] + 8003c22: 4a1d ldr r2, [pc, #116] @ (8003c98 ) + 8003c24: 401a ands r2, r3 + 8003c26: 683b ldr r3, [r7, #0] + 8003c28: 6a9b ldr r3, [r3, #40] @ 0x28 + 8003c2a: 051b lsls r3, r3, #20 + 8003c2c: 4313 orrs r3, r2 + 8003c2e: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); - 800336c: 68fb ldr r3, [r7, #12] - 800336e: 4a1a ldr r2, [pc, #104] @ (80033d8 ) - 8003370: 401a ands r2, r3 - 8003372: 683b ldr r3, [r7, #0] - 8003374: 6a1b ldr r3, [r3, #32] - 8003376: 4313 orrs r3, r2 - 8003378: 60fb str r3, [r7, #12] + 8003c30: 68fb ldr r3, [r7, #12] + 8003c32: 4a1a ldr r2, [pc, #104] @ (8003c9c ) + 8003c34: 401a ands r2, r3 + 8003c36: 683b ldr r3, [r7, #0] + 8003c38: 6a1b ldr r3, [r3, #32] + 8003c3a: 4313 orrs r3, r2 + 8003c3c: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); - 800337a: 68fb ldr r3, [r7, #12] - 800337c: 4a17 ldr r2, [pc, #92] @ (80033dc ) - 800337e: 401a ands r2, r3 - 8003380: 683b ldr r3, [r7, #0] - 8003382: 6a5b ldr r3, [r3, #36] @ 0x24 - 8003384: 4313 orrs r3, r2 - 8003386: 60fb str r3, [r7, #12] + 8003c3e: 68fb ldr r3, [r7, #12] + 8003c40: 4a17 ldr r2, [pc, #92] @ (8003ca0 ) + 8003c42: 401a ands r2, r3 + 8003c44: 683b ldr r3, [r7, #0] + 8003c46: 6a5b ldr r3, [r3, #36] @ 0x24 + 8003c48: 4313 orrs r3, r2 + 8003c4a: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); - 8003388: 68fb ldr r3, [r7, #12] - 800338a: 4a15 ldr r2, [pc, #84] @ (80033e0 ) - 800338c: 401a ands r2, r3 - 800338e: 683b ldr r3, [r7, #0] - 8003390: 6adb ldr r3, [r3, #44] @ 0x2c - 8003392: 4313 orrs r3, r2 - 8003394: 60fb str r3, [r7, #12] + 8003c4c: 68fb ldr r3, [r7, #12] + 8003c4e: 4a15 ldr r2, [pc, #84] @ (8003ca4 ) + 8003c50: 401a ands r2, r3 + 8003c52: 683b ldr r3, [r7, #0] + 8003c54: 6adb ldr r3, [r3, #44] @ 0x2c + 8003c56: 4313 orrs r3, r2 + 8003c58: 60fb str r3, [r7, #12] } /* Set TIMx_BDTR */ htim->Instance->BDTR = tmpbdtr; - 8003396: 687b ldr r3, [r7, #4] - 8003398: 681b ldr r3, [r3, #0] - 800339a: 68fa ldr r2, [r7, #12] - 800339c: 645a str r2, [r3, #68] @ 0x44 + 8003c5a: 687b ldr r3, [r7, #4] + 8003c5c: 681b ldr r3, [r3, #0] + 8003c5e: 68fa ldr r2, [r7, #12] + 8003c60: 645a str r2, [r3, #68] @ 0x44 __HAL_UNLOCK(htim); - 800339e: 687b ldr r3, [r7, #4] - 80033a0: 223c movs r2, #60 @ 0x3c - 80033a2: 2100 movs r1, #0 - 80033a4: 5499 strb r1, [r3, r2] + 8003c62: 687b ldr r3, [r7, #4] + 8003c64: 223c movs r2, #60 @ 0x3c + 8003c66: 2100 movs r1, #0 + 8003c68: 5499 strb r1, [r3, r2] return HAL_OK; - 80033a6: 2300 movs r3, #0 + 8003c6a: 2300 movs r3, #0 } - 80033a8: 0018 movs r0, r3 - 80033aa: 46bd mov sp, r7 - 80033ac: b004 add sp, #16 - 80033ae: bd80 pop {r7, pc} - 80033b0: fffffcff .word 0xfffffcff - 80033b4: fffffbff .word 0xfffffbff - 80033b8: fffff7ff .word 0xfffff7ff - 80033bc: ffffefff .word 0xffffefff - 80033c0: ffffdfff .word 0xffffdfff - 80033c4: ffffbfff .word 0xffffbfff - 80033c8: fff0ffff .word 0xfff0ffff - 80033cc: efffffff .word 0xefffffff - 80033d0: 40012c00 .word 0x40012c00 - 80033d4: ff0fffff .word 0xff0fffff - 80033d8: feffffff .word 0xfeffffff - 80033dc: fdffffff .word 0xfdffffff - 80033e0: dfffffff .word 0xdfffffff + 8003c6c: 0018 movs r0, r3 + 8003c6e: 46bd mov sp, r7 + 8003c70: b004 add sp, #16 + 8003c72: bd80 pop {r7, pc} + 8003c74: fffffcff .word 0xfffffcff + 8003c78: fffffbff .word 0xfffffbff + 8003c7c: fffff7ff .word 0xfffff7ff + 8003c80: ffffefff .word 0xffffefff + 8003c84: ffffdfff .word 0xffffdfff + 8003c88: ffffbfff .word 0xffffbfff + 8003c8c: fff0ffff .word 0xfff0ffff + 8003c90: efffffff .word 0xefffffff + 8003c94: 40012c00 .word 0x40012c00 + 8003c98: ff0fffff .word 0xff0fffff + 8003c9c: feffffff .word 0xfeffffff + 8003ca0: fdffffff .word 0xfdffffff + 8003ca4: dfffffff .word 0xdfffffff -080033e4 : +08003ca8 : * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { - 80033e4: b580 push {r7, lr} - 80033e6: b082 sub sp, #8 - 80033e8: af00 add r7, sp, #0 - 80033ea: 6078 str r0, [r7, #4] + 8003ca8: b580 push {r7, lr} + 8003caa: b082 sub sp, #8 + 8003cac: af00 add r7, sp, #0 + 8003cae: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } - 80033ec: 46c0 nop @ (mov r8, r8) - 80033ee: 46bd mov sp, r7 - 80033f0: b002 add sp, #8 - 80033f2: bd80 pop {r7, pc} + 8003cb0: 46c0 nop @ (mov r8, r8) + 8003cb2: 46bd mov sp, r7 + 8003cb4: b002 add sp, #8 + 8003cb6: bd80 pop {r7, pc} -080033f4 : +08003cb8 : * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { - 80033f4: b580 push {r7, lr} - 80033f6: b082 sub sp, #8 - 80033f8: af00 add r7, sp, #0 - 80033fa: 6078 str r0, [r7, #4] + 8003cb8: b580 push {r7, lr} + 8003cba: b082 sub sp, #8 + 8003cbc: af00 add r7, sp, #0 + 8003cbe: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } - 80033fc: 46c0 nop @ (mov r8, r8) - 80033fe: 46bd mov sp, r7 - 8003400: b002 add sp, #8 - 8003402: bd80 pop {r7, pc} + 8003cc0: 46c0 nop @ (mov r8, r8) + 8003cc2: 46bd mov sp, r7 + 8003cc4: b002 add sp, #8 + 8003cc6: bd80 pop {r7, pc} -08003404 : +08003cc8 : * @brief Break2 detection callback in non blocking mode * @param htim: TIM handle * @retval None */ __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) { - 8003404: b580 push {r7, lr} - 8003406: b082 sub sp, #8 - 8003408: af00 add r7, sp, #0 - 800340a: 6078 str r0, [r7, #4] + 8003cc8: b580 push {r7, lr} + 8003cca: b082 sub sp, #8 + 8003ccc: af00 add r7, sp, #0 + 8003cce: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIMEx_Break2Callback could be implemented in the user file */ } - 800340c: 46c0 nop @ (mov r8, r8) - 800340e: 46bd mov sp, r7 - 8003410: b002 add sp, #8 - 8003412: bd80 pop {r7, pc} + 8003cd0: 46c0 nop @ (mov r8, r8) + 8003cd2: 46bd mov sp, r7 + 8003cd4: b002 add sp, #8 + 8003cd6: bd80 pop {r7, pc} -08003414 : +08003cd8 : * parameters in the UART_InitTypeDef and initialize the associated handle. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { - 8003414: b580 push {r7, lr} - 8003416: b082 sub sp, #8 - 8003418: af00 add r7, sp, #0 - 800341a: 6078 str r0, [r7, #4] + 8003cd8: b580 push {r7, lr} + 8003cda: b082 sub sp, #8 + 8003cdc: af00 add r7, sp, #0 + 8003cde: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) - 800341c: 687b ldr r3, [r7, #4] - 800341e: 2b00 cmp r3, #0 - 8003420: d101 bne.n 8003426 + 8003ce0: 687b ldr r3, [r7, #4] + 8003ce2: 2b00 cmp r3, #0 + 8003ce4: d101 bne.n 8003cea { return HAL_ERROR; - 8003422: 2301 movs r3, #1 - 8003424: e046 b.n 80034b4 + 8003ce6: 2301 movs r3, #1 + 8003ce8: e046 b.n 8003d78 { /* Check the parameters */ assert_param(IS_UART_INSTANCE(huart->Instance)); } if (huart->gState == HAL_UART_STATE_RESET) - 8003426: 687b ldr r3, [r7, #4] - 8003428: 2288 movs r2, #136 @ 0x88 - 800342a: 589b ldr r3, [r3, r2] - 800342c: 2b00 cmp r3, #0 - 800342e: d107 bne.n 8003440 + 8003cea: 687b ldr r3, [r7, #4] + 8003cec: 2288 movs r2, #136 @ 0x88 + 8003cee: 589b ldr r3, [r3, r2] + 8003cf0: 2b00 cmp r3, #0 + 8003cf2: d107 bne.n 8003d04 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; - 8003430: 687b ldr r3, [r7, #4] - 8003432: 2284 movs r2, #132 @ 0x84 - 8003434: 2100 movs r1, #0 - 8003436: 5499 strb r1, [r3, r2] + 8003cf4: 687b ldr r3, [r7, #4] + 8003cf6: 2284 movs r2, #132 @ 0x84 + 8003cf8: 2100 movs r1, #0 + 8003cfa: 5499 strb r1, [r3, r2] /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); - 8003438: 687b ldr r3, [r7, #4] - 800343a: 0018 movs r0, r3 - 800343c: f7fd fc8c bl 8000d58 + 8003cfc: 687b ldr r3, [r7, #4] + 8003cfe: 0018 movs r0, r3 + 8003d00: f7fd fb14 bl 800132c #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; - 8003440: 687b ldr r3, [r7, #4] - 8003442: 2288 movs r2, #136 @ 0x88 - 8003444: 2124 movs r1, #36 @ 0x24 - 8003446: 5099 str r1, [r3, r2] + 8003d04: 687b ldr r3, [r7, #4] + 8003d06: 2288 movs r2, #136 @ 0x88 + 8003d08: 2124 movs r1, #36 @ 0x24 + 8003d0a: 5099 str r1, [r3, r2] __HAL_UART_DISABLE(huart); - 8003448: 687b ldr r3, [r7, #4] - 800344a: 681b ldr r3, [r3, #0] - 800344c: 681a ldr r2, [r3, #0] - 800344e: 687b ldr r3, [r7, #4] - 8003450: 681b ldr r3, [r3, #0] - 8003452: 2101 movs r1, #1 - 8003454: 438a bics r2, r1 - 8003456: 601a str r2, [r3, #0] + 8003d0c: 687b ldr r3, [r7, #4] + 8003d0e: 681b ldr r3, [r3, #0] + 8003d10: 681a ldr r2, [r3, #0] + 8003d12: 687b ldr r3, [r7, #4] + 8003d14: 681b ldr r3, [r3, #0] + 8003d16: 2101 movs r1, #1 + 8003d18: 438a bics r2, r1 + 8003d1a: 601a str r2, [r3, #0] /* Perform advanced settings configuration */ /* For some items, configuration requires to be done prior TE and RE bits are set */ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - 8003458: 687b ldr r3, [r7, #4] - 800345a: 6a9b ldr r3, [r3, #40] @ 0x28 - 800345c: 2b00 cmp r3, #0 - 800345e: d003 beq.n 8003468 + 8003d1c: 687b ldr r3, [r7, #4] + 8003d1e: 6a9b ldr r3, [r3, #40] @ 0x28 + 8003d20: 2b00 cmp r3, #0 + 8003d22: d003 beq.n 8003d2c { UART_AdvFeatureConfig(huart); - 8003460: 687b ldr r3, [r7, #4] - 8003462: 0018 movs r0, r3 - 8003464: f000 f9aa bl 80037bc + 8003d24: 687b ldr r3, [r7, #4] + 8003d26: 0018 movs r0, r3 + 8003d28: f000 f9c2 bl 80040b0 } /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) - 8003468: 687b ldr r3, [r7, #4] - 800346a: 0018 movs r0, r3 - 800346c: f000 f828 bl 80034c0 - 8003470: 0003 movs r3, r0 - 8003472: 2b01 cmp r3, #1 - 8003474: d101 bne.n 800347a + 8003d2c: 687b ldr r3, [r7, #4] + 8003d2e: 0018 movs r0, r3 + 8003d30: f000 f840 bl 8003db4 + 8003d34: 0003 movs r3, r0 + 8003d36: 2b01 cmp r3, #1 + 8003d38: d101 bne.n 8003d3e { return HAL_ERROR; - 8003476: 2301 movs r3, #1 - 8003478: e01c b.n 80034b4 + 8003d3a: 2301 movs r3, #1 + 8003d3c: e01c b.n 8003d78 } /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - 800347a: 687b ldr r3, [r7, #4] - 800347c: 681b ldr r3, [r3, #0] - 800347e: 685a ldr r2, [r3, #4] - 8003480: 687b ldr r3, [r7, #4] - 8003482: 681b ldr r3, [r3, #0] - 8003484: 490d ldr r1, [pc, #52] @ (80034bc ) - 8003486: 400a ands r2, r1 - 8003488: 605a str r2, [r3, #4] + 8003d3e: 687b ldr r3, [r7, #4] + 8003d40: 681b ldr r3, [r3, #0] + 8003d42: 685a ldr r2, [r3, #4] + 8003d44: 687b ldr r3, [r7, #4] + 8003d46: 681b ldr r3, [r3, #0] + 8003d48: 490d ldr r1, [pc, #52] @ (8003d80 ) + 8003d4a: 400a ands r2, r1 + 8003d4c: 605a str r2, [r3, #4] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - 800348a: 687b ldr r3, [r7, #4] - 800348c: 681b ldr r3, [r3, #0] - 800348e: 689a ldr r2, [r3, #8] - 8003490: 687b ldr r3, [r7, #4] - 8003492: 681b ldr r3, [r3, #0] - 8003494: 212a movs r1, #42 @ 0x2a - 8003496: 438a bics r2, r1 - 8003498: 609a str r2, [r3, #8] + 8003d4e: 687b ldr r3, [r7, #4] + 8003d50: 681b ldr r3, [r3, #0] + 8003d52: 689a ldr r2, [r3, #8] + 8003d54: 687b ldr r3, [r7, #4] + 8003d56: 681b ldr r3, [r3, #0] + 8003d58: 212a movs r1, #42 @ 0x2a + 8003d5a: 438a bics r2, r1 + 8003d5c: 609a str r2, [r3, #8] __HAL_UART_ENABLE(huart); - 800349a: 687b ldr r3, [r7, #4] - 800349c: 681b ldr r3, [r3, #0] - 800349e: 681a ldr r2, [r3, #0] - 80034a0: 687b ldr r3, [r7, #4] - 80034a2: 681b ldr r3, [r3, #0] - 80034a4: 2101 movs r1, #1 - 80034a6: 430a orrs r2, r1 - 80034a8: 601a str r2, [r3, #0] + 8003d5e: 687b ldr r3, [r7, #4] + 8003d60: 681b ldr r3, [r3, #0] + 8003d62: 681a ldr r2, [r3, #0] + 8003d64: 687b ldr r3, [r7, #4] + 8003d66: 681b ldr r3, [r3, #0] + 8003d68: 2101 movs r1, #1 + 8003d6a: 430a orrs r2, r1 + 8003d6c: 601a str r2, [r3, #0] /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); - 80034aa: 687b ldr r3, [r7, #4] - 80034ac: 0018 movs r0, r3 - 80034ae: f000 fa39 bl 8003924 - 80034b2: 0003 movs r3, r0 + 8003d6e: 687b ldr r3, [r7, #4] + 8003d70: 0018 movs r0, r3 + 8003d72: f000 fa51 bl 8004218 + 8003d76: 0003 movs r3, r0 } - 80034b4: 0018 movs r0, r3 - 80034b6: 46bd mov sp, r7 - 80034b8: b002 add sp, #8 - 80034ba: bd80 pop {r7, pc} - 80034bc: ffffb7ff .word 0xffffb7ff + 8003d78: 0018 movs r0, r3 + 8003d7a: 46bd mov sp, r7 + 8003d7c: b002 add sp, #8 + 8003d7e: bd80 pop {r7, pc} + 8003d80: ffffb7ff .word 0xffffb7ff -080034c0 : +08003d84 : + * @brief Rx Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) +{ + 8003d84: b580 push {r7, lr} + 8003d86: b082 sub sp, #8 + 8003d88: af00 add r7, sp, #0 + 8003d8a: 6078 str r0, [r7, #4] + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_RxCpltCallback can be implemented in the user file. + */ +} + 8003d8c: 46c0 nop @ (mov r8, r8) + 8003d8e: 46bd mov sp, r7 + 8003d90: b002 add sp, #8 + 8003d92: bd80 pop {r7, pc} + +08003d94 : + * @brief Rx Half Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + 8003d94: b580 push {r7, lr} + 8003d96: b082 sub sp, #8 + 8003d98: af00 add r7, sp, #0 + 8003d9a: 6078 str r0, [r7, #4] + UNUSED(huart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_RxHalfCpltCallback can be implemented in the user file. + */ +} + 8003d9c: 46c0 nop @ (mov r8, r8) + 8003d9e: 46bd mov sp, r7 + 8003da0: b002 add sp, #8 + 8003da2: bd80 pop {r7, pc} + +08003da4 : + * @brief UART error callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ + 8003da4: b580 push {r7, lr} + 8003da6: b082 sub sp, #8 + 8003da8: af00 add r7, sp, #0 + 8003daa: 6078 str r0, [r7, #4] + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_ErrorCallback can be implemented in the user file. + */ +} + 8003dac: 46c0 nop @ (mov r8, r8) + 8003dae: 46bd mov sp, r7 + 8003db0: b002 add sp, #8 + 8003db2: bd80 pop {r7, pc} + +08003db4 : * @brief Configure the UART peripheral. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { - 80034c0: b580 push {r7, lr} - 80034c2: b088 sub sp, #32 - 80034c4: af00 add r7, sp, #0 - 80034c6: 6078 str r0, [r7, #4] + 8003db4: b580 push {r7, lr} + 8003db6: b088 sub sp, #32 + 8003db8: af00 add r7, sp, #0 + 8003dba: 6078 str r0, [r7, #4] uint32_t tmpreg; uint16_t brrtemp; UART_ClockSourceTypeDef clocksource; uint32_t usartdiv; HAL_StatusTypeDef ret = HAL_OK; - 80034c8: 231e movs r3, #30 - 80034ca: 18fb adds r3, r7, r3 - 80034cc: 2200 movs r2, #0 - 80034ce: 701a strb r2, [r3, #0] + 8003dbc: 231e movs r3, #30 + 8003dbe: 18fb adds r3, r7, r3 + 8003dc0: 2200 movs r2, #0 + 8003dc2: 701a strb r2, [r3, #0] * the UART Word Length, Parity, Mode and oversampling: * set the M bits according to huart->Init.WordLength value * set PCE and PS bits according to huart->Init.Parity value * set TE and RE bits according to huart->Init.Mode value * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; - 80034d0: 687b ldr r3, [r7, #4] - 80034d2: 689a ldr r2, [r3, #8] - 80034d4: 687b ldr r3, [r7, #4] - 80034d6: 691b ldr r3, [r3, #16] - 80034d8: 431a orrs r2, r3 - 80034da: 687b ldr r3, [r7, #4] - 80034dc: 695b ldr r3, [r3, #20] - 80034de: 431a orrs r2, r3 - 80034e0: 687b ldr r3, [r7, #4] - 80034e2: 69db ldr r3, [r3, #28] - 80034e4: 4313 orrs r3, r2 - 80034e6: 617b str r3, [r7, #20] + 8003dc4: 687b ldr r3, [r7, #4] + 8003dc6: 689a ldr r2, [r3, #8] + 8003dc8: 687b ldr r3, [r7, #4] + 8003dca: 691b ldr r3, [r3, #16] + 8003dcc: 431a orrs r2, r3 + 8003dce: 687b ldr r3, [r7, #4] + 8003dd0: 695b ldr r3, [r3, #20] + 8003dd2: 431a orrs r2, r3 + 8003dd4: 687b ldr r3, [r7, #4] + 8003dd6: 69db ldr r3, [r3, #28] + 8003dd8: 4313 orrs r3, r2 + 8003dda: 617b str r3, [r7, #20] MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); - 80034e8: 687b ldr r3, [r7, #4] - 80034ea: 681b ldr r3, [r3, #0] - 80034ec: 681b ldr r3, [r3, #0] - 80034ee: 4aab ldr r2, [pc, #684] @ (800379c ) - 80034f0: 4013 ands r3, r2 - 80034f2: 0019 movs r1, r3 - 80034f4: 687b ldr r3, [r7, #4] - 80034f6: 681b ldr r3, [r3, #0] - 80034f8: 697a ldr r2, [r7, #20] - 80034fa: 430a orrs r2, r1 - 80034fc: 601a str r2, [r3, #0] + 8003ddc: 687b ldr r3, [r7, #4] + 8003dde: 681b ldr r3, [r3, #0] + 8003de0: 681b ldr r3, [r3, #0] + 8003de2: 4aab ldr r2, [pc, #684] @ (8004090 ) + 8003de4: 4013 ands r3, r2 + 8003de6: 0019 movs r1, r3 + 8003de8: 687b ldr r3, [r7, #4] + 8003dea: 681b ldr r3, [r3, #0] + 8003dec: 697a ldr r2, [r7, #20] + 8003dee: 430a orrs r2, r1 + 8003df0: 601a str r2, [r3, #0] /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); - 80034fe: 687b ldr r3, [r7, #4] - 8003500: 681b ldr r3, [r3, #0] - 8003502: 685b ldr r3, [r3, #4] - 8003504: 4aa6 ldr r2, [pc, #664] @ (80037a0 ) - 8003506: 4013 ands r3, r2 - 8003508: 0019 movs r1, r3 - 800350a: 687b ldr r3, [r7, #4] - 800350c: 68da ldr r2, [r3, #12] - 800350e: 687b ldr r3, [r7, #4] - 8003510: 681b ldr r3, [r3, #0] - 8003512: 430a orrs r2, r1 - 8003514: 605a str r2, [r3, #4] + 8003df2: 687b ldr r3, [r7, #4] + 8003df4: 681b ldr r3, [r3, #0] + 8003df6: 685b ldr r3, [r3, #4] + 8003df8: 4aa6 ldr r2, [pc, #664] @ (8004094 ) + 8003dfa: 4013 ands r3, r2 + 8003dfc: 0019 movs r1, r3 + 8003dfe: 687b ldr r3, [r7, #4] + 8003e00: 68da ldr r2, [r3, #12] + 8003e02: 687b ldr r3, [r7, #4] + 8003e04: 681b ldr r3, [r3, #0] + 8003e06: 430a orrs r2, r1 + 8003e08: 605a str r2, [r3, #4] /* Configure * - UART HardWare Flow Control: set CTSE and RTSE bits according * to huart->Init.HwFlowCtl value * - one-bit sampling method versus three samples' majority rule according * to huart->Init.OneBitSampling (not applicable to LPUART) */ tmpreg = (uint32_t)huart->Init.HwFlowCtl; - 8003516: 687b ldr r3, [r7, #4] - 8003518: 699b ldr r3, [r3, #24] - 800351a: 617b str r3, [r7, #20] + 8003e0a: 687b ldr r3, [r7, #4] + 8003e0c: 699b ldr r3, [r3, #24] + 8003e0e: 617b str r3, [r7, #20] tmpreg |= huart->Init.OneBitSampling; - 800351c: 687b ldr r3, [r7, #4] - 800351e: 6a1b ldr r3, [r3, #32] - 8003520: 697a ldr r2, [r7, #20] - 8003522: 4313 orrs r3, r2 - 8003524: 617b str r3, [r7, #20] + 8003e10: 687b ldr r3, [r7, #4] + 8003e12: 6a1b ldr r3, [r3, #32] + 8003e14: 697a ldr r2, [r7, #20] + 8003e16: 4313 orrs r3, r2 + 8003e18: 617b str r3, [r7, #20] MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); - 8003526: 687b ldr r3, [r7, #4] - 8003528: 681b ldr r3, [r3, #0] - 800352a: 689b ldr r3, [r3, #8] - 800352c: 4a9d ldr r2, [pc, #628] @ (80037a4 ) - 800352e: 4013 ands r3, r2 - 8003530: 0019 movs r1, r3 - 8003532: 687b ldr r3, [r7, #4] - 8003534: 681b ldr r3, [r3, #0] - 8003536: 697a ldr r2, [r7, #20] - 8003538: 430a orrs r2, r1 - 800353a: 609a str r2, [r3, #8] + 8003e1a: 687b ldr r3, [r7, #4] + 8003e1c: 681b ldr r3, [r3, #0] + 8003e1e: 689b ldr r3, [r3, #8] + 8003e20: 4a9d ldr r2, [pc, #628] @ (8004098 ) + 8003e22: 4013 ands r3, r2 + 8003e24: 0019 movs r1, r3 + 8003e26: 687b ldr r3, [r7, #4] + 8003e28: 681b ldr r3, [r3, #0] + 8003e2a: 697a ldr r2, [r7, #20] + 8003e2c: 430a orrs r2, r1 + 8003e2e: 609a str r2, [r3, #8] /*-------------------------- USART PRESC Configuration -----------------------*/ /* Configure * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); - 800353c: 687b ldr r3, [r7, #4] - 800353e: 681b ldr r3, [r3, #0] - 8003540: 6adb ldr r3, [r3, #44] @ 0x2c - 8003542: 220f movs r2, #15 - 8003544: 4393 bics r3, r2 - 8003546: 0019 movs r1, r3 - 8003548: 687b ldr r3, [r7, #4] - 800354a: 6a5a ldr r2, [r3, #36] @ 0x24 - 800354c: 687b ldr r3, [r7, #4] - 800354e: 681b ldr r3, [r3, #0] - 8003550: 430a orrs r2, r1 - 8003552: 62da str r2, [r3, #44] @ 0x2c + 8003e30: 687b ldr r3, [r7, #4] + 8003e32: 681b ldr r3, [r3, #0] + 8003e34: 6adb ldr r3, [r3, #44] @ 0x2c + 8003e36: 220f movs r2, #15 + 8003e38: 4393 bics r3, r2 + 8003e3a: 0019 movs r1, r3 + 8003e3c: 687b ldr r3, [r7, #4] + 8003e3e: 6a5a ldr r2, [r3, #36] @ 0x24 + 8003e40: 687b ldr r3, [r7, #4] + 8003e42: 681b ldr r3, [r3, #0] + 8003e44: 430a orrs r2, r1 + 8003e46: 62da str r2, [r3, #44] @ 0x2c /*-------------------------- USART BRR Configuration -----------------------*/ UART_GETCLOCKSOURCE(huart, clocksource); - 8003554: 687b ldr r3, [r7, #4] - 8003556: 681b ldr r3, [r3, #0] - 8003558: 4a93 ldr r2, [pc, #588] @ (80037a8 ) - 800355a: 4293 cmp r3, r2 - 800355c: d127 bne.n 80035ae - 800355e: 4b93 ldr r3, [pc, #588] @ (80037ac ) - 8003560: 6d5b ldr r3, [r3, #84] @ 0x54 - 8003562: 2203 movs r2, #3 - 8003564: 4013 ands r3, r2 - 8003566: 2b03 cmp r3, #3 - 8003568: d017 beq.n 800359a - 800356a: d81b bhi.n 80035a4 - 800356c: 2b02 cmp r3, #2 - 800356e: d00a beq.n 8003586 - 8003570: d818 bhi.n 80035a4 - 8003572: 2b00 cmp r3, #0 - 8003574: d002 beq.n 800357c - 8003576: 2b01 cmp r3, #1 - 8003578: d00a beq.n 8003590 - 800357a: e013 b.n 80035a4 - 800357c: 231f movs r3, #31 - 800357e: 18fb adds r3, r7, r3 - 8003580: 2200 movs r2, #0 - 8003582: 701a strb r2, [r3, #0] - 8003584: e021 b.n 80035ca - 8003586: 231f movs r3, #31 - 8003588: 18fb adds r3, r7, r3 - 800358a: 2202 movs r2, #2 - 800358c: 701a strb r2, [r3, #0] - 800358e: e01c b.n 80035ca - 8003590: 231f movs r3, #31 - 8003592: 18fb adds r3, r7, r3 - 8003594: 2204 movs r2, #4 - 8003596: 701a strb r2, [r3, #0] - 8003598: e017 b.n 80035ca - 800359a: 231f movs r3, #31 - 800359c: 18fb adds r3, r7, r3 - 800359e: 2208 movs r2, #8 - 80035a0: 701a strb r2, [r3, #0] - 80035a2: e012 b.n 80035ca - 80035a4: 231f movs r3, #31 - 80035a6: 18fb adds r3, r7, r3 - 80035a8: 2210 movs r2, #16 - 80035aa: 701a strb r2, [r3, #0] - 80035ac: e00d b.n 80035ca - 80035ae: 687b ldr r3, [r7, #4] - 80035b0: 681b ldr r3, [r3, #0] - 80035b2: 4a7f ldr r2, [pc, #508] @ (80037b0 ) - 80035b4: 4293 cmp r3, r2 - 80035b6: d104 bne.n 80035c2 - 80035b8: 231f movs r3, #31 - 80035ba: 18fb adds r3, r7, r3 - 80035bc: 2200 movs r2, #0 - 80035be: 701a strb r2, [r3, #0] - 80035c0: e003 b.n 80035ca - 80035c2: 231f movs r3, #31 - 80035c4: 18fb adds r3, r7, r3 - 80035c6: 2210 movs r2, #16 - 80035c8: 701a strb r2, [r3, #0] + 8003e48: 687b ldr r3, [r7, #4] + 8003e4a: 681b ldr r3, [r3, #0] + 8003e4c: 4a93 ldr r2, [pc, #588] @ (800409c ) + 8003e4e: 4293 cmp r3, r2 + 8003e50: d127 bne.n 8003ea2 + 8003e52: 4b93 ldr r3, [pc, #588] @ (80040a0 ) + 8003e54: 6d5b ldr r3, [r3, #84] @ 0x54 + 8003e56: 2203 movs r2, #3 + 8003e58: 4013 ands r3, r2 + 8003e5a: 2b03 cmp r3, #3 + 8003e5c: d017 beq.n 8003e8e + 8003e5e: d81b bhi.n 8003e98 + 8003e60: 2b02 cmp r3, #2 + 8003e62: d00a beq.n 8003e7a + 8003e64: d818 bhi.n 8003e98 + 8003e66: 2b00 cmp r3, #0 + 8003e68: d002 beq.n 8003e70 + 8003e6a: 2b01 cmp r3, #1 + 8003e6c: d00a beq.n 8003e84 + 8003e6e: e013 b.n 8003e98 + 8003e70: 231f movs r3, #31 + 8003e72: 18fb adds r3, r7, r3 + 8003e74: 2200 movs r2, #0 + 8003e76: 701a strb r2, [r3, #0] + 8003e78: e021 b.n 8003ebe + 8003e7a: 231f movs r3, #31 + 8003e7c: 18fb adds r3, r7, r3 + 8003e7e: 2202 movs r2, #2 + 8003e80: 701a strb r2, [r3, #0] + 8003e82: e01c b.n 8003ebe + 8003e84: 231f movs r3, #31 + 8003e86: 18fb adds r3, r7, r3 + 8003e88: 2204 movs r2, #4 + 8003e8a: 701a strb r2, [r3, #0] + 8003e8c: e017 b.n 8003ebe + 8003e8e: 231f movs r3, #31 + 8003e90: 18fb adds r3, r7, r3 + 8003e92: 2208 movs r2, #8 + 8003e94: 701a strb r2, [r3, #0] + 8003e96: e012 b.n 8003ebe + 8003e98: 231f movs r3, #31 + 8003e9a: 18fb adds r3, r7, r3 + 8003e9c: 2210 movs r2, #16 + 8003e9e: 701a strb r2, [r3, #0] + 8003ea0: e00d b.n 8003ebe + 8003ea2: 687b ldr r3, [r7, #4] + 8003ea4: 681b ldr r3, [r3, #0] + 8003ea6: 4a7f ldr r2, [pc, #508] @ (80040a4 ) + 8003ea8: 4293 cmp r3, r2 + 8003eaa: d104 bne.n 8003eb6 + 8003eac: 231f movs r3, #31 + 8003eae: 18fb adds r3, r7, r3 + 8003eb0: 2200 movs r2, #0 + 8003eb2: 701a strb r2, [r3, #0] + 8003eb4: e003 b.n 8003ebe + 8003eb6: 231f movs r3, #31 + 8003eb8: 18fb adds r3, r7, r3 + 8003eba: 2210 movs r2, #16 + 8003ebc: 701a strb r2, [r3, #0] if (huart->Init.OverSampling == UART_OVERSAMPLING_8) - 80035ca: 687b ldr r3, [r7, #4] - 80035cc: 69da ldr r2, [r3, #28] - 80035ce: 2380 movs r3, #128 @ 0x80 - 80035d0: 021b lsls r3, r3, #8 - 80035d2: 429a cmp r2, r3 - 80035d4: d000 beq.n 80035d8 - 80035d6: e06f b.n 80036b8 + 8003ebe: 687b ldr r3, [r7, #4] + 8003ec0: 69da ldr r2, [r3, #28] + 8003ec2: 2380 movs r3, #128 @ 0x80 + 8003ec4: 021b lsls r3, r3, #8 + 8003ec6: 429a cmp r2, r3 + 8003ec8: d000 beq.n 8003ecc + 8003eca: e06f b.n 8003fac { switch (clocksource) - 80035d8: 231f movs r3, #31 - 80035da: 18fb adds r3, r7, r3 - 80035dc: 781b ldrb r3, [r3, #0] - 80035de: 2b08 cmp r3, #8 - 80035e0: d01f beq.n 8003622 - 80035e2: dc22 bgt.n 800362a - 80035e4: 2b04 cmp r3, #4 - 80035e6: d017 beq.n 8003618 - 80035e8: dc1f bgt.n 800362a - 80035ea: 2b00 cmp r3, #0 - 80035ec: d002 beq.n 80035f4 - 80035ee: 2b02 cmp r3, #2 - 80035f0: d005 beq.n 80035fe - 80035f2: e01a b.n 800362a + 8003ecc: 231f movs r3, #31 + 8003ece: 18fb adds r3, r7, r3 + 8003ed0: 781b ldrb r3, [r3, #0] + 8003ed2: 2b08 cmp r3, #8 + 8003ed4: d01f beq.n 8003f16 + 8003ed6: dc22 bgt.n 8003f1e + 8003ed8: 2b04 cmp r3, #4 + 8003eda: d017 beq.n 8003f0c + 8003edc: dc1f bgt.n 8003f1e + 8003ede: 2b00 cmp r3, #0 + 8003ee0: d002 beq.n 8003ee8 + 8003ee2: 2b02 cmp r3, #2 + 8003ee4: d005 beq.n 8003ef2 + 8003ee6: e01a b.n 8003f1e { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); - 80035f4: f7fe fcdc bl 8001fb0 - 80035f8: 0003 movs r3, r0 - 80035fa: 61bb str r3, [r7, #24] + 8003ee8: f7fe fcc4 bl 8002874 + 8003eec: 0003 movs r3, r0 + 8003eee: 61bb str r3, [r7, #24] break; - 80035fc: e01c b.n 8003638 + 8003ef0: e01c b.n 8003f2c case UART_CLOCKSOURCE_HSI: pclk = (HSI_VALUE / ((__HAL_RCC_GET_HSIKER_DIVIDER() >> RCC_CR_HSIKERDIV_Pos) + 1U)); - 80035fe: 4b6b ldr r3, [pc, #428] @ (80037ac ) - 8003600: 681b ldr r3, [r3, #0] - 8003602: 095b lsrs r3, r3, #5 - 8003604: 2207 movs r2, #7 - 8003606: 4013 ands r3, r2 - 8003608: 3301 adds r3, #1 - 800360a: 0019 movs r1, r3 - 800360c: 4869 ldr r0, [pc, #420] @ (80037b4 ) - 800360e: f7fc fd7b bl 8000108 <__udivsi3> - 8003612: 0003 movs r3, r0 - 8003614: 61bb str r3, [r7, #24] + 8003ef2: 4b6b ldr r3, [pc, #428] @ (80040a0 ) + 8003ef4: 681b ldr r3, [r3, #0] + 8003ef6: 095b lsrs r3, r3, #5 + 8003ef8: 2207 movs r2, #7 + 8003efa: 4013 ands r3, r2 + 8003efc: 3301 adds r3, #1 + 8003efe: 0019 movs r1, r3 + 8003f00: 4869 ldr r0, [pc, #420] @ (80040a8 ) + 8003f02: f7fc f901 bl 8000108 <__udivsi3> + 8003f06: 0003 movs r3, r0 + 8003f08: 61bb str r3, [r7, #24] break; - 8003616: e00f b.n 8003638 + 8003f0a: e00f b.n 8003f2c case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); - 8003618: f7fe fc5c bl 8001ed4 - 800361c: 0003 movs r3, r0 - 800361e: 61bb str r3, [r7, #24] + 8003f0c: f7fe fc44 bl 8002798 + 8003f10: 0003 movs r3, r0 + 8003f12: 61bb str r3, [r7, #24] break; - 8003620: e00a b.n 8003638 + 8003f14: e00a b.n 8003f2c case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; - 8003622: 2380 movs r3, #128 @ 0x80 - 8003624: 021b lsls r3, r3, #8 - 8003626: 61bb str r3, [r7, #24] + 8003f16: 2380 movs r3, #128 @ 0x80 + 8003f18: 021b lsls r3, r3, #8 + 8003f1a: 61bb str r3, [r7, #24] break; - 8003628: e006 b.n 8003638 + 8003f1c: e006 b.n 8003f2c default: pclk = 0U; - 800362a: 2300 movs r3, #0 - 800362c: 61bb str r3, [r7, #24] + 8003f1e: 2300 movs r3, #0 + 8003f20: 61bb str r3, [r7, #24] ret = HAL_ERROR; - 800362e: 231e movs r3, #30 - 8003630: 18fb adds r3, r7, r3 - 8003632: 2201 movs r2, #1 - 8003634: 701a strb r2, [r3, #0] + 8003f22: 231e movs r3, #30 + 8003f24: 18fb adds r3, r7, r3 + 8003f26: 2201 movs r2, #1 + 8003f28: 701a strb r2, [r3, #0] break; - 8003636: 46c0 nop @ (mov r8, r8) + 8003f2a: 46c0 nop @ (mov r8, r8) } /* USARTDIV must be greater than or equal to 0d16 */ if (pclk != 0U) - 8003638: 69bb ldr r3, [r7, #24] - 800363a: 2b00 cmp r3, #0 - 800363c: d100 bne.n 8003640 - 800363e: e097 b.n 8003770 + 8003f2c: 69bb ldr r3, [r7, #24] + 8003f2e: 2b00 cmp r3, #0 + 8003f30: d100 bne.n 8003f34 + 8003f32: e097 b.n 8004064 { usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); - 8003640: 687b ldr r3, [r7, #4] - 8003642: 6a5a ldr r2, [r3, #36] @ 0x24 - 8003644: 4b5c ldr r3, [pc, #368] @ (80037b8 ) - 8003646: 0052 lsls r2, r2, #1 - 8003648: 5ad3 ldrh r3, [r2, r3] - 800364a: 0019 movs r1, r3 - 800364c: 69b8 ldr r0, [r7, #24] - 800364e: f7fc fd5b bl 8000108 <__udivsi3> - 8003652: 0003 movs r3, r0 - 8003654: 005a lsls r2, r3, #1 - 8003656: 687b ldr r3, [r7, #4] - 8003658: 685b ldr r3, [r3, #4] - 800365a: 085b lsrs r3, r3, #1 - 800365c: 18d2 adds r2, r2, r3 - 800365e: 687b ldr r3, [r7, #4] - 8003660: 685b ldr r3, [r3, #4] - 8003662: 0019 movs r1, r3 - 8003664: 0010 movs r0, r2 - 8003666: f7fc fd4f bl 8000108 <__udivsi3> - 800366a: 0003 movs r3, r0 - 800366c: 613b str r3, [r7, #16] + 8003f34: 687b ldr r3, [r7, #4] + 8003f36: 6a5a ldr r2, [r3, #36] @ 0x24 + 8003f38: 4b5c ldr r3, [pc, #368] @ (80040ac ) + 8003f3a: 0052 lsls r2, r2, #1 + 8003f3c: 5ad3 ldrh r3, [r2, r3] + 8003f3e: 0019 movs r1, r3 + 8003f40: 69b8 ldr r0, [r7, #24] + 8003f42: f7fc f8e1 bl 8000108 <__udivsi3> + 8003f46: 0003 movs r3, r0 + 8003f48: 005a lsls r2, r3, #1 + 8003f4a: 687b ldr r3, [r7, #4] + 8003f4c: 685b ldr r3, [r3, #4] + 8003f4e: 085b lsrs r3, r3, #1 + 8003f50: 18d2 adds r2, r2, r3 + 8003f52: 687b ldr r3, [r7, #4] + 8003f54: 685b ldr r3, [r3, #4] + 8003f56: 0019 movs r1, r3 + 8003f58: 0010 movs r0, r2 + 8003f5a: f7fc f8d5 bl 8000108 <__udivsi3> + 8003f5e: 0003 movs r3, r0 + 8003f60: 613b str r3, [r7, #16] if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) - 800366e: 693b ldr r3, [r7, #16] - 8003670: 2b0f cmp r3, #15 - 8003672: d91c bls.n 80036ae - 8003674: 693a ldr r2, [r7, #16] - 8003676: 2380 movs r3, #128 @ 0x80 - 8003678: 025b lsls r3, r3, #9 - 800367a: 429a cmp r2, r3 - 800367c: d217 bcs.n 80036ae + 8003f62: 693b ldr r3, [r7, #16] + 8003f64: 2b0f cmp r3, #15 + 8003f66: d91c bls.n 8003fa2 + 8003f68: 693a ldr r2, [r7, #16] + 8003f6a: 2380 movs r3, #128 @ 0x80 + 8003f6c: 025b lsls r3, r3, #9 + 8003f6e: 429a cmp r2, r3 + 8003f70: d217 bcs.n 8003fa2 { brrtemp = (uint16_t)(usartdiv & 0xFFF0U); - 800367e: 693b ldr r3, [r7, #16] - 8003680: b29a uxth r2, r3 - 8003682: 200e movs r0, #14 - 8003684: 183b adds r3, r7, r0 - 8003686: 210f movs r1, #15 - 8003688: 438a bics r2, r1 - 800368a: 801a strh r2, [r3, #0] + 8003f72: 693b ldr r3, [r7, #16] + 8003f74: b29a uxth r2, r3 + 8003f76: 200e movs r0, #14 + 8003f78: 183b adds r3, r7, r0 + 8003f7a: 210f movs r1, #15 + 8003f7c: 438a bics r2, r1 + 8003f7e: 801a strh r2, [r3, #0] brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); - 800368c: 693b ldr r3, [r7, #16] - 800368e: 085b lsrs r3, r3, #1 - 8003690: b29b uxth r3, r3 - 8003692: 2207 movs r2, #7 - 8003694: 4013 ands r3, r2 - 8003696: b299 uxth r1, r3 - 8003698: 183b adds r3, r7, r0 - 800369a: 183a adds r2, r7, r0 - 800369c: 8812 ldrh r2, [r2, #0] - 800369e: 430a orrs r2, r1 - 80036a0: 801a strh r2, [r3, #0] + 8003f80: 693b ldr r3, [r7, #16] + 8003f82: 085b lsrs r3, r3, #1 + 8003f84: b29b uxth r3, r3 + 8003f86: 2207 movs r2, #7 + 8003f88: 4013 ands r3, r2 + 8003f8a: b299 uxth r1, r3 + 8003f8c: 183b adds r3, r7, r0 + 8003f8e: 183a adds r2, r7, r0 + 8003f90: 8812 ldrh r2, [r2, #0] + 8003f92: 430a orrs r2, r1 + 8003f94: 801a strh r2, [r3, #0] huart->Instance->BRR = brrtemp; - 80036a2: 687b ldr r3, [r7, #4] - 80036a4: 681b ldr r3, [r3, #0] - 80036a6: 183a adds r2, r7, r0 - 80036a8: 8812 ldrh r2, [r2, #0] - 80036aa: 60da str r2, [r3, #12] - 80036ac: e060 b.n 8003770 + 8003f96: 687b ldr r3, [r7, #4] + 8003f98: 681b ldr r3, [r3, #0] + 8003f9a: 183a adds r2, r7, r0 + 8003f9c: 8812 ldrh r2, [r2, #0] + 8003f9e: 60da str r2, [r3, #12] + 8003fa0: e060 b.n 8004064 } else { ret = HAL_ERROR; - 80036ae: 231e movs r3, #30 - 80036b0: 18fb adds r3, r7, r3 - 80036b2: 2201 movs r2, #1 - 80036b4: 701a strb r2, [r3, #0] - 80036b6: e05b b.n 8003770 + 8003fa2: 231e movs r3, #30 + 8003fa4: 18fb adds r3, r7, r3 + 8003fa6: 2201 movs r2, #1 + 8003fa8: 701a strb r2, [r3, #0] + 8003faa: e05b b.n 8004064 } } } else { switch (clocksource) - 80036b8: 231f movs r3, #31 - 80036ba: 18fb adds r3, r7, r3 - 80036bc: 781b ldrb r3, [r3, #0] - 80036be: 2b08 cmp r3, #8 - 80036c0: d01f beq.n 8003702 - 80036c2: dc22 bgt.n 800370a - 80036c4: 2b04 cmp r3, #4 - 80036c6: d017 beq.n 80036f8 - 80036c8: dc1f bgt.n 800370a - 80036ca: 2b00 cmp r3, #0 - 80036cc: d002 beq.n 80036d4 - 80036ce: 2b02 cmp r3, #2 - 80036d0: d005 beq.n 80036de - 80036d2: e01a b.n 800370a + 8003fac: 231f movs r3, #31 + 8003fae: 18fb adds r3, r7, r3 + 8003fb0: 781b ldrb r3, [r3, #0] + 8003fb2: 2b08 cmp r3, #8 + 8003fb4: d01f beq.n 8003ff6 + 8003fb6: dc22 bgt.n 8003ffe + 8003fb8: 2b04 cmp r3, #4 + 8003fba: d017 beq.n 8003fec + 8003fbc: dc1f bgt.n 8003ffe + 8003fbe: 2b00 cmp r3, #0 + 8003fc0: d002 beq.n 8003fc8 + 8003fc2: 2b02 cmp r3, #2 + 8003fc4: d005 beq.n 8003fd2 + 8003fc6: e01a b.n 8003ffe { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); - 80036d4: f7fe fc6c bl 8001fb0 - 80036d8: 0003 movs r3, r0 - 80036da: 61bb str r3, [r7, #24] + 8003fc8: f7fe fc54 bl 8002874 + 8003fcc: 0003 movs r3, r0 + 8003fce: 61bb str r3, [r7, #24] break; - 80036dc: e01c b.n 8003718 + 8003fd0: e01c b.n 800400c case UART_CLOCKSOURCE_HSI: pclk = (HSI_VALUE / ((__HAL_RCC_GET_HSIKER_DIVIDER() >> RCC_CR_HSIKERDIV_Pos) + 1U)); - 80036de: 4b33 ldr r3, [pc, #204] @ (80037ac ) - 80036e0: 681b ldr r3, [r3, #0] - 80036e2: 095b lsrs r3, r3, #5 - 80036e4: 2207 movs r2, #7 - 80036e6: 4013 ands r3, r2 - 80036e8: 3301 adds r3, #1 - 80036ea: 0019 movs r1, r3 - 80036ec: 4831 ldr r0, [pc, #196] @ (80037b4 ) - 80036ee: f7fc fd0b bl 8000108 <__udivsi3> - 80036f2: 0003 movs r3, r0 - 80036f4: 61bb str r3, [r7, #24] + 8003fd2: 4b33 ldr r3, [pc, #204] @ (80040a0 ) + 8003fd4: 681b ldr r3, [r3, #0] + 8003fd6: 095b lsrs r3, r3, #5 + 8003fd8: 2207 movs r2, #7 + 8003fda: 4013 ands r3, r2 + 8003fdc: 3301 adds r3, #1 + 8003fde: 0019 movs r1, r3 + 8003fe0: 4831 ldr r0, [pc, #196] @ (80040a8 ) + 8003fe2: f7fc f891 bl 8000108 <__udivsi3> + 8003fe6: 0003 movs r3, r0 + 8003fe8: 61bb str r3, [r7, #24] break; - 80036f6: e00f b.n 8003718 + 8003fea: e00f b.n 800400c case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); - 80036f8: f7fe fbec bl 8001ed4 - 80036fc: 0003 movs r3, r0 - 80036fe: 61bb str r3, [r7, #24] + 8003fec: f7fe fbd4 bl 8002798 + 8003ff0: 0003 movs r3, r0 + 8003ff2: 61bb str r3, [r7, #24] break; - 8003700: e00a b.n 8003718 + 8003ff4: e00a b.n 800400c case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; - 8003702: 2380 movs r3, #128 @ 0x80 - 8003704: 021b lsls r3, r3, #8 - 8003706: 61bb str r3, [r7, #24] + 8003ff6: 2380 movs r3, #128 @ 0x80 + 8003ff8: 021b lsls r3, r3, #8 + 8003ffa: 61bb str r3, [r7, #24] break; - 8003708: e006 b.n 8003718 + 8003ffc: e006 b.n 800400c default: pclk = 0U; - 800370a: 2300 movs r3, #0 - 800370c: 61bb str r3, [r7, #24] + 8003ffe: 2300 movs r3, #0 + 8004000: 61bb str r3, [r7, #24] ret = HAL_ERROR; - 800370e: 231e movs r3, #30 - 8003710: 18fb adds r3, r7, r3 - 8003712: 2201 movs r2, #1 - 8003714: 701a strb r2, [r3, #0] + 8004002: 231e movs r3, #30 + 8004004: 18fb adds r3, r7, r3 + 8004006: 2201 movs r2, #1 + 8004008: 701a strb r2, [r3, #0] break; - 8003716: 46c0 nop @ (mov r8, r8) + 800400a: 46c0 nop @ (mov r8, r8) } if (pclk != 0U) - 8003718: 69bb ldr r3, [r7, #24] - 800371a: 2b00 cmp r3, #0 - 800371c: d028 beq.n 8003770 + 800400c: 69bb ldr r3, [r7, #24] + 800400e: 2b00 cmp r3, #0 + 8004010: d028 beq.n 8004064 { /* USARTDIV must be greater than or equal to 0d16 */ usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); - 800371e: 687b ldr r3, [r7, #4] - 8003720: 6a5a ldr r2, [r3, #36] @ 0x24 - 8003722: 4b25 ldr r3, [pc, #148] @ (80037b8 ) - 8003724: 0052 lsls r2, r2, #1 - 8003726: 5ad3 ldrh r3, [r2, r3] - 8003728: 0019 movs r1, r3 - 800372a: 69b8 ldr r0, [r7, #24] - 800372c: f7fc fcec bl 8000108 <__udivsi3> - 8003730: 0003 movs r3, r0 - 8003732: 001a movs r2, r3 - 8003734: 687b ldr r3, [r7, #4] - 8003736: 685b ldr r3, [r3, #4] - 8003738: 085b lsrs r3, r3, #1 - 800373a: 18d2 adds r2, r2, r3 - 800373c: 687b ldr r3, [r7, #4] - 800373e: 685b ldr r3, [r3, #4] - 8003740: 0019 movs r1, r3 - 8003742: 0010 movs r0, r2 - 8003744: f7fc fce0 bl 8000108 <__udivsi3> - 8003748: 0003 movs r3, r0 - 800374a: 613b str r3, [r7, #16] + 8004012: 687b ldr r3, [r7, #4] + 8004014: 6a5a ldr r2, [r3, #36] @ 0x24 + 8004016: 4b25 ldr r3, [pc, #148] @ (80040ac ) + 8004018: 0052 lsls r2, r2, #1 + 800401a: 5ad3 ldrh r3, [r2, r3] + 800401c: 0019 movs r1, r3 + 800401e: 69b8 ldr r0, [r7, #24] + 8004020: f7fc f872 bl 8000108 <__udivsi3> + 8004024: 0003 movs r3, r0 + 8004026: 001a movs r2, r3 + 8004028: 687b ldr r3, [r7, #4] + 800402a: 685b ldr r3, [r3, #4] + 800402c: 085b lsrs r3, r3, #1 + 800402e: 18d2 adds r2, r2, r3 + 8004030: 687b ldr r3, [r7, #4] + 8004032: 685b ldr r3, [r3, #4] + 8004034: 0019 movs r1, r3 + 8004036: 0010 movs r0, r2 + 8004038: f7fc f866 bl 8000108 <__udivsi3> + 800403c: 0003 movs r3, r0 + 800403e: 613b str r3, [r7, #16] if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) - 800374c: 693b ldr r3, [r7, #16] - 800374e: 2b0f cmp r3, #15 - 8003750: d90a bls.n 8003768 - 8003752: 693a ldr r2, [r7, #16] - 8003754: 2380 movs r3, #128 @ 0x80 - 8003756: 025b lsls r3, r3, #9 - 8003758: 429a cmp r2, r3 - 800375a: d205 bcs.n 8003768 + 8004040: 693b ldr r3, [r7, #16] + 8004042: 2b0f cmp r3, #15 + 8004044: d90a bls.n 800405c + 8004046: 693a ldr r2, [r7, #16] + 8004048: 2380 movs r3, #128 @ 0x80 + 800404a: 025b lsls r3, r3, #9 + 800404c: 429a cmp r2, r3 + 800404e: d205 bcs.n 800405c { huart->Instance->BRR = (uint16_t)usartdiv; - 800375c: 693b ldr r3, [r7, #16] - 800375e: b29a uxth r2, r3 - 8003760: 687b ldr r3, [r7, #4] - 8003762: 681b ldr r3, [r3, #0] - 8003764: 60da str r2, [r3, #12] - 8003766: e003 b.n 8003770 + 8004050: 693b ldr r3, [r7, #16] + 8004052: b29a uxth r2, r3 + 8004054: 687b ldr r3, [r7, #4] + 8004056: 681b ldr r3, [r3, #0] + 8004058: 60da str r2, [r3, #12] + 800405a: e003 b.n 8004064 } else { ret = HAL_ERROR; - 8003768: 231e movs r3, #30 - 800376a: 18fb adds r3, r7, r3 - 800376c: 2201 movs r2, #1 - 800376e: 701a strb r2, [r3, #0] + 800405c: 231e movs r3, #30 + 800405e: 18fb adds r3, r7, r3 + 8004060: 2201 movs r2, #1 + 8004062: 701a strb r2, [r3, #0] } } } /* Initialize the number of data to process during RX/TX ISR execution */ huart->NbTxDataToProcess = 1; - 8003770: 687b ldr r3, [r7, #4] - 8003772: 226a movs r2, #106 @ 0x6a - 8003774: 2101 movs r1, #1 - 8003776: 5299 strh r1, [r3, r2] + 8004064: 687b ldr r3, [r7, #4] + 8004066: 226a movs r2, #106 @ 0x6a + 8004068: 2101 movs r1, #1 + 800406a: 5299 strh r1, [r3, r2] huart->NbRxDataToProcess = 1; - 8003778: 687b ldr r3, [r7, #4] - 800377a: 2268 movs r2, #104 @ 0x68 - 800377c: 2101 movs r1, #1 - 800377e: 5299 strh r1, [r3, r2] + 800406c: 687b ldr r3, [r7, #4] + 800406e: 2268 movs r2, #104 @ 0x68 + 8004070: 2101 movs r1, #1 + 8004072: 5299 strh r1, [r3, r2] /* Clear ISR function pointers */ huart->RxISR = NULL; - 8003780: 687b ldr r3, [r7, #4] - 8003782: 2200 movs r2, #0 - 8003784: 675a str r2, [r3, #116] @ 0x74 + 8004074: 687b ldr r3, [r7, #4] + 8004076: 2200 movs r2, #0 + 8004078: 675a str r2, [r3, #116] @ 0x74 huart->TxISR = NULL; - 8003786: 687b ldr r3, [r7, #4] - 8003788: 2200 movs r2, #0 - 800378a: 679a str r2, [r3, #120] @ 0x78 + 800407a: 687b ldr r3, [r7, #4] + 800407c: 2200 movs r2, #0 + 800407e: 679a str r2, [r3, #120] @ 0x78 return ret; - 800378c: 231e movs r3, #30 - 800378e: 18fb adds r3, r7, r3 - 8003790: 781b ldrb r3, [r3, #0] + 8004080: 231e movs r3, #30 + 8004082: 18fb adds r3, r7, r3 + 8004084: 781b ldrb r3, [r3, #0] } - 8003792: 0018 movs r0, r3 - 8003794: 46bd mov sp, r7 - 8003796: b008 add sp, #32 - 8003798: bd80 pop {r7, pc} - 800379a: 46c0 nop @ (mov r8, r8) - 800379c: cfff69f3 .word 0xcfff69f3 - 80037a0: ffffcfff .word 0xffffcfff - 80037a4: 11fff4ff .word 0x11fff4ff - 80037a8: 40013800 .word 0x40013800 - 80037ac: 40021000 .word 0x40021000 - 80037b0: 40004400 .word 0x40004400 - 80037b4: 02dc6c00 .word 0x02dc6c00 - 80037b8: 08004060 .word 0x08004060 + 8004086: 0018 movs r0, r3 + 8004088: 46bd mov sp, r7 + 800408a: b008 add sp, #32 + 800408c: bd80 pop {r7, pc} + 800408e: 46c0 nop @ (mov r8, r8) + 8004090: cfff69f3 .word 0xcfff69f3 + 8004094: ffffcfff .word 0xffffcfff + 8004098: 11fff4ff .word 0x11fff4ff + 800409c: 40013800 .word 0x40013800 + 80040a0: 40021000 .word 0x40021000 + 80040a4: 40004400 .word 0x40004400 + 80040a8: 02dc6c00 .word 0x02dc6c00 + 80040ac: 08004e70 .word 0x08004e70 -080037bc : +080040b0 : * @brief Configure the UART peripheral advanced features. * @param huart UART handle. * @retval None */ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) { - 80037bc: b580 push {r7, lr} - 80037be: b082 sub sp, #8 - 80037c0: af00 add r7, sp, #0 - 80037c2: 6078 str r0, [r7, #4] + 80040b0: b580 push {r7, lr} + 80040b2: b082 sub sp, #8 + 80040b4: af00 add r7, sp, #0 + 80040b6: 6078 str r0, [r7, #4] /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); /* if required, configure RX/TX pins swap */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) - 80037c4: 687b ldr r3, [r7, #4] - 80037c6: 6a9b ldr r3, [r3, #40] @ 0x28 - 80037c8: 2208 movs r2, #8 - 80037ca: 4013 ands r3, r2 - 80037cc: d00b beq.n 80037e6 + 80040b8: 687b ldr r3, [r7, #4] + 80040ba: 6a9b ldr r3, [r3, #40] @ 0x28 + 80040bc: 2208 movs r2, #8 + 80040be: 4013 ands r3, r2 + 80040c0: d00b beq.n 80040da { assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); - 80037ce: 687b ldr r3, [r7, #4] - 80037d0: 681b ldr r3, [r3, #0] - 80037d2: 685b ldr r3, [r3, #4] - 80037d4: 4a4a ldr r2, [pc, #296] @ (8003900 ) - 80037d6: 4013 ands r3, r2 - 80037d8: 0019 movs r1, r3 - 80037da: 687b ldr r3, [r7, #4] - 80037dc: 6b9a ldr r2, [r3, #56] @ 0x38 - 80037de: 687b ldr r3, [r7, #4] - 80037e0: 681b ldr r3, [r3, #0] - 80037e2: 430a orrs r2, r1 - 80037e4: 605a str r2, [r3, #4] + 80040c2: 687b ldr r3, [r7, #4] + 80040c4: 681b ldr r3, [r3, #0] + 80040c6: 685b ldr r3, [r3, #4] + 80040c8: 4a4a ldr r2, [pc, #296] @ (80041f4 ) + 80040ca: 4013 ands r3, r2 + 80040cc: 0019 movs r1, r3 + 80040ce: 687b ldr r3, [r7, #4] + 80040d0: 6b9a ldr r2, [r3, #56] @ 0x38 + 80040d2: 687b ldr r3, [r7, #4] + 80040d4: 681b ldr r3, [r3, #0] + 80040d6: 430a orrs r2, r1 + 80040d8: 605a str r2, [r3, #4] } /* if required, configure TX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) - 80037e6: 687b ldr r3, [r7, #4] - 80037e8: 6a9b ldr r3, [r3, #40] @ 0x28 - 80037ea: 2201 movs r2, #1 - 80037ec: 4013 ands r3, r2 - 80037ee: d00b beq.n 8003808 + 80040da: 687b ldr r3, [r7, #4] + 80040dc: 6a9b ldr r3, [r3, #40] @ 0x28 + 80040de: 2201 movs r2, #1 + 80040e0: 4013 ands r3, r2 + 80040e2: d00b beq.n 80040fc { assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); - 80037f0: 687b ldr r3, [r7, #4] - 80037f2: 681b ldr r3, [r3, #0] - 80037f4: 685b ldr r3, [r3, #4] - 80037f6: 4a43 ldr r2, [pc, #268] @ (8003904 ) - 80037f8: 4013 ands r3, r2 - 80037fa: 0019 movs r1, r3 - 80037fc: 687b ldr r3, [r7, #4] - 80037fe: 6ada ldr r2, [r3, #44] @ 0x2c - 8003800: 687b ldr r3, [r7, #4] - 8003802: 681b ldr r3, [r3, #0] - 8003804: 430a orrs r2, r1 - 8003806: 605a str r2, [r3, #4] + 80040e4: 687b ldr r3, [r7, #4] + 80040e6: 681b ldr r3, [r3, #0] + 80040e8: 685b ldr r3, [r3, #4] + 80040ea: 4a43 ldr r2, [pc, #268] @ (80041f8 ) + 80040ec: 4013 ands r3, r2 + 80040ee: 0019 movs r1, r3 + 80040f0: 687b ldr r3, [r7, #4] + 80040f2: 6ada ldr r2, [r3, #44] @ 0x2c + 80040f4: 687b ldr r3, [r7, #4] + 80040f6: 681b ldr r3, [r3, #0] + 80040f8: 430a orrs r2, r1 + 80040fa: 605a str r2, [r3, #4] } /* if required, configure RX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) - 8003808: 687b ldr r3, [r7, #4] - 800380a: 6a9b ldr r3, [r3, #40] @ 0x28 - 800380c: 2202 movs r2, #2 - 800380e: 4013 ands r3, r2 - 8003810: d00b beq.n 800382a + 80040fc: 687b ldr r3, [r7, #4] + 80040fe: 6a9b ldr r3, [r3, #40] @ 0x28 + 8004100: 2202 movs r2, #2 + 8004102: 4013 ands r3, r2 + 8004104: d00b beq.n 800411e { assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); - 8003812: 687b ldr r3, [r7, #4] - 8003814: 681b ldr r3, [r3, #0] - 8003816: 685b ldr r3, [r3, #4] - 8003818: 4a3b ldr r2, [pc, #236] @ (8003908 ) - 800381a: 4013 ands r3, r2 - 800381c: 0019 movs r1, r3 - 800381e: 687b ldr r3, [r7, #4] - 8003820: 6b1a ldr r2, [r3, #48] @ 0x30 - 8003822: 687b ldr r3, [r7, #4] - 8003824: 681b ldr r3, [r3, #0] - 8003826: 430a orrs r2, r1 - 8003828: 605a str r2, [r3, #4] + 8004106: 687b ldr r3, [r7, #4] + 8004108: 681b ldr r3, [r3, #0] + 800410a: 685b ldr r3, [r3, #4] + 800410c: 4a3b ldr r2, [pc, #236] @ (80041fc ) + 800410e: 4013 ands r3, r2 + 8004110: 0019 movs r1, r3 + 8004112: 687b ldr r3, [r7, #4] + 8004114: 6b1a ldr r2, [r3, #48] @ 0x30 + 8004116: 687b ldr r3, [r7, #4] + 8004118: 681b ldr r3, [r3, #0] + 800411a: 430a orrs r2, r1 + 800411c: 605a str r2, [r3, #4] } /* if required, configure data inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) - 800382a: 687b ldr r3, [r7, #4] - 800382c: 6a9b ldr r3, [r3, #40] @ 0x28 - 800382e: 2204 movs r2, #4 - 8003830: 4013 ands r3, r2 - 8003832: d00b beq.n 800384c + 800411e: 687b ldr r3, [r7, #4] + 8004120: 6a9b ldr r3, [r3, #40] @ 0x28 + 8004122: 2204 movs r2, #4 + 8004124: 4013 ands r3, r2 + 8004126: d00b beq.n 8004140 { assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); - 8003834: 687b ldr r3, [r7, #4] - 8003836: 681b ldr r3, [r3, #0] - 8003838: 685b ldr r3, [r3, #4] - 800383a: 4a34 ldr r2, [pc, #208] @ (800390c ) - 800383c: 4013 ands r3, r2 - 800383e: 0019 movs r1, r3 - 8003840: 687b ldr r3, [r7, #4] - 8003842: 6b5a ldr r2, [r3, #52] @ 0x34 - 8003844: 687b ldr r3, [r7, #4] - 8003846: 681b ldr r3, [r3, #0] - 8003848: 430a orrs r2, r1 - 800384a: 605a str r2, [r3, #4] + 8004128: 687b ldr r3, [r7, #4] + 800412a: 681b ldr r3, [r3, #0] + 800412c: 685b ldr r3, [r3, #4] + 800412e: 4a34 ldr r2, [pc, #208] @ (8004200 ) + 8004130: 4013 ands r3, r2 + 8004132: 0019 movs r1, r3 + 8004134: 687b ldr r3, [r7, #4] + 8004136: 6b5a ldr r2, [r3, #52] @ 0x34 + 8004138: 687b ldr r3, [r7, #4] + 800413a: 681b ldr r3, [r3, #0] + 800413c: 430a orrs r2, r1 + 800413e: 605a str r2, [r3, #4] } /* if required, configure RX overrun detection disabling */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) - 800384c: 687b ldr r3, [r7, #4] - 800384e: 6a9b ldr r3, [r3, #40] @ 0x28 - 8003850: 2210 movs r2, #16 - 8003852: 4013 ands r3, r2 - 8003854: d00b beq.n 800386e + 8004140: 687b ldr r3, [r7, #4] + 8004142: 6a9b ldr r3, [r3, #40] @ 0x28 + 8004144: 2210 movs r2, #16 + 8004146: 4013 ands r3, r2 + 8004148: d00b beq.n 8004162 { assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); - 8003856: 687b ldr r3, [r7, #4] - 8003858: 681b ldr r3, [r3, #0] - 800385a: 689b ldr r3, [r3, #8] - 800385c: 4a2c ldr r2, [pc, #176] @ (8003910 ) - 800385e: 4013 ands r3, r2 - 8003860: 0019 movs r1, r3 - 8003862: 687b ldr r3, [r7, #4] - 8003864: 6bda ldr r2, [r3, #60] @ 0x3c - 8003866: 687b ldr r3, [r7, #4] - 8003868: 681b ldr r3, [r3, #0] - 800386a: 430a orrs r2, r1 - 800386c: 609a str r2, [r3, #8] + 800414a: 687b ldr r3, [r7, #4] + 800414c: 681b ldr r3, [r3, #0] + 800414e: 689b ldr r3, [r3, #8] + 8004150: 4a2c ldr r2, [pc, #176] @ (8004204 ) + 8004152: 4013 ands r3, r2 + 8004154: 0019 movs r1, r3 + 8004156: 687b ldr r3, [r7, #4] + 8004158: 6bda ldr r2, [r3, #60] @ 0x3c + 800415a: 687b ldr r3, [r7, #4] + 800415c: 681b ldr r3, [r3, #0] + 800415e: 430a orrs r2, r1 + 8004160: 609a str r2, [r3, #8] } #if defined(HAL_DMA_MODULE_ENABLED) /* if required, configure DMA disabling on reception error */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) - 800386e: 687b ldr r3, [r7, #4] - 8003870: 6a9b ldr r3, [r3, #40] @ 0x28 - 8003872: 2220 movs r2, #32 - 8003874: 4013 ands r3, r2 - 8003876: d00b beq.n 8003890 + 8004162: 687b ldr r3, [r7, #4] + 8004164: 6a9b ldr r3, [r3, #40] @ 0x28 + 8004166: 2220 movs r2, #32 + 8004168: 4013 ands r3, r2 + 800416a: d00b beq.n 8004184 { assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); - 8003878: 687b ldr r3, [r7, #4] - 800387a: 681b ldr r3, [r3, #0] - 800387c: 689b ldr r3, [r3, #8] - 800387e: 4a25 ldr r2, [pc, #148] @ (8003914 ) - 8003880: 4013 ands r3, r2 - 8003882: 0019 movs r1, r3 - 8003884: 687b ldr r3, [r7, #4] - 8003886: 6c1a ldr r2, [r3, #64] @ 0x40 - 8003888: 687b ldr r3, [r7, #4] - 800388a: 681b ldr r3, [r3, #0] - 800388c: 430a orrs r2, r1 - 800388e: 609a str r2, [r3, #8] + 800416c: 687b ldr r3, [r7, #4] + 800416e: 681b ldr r3, [r3, #0] + 8004170: 689b ldr r3, [r3, #8] + 8004172: 4a25 ldr r2, [pc, #148] @ (8004208 ) + 8004174: 4013 ands r3, r2 + 8004176: 0019 movs r1, r3 + 8004178: 687b ldr r3, [r7, #4] + 800417a: 6c1a ldr r2, [r3, #64] @ 0x40 + 800417c: 687b ldr r3, [r7, #4] + 800417e: 681b ldr r3, [r3, #0] + 8004180: 430a orrs r2, r1 + 8004182: 609a str r2, [r3, #8] } #endif /* HAL_DMA_MODULE_ENABLED */ /* if required, configure auto Baud rate detection scheme */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) - 8003890: 687b ldr r3, [r7, #4] - 8003892: 6a9b ldr r3, [r3, #40] @ 0x28 - 8003894: 2240 movs r2, #64 @ 0x40 - 8003896: 4013 ands r3, r2 - 8003898: d01d beq.n 80038d6 + 8004184: 687b ldr r3, [r7, #4] + 8004186: 6a9b ldr r3, [r3, #40] @ 0x28 + 8004188: 2240 movs r2, #64 @ 0x40 + 800418a: 4013 ands r3, r2 + 800418c: d01d beq.n 80041ca { assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); - 800389a: 687b ldr r3, [r7, #4] - 800389c: 681b ldr r3, [r3, #0] - 800389e: 685b ldr r3, [r3, #4] - 80038a0: 4a1d ldr r2, [pc, #116] @ (8003918 ) - 80038a2: 4013 ands r3, r2 - 80038a4: 0019 movs r1, r3 - 80038a6: 687b ldr r3, [r7, #4] - 80038a8: 6c5a ldr r2, [r3, #68] @ 0x44 - 80038aa: 687b ldr r3, [r7, #4] - 80038ac: 681b ldr r3, [r3, #0] - 80038ae: 430a orrs r2, r1 - 80038b0: 605a str r2, [r3, #4] + 800418e: 687b ldr r3, [r7, #4] + 8004190: 681b ldr r3, [r3, #0] + 8004192: 685b ldr r3, [r3, #4] + 8004194: 4a1d ldr r2, [pc, #116] @ (800420c ) + 8004196: 4013 ands r3, r2 + 8004198: 0019 movs r1, r3 + 800419a: 687b ldr r3, [r7, #4] + 800419c: 6c5a ldr r2, [r3, #68] @ 0x44 + 800419e: 687b ldr r3, [r7, #4] + 80041a0: 681b ldr r3, [r3, #0] + 80041a2: 430a orrs r2, r1 + 80041a4: 605a str r2, [r3, #4] /* set auto Baudrate detection parameters if detection is enabled */ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) - 80038b2: 687b ldr r3, [r7, #4] - 80038b4: 6c5a ldr r2, [r3, #68] @ 0x44 - 80038b6: 2380 movs r3, #128 @ 0x80 - 80038b8: 035b lsls r3, r3, #13 - 80038ba: 429a cmp r2, r3 - 80038bc: d10b bne.n 80038d6 + 80041a6: 687b ldr r3, [r7, #4] + 80041a8: 6c5a ldr r2, [r3, #68] @ 0x44 + 80041aa: 2380 movs r3, #128 @ 0x80 + 80041ac: 035b lsls r3, r3, #13 + 80041ae: 429a cmp r2, r3 + 80041b0: d10b bne.n 80041ca { assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); - 80038be: 687b ldr r3, [r7, #4] - 80038c0: 681b ldr r3, [r3, #0] - 80038c2: 685b ldr r3, [r3, #4] - 80038c4: 4a15 ldr r2, [pc, #84] @ (800391c ) - 80038c6: 4013 ands r3, r2 - 80038c8: 0019 movs r1, r3 - 80038ca: 687b ldr r3, [r7, #4] - 80038cc: 6c9a ldr r2, [r3, #72] @ 0x48 - 80038ce: 687b ldr r3, [r7, #4] - 80038d0: 681b ldr r3, [r3, #0] - 80038d2: 430a orrs r2, r1 - 80038d4: 605a str r2, [r3, #4] + 80041b2: 687b ldr r3, [r7, #4] + 80041b4: 681b ldr r3, [r3, #0] + 80041b6: 685b ldr r3, [r3, #4] + 80041b8: 4a15 ldr r2, [pc, #84] @ (8004210 ) + 80041ba: 4013 ands r3, r2 + 80041bc: 0019 movs r1, r3 + 80041be: 687b ldr r3, [r7, #4] + 80041c0: 6c9a ldr r2, [r3, #72] @ 0x48 + 80041c2: 687b ldr r3, [r7, #4] + 80041c4: 681b ldr r3, [r3, #0] + 80041c6: 430a orrs r2, r1 + 80041c8: 605a str r2, [r3, #4] } } /* if required, configure MSB first on communication line */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) - 80038d6: 687b ldr r3, [r7, #4] - 80038d8: 6a9b ldr r3, [r3, #40] @ 0x28 - 80038da: 2280 movs r2, #128 @ 0x80 - 80038dc: 4013 ands r3, r2 - 80038de: d00b beq.n 80038f8 + 80041ca: 687b ldr r3, [r7, #4] + 80041cc: 6a9b ldr r3, [r3, #40] @ 0x28 + 80041ce: 2280 movs r2, #128 @ 0x80 + 80041d0: 4013 ands r3, r2 + 80041d2: d00b beq.n 80041ec { assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); - 80038e0: 687b ldr r3, [r7, #4] - 80038e2: 681b ldr r3, [r3, #0] - 80038e4: 685b ldr r3, [r3, #4] - 80038e6: 4a0e ldr r2, [pc, #56] @ (8003920 ) - 80038e8: 4013 ands r3, r2 - 80038ea: 0019 movs r1, r3 - 80038ec: 687b ldr r3, [r7, #4] - 80038ee: 6cda ldr r2, [r3, #76] @ 0x4c - 80038f0: 687b ldr r3, [r7, #4] - 80038f2: 681b ldr r3, [r3, #0] - 80038f4: 430a orrs r2, r1 - 80038f6: 605a str r2, [r3, #4] + 80041d4: 687b ldr r3, [r7, #4] + 80041d6: 681b ldr r3, [r3, #0] + 80041d8: 685b ldr r3, [r3, #4] + 80041da: 4a0e ldr r2, [pc, #56] @ (8004214 ) + 80041dc: 4013 ands r3, r2 + 80041de: 0019 movs r1, r3 + 80041e0: 687b ldr r3, [r7, #4] + 80041e2: 6cda ldr r2, [r3, #76] @ 0x4c + 80041e4: 687b ldr r3, [r7, #4] + 80041e6: 681b ldr r3, [r3, #0] + 80041e8: 430a orrs r2, r1 + 80041ea: 605a str r2, [r3, #4] } } - 80038f8: 46c0 nop @ (mov r8, r8) - 80038fa: 46bd mov sp, r7 - 80038fc: b002 add sp, #8 - 80038fe: bd80 pop {r7, pc} - 8003900: ffff7fff .word 0xffff7fff - 8003904: fffdffff .word 0xfffdffff - 8003908: fffeffff .word 0xfffeffff - 800390c: fffbffff .word 0xfffbffff - 8003910: ffffefff .word 0xffffefff - 8003914: ffffdfff .word 0xffffdfff - 8003918: ffefffff .word 0xffefffff - 800391c: ff9fffff .word 0xff9fffff - 8003920: fff7ffff .word 0xfff7ffff + 80041ec: 46c0 nop @ (mov r8, r8) + 80041ee: 46bd mov sp, r7 + 80041f0: b002 add sp, #8 + 80041f2: bd80 pop {r7, pc} + 80041f4: ffff7fff .word 0xffff7fff + 80041f8: fffdffff .word 0xfffdffff + 80041fc: fffeffff .word 0xfffeffff + 8004200: fffbffff .word 0xfffbffff + 8004204: ffffefff .word 0xffffefff + 8004208: ffffdfff .word 0xffffdfff + 800420c: ffefffff .word 0xffefffff + 8004210: ff9fffff .word 0xff9fffff + 8004214: fff7ffff .word 0xfff7ffff -08003924 : +08004218 : * @brief Check the UART Idle State. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { - 8003924: b580 push {r7, lr} - 8003926: b092 sub sp, #72 @ 0x48 - 8003928: af02 add r7, sp, #8 - 800392a: 6078 str r0, [r7, #4] + 8004218: b580 push {r7, lr} + 800421a: b092 sub sp, #72 @ 0x48 + 800421c: af02 add r7, sp, #8 + 800421e: 6078 str r0, [r7, #4] uint32_t tickstart; /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; - 800392c: 687b ldr r3, [r7, #4] - 800392e: 2290 movs r2, #144 @ 0x90 - 8003930: 2100 movs r1, #0 - 8003932: 5099 str r1, [r3, r2] + 8004220: 687b ldr r3, [r7, #4] + 8004222: 2290 movs r2, #144 @ 0x90 + 8004224: 2100 movs r1, #0 + 8004226: 5099 str r1, [r3, r2] /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); - 8003934: f7fd fb9e bl 8001074 - 8003938: 0003 movs r3, r0 - 800393a: 63fb str r3, [r7, #60] @ 0x3c + 8004228: f7fd fa84 bl 8001734 + 800422c: 0003 movs r3, r0 + 800422e: 63fb str r3, [r7, #60] @ 0x3c /* Check if the Transmitter is enabled */ if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) - 800393c: 687b ldr r3, [r7, #4] - 800393e: 681b ldr r3, [r3, #0] - 8003940: 681b ldr r3, [r3, #0] - 8003942: 2208 movs r2, #8 - 8003944: 4013 ands r3, r2 - 8003946: 2b08 cmp r3, #8 - 8003948: d12d bne.n 80039a6 + 8004230: 687b ldr r3, [r7, #4] + 8004232: 681b ldr r3, [r3, #0] + 8004234: 681b ldr r3, [r3, #0] + 8004236: 2208 movs r2, #8 + 8004238: 4013 ands r3, r2 + 800423a: 2b08 cmp r3, #8 + 800423c: d12d bne.n 800429a { /* Wait until TEACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - 800394a: 6bfb ldr r3, [r7, #60] @ 0x3c - 800394c: 2280 movs r2, #128 @ 0x80 - 800394e: 0391 lsls r1, r2, #14 - 8003950: 6878 ldr r0, [r7, #4] - 8003952: 4a47 ldr r2, [pc, #284] @ (8003a70 ) - 8003954: 9200 str r2, [sp, #0] - 8003956: 2200 movs r2, #0 - 8003958: f000 f88e bl 8003a78 - 800395c: 1e03 subs r3, r0, #0 - 800395e: d022 beq.n 80039a6 + 800423e: 6bfb ldr r3, [r7, #60] @ 0x3c + 8004240: 2280 movs r2, #128 @ 0x80 + 8004242: 0391 lsls r1, r2, #14 + 8004244: 6878 ldr r0, [r7, #4] + 8004246: 4a47 ldr r2, [pc, #284] @ (8004364 ) + 8004248: 9200 str r2, [sp, #0] + 800424a: 2200 movs r2, #0 + 800424c: f000 f88e bl 800436c + 8004250: 1e03 subs r3, r0, #0 + 8004252: d022 beq.n 800429a */ __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) { uint32_t result; __ASM volatile ("MRS %0, primask" : "=r" (result) ); - 8003960: f3ef 8310 mrs r3, PRIMASK - 8003964: 627b str r3, [r7, #36] @ 0x24 + 8004254: f3ef 8310 mrs r3, PRIMASK + 8004258: 627b str r3, [r7, #36] @ 0x24 return(result); - 8003966: 6a7b ldr r3, [r7, #36] @ 0x24 + 800425a: 6a7b ldr r3, [r7, #36] @ 0x24 { /* Disable TXE interrupt for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); - 8003968: 63bb str r3, [r7, #56] @ 0x38 - 800396a: 2301 movs r3, #1 - 800396c: 62bb str r3, [r7, #40] @ 0x28 + 800425c: 63bb str r3, [r7, #56] @ 0x38 + 800425e: 2301 movs r3, #1 + 8004260: 62bb str r3, [r7, #40] @ 0x28 \details Assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) { __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 800396e: 6abb ldr r3, [r7, #40] @ 0x28 - 8003970: f383 8810 msr PRIMASK, r3 + 8004262: 6abb ldr r3, [r7, #40] @ 0x28 + 8004264: f383 8810 msr PRIMASK, r3 } - 8003974: 46c0 nop @ (mov r8, r8) - 8003976: 687b ldr r3, [r7, #4] - 8003978: 681b ldr r3, [r3, #0] - 800397a: 681a ldr r2, [r3, #0] - 800397c: 687b ldr r3, [r7, #4] - 800397e: 681b ldr r3, [r3, #0] - 8003980: 2180 movs r1, #128 @ 0x80 - 8003982: 438a bics r2, r1 - 8003984: 601a str r2, [r3, #0] - 8003986: 6bbb ldr r3, [r7, #56] @ 0x38 - 8003988: 62fb str r3, [r7, #44] @ 0x2c + 8004268: 46c0 nop @ (mov r8, r8) + 800426a: 687b ldr r3, [r7, #4] + 800426c: 681b ldr r3, [r3, #0] + 800426e: 681a ldr r2, [r3, #0] + 8004270: 687b ldr r3, [r7, #4] + 8004272: 681b ldr r3, [r3, #0] + 8004274: 2180 movs r1, #128 @ 0x80 + 8004276: 438a bics r2, r1 + 8004278: 601a str r2, [r3, #0] + 800427a: 6bbb ldr r3, [r7, #56] @ 0x38 + 800427c: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 800398a: 6afb ldr r3, [r7, #44] @ 0x2c - 800398c: f383 8810 msr PRIMASK, r3 + 800427e: 6afb ldr r3, [r7, #44] @ 0x2c + 8004280: f383 8810 msr PRIMASK, r3 } - 8003990: 46c0 nop @ (mov r8, r8) + 8004284: 46c0 nop @ (mov r8, r8) huart->gState = HAL_UART_STATE_READY; - 8003992: 687b ldr r3, [r7, #4] - 8003994: 2288 movs r2, #136 @ 0x88 - 8003996: 2120 movs r1, #32 - 8003998: 5099 str r1, [r3, r2] + 8004286: 687b ldr r3, [r7, #4] + 8004288: 2288 movs r2, #136 @ 0x88 + 800428a: 2120 movs r1, #32 + 800428c: 5099 str r1, [r3, r2] __HAL_UNLOCK(huart); - 800399a: 687b ldr r3, [r7, #4] - 800399c: 2284 movs r2, #132 @ 0x84 - 800399e: 2100 movs r1, #0 - 80039a0: 5499 strb r1, [r3, r2] + 800428e: 687b ldr r3, [r7, #4] + 8004290: 2284 movs r2, #132 @ 0x84 + 8004292: 2100 movs r1, #0 + 8004294: 5499 strb r1, [r3, r2] /* Timeout occurred */ return HAL_TIMEOUT; - 80039a2: 2303 movs r3, #3 - 80039a4: e060 b.n 8003a68 + 8004296: 2303 movs r3, #3 + 8004298: e060 b.n 800435c } } /* Check if the Receiver is enabled */ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) - 80039a6: 687b ldr r3, [r7, #4] - 80039a8: 681b ldr r3, [r3, #0] - 80039aa: 681b ldr r3, [r3, #0] - 80039ac: 2204 movs r2, #4 - 80039ae: 4013 ands r3, r2 - 80039b0: 2b04 cmp r3, #4 - 80039b2: d146 bne.n 8003a42 + 800429a: 687b ldr r3, [r7, #4] + 800429c: 681b ldr r3, [r3, #0] + 800429e: 681b ldr r3, [r3, #0] + 80042a0: 2204 movs r2, #4 + 80042a2: 4013 ands r3, r2 + 80042a4: 2b04 cmp r3, #4 + 80042a6: d146 bne.n 8004336 { /* Wait until REACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - 80039b4: 6bfb ldr r3, [r7, #60] @ 0x3c - 80039b6: 2280 movs r2, #128 @ 0x80 - 80039b8: 03d1 lsls r1, r2, #15 - 80039ba: 6878 ldr r0, [r7, #4] - 80039bc: 4a2c ldr r2, [pc, #176] @ (8003a70 ) - 80039be: 9200 str r2, [sp, #0] - 80039c0: 2200 movs r2, #0 - 80039c2: f000 f859 bl 8003a78 - 80039c6: 1e03 subs r3, r0, #0 - 80039c8: d03b beq.n 8003a42 + 80042a8: 6bfb ldr r3, [r7, #60] @ 0x3c + 80042aa: 2280 movs r2, #128 @ 0x80 + 80042ac: 03d1 lsls r1, r2, #15 + 80042ae: 6878 ldr r0, [r7, #4] + 80042b0: 4a2c ldr r2, [pc, #176] @ (8004364 ) + 80042b2: 9200 str r2, [sp, #0] + 80042b4: 2200 movs r2, #0 + 80042b6: f000 f859 bl 800436c + 80042ba: 1e03 subs r3, r0, #0 + 80042bc: d03b beq.n 8004336 __ASM volatile ("MRS %0, primask" : "=r" (result) ); - 80039ca: f3ef 8310 mrs r3, PRIMASK - 80039ce: 60fb str r3, [r7, #12] + 80042be: f3ef 8310 mrs r3, PRIMASK + 80042c2: 60fb str r3, [r7, #12] return(result); - 80039d0: 68fb ldr r3, [r7, #12] + 80042c4: 68fb ldr r3, [r7, #12] { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); - 80039d2: 637b str r3, [r7, #52] @ 0x34 - 80039d4: 2301 movs r3, #1 - 80039d6: 613b str r3, [r7, #16] + 80042c6: 637b str r3, [r7, #52] @ 0x34 + 80042c8: 2301 movs r3, #1 + 80042ca: 613b str r3, [r7, #16] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 80039d8: 693b ldr r3, [r7, #16] - 80039da: f383 8810 msr PRIMASK, r3 + 80042cc: 693b ldr r3, [r7, #16] + 80042ce: f383 8810 msr PRIMASK, r3 } - 80039de: 46c0 nop @ (mov r8, r8) - 80039e0: 687b ldr r3, [r7, #4] - 80039e2: 681b ldr r3, [r3, #0] - 80039e4: 681a ldr r2, [r3, #0] - 80039e6: 687b ldr r3, [r7, #4] - 80039e8: 681b ldr r3, [r3, #0] - 80039ea: 4922 ldr r1, [pc, #136] @ (8003a74 ) - 80039ec: 400a ands r2, r1 - 80039ee: 601a str r2, [r3, #0] - 80039f0: 6b7b ldr r3, [r7, #52] @ 0x34 - 80039f2: 617b str r3, [r7, #20] + 80042d2: 46c0 nop @ (mov r8, r8) + 80042d4: 687b ldr r3, [r7, #4] + 80042d6: 681b ldr r3, [r3, #0] + 80042d8: 681a ldr r2, [r3, #0] + 80042da: 687b ldr r3, [r7, #4] + 80042dc: 681b ldr r3, [r3, #0] + 80042de: 4922 ldr r1, [pc, #136] @ (8004368 ) + 80042e0: 400a ands r2, r1 + 80042e2: 601a str r2, [r3, #0] + 80042e4: 6b7b ldr r3, [r7, #52] @ 0x34 + 80042e6: 617b str r3, [r7, #20] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 80039f4: 697b ldr r3, [r7, #20] - 80039f6: f383 8810 msr PRIMASK, r3 + 80042e8: 697b ldr r3, [r7, #20] + 80042ea: f383 8810 msr PRIMASK, r3 } - 80039fa: 46c0 nop @ (mov r8, r8) + 80042ee: 46c0 nop @ (mov r8, r8) __ASM volatile ("MRS %0, primask" : "=r" (result) ); - 80039fc: f3ef 8310 mrs r3, PRIMASK - 8003a00: 61bb str r3, [r7, #24] + 80042f0: f3ef 8310 mrs r3, PRIMASK + 80042f4: 61bb str r3, [r7, #24] return(result); - 8003a02: 69bb ldr r3, [r7, #24] + 80042f6: 69bb ldr r3, [r7, #24] ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - 8003a04: 633b str r3, [r7, #48] @ 0x30 - 8003a06: 2301 movs r3, #1 - 8003a08: 61fb str r3, [r7, #28] + 80042f8: 633b str r3, [r7, #48] @ 0x30 + 80042fa: 2301 movs r3, #1 + 80042fc: 61fb str r3, [r7, #28] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 8003a0a: 69fb ldr r3, [r7, #28] - 8003a0c: f383 8810 msr PRIMASK, r3 + 80042fe: 69fb ldr r3, [r7, #28] + 8004300: f383 8810 msr PRIMASK, r3 } - 8003a10: 46c0 nop @ (mov r8, r8) - 8003a12: 687b ldr r3, [r7, #4] - 8003a14: 681b ldr r3, [r3, #0] - 8003a16: 689a ldr r2, [r3, #8] - 8003a18: 687b ldr r3, [r7, #4] - 8003a1a: 681b ldr r3, [r3, #0] - 8003a1c: 2101 movs r1, #1 - 8003a1e: 438a bics r2, r1 - 8003a20: 609a str r2, [r3, #8] - 8003a22: 6b3b ldr r3, [r7, #48] @ 0x30 - 8003a24: 623b str r3, [r7, #32] + 8004304: 46c0 nop @ (mov r8, r8) + 8004306: 687b ldr r3, [r7, #4] + 8004308: 681b ldr r3, [r3, #0] + 800430a: 689a ldr r2, [r3, #8] + 800430c: 687b ldr r3, [r7, #4] + 800430e: 681b ldr r3, [r3, #0] + 8004310: 2101 movs r1, #1 + 8004312: 438a bics r2, r1 + 8004314: 609a str r2, [r3, #8] + 8004316: 6b3b ldr r3, [r7, #48] @ 0x30 + 8004318: 623b str r3, [r7, #32] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 8003a26: 6a3b ldr r3, [r7, #32] - 8003a28: f383 8810 msr PRIMASK, r3 + 800431a: 6a3b ldr r3, [r7, #32] + 800431c: f383 8810 msr PRIMASK, r3 } - 8003a2c: 46c0 nop @ (mov r8, r8) + 8004320: 46c0 nop @ (mov r8, r8) huart->RxState = HAL_UART_STATE_READY; - 8003a2e: 687b ldr r3, [r7, #4] - 8003a30: 228c movs r2, #140 @ 0x8c - 8003a32: 2120 movs r1, #32 - 8003a34: 5099 str r1, [r3, r2] + 8004322: 687b ldr r3, [r7, #4] + 8004324: 228c movs r2, #140 @ 0x8c + 8004326: 2120 movs r1, #32 + 8004328: 5099 str r1, [r3, r2] __HAL_UNLOCK(huart); - 8003a36: 687b ldr r3, [r7, #4] - 8003a38: 2284 movs r2, #132 @ 0x84 - 8003a3a: 2100 movs r1, #0 - 8003a3c: 5499 strb r1, [r3, r2] + 800432a: 687b ldr r3, [r7, #4] + 800432c: 2284 movs r2, #132 @ 0x84 + 800432e: 2100 movs r1, #0 + 8004330: 5499 strb r1, [r3, r2] /* Timeout occurred */ return HAL_TIMEOUT; - 8003a3e: 2303 movs r3, #3 - 8003a40: e012 b.n 8003a68 + 8004332: 2303 movs r3, #3 + 8004334: e012 b.n 800435c } } /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; - 8003a42: 687b ldr r3, [r7, #4] - 8003a44: 2288 movs r2, #136 @ 0x88 - 8003a46: 2120 movs r1, #32 - 8003a48: 5099 str r1, [r3, r2] + 8004336: 687b ldr r3, [r7, #4] + 8004338: 2288 movs r2, #136 @ 0x88 + 800433a: 2120 movs r1, #32 + 800433c: 5099 str r1, [r3, r2] huart->RxState = HAL_UART_STATE_READY; - 8003a4a: 687b ldr r3, [r7, #4] - 8003a4c: 228c movs r2, #140 @ 0x8c - 8003a4e: 2120 movs r1, #32 - 8003a50: 5099 str r1, [r3, r2] + 800433e: 687b ldr r3, [r7, #4] + 8004340: 228c movs r2, #140 @ 0x8c + 8004342: 2120 movs r1, #32 + 8004344: 5099 str r1, [r3, r2] huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - 8003a52: 687b ldr r3, [r7, #4] - 8003a54: 2200 movs r2, #0 - 8003a56: 66da str r2, [r3, #108] @ 0x6c + 8004346: 687b ldr r3, [r7, #4] + 8004348: 2200 movs r2, #0 + 800434a: 66da str r2, [r3, #108] @ 0x6c huart->RxEventType = HAL_UART_RXEVENT_TC; - 8003a58: 687b ldr r3, [r7, #4] - 8003a5a: 2200 movs r2, #0 - 8003a5c: 671a str r2, [r3, #112] @ 0x70 + 800434c: 687b ldr r3, [r7, #4] + 800434e: 2200 movs r2, #0 + 8004350: 671a str r2, [r3, #112] @ 0x70 __HAL_UNLOCK(huart); - 8003a5e: 687b ldr r3, [r7, #4] - 8003a60: 2284 movs r2, #132 @ 0x84 - 8003a62: 2100 movs r1, #0 - 8003a64: 5499 strb r1, [r3, r2] + 8004352: 687b ldr r3, [r7, #4] + 8004354: 2284 movs r2, #132 @ 0x84 + 8004356: 2100 movs r1, #0 + 8004358: 5499 strb r1, [r3, r2] return HAL_OK; - 8003a66: 2300 movs r3, #0 + 800435a: 2300 movs r3, #0 } - 8003a68: 0018 movs r0, r3 - 8003a6a: 46bd mov sp, r7 - 8003a6c: b010 add sp, #64 @ 0x40 - 8003a6e: bd80 pop {r7, pc} - 8003a70: 01ffffff .word 0x01ffffff - 8003a74: fffffedf .word 0xfffffedf + 800435c: 0018 movs r0, r3 + 800435e: 46bd mov sp, r7 + 8004360: b010 add sp, #64 @ 0x40 + 8004362: bd80 pop {r7, pc} + 8004364: 01ffffff .word 0x01ffffff + 8004368: fffffedf .word 0xfffffedf -08003a78 : +0800436c : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { - 8003a78: b580 push {r7, lr} - 8003a7a: b084 sub sp, #16 - 8003a7c: af00 add r7, sp, #0 - 8003a7e: 60f8 str r0, [r7, #12] - 8003a80: 60b9 str r1, [r7, #8] - 8003a82: 603b str r3, [r7, #0] - 8003a84: 1dfb adds r3, r7, #7 - 8003a86: 701a strb r2, [r3, #0] + 800436c: b580 push {r7, lr} + 800436e: b084 sub sp, #16 + 8004370: af00 add r7, sp, #0 + 8004372: 60f8 str r0, [r7, #12] + 8004374: 60b9 str r1, [r7, #8] + 8004376: 603b str r3, [r7, #0] + 8004378: 1dfb adds r3, r7, #7 + 800437a: 701a strb r2, [r3, #0] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) - 8003a88: e051 b.n 8003b2e + 800437c: e051 b.n 8004422 { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) - 8003a8a: 69bb ldr r3, [r7, #24] - 8003a8c: 3301 adds r3, #1 - 8003a8e: d04e beq.n 8003b2e + 800437e: 69bb ldr r3, [r7, #24] + 8004380: 3301 adds r3, #1 + 8004382: d04e beq.n 8004422 { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) - 8003a90: f7fd faf0 bl 8001074 - 8003a94: 0002 movs r2, r0 - 8003a96: 683b ldr r3, [r7, #0] - 8003a98: 1ad3 subs r3, r2, r3 - 8003a9a: 69ba ldr r2, [r7, #24] - 8003a9c: 429a cmp r2, r3 - 8003a9e: d302 bcc.n 8003aa6 - 8003aa0: 69bb ldr r3, [r7, #24] - 8003aa2: 2b00 cmp r3, #0 - 8003aa4: d101 bne.n 8003aaa + 8004384: f7fd f9d6 bl 8001734 + 8004388: 0002 movs r2, r0 + 800438a: 683b ldr r3, [r7, #0] + 800438c: 1ad3 subs r3, r2, r3 + 800438e: 69ba ldr r2, [r7, #24] + 8004390: 429a cmp r2, r3 + 8004392: d302 bcc.n 800439a + 8004394: 69bb ldr r3, [r7, #24] + 8004396: 2b00 cmp r3, #0 + 8004398: d101 bne.n 800439e { return HAL_TIMEOUT; - 8003aa6: 2303 movs r3, #3 - 8003aa8: e051 b.n 8003b4e + 800439a: 2303 movs r3, #3 + 800439c: e051 b.n 8004442 } if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) - 8003aaa: 68fb ldr r3, [r7, #12] - 8003aac: 681b ldr r3, [r3, #0] - 8003aae: 681b ldr r3, [r3, #0] - 8003ab0: 2204 movs r2, #4 - 8003ab2: 4013 ands r3, r2 - 8003ab4: d03b beq.n 8003b2e - 8003ab6: 68bb ldr r3, [r7, #8] - 8003ab8: 2b80 cmp r3, #128 @ 0x80 - 8003aba: d038 beq.n 8003b2e - 8003abc: 68bb ldr r3, [r7, #8] - 8003abe: 2b40 cmp r3, #64 @ 0x40 - 8003ac0: d035 beq.n 8003b2e + 800439e: 68fb ldr r3, [r7, #12] + 80043a0: 681b ldr r3, [r3, #0] + 80043a2: 681b ldr r3, [r3, #0] + 80043a4: 2204 movs r2, #4 + 80043a6: 4013 ands r3, r2 + 80043a8: d03b beq.n 8004422 + 80043aa: 68bb ldr r3, [r7, #8] + 80043ac: 2b80 cmp r3, #128 @ 0x80 + 80043ae: d038 beq.n 8004422 + 80043b0: 68bb ldr r3, [r7, #8] + 80043b2: 2b40 cmp r3, #64 @ 0x40 + 80043b4: d035 beq.n 8004422 { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) - 8003ac2: 68fb ldr r3, [r7, #12] - 8003ac4: 681b ldr r3, [r3, #0] - 8003ac6: 69db ldr r3, [r3, #28] - 8003ac8: 2208 movs r2, #8 - 8003aca: 4013 ands r3, r2 - 8003acc: 2b08 cmp r3, #8 - 8003ace: d111 bne.n 8003af4 + 80043b6: 68fb ldr r3, [r7, #12] + 80043b8: 681b ldr r3, [r3, #0] + 80043ba: 69db ldr r3, [r3, #28] + 80043bc: 2208 movs r2, #8 + 80043be: 4013 ands r3, r2 + 80043c0: 2b08 cmp r3, #8 + 80043c2: d111 bne.n 80043e8 { /* Clear Overrun Error flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); - 8003ad0: 68fb ldr r3, [r7, #12] - 8003ad2: 681b ldr r3, [r3, #0] - 8003ad4: 2208 movs r2, #8 - 8003ad6: 621a str r2, [r3, #32] + 80043c4: 68fb ldr r3, [r7, #12] + 80043c6: 681b ldr r3, [r3, #0] + 80043c8: 2208 movs r2, #8 + 80043ca: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); - 8003ad8: 68fb ldr r3, [r7, #12] - 8003ada: 0018 movs r0, r3 - 8003adc: f000 f83c bl 8003b58 + 80043cc: 68fb ldr r3, [r7, #12] + 80043ce: 0018 movs r0, r3 + 80043d0: f000 f922 bl 8004618 huart->ErrorCode = HAL_UART_ERROR_ORE; - 8003ae0: 68fb ldr r3, [r7, #12] - 8003ae2: 2290 movs r2, #144 @ 0x90 - 8003ae4: 2108 movs r1, #8 - 8003ae6: 5099 str r1, [r3, r2] + 80043d4: 68fb ldr r3, [r7, #12] + 80043d6: 2290 movs r2, #144 @ 0x90 + 80043d8: 2108 movs r1, #8 + 80043da: 5099 str r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(huart); - 8003ae8: 68fb ldr r3, [r7, #12] - 8003aea: 2284 movs r2, #132 @ 0x84 - 8003aec: 2100 movs r1, #0 - 8003aee: 5499 strb r1, [r3, r2] + 80043dc: 68fb ldr r3, [r7, #12] + 80043de: 2284 movs r2, #132 @ 0x84 + 80043e0: 2100 movs r1, #0 + 80043e2: 5499 strb r1, [r3, r2] return HAL_ERROR; - 8003af0: 2301 movs r3, #1 - 8003af2: e02c b.n 8003b4e + 80043e4: 2301 movs r3, #1 + 80043e6: e02c b.n 8004442 } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) - 8003af4: 68fb ldr r3, [r7, #12] - 8003af6: 681b ldr r3, [r3, #0] - 8003af8: 69da ldr r2, [r3, #28] - 8003afa: 2380 movs r3, #128 @ 0x80 - 8003afc: 011b lsls r3, r3, #4 - 8003afe: 401a ands r2, r3 - 8003b00: 2380 movs r3, #128 @ 0x80 - 8003b02: 011b lsls r3, r3, #4 - 8003b04: 429a cmp r2, r3 - 8003b06: d112 bne.n 8003b2e + 80043e8: 68fb ldr r3, [r7, #12] + 80043ea: 681b ldr r3, [r3, #0] + 80043ec: 69da ldr r2, [r3, #28] + 80043ee: 2380 movs r3, #128 @ 0x80 + 80043f0: 011b lsls r3, r3, #4 + 80043f2: 401a ands r2, r3 + 80043f4: 2380 movs r3, #128 @ 0x80 + 80043f6: 011b lsls r3, r3, #4 + 80043f8: 429a cmp r2, r3 + 80043fa: d112 bne.n 8004422 { /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); - 8003b08: 68fb ldr r3, [r7, #12] - 8003b0a: 681b ldr r3, [r3, #0] - 8003b0c: 2280 movs r2, #128 @ 0x80 - 8003b0e: 0112 lsls r2, r2, #4 - 8003b10: 621a str r2, [r3, #32] + 80043fc: 68fb ldr r3, [r7, #12] + 80043fe: 681b ldr r3, [r3, #0] + 8004400: 2280 movs r2, #128 @ 0x80 + 8004402: 0112 lsls r2, r2, #4 + 8004404: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); - 8003b12: 68fb ldr r3, [r7, #12] - 8003b14: 0018 movs r0, r3 - 8003b16: f000 f81f bl 8003b58 + 8004406: 68fb ldr r3, [r7, #12] + 8004408: 0018 movs r0, r3 + 800440a: f000 f905 bl 8004618 huart->ErrorCode = HAL_UART_ERROR_RTO; - 8003b1a: 68fb ldr r3, [r7, #12] - 8003b1c: 2290 movs r2, #144 @ 0x90 - 8003b1e: 2120 movs r1, #32 - 8003b20: 5099 str r1, [r3, r2] + 800440e: 68fb ldr r3, [r7, #12] + 8004410: 2290 movs r2, #144 @ 0x90 + 8004412: 2120 movs r1, #32 + 8004414: 5099 str r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(huart); - 8003b22: 68fb ldr r3, [r7, #12] - 8003b24: 2284 movs r2, #132 @ 0x84 - 8003b26: 2100 movs r1, #0 - 8003b28: 5499 strb r1, [r3, r2] + 8004416: 68fb ldr r3, [r7, #12] + 8004418: 2284 movs r2, #132 @ 0x84 + 800441a: 2100 movs r1, #0 + 800441c: 5499 strb r1, [r3, r2] return HAL_TIMEOUT; - 8003b2a: 2303 movs r3, #3 - 8003b2c: e00f b.n 8003b4e + 800441e: 2303 movs r3, #3 + 8004420: e00f b.n 8004442 while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) - 8003b2e: 68fb ldr r3, [r7, #12] - 8003b30: 681b ldr r3, [r3, #0] - 8003b32: 69db ldr r3, [r3, #28] - 8003b34: 68ba ldr r2, [r7, #8] - 8003b36: 4013 ands r3, r2 - 8003b38: 68ba ldr r2, [r7, #8] - 8003b3a: 1ad3 subs r3, r2, r3 - 8003b3c: 425a negs r2, r3 - 8003b3e: 4153 adcs r3, r2 - 8003b40: b2db uxtb r3, r3 - 8003b42: 001a movs r2, r3 - 8003b44: 1dfb adds r3, r7, #7 - 8003b46: 781b ldrb r3, [r3, #0] - 8003b48: 429a cmp r2, r3 - 8003b4a: d09e beq.n 8003a8a + 8004422: 68fb ldr r3, [r7, #12] + 8004424: 681b ldr r3, [r3, #0] + 8004426: 69db ldr r3, [r3, #28] + 8004428: 68ba ldr r2, [r7, #8] + 800442a: 4013 ands r3, r2 + 800442c: 68ba ldr r2, [r7, #8] + 800442e: 1ad3 subs r3, r2, r3 + 8004430: 425a negs r2, r3 + 8004432: 4153 adcs r3, r2 + 8004434: b2db uxtb r3, r3 + 8004436: 001a movs r2, r3 + 8004438: 1dfb adds r3, r7, #7 + 800443a: 781b ldrb r3, [r3, #0] + 800443c: 429a cmp r2, r3 + 800443e: d09e beq.n 800437e } } } } return HAL_OK; - 8003b4c: 2300 movs r3, #0 + 8004440: 2300 movs r3, #0 } - 8003b4e: 0018 movs r0, r3 - 8003b50: 46bd mov sp, r7 - 8003b52: b004 add sp, #16 - 8003b54: bd80 pop {r7, pc} + 8004442: 0018 movs r0, r3 + 8004444: 46bd mov sp, r7 + 8004446: b004 add sp, #16 + 8004448: bd80 pop {r7, pc} ... -08003b58 : +0800444c : + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + 800444c: b580 push {r7, lr} + 800444e: b090 sub sp, #64 @ 0x40 + 8004450: af00 add r7, sp, #0 + 8004452: 60f8 str r0, [r7, #12] + 8004454: 60b9 str r1, [r7, #8] + 8004456: 1dbb adds r3, r7, #6 + 8004458: 801a strh r2, [r3, #0] + huart->pRxBuffPtr = pData; + 800445a: 68fb ldr r3, [r7, #12] + 800445c: 68ba ldr r2, [r7, #8] + 800445e: 659a str r2, [r3, #88] @ 0x58 + huart->RxXferSize = Size; + 8004460: 68fb ldr r3, [r7, #12] + 8004462: 1dba adds r2, r7, #6 + 8004464: 215c movs r1, #92 @ 0x5c + 8004466: 8812 ldrh r2, [r2, #0] + 8004468: 525a strh r2, [r3, r1] + + huart->ErrorCode = HAL_UART_ERROR_NONE; + 800446a: 68fb ldr r3, [r7, #12] + 800446c: 2290 movs r2, #144 @ 0x90 + 800446e: 2100 movs r1, #0 + 8004470: 5099 str r1, [r3, r2] + huart->RxState = HAL_UART_STATE_BUSY_RX; + 8004472: 68fb ldr r3, [r7, #12] + 8004474: 228c movs r2, #140 @ 0x8c + 8004476: 2122 movs r1, #34 @ 0x22 + 8004478: 5099 str r1, [r3, r2] + + if (huart->hdmarx != NULL) + 800447a: 68fb ldr r3, [r7, #12] + 800447c: 2280 movs r2, #128 @ 0x80 + 800447e: 589b ldr r3, [r3, r2] + 8004480: 2b00 cmp r3, #0 + 8004482: d02d beq.n 80044e0 + { + /* Set the UART DMA transfer complete callback */ + huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; + 8004484: 68fb ldr r3, [r7, #12] + 8004486: 2280 movs r2, #128 @ 0x80 + 8004488: 589b ldr r3, [r3, r2] + 800448a: 4a40 ldr r2, [pc, #256] @ (800458c ) + 800448c: 62da str r2, [r3, #44] @ 0x2c + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; + 800448e: 68fb ldr r3, [r7, #12] + 8004490: 2280 movs r2, #128 @ 0x80 + 8004492: 589b ldr r3, [r3, r2] + 8004494: 4a3e ldr r2, [pc, #248] @ (8004590 ) + 8004496: 631a str r2, [r3, #48] @ 0x30 + + /* Set the DMA error callback */ + huart->hdmarx->XferErrorCallback = UART_DMAError; + 8004498: 68fb ldr r3, [r7, #12] + 800449a: 2280 movs r2, #128 @ 0x80 + 800449c: 589b ldr r3, [r3, r2] + 800449e: 4a3d ldr r2, [pc, #244] @ (8004594 ) + 80044a0: 635a str r2, [r3, #52] @ 0x34 + + /* Set the DMA abort callback */ + huart->hdmarx->XferAbortCallback = NULL; + 80044a2: 68fb ldr r3, [r7, #12] + 80044a4: 2280 movs r2, #128 @ 0x80 + 80044a6: 589b ldr r3, [r3, r2] + 80044a8: 2200 movs r2, #0 + 80044aa: 639a str r2, [r3, #56] @ 0x38 + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK) + 80044ac: 68fb ldr r3, [r7, #12] + 80044ae: 2280 movs r2, #128 @ 0x80 + 80044b0: 5898 ldr r0, [r3, r2] + 80044b2: 68fb ldr r3, [r7, #12] + 80044b4: 681b ldr r3, [r3, #0] + 80044b6: 3324 adds r3, #36 @ 0x24 + 80044b8: 0019 movs r1, r3 + 80044ba: 68fb ldr r3, [r7, #12] + 80044bc: 6d9b ldr r3, [r3, #88] @ 0x58 + 80044be: 001a movs r2, r3 + 80044c0: 1dbb adds r3, r7, #6 + 80044c2: 881b ldrh r3, [r3, #0] + 80044c4: f7fd fac6 bl 8001a54 + 80044c8: 1e03 subs r3, r0, #0 + 80044ca: d009 beq.n 80044e0 + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + 80044cc: 68fb ldr r3, [r7, #12] + 80044ce: 2290 movs r2, #144 @ 0x90 + 80044d0: 2110 movs r1, #16 + 80044d2: 5099 str r1, [r3, r2] + + /* Restore huart->RxState to ready */ + huart->RxState = HAL_UART_STATE_READY; + 80044d4: 68fb ldr r3, [r7, #12] + 80044d6: 228c movs r2, #140 @ 0x8c + 80044d8: 2120 movs r1, #32 + 80044da: 5099 str r1, [r3, r2] + + return HAL_ERROR; + 80044dc: 2301 movs r3, #1 + 80044de: e050 b.n 8004582 + } + } + + /* Enable the UART Parity Error Interrupt */ + if (huart->Init.Parity != UART_PARITY_NONE) + 80044e0: 68fb ldr r3, [r7, #12] + 80044e2: 691b ldr r3, [r3, #16] + 80044e4: 2b00 cmp r3, #0 + 80044e6: d019 beq.n 800451c + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + 80044e8: f3ef 8310 mrs r3, PRIMASK + 80044ec: 62bb str r3, [r7, #40] @ 0x28 + return(result); + 80044ee: 6abb ldr r3, [r7, #40] @ 0x28 + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + 80044f0: 63fb str r3, [r7, #60] @ 0x3c + 80044f2: 2301 movs r3, #1 + 80044f4: 62fb str r3, [r7, #44] @ 0x2c + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 80044f6: 6afb ldr r3, [r7, #44] @ 0x2c + 80044f8: f383 8810 msr PRIMASK, r3 +} + 80044fc: 46c0 nop @ (mov r8, r8) + 80044fe: 68fb ldr r3, [r7, #12] + 8004500: 681b ldr r3, [r3, #0] + 8004502: 681a ldr r2, [r3, #0] + 8004504: 68fb ldr r3, [r7, #12] + 8004506: 681b ldr r3, [r3, #0] + 8004508: 2180 movs r1, #128 @ 0x80 + 800450a: 0049 lsls r1, r1, #1 + 800450c: 430a orrs r2, r1 + 800450e: 601a str r2, [r3, #0] + 8004510: 6bfb ldr r3, [r7, #60] @ 0x3c + 8004512: 633b str r3, [r7, #48] @ 0x30 + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8004514: 6b3b ldr r3, [r7, #48] @ 0x30 + 8004516: f383 8810 msr PRIMASK, r3 +} + 800451a: 46c0 nop @ (mov r8, r8) + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + 800451c: f3ef 8310 mrs r3, PRIMASK + 8004520: 613b str r3, [r7, #16] + return(result); + 8004522: 693b ldr r3, [r7, #16] + } + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + 8004524: 63bb str r3, [r7, #56] @ 0x38 + 8004526: 2301 movs r3, #1 + 8004528: 617b str r3, [r7, #20] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800452a: 697b ldr r3, [r7, #20] + 800452c: f383 8810 msr PRIMASK, r3 +} + 8004530: 46c0 nop @ (mov r8, r8) + 8004532: 68fb ldr r3, [r7, #12] + 8004534: 681b ldr r3, [r3, #0] + 8004536: 689a ldr r2, [r3, #8] + 8004538: 68fb ldr r3, [r7, #12] + 800453a: 681b ldr r3, [r3, #0] + 800453c: 2101 movs r1, #1 + 800453e: 430a orrs r2, r1 + 8004540: 609a str r2, [r3, #8] + 8004542: 6bbb ldr r3, [r7, #56] @ 0x38 + 8004544: 61bb str r3, [r7, #24] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8004546: 69bb ldr r3, [r7, #24] + 8004548: f383 8810 msr PRIMASK, r3 +} + 800454c: 46c0 nop @ (mov r8, r8) + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + 800454e: f3ef 8310 mrs r3, PRIMASK + 8004552: 61fb str r3, [r7, #28] + return(result); + 8004554: 69fb ldr r3, [r7, #28] + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the UART CR3 register */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + 8004556: 637b str r3, [r7, #52] @ 0x34 + 8004558: 2301 movs r3, #1 + 800455a: 623b str r3, [r7, #32] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800455c: 6a3b ldr r3, [r7, #32] + 800455e: f383 8810 msr PRIMASK, r3 +} + 8004562: 46c0 nop @ (mov r8, r8) + 8004564: 68fb ldr r3, [r7, #12] + 8004566: 681b ldr r3, [r3, #0] + 8004568: 689a ldr r2, [r3, #8] + 800456a: 68fb ldr r3, [r7, #12] + 800456c: 681b ldr r3, [r3, #0] + 800456e: 2140 movs r1, #64 @ 0x40 + 8004570: 430a orrs r2, r1 + 8004572: 609a str r2, [r3, #8] + 8004574: 6b7b ldr r3, [r7, #52] @ 0x34 + 8004576: 627b str r3, [r7, #36] @ 0x24 + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8004578: 6a7b ldr r3, [r7, #36] @ 0x24 + 800457a: f383 8810 msr PRIMASK, r3 +} + 800457e: 46c0 nop @ (mov r8, r8) + + return HAL_OK; + 8004580: 2300 movs r3, #0 +} + 8004582: 0018 movs r0, r3 + 8004584: 46bd mov sp, r7 + 8004586: b010 add sp, #64 @ 0x40 + 8004588: bd80 pop {r7, pc} + 800458a: 46c0 nop @ (mov r8, r8) + 800458c: 080046e5 .word 0x080046e5 + 8004590: 0800484d .word 0x0800484d + 8004594: 080048cb .word 0x080048cb + +08004598 : + * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndTxTransfer(UART_HandleTypeDef *huart) +{ + 8004598: b580 push {r7, lr} + 800459a: b08a sub sp, #40 @ 0x28 + 800459c: af00 add r7, sp, #0 + 800459e: 6078 str r0, [r7, #4] + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + 80045a0: f3ef 8310 mrs r3, PRIMASK + 80045a4: 60bb str r3, [r7, #8] + return(result); + 80045a6: 68bb ldr r3, [r7, #8] + /* Disable TXEIE, TCIE, TXFT interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + 80045a8: 627b str r3, [r7, #36] @ 0x24 + 80045aa: 2301 movs r3, #1 + 80045ac: 60fb str r3, [r7, #12] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 80045ae: 68fb ldr r3, [r7, #12] + 80045b0: f383 8810 msr PRIMASK, r3 +} + 80045b4: 46c0 nop @ (mov r8, r8) + 80045b6: 687b ldr r3, [r7, #4] + 80045b8: 681b ldr r3, [r3, #0] + 80045ba: 681a ldr r2, [r3, #0] + 80045bc: 687b ldr r3, [r7, #4] + 80045be: 681b ldr r3, [r3, #0] + 80045c0: 21c0 movs r1, #192 @ 0xc0 + 80045c2: 438a bics r2, r1 + 80045c4: 601a str r2, [r3, #0] + 80045c6: 6a7b ldr r3, [r7, #36] @ 0x24 + 80045c8: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 80045ca: 693b ldr r3, [r7, #16] + 80045cc: f383 8810 msr PRIMASK, r3 +} + 80045d0: 46c0 nop @ (mov r8, r8) + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + 80045d2: f3ef 8310 mrs r3, PRIMASK + 80045d6: 617b str r3, [r7, #20] + return(result); + 80045d8: 697b ldr r3, [r7, #20] + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE)); + 80045da: 623b str r3, [r7, #32] + 80045dc: 2301 movs r3, #1 + 80045de: 61bb str r3, [r7, #24] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 80045e0: 69bb ldr r3, [r7, #24] + 80045e2: f383 8810 msr PRIMASK, r3 +} + 80045e6: 46c0 nop @ (mov r8, r8) + 80045e8: 687b ldr r3, [r7, #4] + 80045ea: 681b ldr r3, [r3, #0] + 80045ec: 689a ldr r2, [r3, #8] + 80045ee: 687b ldr r3, [r7, #4] + 80045f0: 681b ldr r3, [r3, #0] + 80045f2: 4908 ldr r1, [pc, #32] @ (8004614 ) + 80045f4: 400a ands r2, r1 + 80045f6: 609a str r2, [r3, #8] + 80045f8: 6a3b ldr r3, [r7, #32] + 80045fa: 61fb str r3, [r7, #28] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 80045fc: 69fb ldr r3, [r7, #28] + 80045fe: f383 8810 msr PRIMASK, r3 +} + 8004602: 46c0 nop @ (mov r8, r8) + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + 8004604: 687b ldr r3, [r7, #4] + 8004606: 2288 movs r2, #136 @ 0x88 + 8004608: 2120 movs r1, #32 + 800460a: 5099 str r1, [r3, r2] +} + 800460c: 46c0 nop @ (mov r8, r8) + 800460e: 46bd mov sp, r7 + 8004610: b00a add sp, #40 @ 0x28 + 8004612: bd80 pop {r7, pc} + 8004614: ff7fffff .word 0xff7fffff + +08004618 : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { - 8003b58: b580 push {r7, lr} - 8003b5a: b08e sub sp, #56 @ 0x38 - 8003b5c: af00 add r7, sp, #0 - 8003b5e: 6078 str r0, [r7, #4] + 8004618: b580 push {r7, lr} + 800461a: b08e sub sp, #56 @ 0x38 + 800461c: af00 add r7, sp, #0 + 800461e: 6078 str r0, [r7, #4] __ASM volatile ("MRS %0, primask" : "=r" (result) ); - 8003b60: f3ef 8310 mrs r3, PRIMASK - 8003b64: 617b str r3, [r7, #20] + 8004620: f3ef 8310 mrs r3, PRIMASK + 8004624: 617b str r3, [r7, #20] return(result); - 8003b66: 697b ldr r3, [r7, #20] + 8004626: 697b ldr r3, [r7, #20] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); - 8003b68: 637b str r3, [r7, #52] @ 0x34 - 8003b6a: 2301 movs r3, #1 - 8003b6c: 61bb str r3, [r7, #24] + 8004628: 637b str r3, [r7, #52] @ 0x34 + 800462a: 2301 movs r3, #1 + 800462c: 61bb str r3, [r7, #24] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 8003b6e: 69bb ldr r3, [r7, #24] - 8003b70: f383 8810 msr PRIMASK, r3 + 800462e: 69bb ldr r3, [r7, #24] + 8004630: f383 8810 msr PRIMASK, r3 } - 8003b74: 46c0 nop @ (mov r8, r8) - 8003b76: 687b ldr r3, [r7, #4] - 8003b78: 681b ldr r3, [r3, #0] - 8003b7a: 681a ldr r2, [r3, #0] - 8003b7c: 687b ldr r3, [r7, #4] - 8003b7e: 681b ldr r3, [r3, #0] - 8003b80: 4926 ldr r1, [pc, #152] @ (8003c1c ) - 8003b82: 400a ands r2, r1 - 8003b84: 601a str r2, [r3, #0] - 8003b86: 6b7b ldr r3, [r7, #52] @ 0x34 - 8003b88: 61fb str r3, [r7, #28] + 8004634: 46c0 nop @ (mov r8, r8) + 8004636: 687b ldr r3, [r7, #4] + 8004638: 681b ldr r3, [r3, #0] + 800463a: 681a ldr r2, [r3, #0] + 800463c: 687b ldr r3, [r7, #4] + 800463e: 681b ldr r3, [r3, #0] + 8004640: 4926 ldr r1, [pc, #152] @ (80046dc ) + 8004642: 400a ands r2, r1 + 8004644: 601a str r2, [r3, #0] + 8004646: 6b7b ldr r3, [r7, #52] @ 0x34 + 8004648: 61fb str r3, [r7, #28] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 8003b8a: 69fb ldr r3, [r7, #28] - 8003b8c: f383 8810 msr PRIMASK, r3 + 800464a: 69fb ldr r3, [r7, #28] + 800464c: f383 8810 msr PRIMASK, r3 } - 8003b90: 46c0 nop @ (mov r8, r8) + 8004650: 46c0 nop @ (mov r8, r8) __ASM volatile ("MRS %0, primask" : "=r" (result) ); - 8003b92: f3ef 8310 mrs r3, PRIMASK - 8003b96: 623b str r3, [r7, #32] + 8004652: f3ef 8310 mrs r3, PRIMASK + 8004656: 623b str r3, [r7, #32] return(result); - 8003b98: 6a3b ldr r3, [r7, #32] + 8004658: 6a3b ldr r3, [r7, #32] ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); - 8003b9a: 633b str r3, [r7, #48] @ 0x30 - 8003b9c: 2301 movs r3, #1 - 8003b9e: 627b str r3, [r7, #36] @ 0x24 + 800465a: 633b str r3, [r7, #48] @ 0x30 + 800465c: 2301 movs r3, #1 + 800465e: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 8003ba0: 6a7b ldr r3, [r7, #36] @ 0x24 - 8003ba2: f383 8810 msr PRIMASK, r3 + 8004660: 6a7b ldr r3, [r7, #36] @ 0x24 + 8004662: f383 8810 msr PRIMASK, r3 } - 8003ba6: 46c0 nop @ (mov r8, r8) - 8003ba8: 687b ldr r3, [r7, #4] - 8003baa: 681b ldr r3, [r3, #0] - 8003bac: 689a ldr r2, [r3, #8] - 8003bae: 687b ldr r3, [r7, #4] - 8003bb0: 681b ldr r3, [r3, #0] - 8003bb2: 491b ldr r1, [pc, #108] @ (8003c20 ) - 8003bb4: 400a ands r2, r1 - 8003bb6: 609a str r2, [r3, #8] - 8003bb8: 6b3b ldr r3, [r7, #48] @ 0x30 - 8003bba: 62bb str r3, [r7, #40] @ 0x28 + 8004666: 46c0 nop @ (mov r8, r8) + 8004668: 687b ldr r3, [r7, #4] + 800466a: 681b ldr r3, [r3, #0] + 800466c: 689a ldr r2, [r3, #8] + 800466e: 687b ldr r3, [r7, #4] + 8004670: 681b ldr r3, [r3, #0] + 8004672: 491b ldr r1, [pc, #108] @ (80046e0 ) + 8004674: 400a ands r2, r1 + 8004676: 609a str r2, [r3, #8] + 8004678: 6b3b ldr r3, [r7, #48] @ 0x30 + 800467a: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 8003bbc: 6abb ldr r3, [r7, #40] @ 0x28 - 8003bbe: f383 8810 msr PRIMASK, r3 + 800467c: 6abb ldr r3, [r7, #40] @ 0x28 + 800467e: f383 8810 msr PRIMASK, r3 } - 8003bc2: 46c0 nop @ (mov r8, r8) + 8004682: 46c0 nop @ (mov r8, r8) /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - 8003bc4: 687b ldr r3, [r7, #4] - 8003bc6: 6edb ldr r3, [r3, #108] @ 0x6c - 8003bc8: 2b01 cmp r3, #1 - 8003bca: d118 bne.n 8003bfe + 8004684: 687b ldr r3, [r7, #4] + 8004686: 6edb ldr r3, [r3, #108] @ 0x6c + 8004688: 2b01 cmp r3, #1 + 800468a: d118 bne.n 80046be __ASM volatile ("MRS %0, primask" : "=r" (result) ); - 8003bcc: f3ef 8310 mrs r3, PRIMASK - 8003bd0: 60bb str r3, [r7, #8] + 800468c: f3ef 8310 mrs r3, PRIMASK + 8004690: 60bb str r3, [r7, #8] return(result); - 8003bd2: 68bb ldr r3, [r7, #8] + 8004692: 68bb ldr r3, [r7, #8] { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - 8003bd4: 62fb str r3, [r7, #44] @ 0x2c - 8003bd6: 2301 movs r3, #1 - 8003bd8: 60fb str r3, [r7, #12] + 8004694: 62fb str r3, [r7, #44] @ 0x2c + 8004696: 2301 movs r3, #1 + 8004698: 60fb str r3, [r7, #12] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 8003bda: 68fb ldr r3, [r7, #12] - 8003bdc: f383 8810 msr PRIMASK, r3 + 800469a: 68fb ldr r3, [r7, #12] + 800469c: f383 8810 msr PRIMASK, r3 } - 8003be0: 46c0 nop @ (mov r8, r8) - 8003be2: 687b ldr r3, [r7, #4] - 8003be4: 681b ldr r3, [r3, #0] - 8003be6: 681a ldr r2, [r3, #0] - 8003be8: 687b ldr r3, [r7, #4] - 8003bea: 681b ldr r3, [r3, #0] - 8003bec: 2110 movs r1, #16 - 8003bee: 438a bics r2, r1 - 8003bf0: 601a str r2, [r3, #0] - 8003bf2: 6afb ldr r3, [r7, #44] @ 0x2c - 8003bf4: 613b str r3, [r7, #16] + 80046a0: 46c0 nop @ (mov r8, r8) + 80046a2: 687b ldr r3, [r7, #4] + 80046a4: 681b ldr r3, [r3, #0] + 80046a6: 681a ldr r2, [r3, #0] + 80046a8: 687b ldr r3, [r7, #4] + 80046aa: 681b ldr r3, [r3, #0] + 80046ac: 2110 movs r1, #16 + 80046ae: 438a bics r2, r1 + 80046b0: 601a str r2, [r3, #0] + 80046b2: 6afb ldr r3, [r7, #44] @ 0x2c + 80046b4: 613b str r3, [r7, #16] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); - 8003bf6: 693b ldr r3, [r7, #16] - 8003bf8: f383 8810 msr PRIMASK, r3 + 80046b6: 693b ldr r3, [r7, #16] + 80046b8: f383 8810 msr PRIMASK, r3 } - 8003bfc: 46c0 nop @ (mov r8, r8) + 80046bc: 46c0 nop @ (mov r8, r8) } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - 8003bfe: 687b ldr r3, [r7, #4] - 8003c00: 228c movs r2, #140 @ 0x8c - 8003c02: 2120 movs r1, #32 - 8003c04: 5099 str r1, [r3, r2] + 80046be: 687b ldr r3, [r7, #4] + 80046c0: 228c movs r2, #140 @ 0x8c + 80046c2: 2120 movs r1, #32 + 80046c4: 5099 str r1, [r3, r2] huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - 8003c06: 687b ldr r3, [r7, #4] - 8003c08: 2200 movs r2, #0 - 8003c0a: 66da str r2, [r3, #108] @ 0x6c + 80046c6: 687b ldr r3, [r7, #4] + 80046c8: 2200 movs r2, #0 + 80046ca: 66da str r2, [r3, #108] @ 0x6c /* Reset RxIsr function pointer */ huart->RxISR = NULL; - 8003c0c: 687b ldr r3, [r7, #4] - 8003c0e: 2200 movs r2, #0 - 8003c10: 675a str r2, [r3, #116] @ 0x74 + 80046cc: 687b ldr r3, [r7, #4] + 80046ce: 2200 movs r2, #0 + 80046d0: 675a str r2, [r3, #116] @ 0x74 } - 8003c12: 46c0 nop @ (mov r8, r8) - 8003c14: 46bd mov sp, r7 - 8003c16: b00e add sp, #56 @ 0x38 - 8003c18: bd80 pop {r7, pc} - 8003c1a: 46c0 nop @ (mov r8, r8) - 8003c1c: fffffedf .word 0xfffffedf - 8003c20: effffffe .word 0xeffffffe + 80046d2: 46c0 nop @ (mov r8, r8) + 80046d4: 46bd mov sp, r7 + 80046d6: b00e add sp, #56 @ 0x38 + 80046d8: bd80 pop {r7, pc} + 80046da: 46c0 nop @ (mov r8, r8) + 80046dc: fffffedf .word 0xfffffedf + 80046e0: effffffe .word 0xeffffffe -08003c24 : +080046e4 : + * @brief DMA UART receive process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + 80046e4: b580 push {r7, lr} + 80046e6: b094 sub sp, #80 @ 0x50 + 80046e8: af00 add r7, sp, #0 + 80046ea: 6078 str r0, [r7, #4] + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 80046ec: 687b ldr r3, [r7, #4] + 80046ee: 6a9b ldr r3, [r3, #40] @ 0x28 + 80046f0: 64fb str r3, [r7, #76] @ 0x4c + + /* DMA Normal mode */ + if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) + 80046f2: 687b ldr r3, [r7, #4] + 80046f4: 681b ldr r3, [r3, #0] + 80046f6: 681b ldr r3, [r3, #0] + 80046f8: 2220 movs r2, #32 + 80046fa: 4013 ands r3, r2 + 80046fc: d16f bne.n 80047de + { + huart->RxXferCount = 0U; + 80046fe: 6cfb ldr r3, [r7, #76] @ 0x4c + 8004700: 225e movs r2, #94 @ 0x5e + 8004702: 2100 movs r1, #0 + 8004704: 5299 strh r1, [r3, r2] + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + 8004706: f3ef 8310 mrs r3, PRIMASK + 800470a: 617b str r3, [r7, #20] + return(result); + 800470c: 697b ldr r3, [r7, #20] + + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + 800470e: 64bb str r3, [r7, #72] @ 0x48 + 8004710: 2301 movs r3, #1 + 8004712: 61bb str r3, [r7, #24] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8004714: 69bb ldr r3, [r7, #24] + 8004716: f383 8810 msr PRIMASK, r3 +} + 800471a: 46c0 nop @ (mov r8, r8) + 800471c: 6cfb ldr r3, [r7, #76] @ 0x4c + 800471e: 681b ldr r3, [r3, #0] + 8004720: 681a ldr r2, [r3, #0] + 8004722: 6cfb ldr r3, [r7, #76] @ 0x4c + 8004724: 681b ldr r3, [r3, #0] + 8004726: 4948 ldr r1, [pc, #288] @ (8004848 ) + 8004728: 400a ands r2, r1 + 800472a: 601a str r2, [r3, #0] + 800472c: 6cbb ldr r3, [r7, #72] @ 0x48 + 800472e: 61fb str r3, [r7, #28] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8004730: 69fb ldr r3, [r7, #28] + 8004732: f383 8810 msr PRIMASK, r3 +} + 8004736: 46c0 nop @ (mov r8, r8) + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + 8004738: f3ef 8310 mrs r3, PRIMASK + 800473c: 623b str r3, [r7, #32] + return(result); + 800473e: 6a3b ldr r3, [r7, #32] + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 8004740: 647b str r3, [r7, #68] @ 0x44 + 8004742: 2301 movs r3, #1 + 8004744: 627b str r3, [r7, #36] @ 0x24 + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8004746: 6a7b ldr r3, [r7, #36] @ 0x24 + 8004748: f383 8810 msr PRIMASK, r3 +} + 800474c: 46c0 nop @ (mov r8, r8) + 800474e: 6cfb ldr r3, [r7, #76] @ 0x4c + 8004750: 681b ldr r3, [r3, #0] + 8004752: 689a ldr r2, [r3, #8] + 8004754: 6cfb ldr r3, [r7, #76] @ 0x4c + 8004756: 681b ldr r3, [r3, #0] + 8004758: 2101 movs r1, #1 + 800475a: 438a bics r2, r1 + 800475c: 609a str r2, [r3, #8] + 800475e: 6c7b ldr r3, [r7, #68] @ 0x44 + 8004760: 62bb str r3, [r7, #40] @ 0x28 + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8004762: 6abb ldr r3, [r7, #40] @ 0x28 + 8004764: f383 8810 msr PRIMASK, r3 +} + 8004768: 46c0 nop @ (mov r8, r8) + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + 800476a: f3ef 8310 mrs r3, PRIMASK + 800476e: 62fb str r3, [r7, #44] @ 0x2c + return(result); + 8004770: 6afb ldr r3, [r7, #44] @ 0x2c + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + 8004772: 643b str r3, [r7, #64] @ 0x40 + 8004774: 2301 movs r3, #1 + 8004776: 633b str r3, [r7, #48] @ 0x30 + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8004778: 6b3b ldr r3, [r7, #48] @ 0x30 + 800477a: f383 8810 msr PRIMASK, r3 +} + 800477e: 46c0 nop @ (mov r8, r8) + 8004780: 6cfb ldr r3, [r7, #76] @ 0x4c + 8004782: 681b ldr r3, [r3, #0] + 8004784: 689a ldr r2, [r3, #8] + 8004786: 6cfb ldr r3, [r7, #76] @ 0x4c + 8004788: 681b ldr r3, [r3, #0] + 800478a: 2140 movs r1, #64 @ 0x40 + 800478c: 438a bics r2, r1 + 800478e: 609a str r2, [r3, #8] + 8004790: 6c3b ldr r3, [r7, #64] @ 0x40 + 8004792: 637b str r3, [r7, #52] @ 0x34 + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8004794: 6b7b ldr r3, [r7, #52] @ 0x34 + 8004796: f383 8810 msr PRIMASK, r3 +} + 800479a: 46c0 nop @ (mov r8, r8) + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 800479c: 6cfb ldr r3, [r7, #76] @ 0x4c + 800479e: 228c movs r2, #140 @ 0x8c + 80047a0: 2120 movs r1, #32 + 80047a2: 5099 str r1, [r3, r2] + + /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + 80047a4: 6cfb ldr r3, [r7, #76] @ 0x4c + 80047a6: 6edb ldr r3, [r3, #108] @ 0x6c + 80047a8: 2b01 cmp r3, #1 + 80047aa: d118 bne.n 80047de + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + 80047ac: f3ef 8310 mrs r3, PRIMASK + 80047b0: 60bb str r3, [r7, #8] + return(result); + 80047b2: 68bb ldr r3, [r7, #8] + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + 80047b4: 63fb str r3, [r7, #60] @ 0x3c + 80047b6: 2301 movs r3, #1 + 80047b8: 60fb str r3, [r7, #12] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 80047ba: 68fb ldr r3, [r7, #12] + 80047bc: f383 8810 msr PRIMASK, r3 +} + 80047c0: 46c0 nop @ (mov r8, r8) + 80047c2: 6cfb ldr r3, [r7, #76] @ 0x4c + 80047c4: 681b ldr r3, [r3, #0] + 80047c6: 681a ldr r2, [r3, #0] + 80047c8: 6cfb ldr r3, [r7, #76] @ 0x4c + 80047ca: 681b ldr r3, [r3, #0] + 80047cc: 2110 movs r1, #16 + 80047ce: 438a bics r2, r1 + 80047d0: 601a str r2, [r3, #0] + 80047d2: 6bfb ldr r3, [r7, #60] @ 0x3c + 80047d4: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 80047d6: 693b ldr r3, [r7, #16] + 80047d8: f383 8810 msr PRIMASK, r3 +} + 80047dc: 46c0 nop @ (mov r8, r8) + } + } + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + 80047de: 6cfb ldr r3, [r7, #76] @ 0x4c + 80047e0: 2200 movs r2, #0 + 80047e2: 671a str r2, [r3, #112] @ 0x70 + + /* Check current reception Mode : + If Reception till IDLE event has been selected : use Rx Event callback */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + 80047e4: 6cfb ldr r3, [r7, #76] @ 0x4c + 80047e6: 6edb ldr r3, [r3, #108] @ 0x6c + 80047e8: 2b01 cmp r3, #1 + 80047ea: d124 bne.n 8004836 + { + huart->RxXferCount = 0; + 80047ec: 6cfb ldr r3, [r7, #76] @ 0x4c + 80047ee: 225e movs r2, #94 @ 0x5e + 80047f0: 2100 movs r1, #0 + 80047f2: 5299 strh r1, [r3, r2] + + /* Check current nb of data still to be received on DMA side. + DMA Normal mode, remaining nb of data will be 0 + DMA Circular mode, remaining nb of data is reset to RxXferSize */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma); + 80047f4: 687b ldr r3, [r7, #4] + 80047f6: 681b ldr r3, [r3, #0] + 80047f8: 685a ldr r2, [r3, #4] + 80047fa: 213a movs r1, #58 @ 0x3a + 80047fc: 187b adds r3, r7, r1 + 80047fe: 801a strh r2, [r3, #0] + if (nb_remaining_rx_data < huart->RxXferSize) + 8004800: 6cfb ldr r3, [r7, #76] @ 0x4c + 8004802: 225c movs r2, #92 @ 0x5c + 8004804: 5a9b ldrh r3, [r3, r2] + 8004806: 187a adds r2, r7, r1 + 8004808: 8812 ldrh r2, [r2, #0] + 800480a: 429a cmp r2, r3 + 800480c: d204 bcs.n 8004818 + { + /* Update nb of remaining data */ + huart->RxXferCount = nb_remaining_rx_data; + 800480e: 6cfb ldr r3, [r7, #76] @ 0x4c + 8004810: 187a adds r2, r7, r1 + 8004812: 215e movs r1, #94 @ 0x5e + 8004814: 8812 ldrh r2, [r2, #0] + 8004816: 525a strh r2, [r3, r1] +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); + 8004818: 6cfb ldr r3, [r7, #76] @ 0x4c + 800481a: 225c movs r2, #92 @ 0x5c + 800481c: 5a9a ldrh r2, [r3, r2] + 800481e: 6cfb ldr r3, [r7, #76] @ 0x4c + 8004820: 215e movs r1, #94 @ 0x5e + 8004822: 5a5b ldrh r3, [r3, r1] + 8004824: b29b uxth r3, r3 + 8004826: 1ad3 subs r3, r2, r3 + 8004828: b29a uxth r2, r3 + 800482a: 6cfb ldr r3, [r7, #76] @ 0x4c + 800482c: 0011 movs r1, r2 + 800482e: 0018 movs r0, r3 + 8004830: f7fc fbf8 bl 8001024 +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + 8004834: e003 b.n 800483e + HAL_UART_RxCpltCallback(huart); + 8004836: 6cfb ldr r3, [r7, #76] @ 0x4c + 8004838: 0018 movs r0, r3 + 800483a: f7ff faa3 bl 8003d84 +} + 800483e: 46c0 nop @ (mov r8, r8) + 8004840: 46bd mov sp, r7 + 8004842: b014 add sp, #80 @ 0x50 + 8004844: bd80 pop {r7, pc} + 8004846: 46c0 nop @ (mov r8, r8) + 8004848: fffffeff .word 0xfffffeff + +0800484c : + * @brief DMA UART receive process half complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +{ + 800484c: b580 push {r7, lr} + 800484e: b084 sub sp, #16 + 8004850: af00 add r7, sp, #0 + 8004852: 6078 str r0, [r7, #4] + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 8004854: 687b ldr r3, [r7, #4] + 8004856: 6a9b ldr r3, [r3, #40] @ 0x28 + 8004858: 60fb str r3, [r7, #12] + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Half Transfer */ + huart->RxEventType = HAL_UART_RXEVENT_HT; + 800485a: 68fb ldr r3, [r7, #12] + 800485c: 2201 movs r2, #1 + 800485e: 671a str r2, [r3, #112] @ 0x70 + + /* Check current reception Mode : + If Reception till IDLE event has been selected : use Rx Event callback */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + 8004860: 68fb ldr r3, [r7, #12] + 8004862: 6edb ldr r3, [r3, #108] @ 0x6c + 8004864: 2b01 cmp r3, #1 + 8004866: d128 bne.n 80048ba + { + huart->RxXferCount = huart->RxXferSize / 2U; + 8004868: 68fb ldr r3, [r7, #12] + 800486a: 225c movs r2, #92 @ 0x5c + 800486c: 5a9b ldrh r3, [r3, r2] + 800486e: 085b lsrs r3, r3, #1 + 8004870: b299 uxth r1, r3 + 8004872: 68fb ldr r3, [r7, #12] + 8004874: 225e movs r2, #94 @ 0x5e + 8004876: 5299 strh r1, [r3, r2] + + /* Check current nb of data still to be received on DMA side. */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma); + 8004878: 687b ldr r3, [r7, #4] + 800487a: 681b ldr r3, [r3, #0] + 800487c: 685a ldr r2, [r3, #4] + 800487e: 210a movs r1, #10 + 8004880: 187b adds r3, r7, r1 + 8004882: 801a strh r2, [r3, #0] + if (nb_remaining_rx_data <= huart->RxXferSize) + 8004884: 68fb ldr r3, [r7, #12] + 8004886: 225c movs r2, #92 @ 0x5c + 8004888: 5a9b ldrh r3, [r3, r2] + 800488a: 187a adds r2, r7, r1 + 800488c: 8812 ldrh r2, [r2, #0] + 800488e: 429a cmp r2, r3 + 8004890: d804 bhi.n 800489c + { + /* Update nb of remaining data */ + huart->RxXferCount = nb_remaining_rx_data; + 8004892: 68fb ldr r3, [r7, #12] + 8004894: 187a adds r2, r7, r1 + 8004896: 215e movs r1, #94 @ 0x5e + 8004898: 8812 ldrh r2, [r2, #0] + 800489a: 525a strh r2, [r3, r1] +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); + 800489c: 68fb ldr r3, [r7, #12] + 800489e: 225c movs r2, #92 @ 0x5c + 80048a0: 5a9a ldrh r2, [r3, r2] + 80048a2: 68fb ldr r3, [r7, #12] + 80048a4: 215e movs r1, #94 @ 0x5e + 80048a6: 5a5b ldrh r3, [r3, r1] + 80048a8: b29b uxth r3, r3 + 80048aa: 1ad3 subs r3, r2, r3 + 80048ac: b29a uxth r2, r3 + 80048ae: 68fb ldr r3, [r7, #12] + 80048b0: 0011 movs r1, r2 + 80048b2: 0018 movs r0, r3 + 80048b4: f7fc fbb6 bl 8001024 +#else + /*Call legacy weak Rx Half complete callback*/ + HAL_UART_RxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + 80048b8: e003 b.n 80048c2 + HAL_UART_RxHalfCpltCallback(huart); + 80048ba: 68fb ldr r3, [r7, #12] + 80048bc: 0018 movs r0, r3 + 80048be: f7ff fa69 bl 8003d94 +} + 80048c2: 46c0 nop @ (mov r8, r8) + 80048c4: 46bd mov sp, r7 + 80048c6: b004 add sp, #16 + 80048c8: bd80 pop {r7, pc} + +080048ca : + * @brief DMA UART communication error callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAError(DMA_HandleTypeDef *hdma) +{ + 80048ca: b580 push {r7, lr} + 80048cc: b086 sub sp, #24 + 80048ce: af00 add r7, sp, #0 + 80048d0: 6078 str r0, [r7, #4] + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 80048d2: 687b ldr r3, [r7, #4] + 80048d4: 6a9b ldr r3, [r3, #40] @ 0x28 + 80048d6: 617b str r3, [r7, #20] + + const HAL_UART_StateTypeDef gstate = huart->gState; + 80048d8: 697b ldr r3, [r7, #20] + 80048da: 2288 movs r2, #136 @ 0x88 + 80048dc: 589b ldr r3, [r3, r2] + 80048de: 613b str r3, [r7, #16] + const HAL_UART_StateTypeDef rxstate = huart->RxState; + 80048e0: 697b ldr r3, [r7, #20] + 80048e2: 228c movs r2, #140 @ 0x8c + 80048e4: 589b ldr r3, [r3, r2] + 80048e6: 60fb str r3, [r7, #12] + + /* Stop UART DMA Tx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + 80048e8: 697b ldr r3, [r7, #20] + 80048ea: 681b ldr r3, [r3, #0] + 80048ec: 689b ldr r3, [r3, #8] + 80048ee: 2280 movs r2, #128 @ 0x80 + 80048f0: 4013 ands r3, r2 + 80048f2: 2b80 cmp r3, #128 @ 0x80 + 80048f4: d10a bne.n 800490c + 80048f6: 693b ldr r3, [r7, #16] + 80048f8: 2b21 cmp r3, #33 @ 0x21 + 80048fa: d107 bne.n 800490c + (gstate == HAL_UART_STATE_BUSY_TX)) + { + huart->TxXferCount = 0U; + 80048fc: 697b ldr r3, [r7, #20] + 80048fe: 2256 movs r2, #86 @ 0x56 + 8004900: 2100 movs r1, #0 + 8004902: 5299 strh r1, [r3, r2] + UART_EndTxTransfer(huart); + 8004904: 697b ldr r3, [r7, #20] + 8004906: 0018 movs r0, r3 + 8004908: f7ff fe46 bl 8004598 + } + + /* Stop UART DMA Rx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + 800490c: 697b ldr r3, [r7, #20] + 800490e: 681b ldr r3, [r3, #0] + 8004910: 689b ldr r3, [r3, #8] + 8004912: 2240 movs r2, #64 @ 0x40 + 8004914: 4013 ands r3, r2 + 8004916: 2b40 cmp r3, #64 @ 0x40 + 8004918: d10a bne.n 8004930 + 800491a: 68fb ldr r3, [r7, #12] + 800491c: 2b22 cmp r3, #34 @ 0x22 + 800491e: d107 bne.n 8004930 + (rxstate == HAL_UART_STATE_BUSY_RX)) + { + huart->RxXferCount = 0U; + 8004920: 697b ldr r3, [r7, #20] + 8004922: 225e movs r2, #94 @ 0x5e + 8004924: 2100 movs r1, #0 + 8004926: 5299 strh r1, [r3, r2] + UART_EndRxTransfer(huart); + 8004928: 697b ldr r3, [r7, #20] + 800492a: 0018 movs r0, r3 + 800492c: f7ff fe74 bl 8004618 + } + + huart->ErrorCode |= HAL_UART_ERROR_DMA; + 8004930: 697b ldr r3, [r7, #20] + 8004932: 2290 movs r2, #144 @ 0x90 + 8004934: 589b ldr r3, [r3, r2] + 8004936: 2210 movs r2, #16 + 8004938: 431a orrs r2, r3 + 800493a: 697b ldr r3, [r7, #20] + 800493c: 2190 movs r1, #144 @ 0x90 + 800493e: 505a str r2, [r3, r1] +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 8004940: 697b ldr r3, [r7, #20] + 8004942: 0018 movs r0, r3 + 8004944: f7ff fa2e bl 8003da4 +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + 8004948: 46c0 nop @ (mov r8, r8) + 800494a: 46bd mov sp, r7 + 800494c: b006 add sp, #24 + 800494e: bd80 pop {r7, pc} + +08004950 : * oversampling rate). * @retval HAL status */ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime) { - 8003c24: b580 push {r7, lr} - 8003c26: b086 sub sp, #24 - 8003c28: af00 add r7, sp, #0 - 8003c2a: 60f8 str r0, [r7, #12] - 8003c2c: 60b9 str r1, [r7, #8] - 8003c2e: 607a str r2, [r7, #4] - 8003c30: 603b str r3, [r7, #0] + 8004950: b580 push {r7, lr} + 8004952: b086 sub sp, #24 + 8004954: af00 add r7, sp, #0 + 8004956: 60f8 str r0, [r7, #12] + 8004958: 60b9 str r1, [r7, #8] + 800495a: 607a str r2, [r7, #4] + 800495c: 603b str r3, [r7, #0] uint32_t temp; /* Check the UART handle allocation */ if (huart == NULL) - 8003c32: 68fb ldr r3, [r7, #12] - 8003c34: 2b00 cmp r3, #0 - 8003c36: d101 bne.n 8003c3c + 800495e: 68fb ldr r3, [r7, #12] + 8004960: 2b00 cmp r3, #0 + 8004962: d101 bne.n 8004968 { return HAL_ERROR; - 8003c38: 2301 movs r3, #1 - 8003c3a: e05d b.n 8003cf8 + 8004964: 2301 movs r3, #1 + 8004966: e05d b.n 8004a24 assert_param(IS_UART_ASSERTIONTIME(AssertionTime)); /* Check the Driver Enable deassertion time */ assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime)); if (huart->gState == HAL_UART_STATE_RESET) - 8003c3c: 68fb ldr r3, [r7, #12] - 8003c3e: 2288 movs r2, #136 @ 0x88 - 8003c40: 589b ldr r3, [r3, r2] - 8003c42: 2b00 cmp r3, #0 - 8003c44: d107 bne.n 8003c56 + 8004968: 68fb ldr r3, [r7, #12] + 800496a: 2288 movs r2, #136 @ 0x88 + 800496c: 589b ldr r3, [r3, r2] + 800496e: 2b00 cmp r3, #0 + 8004970: d107 bne.n 8004982 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; - 8003c46: 68fb ldr r3, [r7, #12] - 8003c48: 2284 movs r2, #132 @ 0x84 - 8003c4a: 2100 movs r1, #0 - 8003c4c: 5499 strb r1, [r3, r2] + 8004972: 68fb ldr r3, [r7, #12] + 8004974: 2284 movs r2, #132 @ 0x84 + 8004976: 2100 movs r1, #0 + 8004978: 5499 strb r1, [r3, r2] /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK, CORTEX */ HAL_UART_MspInit(huart); - 8003c4e: 68fb ldr r3, [r7, #12] - 8003c50: 0018 movs r0, r3 - 8003c52: f7fd f881 bl 8000d58 + 800497a: 68fb ldr r3, [r7, #12] + 800497c: 0018 movs r0, r3 + 800497e: f7fc fcd5 bl 800132c #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; - 8003c56: 68fb ldr r3, [r7, #12] - 8003c58: 2288 movs r2, #136 @ 0x88 - 8003c5a: 2124 movs r1, #36 @ 0x24 - 8003c5c: 5099 str r1, [r3, r2] + 8004982: 68fb ldr r3, [r7, #12] + 8004984: 2288 movs r2, #136 @ 0x88 + 8004986: 2124 movs r1, #36 @ 0x24 + 8004988: 5099 str r1, [r3, r2] /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - 8003c5e: 68fb ldr r3, [r7, #12] - 8003c60: 681b ldr r3, [r3, #0] - 8003c62: 681a ldr r2, [r3, #0] - 8003c64: 68fb ldr r3, [r7, #12] - 8003c66: 681b ldr r3, [r3, #0] - 8003c68: 2101 movs r1, #1 - 8003c6a: 438a bics r2, r1 - 8003c6c: 601a str r2, [r3, #0] + 800498a: 68fb ldr r3, [r7, #12] + 800498c: 681b ldr r3, [r3, #0] + 800498e: 681a ldr r2, [r3, #0] + 8004990: 68fb ldr r3, [r7, #12] + 8004992: 681b ldr r3, [r3, #0] + 8004994: 2101 movs r1, #1 + 8004996: 438a bics r2, r1 + 8004998: 601a str r2, [r3, #0] /* Perform advanced settings configuration */ /* For some items, configuration requires to be done prior TE and RE bits are set */ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - 8003c6e: 68fb ldr r3, [r7, #12] - 8003c70: 6a9b ldr r3, [r3, #40] @ 0x28 - 8003c72: 2b00 cmp r3, #0 - 8003c74: d003 beq.n 8003c7e + 800499a: 68fb ldr r3, [r7, #12] + 800499c: 6a9b ldr r3, [r3, #40] @ 0x28 + 800499e: 2b00 cmp r3, #0 + 80049a0: d003 beq.n 80049aa { UART_AdvFeatureConfig(huart); - 8003c76: 68fb ldr r3, [r7, #12] - 8003c78: 0018 movs r0, r3 - 8003c7a: f7ff fd9f bl 80037bc + 80049a2: 68fb ldr r3, [r7, #12] + 80049a4: 0018 movs r0, r3 + 80049a6: f7ff fb83 bl 80040b0 } /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) - 8003c7e: 68fb ldr r3, [r7, #12] - 8003c80: 0018 movs r0, r3 - 8003c82: f7ff fc1d bl 80034c0 - 8003c86: 0003 movs r3, r0 - 8003c88: 2b01 cmp r3, #1 - 8003c8a: d101 bne.n 8003c90 + 80049aa: 68fb ldr r3, [r7, #12] + 80049ac: 0018 movs r0, r3 + 80049ae: f7ff fa01 bl 8003db4 + 80049b2: 0003 movs r3, r0 + 80049b4: 2b01 cmp r3, #1 + 80049b6: d101 bne.n 80049bc { return HAL_ERROR; - 8003c8c: 2301 movs r3, #1 - 8003c8e: e033 b.n 8003cf8 + 80049b8: 2301 movs r3, #1 + 80049ba: e033 b.n 8004a24 } /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ SET_BIT(huart->Instance->CR3, USART_CR3_DEM); - 8003c90: 68fb ldr r3, [r7, #12] - 8003c92: 681b ldr r3, [r3, #0] - 8003c94: 689a ldr r2, [r3, #8] - 8003c96: 68fb ldr r3, [r7, #12] - 8003c98: 681b ldr r3, [r3, #0] - 8003c9a: 2180 movs r1, #128 @ 0x80 - 8003c9c: 01c9 lsls r1, r1, #7 - 8003c9e: 430a orrs r2, r1 - 8003ca0: 609a str r2, [r3, #8] + 80049bc: 68fb ldr r3, [r7, #12] + 80049be: 681b ldr r3, [r3, #0] + 80049c0: 689a ldr r2, [r3, #8] + 80049c2: 68fb ldr r3, [r7, #12] + 80049c4: 681b ldr r3, [r3, #0] + 80049c6: 2180 movs r1, #128 @ 0x80 + 80049c8: 01c9 lsls r1, r1, #7 + 80049ca: 430a orrs r2, r1 + 80049cc: 609a str r2, [r3, #8] /* Set the Driver Enable polarity */ MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity); - 8003ca2: 68fb ldr r3, [r7, #12] - 8003ca4: 681b ldr r3, [r3, #0] - 8003ca6: 689b ldr r3, [r3, #8] - 8003ca8: 4a15 ldr r2, [pc, #84] @ (8003d00 ) - 8003caa: 4013 ands r3, r2 - 8003cac: 0019 movs r1, r3 - 8003cae: 68fb ldr r3, [r7, #12] - 8003cb0: 681b ldr r3, [r3, #0] - 8003cb2: 68ba ldr r2, [r7, #8] - 8003cb4: 430a orrs r2, r1 - 8003cb6: 609a str r2, [r3, #8] + 80049ce: 68fb ldr r3, [r7, #12] + 80049d0: 681b ldr r3, [r3, #0] + 80049d2: 689b ldr r3, [r3, #8] + 80049d4: 4a15 ldr r2, [pc, #84] @ (8004a2c ) + 80049d6: 4013 ands r3, r2 + 80049d8: 0019 movs r1, r3 + 80049da: 68fb ldr r3, [r7, #12] + 80049dc: 681b ldr r3, [r3, #0] + 80049de: 68ba ldr r2, [r7, #8] + 80049e0: 430a orrs r2, r1 + 80049e2: 609a str r2, [r3, #8] /* Set the Driver Enable assertion and deassertion times */ temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS); - 8003cb8: 687b ldr r3, [r7, #4] - 8003cba: 055b lsls r3, r3, #21 - 8003cbc: 617b str r3, [r7, #20] + 80049e4: 687b ldr r3, [r7, #4] + 80049e6: 055b lsls r3, r3, #21 + 80049e8: 617b str r3, [r7, #20] temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS); - 8003cbe: 683b ldr r3, [r7, #0] - 8003cc0: 041b lsls r3, r3, #16 - 8003cc2: 697a ldr r2, [r7, #20] - 8003cc4: 4313 orrs r3, r2 - 8003cc6: 617b str r3, [r7, #20] + 80049ea: 683b ldr r3, [r7, #0] + 80049ec: 041b lsls r3, r3, #16 + 80049ee: 697a ldr r2, [r7, #20] + 80049f0: 4313 orrs r3, r2 + 80049f2: 617b str r3, [r7, #20] MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp); - 8003cc8: 68fb ldr r3, [r7, #12] - 8003cca: 681b ldr r3, [r3, #0] - 8003ccc: 681b ldr r3, [r3, #0] - 8003cce: 4a0d ldr r2, [pc, #52] @ (8003d04 ) - 8003cd0: 4013 ands r3, r2 - 8003cd2: 0019 movs r1, r3 - 8003cd4: 68fb ldr r3, [r7, #12] - 8003cd6: 681b ldr r3, [r3, #0] - 8003cd8: 697a ldr r2, [r7, #20] - 8003cda: 430a orrs r2, r1 - 8003cdc: 601a str r2, [r3, #0] + 80049f4: 68fb ldr r3, [r7, #12] + 80049f6: 681b ldr r3, [r3, #0] + 80049f8: 681b ldr r3, [r3, #0] + 80049fa: 4a0d ldr r2, [pc, #52] @ (8004a30 ) + 80049fc: 4013 ands r3, r2 + 80049fe: 0019 movs r1, r3 + 8004a00: 68fb ldr r3, [r7, #12] + 8004a02: 681b ldr r3, [r3, #0] + 8004a04: 697a ldr r2, [r7, #20] + 8004a06: 430a orrs r2, r1 + 8004a08: 601a str r2, [r3, #0] /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - 8003cde: 68fb ldr r3, [r7, #12] - 8003ce0: 681b ldr r3, [r3, #0] - 8003ce2: 681a ldr r2, [r3, #0] - 8003ce4: 68fb ldr r3, [r7, #12] - 8003ce6: 681b ldr r3, [r3, #0] - 8003ce8: 2101 movs r1, #1 - 8003cea: 430a orrs r2, r1 - 8003cec: 601a str r2, [r3, #0] + 8004a0a: 68fb ldr r3, [r7, #12] + 8004a0c: 681b ldr r3, [r3, #0] + 8004a0e: 681a ldr r2, [r3, #0] + 8004a10: 68fb ldr r3, [r7, #12] + 8004a12: 681b ldr r3, [r3, #0] + 8004a14: 2101 movs r1, #1 + 8004a16: 430a orrs r2, r1 + 8004a18: 601a str r2, [r3, #0] /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); - 8003cee: 68fb ldr r3, [r7, #12] - 8003cf0: 0018 movs r0, r3 - 8003cf2: f7ff fe17 bl 8003924 - 8003cf6: 0003 movs r3, r0 + 8004a1a: 68fb ldr r3, [r7, #12] + 8004a1c: 0018 movs r0, r3 + 8004a1e: f7ff fbfb bl 8004218 + 8004a22: 0003 movs r3, r0 } - 8003cf8: 0018 movs r0, r3 - 8003cfa: 46bd mov sp, r7 - 8003cfc: b006 add sp, #24 - 8003cfe: bd80 pop {r7, pc} - 8003d00: ffff7fff .word 0xffff7fff - 8003d04: fc00ffff .word 0xfc00ffff + 8004a24: 0018 movs r0, r3 + 8004a26: 46bd mov sp, r7 + 8004a28: b006 add sp, #24 + 8004a2a: bd80 pop {r7, pc} + 8004a2c: ffff7fff .word 0xffff7fff + 8004a30: fc00ffff .word 0xfc00ffff -08003d08 : +08004a34 : * @brief Disable the FIFO mode. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) { - 8003d08: b580 push {r7, lr} - 8003d0a: b084 sub sp, #16 - 8003d0c: af00 add r7, sp, #0 - 8003d0e: 6078 str r0, [r7, #4] + 8004a34: b580 push {r7, lr} + 8004a36: b084 sub sp, #16 + 8004a38: af00 add r7, sp, #0 + 8004a3a: 6078 str r0, [r7, #4] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); /* Process Locked */ __HAL_LOCK(huart); - 8003d10: 687b ldr r3, [r7, #4] - 8003d12: 2284 movs r2, #132 @ 0x84 - 8003d14: 5c9b ldrb r3, [r3, r2] - 8003d16: 2b01 cmp r3, #1 - 8003d18: d101 bne.n 8003d1e - 8003d1a: 2302 movs r3, #2 - 8003d1c: e027 b.n 8003d6e - 8003d1e: 687b ldr r3, [r7, #4] - 8003d20: 2284 movs r2, #132 @ 0x84 - 8003d22: 2101 movs r1, #1 - 8003d24: 5499 strb r1, [r3, r2] + 8004a3c: 687b ldr r3, [r7, #4] + 8004a3e: 2284 movs r2, #132 @ 0x84 + 8004a40: 5c9b ldrb r3, [r3, r2] + 8004a42: 2b01 cmp r3, #1 + 8004a44: d101 bne.n 8004a4a + 8004a46: 2302 movs r3, #2 + 8004a48: e027 b.n 8004a9a + 8004a4a: 687b ldr r3, [r7, #4] + 8004a4c: 2284 movs r2, #132 @ 0x84 + 8004a4e: 2101 movs r1, #1 + 8004a50: 5499 strb r1, [r3, r2] huart->gState = HAL_UART_STATE_BUSY; - 8003d26: 687b ldr r3, [r7, #4] - 8003d28: 2288 movs r2, #136 @ 0x88 - 8003d2a: 2124 movs r1, #36 @ 0x24 - 8003d2c: 5099 str r1, [r3, r2] + 8004a52: 687b ldr r3, [r7, #4] + 8004a54: 2288 movs r2, #136 @ 0x88 + 8004a56: 2124 movs r1, #36 @ 0x24 + 8004a58: 5099 str r1, [r3, r2] /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); - 8003d2e: 687b ldr r3, [r7, #4] - 8003d30: 681b ldr r3, [r3, #0] - 8003d32: 681b ldr r3, [r3, #0] - 8003d34: 60fb str r3, [r7, #12] + 8004a5a: 687b ldr r3, [r7, #4] + 8004a5c: 681b ldr r3, [r3, #0] + 8004a5e: 681b ldr r3, [r3, #0] + 8004a60: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); - 8003d36: 687b ldr r3, [r7, #4] - 8003d38: 681b ldr r3, [r3, #0] - 8003d3a: 681a ldr r2, [r3, #0] - 8003d3c: 687b ldr r3, [r7, #4] - 8003d3e: 681b ldr r3, [r3, #0] - 8003d40: 2101 movs r1, #1 - 8003d42: 438a bics r2, r1 - 8003d44: 601a str r2, [r3, #0] + 8004a62: 687b ldr r3, [r7, #4] + 8004a64: 681b ldr r3, [r3, #0] + 8004a66: 681a ldr r2, [r3, #0] + 8004a68: 687b ldr r3, [r7, #4] + 8004a6a: 681b ldr r3, [r3, #0] + 8004a6c: 2101 movs r1, #1 + 8004a6e: 438a bics r2, r1 + 8004a70: 601a str r2, [r3, #0] /* Disable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); - 8003d46: 68fb ldr r3, [r7, #12] - 8003d48: 4a0b ldr r2, [pc, #44] @ (8003d78 ) - 8003d4a: 4013 ands r3, r2 - 8003d4c: 60fb str r3, [r7, #12] + 8004a72: 68fb ldr r3, [r7, #12] + 8004a74: 4a0b ldr r2, [pc, #44] @ (8004aa4 ) + 8004a76: 4013 ands r3, r2 + 8004a78: 60fb str r3, [r7, #12] huart->FifoMode = UART_FIFOMODE_DISABLE; - 8003d4e: 687b ldr r3, [r7, #4] - 8003d50: 2200 movs r2, #0 - 8003d52: 665a str r2, [r3, #100] @ 0x64 + 8004a7a: 687b ldr r3, [r7, #4] + 8004a7c: 2200 movs r2, #0 + 8004a7e: 665a str r2, [r3, #100] @ 0x64 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); - 8003d54: 687b ldr r3, [r7, #4] - 8003d56: 681b ldr r3, [r3, #0] - 8003d58: 68fa ldr r2, [r7, #12] - 8003d5a: 601a str r2, [r3, #0] + 8004a80: 687b ldr r3, [r7, #4] + 8004a82: 681b ldr r3, [r3, #0] + 8004a84: 68fa ldr r2, [r7, #12] + 8004a86: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; - 8003d5c: 687b ldr r3, [r7, #4] - 8003d5e: 2288 movs r2, #136 @ 0x88 - 8003d60: 2120 movs r1, #32 - 8003d62: 5099 str r1, [r3, r2] + 8004a88: 687b ldr r3, [r7, #4] + 8004a8a: 2288 movs r2, #136 @ 0x88 + 8004a8c: 2120 movs r1, #32 + 8004a8e: 5099 str r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(huart); - 8003d64: 687b ldr r3, [r7, #4] - 8003d66: 2284 movs r2, #132 @ 0x84 - 8003d68: 2100 movs r1, #0 - 8003d6a: 5499 strb r1, [r3, r2] + 8004a90: 687b ldr r3, [r7, #4] + 8004a92: 2284 movs r2, #132 @ 0x84 + 8004a94: 2100 movs r1, #0 + 8004a96: 5499 strb r1, [r3, r2] return HAL_OK; - 8003d6c: 2300 movs r3, #0 + 8004a98: 2300 movs r3, #0 } - 8003d6e: 0018 movs r0, r3 - 8003d70: 46bd mov sp, r7 - 8003d72: b004 add sp, #16 - 8003d74: bd80 pop {r7, pc} - 8003d76: 46c0 nop @ (mov r8, r8) - 8003d78: dfffffff .word 0xdfffffff + 8004a9a: 0018 movs r0, r3 + 8004a9c: 46bd mov sp, r7 + 8004a9e: b004 add sp, #16 + 8004aa0: bd80 pop {r7, pc} + 8004aa2: 46c0 nop @ (mov r8, r8) + 8004aa4: dfffffff .word 0xdfffffff -08003d7c : +08004aa8 : * @arg @ref UART_TXFIFO_THRESHOLD_7_8 * @arg @ref UART_TXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { - 8003d7c: b580 push {r7, lr} - 8003d7e: b084 sub sp, #16 - 8003d80: af00 add r7, sp, #0 - 8003d82: 6078 str r0, [r7, #4] - 8003d84: 6039 str r1, [r7, #0] + 8004aa8: b580 push {r7, lr} + 8004aaa: b084 sub sp, #16 + 8004aac: af00 add r7, sp, #0 + 8004aae: 6078 str r0, [r7, #4] + 8004ab0: 6039 str r1, [r7, #0] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); - 8003d86: 687b ldr r3, [r7, #4] - 8003d88: 2284 movs r2, #132 @ 0x84 - 8003d8a: 5c9b ldrb r3, [r3, r2] - 8003d8c: 2b01 cmp r3, #1 - 8003d8e: d101 bne.n 8003d94 - 8003d90: 2302 movs r3, #2 - 8003d92: e02e b.n 8003df2 - 8003d94: 687b ldr r3, [r7, #4] - 8003d96: 2284 movs r2, #132 @ 0x84 - 8003d98: 2101 movs r1, #1 - 8003d9a: 5499 strb r1, [r3, r2] + 8004ab2: 687b ldr r3, [r7, #4] + 8004ab4: 2284 movs r2, #132 @ 0x84 + 8004ab6: 5c9b ldrb r3, [r3, r2] + 8004ab8: 2b01 cmp r3, #1 + 8004aba: d101 bne.n 8004ac0 + 8004abc: 2302 movs r3, #2 + 8004abe: e02e b.n 8004b1e + 8004ac0: 687b ldr r3, [r7, #4] + 8004ac2: 2284 movs r2, #132 @ 0x84 + 8004ac4: 2101 movs r1, #1 + 8004ac6: 5499 strb r1, [r3, r2] huart->gState = HAL_UART_STATE_BUSY; - 8003d9c: 687b ldr r3, [r7, #4] - 8003d9e: 2288 movs r2, #136 @ 0x88 - 8003da0: 2124 movs r1, #36 @ 0x24 - 8003da2: 5099 str r1, [r3, r2] + 8004ac8: 687b ldr r3, [r7, #4] + 8004aca: 2288 movs r2, #136 @ 0x88 + 8004acc: 2124 movs r1, #36 @ 0x24 + 8004ace: 5099 str r1, [r3, r2] /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); - 8003da4: 687b ldr r3, [r7, #4] - 8003da6: 681b ldr r3, [r3, #0] - 8003da8: 681b ldr r3, [r3, #0] - 8003daa: 60fb str r3, [r7, #12] + 8004ad0: 687b ldr r3, [r7, #4] + 8004ad2: 681b ldr r3, [r3, #0] + 8004ad4: 681b ldr r3, [r3, #0] + 8004ad6: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); - 8003dac: 687b ldr r3, [r7, #4] - 8003dae: 681b ldr r3, [r3, #0] - 8003db0: 681a ldr r2, [r3, #0] - 8003db2: 687b ldr r3, [r7, #4] - 8003db4: 681b ldr r3, [r3, #0] - 8003db6: 2101 movs r1, #1 - 8003db8: 438a bics r2, r1 - 8003dba: 601a str r2, [r3, #0] + 8004ad8: 687b ldr r3, [r7, #4] + 8004ada: 681b ldr r3, [r3, #0] + 8004adc: 681a ldr r2, [r3, #0] + 8004ade: 687b ldr r3, [r7, #4] + 8004ae0: 681b ldr r3, [r3, #0] + 8004ae2: 2101 movs r1, #1 + 8004ae4: 438a bics r2, r1 + 8004ae6: 601a str r2, [r3, #0] /* Update TX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); - 8003dbc: 687b ldr r3, [r7, #4] - 8003dbe: 681b ldr r3, [r3, #0] - 8003dc0: 689b ldr r3, [r3, #8] - 8003dc2: 00db lsls r3, r3, #3 - 8003dc4: 08d9 lsrs r1, r3, #3 - 8003dc6: 687b ldr r3, [r7, #4] - 8003dc8: 681b ldr r3, [r3, #0] - 8003dca: 683a ldr r2, [r7, #0] - 8003dcc: 430a orrs r2, r1 - 8003dce: 609a str r2, [r3, #8] + 8004ae8: 687b ldr r3, [r7, #4] + 8004aea: 681b ldr r3, [r3, #0] + 8004aec: 689b ldr r3, [r3, #8] + 8004aee: 00db lsls r3, r3, #3 + 8004af0: 08d9 lsrs r1, r3, #3 + 8004af2: 687b ldr r3, [r7, #4] + 8004af4: 681b ldr r3, [r3, #0] + 8004af6: 683a ldr r2, [r7, #0] + 8004af8: 430a orrs r2, r1 + 8004afa: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); - 8003dd0: 687b ldr r3, [r7, #4] - 8003dd2: 0018 movs r0, r3 - 8003dd4: f000 f854 bl 8003e80 + 8004afc: 687b ldr r3, [r7, #4] + 8004afe: 0018 movs r0, r3 + 8004b00: f000 f8bc bl 8004c7c /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); - 8003dd8: 687b ldr r3, [r7, #4] - 8003dda: 681b ldr r3, [r3, #0] - 8003ddc: 68fa ldr r2, [r7, #12] - 8003dde: 601a str r2, [r3, #0] + 8004b04: 687b ldr r3, [r7, #4] + 8004b06: 681b ldr r3, [r3, #0] + 8004b08: 68fa ldr r2, [r7, #12] + 8004b0a: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; - 8003de0: 687b ldr r3, [r7, #4] - 8003de2: 2288 movs r2, #136 @ 0x88 - 8003de4: 2120 movs r1, #32 - 8003de6: 5099 str r1, [r3, r2] + 8004b0c: 687b ldr r3, [r7, #4] + 8004b0e: 2288 movs r2, #136 @ 0x88 + 8004b10: 2120 movs r1, #32 + 8004b12: 5099 str r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(huart); - 8003de8: 687b ldr r3, [r7, #4] - 8003dea: 2284 movs r2, #132 @ 0x84 - 8003dec: 2100 movs r1, #0 - 8003dee: 5499 strb r1, [r3, r2] + 8004b14: 687b ldr r3, [r7, #4] + 8004b16: 2284 movs r2, #132 @ 0x84 + 8004b18: 2100 movs r1, #0 + 8004b1a: 5499 strb r1, [r3, r2] return HAL_OK; - 8003df0: 2300 movs r3, #0 + 8004b1c: 2300 movs r3, #0 } - 8003df2: 0018 movs r0, r3 - 8003df4: 46bd mov sp, r7 - 8003df6: b004 add sp, #16 - 8003df8: bd80 pop {r7, pc} + 8004b1e: 0018 movs r0, r3 + 8004b20: 46bd mov sp, r7 + 8004b22: b004 add sp, #16 + 8004b24: bd80 pop {r7, pc} ... -08003dfc : +08004b28 : * @arg @ref UART_RXFIFO_THRESHOLD_7_8 * @arg @ref UART_RXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { - 8003dfc: b580 push {r7, lr} - 8003dfe: b084 sub sp, #16 - 8003e00: af00 add r7, sp, #0 - 8003e02: 6078 str r0, [r7, #4] - 8003e04: 6039 str r1, [r7, #0] + 8004b28: b580 push {r7, lr} + 8004b2a: b084 sub sp, #16 + 8004b2c: af00 add r7, sp, #0 + 8004b2e: 6078 str r0, [r7, #4] + 8004b30: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); - 8003e06: 687b ldr r3, [r7, #4] - 8003e08: 2284 movs r2, #132 @ 0x84 - 8003e0a: 5c9b ldrb r3, [r3, r2] - 8003e0c: 2b01 cmp r3, #1 - 8003e0e: d101 bne.n 8003e14 - 8003e10: 2302 movs r3, #2 - 8003e12: e02f b.n 8003e74 - 8003e14: 687b ldr r3, [r7, #4] - 8003e16: 2284 movs r2, #132 @ 0x84 - 8003e18: 2101 movs r1, #1 - 8003e1a: 5499 strb r1, [r3, r2] + 8004b32: 687b ldr r3, [r7, #4] + 8004b34: 2284 movs r2, #132 @ 0x84 + 8004b36: 5c9b ldrb r3, [r3, r2] + 8004b38: 2b01 cmp r3, #1 + 8004b3a: d101 bne.n 8004b40 + 8004b3c: 2302 movs r3, #2 + 8004b3e: e02f b.n 8004ba0 + 8004b40: 687b ldr r3, [r7, #4] + 8004b42: 2284 movs r2, #132 @ 0x84 + 8004b44: 2101 movs r1, #1 + 8004b46: 5499 strb r1, [r3, r2] huart->gState = HAL_UART_STATE_BUSY; - 8003e1c: 687b ldr r3, [r7, #4] - 8003e1e: 2288 movs r2, #136 @ 0x88 - 8003e20: 2124 movs r1, #36 @ 0x24 - 8003e22: 5099 str r1, [r3, r2] + 8004b48: 687b ldr r3, [r7, #4] + 8004b4a: 2288 movs r2, #136 @ 0x88 + 8004b4c: 2124 movs r1, #36 @ 0x24 + 8004b4e: 5099 str r1, [r3, r2] /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); - 8003e24: 687b ldr r3, [r7, #4] - 8003e26: 681b ldr r3, [r3, #0] - 8003e28: 681b ldr r3, [r3, #0] - 8003e2a: 60fb str r3, [r7, #12] + 8004b50: 687b ldr r3, [r7, #4] + 8004b52: 681b ldr r3, [r3, #0] + 8004b54: 681b ldr r3, [r3, #0] + 8004b56: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); - 8003e2c: 687b ldr r3, [r7, #4] - 8003e2e: 681b ldr r3, [r3, #0] - 8003e30: 681a ldr r2, [r3, #0] - 8003e32: 687b ldr r3, [r7, #4] - 8003e34: 681b ldr r3, [r3, #0] - 8003e36: 2101 movs r1, #1 - 8003e38: 438a bics r2, r1 - 8003e3a: 601a str r2, [r3, #0] + 8004b58: 687b ldr r3, [r7, #4] + 8004b5a: 681b ldr r3, [r3, #0] + 8004b5c: 681a ldr r2, [r3, #0] + 8004b5e: 687b ldr r3, [r7, #4] + 8004b60: 681b ldr r3, [r3, #0] + 8004b62: 2101 movs r1, #1 + 8004b64: 438a bics r2, r1 + 8004b66: 601a str r2, [r3, #0] /* Update RX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); - 8003e3c: 687b ldr r3, [r7, #4] - 8003e3e: 681b ldr r3, [r3, #0] - 8003e40: 689b ldr r3, [r3, #8] - 8003e42: 4a0e ldr r2, [pc, #56] @ (8003e7c ) - 8003e44: 4013 ands r3, r2 - 8003e46: 0019 movs r1, r3 - 8003e48: 687b ldr r3, [r7, #4] - 8003e4a: 681b ldr r3, [r3, #0] - 8003e4c: 683a ldr r2, [r7, #0] - 8003e4e: 430a orrs r2, r1 - 8003e50: 609a str r2, [r3, #8] + 8004b68: 687b ldr r3, [r7, #4] + 8004b6a: 681b ldr r3, [r3, #0] + 8004b6c: 689b ldr r3, [r3, #8] + 8004b6e: 4a0e ldr r2, [pc, #56] @ (8004ba8 ) + 8004b70: 4013 ands r3, r2 + 8004b72: 0019 movs r1, r3 + 8004b74: 687b ldr r3, [r7, #4] + 8004b76: 681b ldr r3, [r3, #0] + 8004b78: 683a ldr r2, [r7, #0] + 8004b7a: 430a orrs r2, r1 + 8004b7c: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); - 8003e52: 687b ldr r3, [r7, #4] - 8003e54: 0018 movs r0, r3 - 8003e56: f000 f813 bl 8003e80 + 8004b7e: 687b ldr r3, [r7, #4] + 8004b80: 0018 movs r0, r3 + 8004b82: f000 f87b bl 8004c7c /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); - 8003e5a: 687b ldr r3, [r7, #4] - 8003e5c: 681b ldr r3, [r3, #0] - 8003e5e: 68fa ldr r2, [r7, #12] - 8003e60: 601a str r2, [r3, #0] + 8004b86: 687b ldr r3, [r7, #4] + 8004b88: 681b ldr r3, [r3, #0] + 8004b8a: 68fa ldr r2, [r7, #12] + 8004b8c: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; - 8003e62: 687b ldr r3, [r7, #4] - 8003e64: 2288 movs r2, #136 @ 0x88 - 8003e66: 2120 movs r1, #32 - 8003e68: 5099 str r1, [r3, r2] + 8004b8e: 687b ldr r3, [r7, #4] + 8004b90: 2288 movs r2, #136 @ 0x88 + 8004b92: 2120 movs r1, #32 + 8004b94: 5099 str r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(huart); - 8003e6a: 687b ldr r3, [r7, #4] - 8003e6c: 2284 movs r2, #132 @ 0x84 - 8003e6e: 2100 movs r1, #0 - 8003e70: 5499 strb r1, [r3, r2] + 8004b96: 687b ldr r3, [r7, #4] + 8004b98: 2284 movs r2, #132 @ 0x84 + 8004b9a: 2100 movs r1, #0 + 8004b9c: 5499 strb r1, [r3, r2] return HAL_OK; - 8003e72: 2300 movs r3, #0 + 8004b9e: 2300 movs r3, #0 } - 8003e74: 0018 movs r0, r3 - 8003e76: 46bd mov sp, r7 - 8003e78: b004 add sp, #16 - 8003e7a: bd80 pop {r7, pc} - 8003e7c: f1ffffff .word 0xf1ffffff + 8004ba0: 0018 movs r0, r3 + 8004ba2: 46bd mov sp, r7 + 8004ba4: b004 add sp, #16 + 8004ba6: bd80 pop {r7, pc} + 8004ba8: f1ffffff .word 0xf1ffffff -08003e80 : +08004bac : + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + 8004bac: b5b0 push {r4, r5, r7, lr} + 8004bae: b08a sub sp, #40 @ 0x28 + 8004bb0: af00 add r7, sp, #0 + 8004bb2: 60f8 str r0, [r7, #12] + 8004bb4: 60b9 str r1, [r7, #8] + 8004bb6: 1dbb adds r3, r7, #6 + 8004bb8: 801a strh r2, [r3, #0] + HAL_StatusTypeDef status; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + 8004bba: 68fb ldr r3, [r7, #12] + 8004bbc: 228c movs r2, #140 @ 0x8c + 8004bbe: 589b ldr r3, [r3, r2] + 8004bc0: 2b20 cmp r3, #32 + 8004bc2: d156 bne.n 8004c72 + { + if ((pData == NULL) || (Size == 0U)) + 8004bc4: 68bb ldr r3, [r7, #8] + 8004bc6: 2b00 cmp r3, #0 + 8004bc8: d003 beq.n 8004bd2 + 8004bca: 1dbb adds r3, r7, #6 + 8004bcc: 881b ldrh r3, [r3, #0] + 8004bce: 2b00 cmp r3, #0 + 8004bd0: d101 bne.n 8004bd6 + { + return HAL_ERROR; + 8004bd2: 2301 movs r3, #1 + 8004bd4: e04e b.n 8004c74 + } + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a uint16_t frontier, as data copy from RDR will be + handled by DMA from a uint16_t frontier. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + 8004bd6: 68fb ldr r3, [r7, #12] + 8004bd8: 689a ldr r2, [r3, #8] + 8004bda: 2380 movs r3, #128 @ 0x80 + 8004bdc: 015b lsls r3, r3, #5 + 8004bde: 429a cmp r2, r3 + 8004be0: d109 bne.n 8004bf6 + 8004be2: 68fb ldr r3, [r7, #12] + 8004be4: 691b ldr r3, [r3, #16] + 8004be6: 2b00 cmp r3, #0 + 8004be8: d105 bne.n 8004bf6 + { + if ((((uint32_t)pData) & 1U) != 0U) + 8004bea: 68bb ldr r3, [r7, #8] + 8004bec: 2201 movs r2, #1 + 8004bee: 4013 ands r3, r2 + 8004bf0: d001 beq.n 8004bf6 + { + return HAL_ERROR; + 8004bf2: 2301 movs r3, #1 + 8004bf4: e03e b.n 8004c74 + } + } + + /* Set Reception type to reception till IDLE Event*/ + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + 8004bf6: 68fb ldr r3, [r7, #12] + 8004bf8: 2201 movs r2, #1 + 8004bfa: 66da str r2, [r3, #108] @ 0x6c + huart->RxEventType = HAL_UART_RXEVENT_TC; + 8004bfc: 68fb ldr r3, [r7, #12] + 8004bfe: 2200 movs r2, #0 + 8004c00: 671a str r2, [r3, #112] @ 0x70 + + status = UART_Start_Receive_DMA(huart, pData, Size); + 8004c02: 2527 movs r5, #39 @ 0x27 + 8004c04: 197c adds r4, r7, r5 + 8004c06: 1dbb adds r3, r7, #6 + 8004c08: 881a ldrh r2, [r3, #0] + 8004c0a: 68b9 ldr r1, [r7, #8] + 8004c0c: 68fb ldr r3, [r7, #12] + 8004c0e: 0018 movs r0, r3 + 8004c10: f7ff fc1c bl 800444c + 8004c14: 0003 movs r3, r0 + 8004c16: 7023 strb r3, [r4, #0] + + /* Check Rx process has been successfully started */ + if (status == HAL_OK) + 8004c18: 197b adds r3, r7, r5 + 8004c1a: 781b ldrb r3, [r3, #0] + 8004c1c: 2b00 cmp r3, #0 + 8004c1e: d124 bne.n 8004c6a + { + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + 8004c20: 68fb ldr r3, [r7, #12] + 8004c22: 6edb ldr r3, [r3, #108] @ 0x6c + 8004c24: 2b01 cmp r3, #1 + 8004c26: d11c bne.n 8004c62 + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + 8004c28: 68fb ldr r3, [r7, #12] + 8004c2a: 681b ldr r3, [r3, #0] + 8004c2c: 2210 movs r2, #16 + 8004c2e: 621a str r2, [r3, #32] + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + 8004c30: f3ef 8310 mrs r3, PRIMASK + 8004c34: 617b str r3, [r7, #20] + return(result); + 8004c36: 697b ldr r3, [r7, #20] + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + 8004c38: 623b str r3, [r7, #32] + 8004c3a: 2301 movs r3, #1 + 8004c3c: 61bb str r3, [r7, #24] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8004c3e: 69bb ldr r3, [r7, #24] + 8004c40: f383 8810 msr PRIMASK, r3 +} + 8004c44: 46c0 nop @ (mov r8, r8) + 8004c46: 68fb ldr r3, [r7, #12] + 8004c48: 681b ldr r3, [r3, #0] + 8004c4a: 681a ldr r2, [r3, #0] + 8004c4c: 68fb ldr r3, [r7, #12] + 8004c4e: 681b ldr r3, [r3, #0] + 8004c50: 2110 movs r1, #16 + 8004c52: 430a orrs r2, r1 + 8004c54: 601a str r2, [r3, #0] + 8004c56: 6a3b ldr r3, [r7, #32] + 8004c58: 61fb str r3, [r7, #28] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8004c5a: 69fb ldr r3, [r7, #28] + 8004c5c: f383 8810 msr PRIMASK, r3 +} + 8004c60: e003 b.n 8004c6a + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; + 8004c62: 2327 movs r3, #39 @ 0x27 + 8004c64: 18fb adds r3, r7, r3 + 8004c66: 2201 movs r2, #1 + 8004c68: 701a strb r2, [r3, #0] + } + } + + return status; + 8004c6a: 2327 movs r3, #39 @ 0x27 + 8004c6c: 18fb adds r3, r7, r3 + 8004c6e: 781b ldrb r3, [r3, #0] + 8004c70: e000 b.n 8004c74 + } + else + { + return HAL_BUSY; + 8004c72: 2302 movs r3, #2 + } +} + 8004c74: 0018 movs r0, r3 + 8004c76: 46bd mov sp, r7 + 8004c78: b00a add sp, #40 @ 0x28 + 8004c7a: bdb0 pop {r4, r5, r7, pc} + +08004c7c : * the UART configuration registers. * @param huart UART handle. * @retval None */ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) { - 8003e80: b5f0 push {r4, r5, r6, r7, lr} - 8003e82: b085 sub sp, #20 - 8003e84: af00 add r7, sp, #0 - 8003e86: 6078 str r0, [r7, #4] + 8004c7c: b5f0 push {r4, r5, r6, r7, lr} + 8004c7e: b085 sub sp, #20 + 8004c80: af00 add r7, sp, #0 + 8004c82: 6078 str r0, [r7, #4] uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (huart->FifoMode == UART_FIFOMODE_DISABLE) - 8003e88: 687b ldr r3, [r7, #4] - 8003e8a: 6e5b ldr r3, [r3, #100] @ 0x64 - 8003e8c: 2b00 cmp r3, #0 - 8003e8e: d108 bne.n 8003ea2 + 8004c84: 687b ldr r3, [r7, #4] + 8004c86: 6e5b ldr r3, [r3, #100] @ 0x64 + 8004c88: 2b00 cmp r3, #0 + 8004c8a: d108 bne.n 8004c9e { huart->NbTxDataToProcess = 1U; - 8003e90: 687b ldr r3, [r7, #4] - 8003e92: 226a movs r2, #106 @ 0x6a - 8003e94: 2101 movs r1, #1 - 8003e96: 5299 strh r1, [r3, r2] + 8004c8c: 687b ldr r3, [r7, #4] + 8004c8e: 226a movs r2, #106 @ 0x6a + 8004c90: 2101 movs r1, #1 + 8004c92: 5299 strh r1, [r3, r2] huart->NbRxDataToProcess = 1U; - 8003e98: 687b ldr r3, [r7, #4] - 8003e9a: 2268 movs r2, #104 @ 0x68 - 8003e9c: 2101 movs r1, #1 - 8003e9e: 5299 strh r1, [r3, r2] + 8004c94: 687b ldr r3, [r7, #4] + 8004c96: 2268 movs r2, #104 @ 0x68 + 8004c98: 2101 movs r1, #1 + 8004c9a: 5299 strh r1, [r3, r2] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; } } - 8003ea0: e043 b.n 8003f2a + 8004c9c: e043 b.n 8004d26 rx_fifo_depth = RX_FIFO_DEPTH; - 8003ea2: 260f movs r6, #15 - 8003ea4: 19bb adds r3, r7, r6 - 8003ea6: 2208 movs r2, #8 - 8003ea8: 701a strb r2, [r3, #0] + 8004c9e: 260f movs r6, #15 + 8004ca0: 19bb adds r3, r7, r6 + 8004ca2: 2208 movs r2, #8 + 8004ca4: 701a strb r2, [r3, #0] tx_fifo_depth = TX_FIFO_DEPTH; - 8003eaa: 200e movs r0, #14 - 8003eac: 183b adds r3, r7, r0 - 8003eae: 2208 movs r2, #8 - 8003eb0: 701a strb r2, [r3, #0] + 8004ca6: 200e movs r0, #14 + 8004ca8: 183b adds r3, r7, r0 + 8004caa: 2208 movs r2, #8 + 8004cac: 701a strb r2, [r3, #0] rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); - 8003eb2: 687b ldr r3, [r7, #4] - 8003eb4: 681b ldr r3, [r3, #0] - 8003eb6: 689b ldr r3, [r3, #8] - 8003eb8: 0e5b lsrs r3, r3, #25 - 8003eba: b2da uxtb r2, r3 - 8003ebc: 240d movs r4, #13 - 8003ebe: 193b adds r3, r7, r4 - 8003ec0: 2107 movs r1, #7 - 8003ec2: 400a ands r2, r1 - 8003ec4: 701a strb r2, [r3, #0] + 8004cae: 687b ldr r3, [r7, #4] + 8004cb0: 681b ldr r3, [r3, #0] + 8004cb2: 689b ldr r3, [r3, #8] + 8004cb4: 0e5b lsrs r3, r3, #25 + 8004cb6: b2da uxtb r2, r3 + 8004cb8: 240d movs r4, #13 + 8004cba: 193b adds r3, r7, r4 + 8004cbc: 2107 movs r1, #7 + 8004cbe: 400a ands r2, r1 + 8004cc0: 701a strb r2, [r3, #0] tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); - 8003ec6: 687b ldr r3, [r7, #4] - 8003ec8: 681b ldr r3, [r3, #0] - 8003eca: 689b ldr r3, [r3, #8] - 8003ecc: 0f5b lsrs r3, r3, #29 - 8003ece: b2da uxtb r2, r3 - 8003ed0: 250c movs r5, #12 - 8003ed2: 197b adds r3, r7, r5 - 8003ed4: 2107 movs r1, #7 - 8003ed6: 400a ands r2, r1 - 8003ed8: 701a strb r2, [r3, #0] + 8004cc2: 687b ldr r3, [r7, #4] + 8004cc4: 681b ldr r3, [r3, #0] + 8004cc6: 689b ldr r3, [r3, #8] + 8004cc8: 0f5b lsrs r3, r3, #29 + 8004cca: b2da uxtb r2, r3 + 8004ccc: 250c movs r5, #12 + 8004cce: 197b adds r3, r7, r5 + 8004cd0: 2107 movs r1, #7 + 8004cd2: 400a ands r2, r1 + 8004cd4: 701a strb r2, [r3, #0] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / - 8003eda: 183b adds r3, r7, r0 - 8003edc: 781b ldrb r3, [r3, #0] - 8003ede: 197a adds r2, r7, r5 - 8003ee0: 7812 ldrb r2, [r2, #0] - 8003ee2: 4914 ldr r1, [pc, #80] @ (8003f34 ) - 8003ee4: 5c8a ldrb r2, [r1, r2] - 8003ee6: 435a muls r2, r3 - 8003ee8: 0010 movs r0, r2 + 8004cd6: 183b adds r3, r7, r0 + 8004cd8: 781b ldrb r3, [r3, #0] + 8004cda: 197a adds r2, r7, r5 + 8004cdc: 7812 ldrb r2, [r2, #0] + 8004cde: 4914 ldr r1, [pc, #80] @ (8004d30 ) + 8004ce0: 5c8a ldrb r2, [r1, r2] + 8004ce2: 435a muls r2, r3 + 8004ce4: 0010 movs r0, r2 (uint16_t)denominator[tx_fifo_threshold]; - 8003eea: 197b adds r3, r7, r5 - 8003eec: 781b ldrb r3, [r3, #0] - 8003eee: 4a12 ldr r2, [pc, #72] @ (8003f38 ) - 8003ef0: 5cd3 ldrb r3, [r2, r3] + 8004ce6: 197b adds r3, r7, r5 + 8004ce8: 781b ldrb r3, [r3, #0] + 8004cea: 4a12 ldr r2, [pc, #72] @ (8004d34 ) + 8004cec: 5cd3 ldrb r3, [r2, r3] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / - 8003ef2: 0019 movs r1, r3 - 8003ef4: f7fc f992 bl 800021c <__divsi3> - 8003ef8: 0003 movs r3, r0 - 8003efa: b299 uxth r1, r3 - 8003efc: 687b ldr r3, [r7, #4] - 8003efe: 226a movs r2, #106 @ 0x6a - 8003f00: 5299 strh r1, [r3, r2] + 8004cee: 0019 movs r1, r3 + 8004cf0: f7fb fa94 bl 800021c <__divsi3> + 8004cf4: 0003 movs r3, r0 + 8004cf6: b299 uxth r1, r3 + 8004cf8: 687b ldr r3, [r7, #4] + 8004cfa: 226a movs r2, #106 @ 0x6a + 8004cfc: 5299 strh r1, [r3, r2] huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / - 8003f02: 19bb adds r3, r7, r6 - 8003f04: 781b ldrb r3, [r3, #0] - 8003f06: 193a adds r2, r7, r4 - 8003f08: 7812 ldrb r2, [r2, #0] - 8003f0a: 490a ldr r1, [pc, #40] @ (8003f34 ) - 8003f0c: 5c8a ldrb r2, [r1, r2] - 8003f0e: 435a muls r2, r3 - 8003f10: 0010 movs r0, r2 + 8004cfe: 19bb adds r3, r7, r6 + 8004d00: 781b ldrb r3, [r3, #0] + 8004d02: 193a adds r2, r7, r4 + 8004d04: 7812 ldrb r2, [r2, #0] + 8004d06: 490a ldr r1, [pc, #40] @ (8004d30 ) + 8004d08: 5c8a ldrb r2, [r1, r2] + 8004d0a: 435a muls r2, r3 + 8004d0c: 0010 movs r0, r2 (uint16_t)denominator[rx_fifo_threshold]; - 8003f12: 193b adds r3, r7, r4 - 8003f14: 781b ldrb r3, [r3, #0] - 8003f16: 4a08 ldr r2, [pc, #32] @ (8003f38 ) - 8003f18: 5cd3 ldrb r3, [r2, r3] + 8004d0e: 193b adds r3, r7, r4 + 8004d10: 781b ldrb r3, [r3, #0] + 8004d12: 4a08 ldr r2, [pc, #32] @ (8004d34 ) + 8004d14: 5cd3 ldrb r3, [r2, r3] huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / - 8003f1a: 0019 movs r1, r3 - 8003f1c: f7fc f97e bl 800021c <__divsi3> - 8003f20: 0003 movs r3, r0 - 8003f22: b299 uxth r1, r3 - 8003f24: 687b ldr r3, [r7, #4] - 8003f26: 2268 movs r2, #104 @ 0x68 - 8003f28: 5299 strh r1, [r3, r2] + 8004d16: 0019 movs r1, r3 + 8004d18: f7fb fa80 bl 800021c <__divsi3> + 8004d1c: 0003 movs r3, r0 + 8004d1e: b299 uxth r1, r3 + 8004d20: 687b ldr r3, [r7, #4] + 8004d22: 2268 movs r2, #104 @ 0x68 + 8004d24: 5299 strh r1, [r3, r2] } - 8003f2a: 46c0 nop @ (mov r8, r8) - 8003f2c: 46bd mov sp, r7 - 8003f2e: b005 add sp, #20 - 8003f30: bdf0 pop {r4, r5, r6, r7, pc} - 8003f32: 46c0 nop @ (mov r8, r8) - 8003f34: 08004078 .word 0x08004078 - 8003f38: 08004080 .word 0x08004080 + 8004d26: 46c0 nop @ (mov r8, r8) + 8004d28: 46bd mov sp, r7 + 8004d2a: b005 add sp, #20 + 8004d2c: bdf0 pop {r4, r5, r6, r7, pc} + 8004d2e: 46c0 nop @ (mov r8, r8) + 8004d30: 08004e88 .word 0x08004e88 + 8004d34: 08004e90 .word 0x08004e90 -08003f3c : - 8003f3c: 0003 movs r3, r0 - 8003f3e: 1882 adds r2, r0, r2 - 8003f40: 4293 cmp r3, r2 - 8003f42: d100 bne.n 8003f46 - 8003f44: 4770 bx lr - 8003f46: 7019 strb r1, [r3, #0] - 8003f48: 3301 adds r3, #1 - 8003f4a: e7f9 b.n 8003f40 +08004d38 : + 8004d38: 0003 movs r3, r0 + 8004d3a: 1882 adds r2, r0, r2 + 8004d3c: 4293 cmp r3, r2 + 8004d3e: d100 bne.n 8004d42 + 8004d40: 4770 bx lr + 8004d42: 7019 strb r1, [r3, #0] + 8004d44: 3301 adds r3, #1 + 8004d46: e7f9 b.n 8004d3c -08003f4c <__libc_init_array>: - 8003f4c: b570 push {r4, r5, r6, lr} - 8003f4e: 2600 movs r6, #0 - 8003f50: 4c0c ldr r4, [pc, #48] @ (8003f84 <__libc_init_array+0x38>) - 8003f52: 4d0d ldr r5, [pc, #52] @ (8003f88 <__libc_init_array+0x3c>) - 8003f54: 1b64 subs r4, r4, r5 - 8003f56: 10a4 asrs r4, r4, #2 - 8003f58: 42a6 cmp r6, r4 - 8003f5a: d109 bne.n 8003f70 <__libc_init_array+0x24> - 8003f5c: 2600 movs r6, #0 - 8003f5e: f000 f819 bl 8003f94 <_init> - 8003f62: 4c0a ldr r4, [pc, #40] @ (8003f8c <__libc_init_array+0x40>) - 8003f64: 4d0a ldr r5, [pc, #40] @ (8003f90 <__libc_init_array+0x44>) - 8003f66: 1b64 subs r4, r4, r5 - 8003f68: 10a4 asrs r4, r4, #2 - 8003f6a: 42a6 cmp r6, r4 - 8003f6c: d105 bne.n 8003f7a <__libc_init_array+0x2e> - 8003f6e: bd70 pop {r4, r5, r6, pc} - 8003f70: 00b3 lsls r3, r6, #2 - 8003f72: 58eb ldr r3, [r5, r3] - 8003f74: 4798 blx r3 - 8003f76: 3601 adds r6, #1 - 8003f78: e7ee b.n 8003f58 <__libc_init_array+0xc> - 8003f7a: 00b3 lsls r3, r6, #2 - 8003f7c: 58eb ldr r3, [r5, r3] - 8003f7e: 4798 blx r3 - 8003f80: 3601 adds r6, #1 - 8003f82: e7f2 b.n 8003f6a <__libc_init_array+0x1e> - 8003f84: 08004088 .word 0x08004088 - 8003f88: 08004088 .word 0x08004088 - 8003f8c: 0800408c .word 0x0800408c - 8003f90: 08004088 .word 0x08004088 +08004d48 <__libc_init_array>: + 8004d48: b570 push {r4, r5, r6, lr} + 8004d4a: 2600 movs r6, #0 + 8004d4c: 4c0c ldr r4, [pc, #48] @ (8004d80 <__libc_init_array+0x38>) + 8004d4e: 4d0d ldr r5, [pc, #52] @ (8004d84 <__libc_init_array+0x3c>) + 8004d50: 1b64 subs r4, r4, r5 + 8004d52: 10a4 asrs r4, r4, #2 + 8004d54: 42a6 cmp r6, r4 + 8004d56: d109 bne.n 8004d6c <__libc_init_array+0x24> + 8004d58: 2600 movs r6, #0 + 8004d5a: f000 f823 bl 8004da4 <_init> + 8004d5e: 4c0a ldr r4, [pc, #40] @ (8004d88 <__libc_init_array+0x40>) + 8004d60: 4d0a ldr r5, [pc, #40] @ (8004d8c <__libc_init_array+0x44>) + 8004d62: 1b64 subs r4, r4, r5 + 8004d64: 10a4 asrs r4, r4, #2 + 8004d66: 42a6 cmp r6, r4 + 8004d68: d105 bne.n 8004d76 <__libc_init_array+0x2e> + 8004d6a: bd70 pop {r4, r5, r6, pc} + 8004d6c: 00b3 lsls r3, r6, #2 + 8004d6e: 58eb ldr r3, [r5, r3] + 8004d70: 4798 blx r3 + 8004d72: 3601 adds r6, #1 + 8004d74: e7ee b.n 8004d54 <__libc_init_array+0xc> + 8004d76: 00b3 lsls r3, r6, #2 + 8004d78: 58eb ldr r3, [r5, r3] + 8004d7a: 4798 blx r3 + 8004d7c: 3601 adds r6, #1 + 8004d7e: e7f2 b.n 8004d66 <__libc_init_array+0x1e> + 8004d80: 08004e98 .word 0x08004e98 + 8004d84: 08004e98 .word 0x08004e98 + 8004d88: 08004e9c .word 0x08004e9c + 8004d8c: 08004e98 .word 0x08004e98 -08003f94 <_init>: - 8003f94: b5f8 push {r3, r4, r5, r6, r7, lr} - 8003f96: 46c0 nop @ (mov r8, r8) - 8003f98: bcf8 pop {r3, r4, r5, r6, r7} - 8003f9a: bc08 pop {r3} - 8003f9c: 469e mov lr, r3 - 8003f9e: 4770 bx lr +08004d90 : + 8004d90: 2300 movs r3, #0 + 8004d92: b510 push {r4, lr} + 8004d94: 429a cmp r2, r3 + 8004d96: d100 bne.n 8004d9a + 8004d98: bd10 pop {r4, pc} + 8004d9a: 5ccc ldrb r4, [r1, r3] + 8004d9c: 54c4 strb r4, [r0, r3] + 8004d9e: 3301 adds r3, #1 + 8004da0: e7f8 b.n 8004d94 + ... -08003fa0 <_fini>: - 8003fa0: b5f8 push {r3, r4, r5, r6, r7, lr} - 8003fa2: 46c0 nop @ (mov r8, r8) - 8003fa4: bcf8 pop {r3, r4, r5, r6, r7} - 8003fa6: bc08 pop {r3} - 8003fa8: 469e mov lr, r3 - 8003faa: 4770 bx lr +08004da4 <_init>: + 8004da4: b5f8 push {r3, r4, r5, r6, r7, lr} + 8004da6: 46c0 nop @ (mov r8, r8) + 8004da8: bcf8 pop {r3, r4, r5, r6, r7} + 8004daa: bc08 pop {r3} + 8004dac: 469e mov lr, r3 + 8004dae: 4770 bx lr + +08004db0 <_fini>: + 8004db0: b5f8 push {r3, r4, r5, r6, r7, lr} + 8004db2: 46c0 nop @ (mov r8, r8) + 8004db4: bcf8 pop {r3, r4, r5, r6, r7} + 8004db6: bc08 pop {r3} + 8004db8: 469e mov lr, r3 + 8004dba: 4770 bx lr diff --git a/code/Debug/feeder_mk2.map b/code/Debug/feeder_mk2.map index 2c94120..8f1f9af 100644 --- a/code/Debug/feeder_mk2.map +++ b/code/Debug/feeder_mk2.map @@ -28,6 +28,8 @@ C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.external C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o (__libc_init_array) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-lock.o) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-findfp.o) (__retarget_lock_init_recursive) +C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memcpy-stub.o) + ./Core/Src/main.o (memcpy) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-freer.o) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-reent.o) (_free_r) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-mallocr.o) @@ -101,17 +103,44 @@ Discarded input sections .group 0x00000000 0xc ./Core/Src/main.o .group 0x00000000 0xc ./Core/Src/main.o .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o .text 0x00000000 0x0 ./Core/Src/main.o .data 0x00000000 0x0 ./Core/Src/main.o .bss 0x00000000 0x0 ./Core/Src/main.o - .bss.sw1_pressed + .bss.is_initialized 0x00000000 0x1 ./Core/Src/main.o - .bss.sw2_pressed + .bss.network_buffer_RX + 0x00000000 0x40 ./Core/Src/main.o + .data.my_address 0x00000000 0x1 ./Core/Src/main.o - .bss.encoder_count - 0x00000000 0x4 ./Core/Src/main.o .text.HAL_GPIO_EXTI_Callback 0x00000000 0x6c ./Core/Src/main.o + .text.set_LED 0x00000000 0x80 ./Core/Src/main.o + .text.handleRS485Message + 0x00000000 0x18 ./Core/Src/main.o + .text.set_Feeder_PWM + 0x00000000 0x4c ./Core/Src/main.o .group 0x00000000 0xc ./Core/Src/stm32c0xx_hal_msp.o .group 0x00000000 0xc ./Core/Src/stm32c0xx_hal_msp.o .group 0x00000000 0xc ./Core/Src/stm32c0xx_hal_msp.o @@ -158,11 +187,11 @@ Discarded input sections .data 0x00000000 0x0 ./Core/Src/stm32c0xx_hal_msp.o .bss 0x00000000 0x0 ./Core/Src/stm32c0xx_hal_msp.o .text.HAL_TIM_Base_MspDeInit - 0x00000000 0x80 ./Core/Src/stm32c0xx_hal_msp.o + 0x00000000 0xa4 ./Core/Src/stm32c0xx_hal_msp.o .text.HAL_TIM_Encoder_MspDeInit - 0x00000000 0x48 ./Core/Src/stm32c0xx_hal_msp.o + 0x00000000 0x3c ./Core/Src/stm32c0xx_hal_msp.o .text.HAL_UART_MspDeInit - 0x00000000 0x6c ./Core/Src/stm32c0xx_hal_msp.o + 0x00000000 0x84 ./Core/Src/stm32c0xx_hal_msp.o .debug_macro 0x00000000 0xaae ./Core/Src/stm32c0xx_hal_msp.o .debug_macro 0x00000000 0x2e ./Core/Src/stm32c0xx_hal_msp.o .debug_macro 0x00000000 0x28 ./Core/Src/stm32c0xx_hal_msp.o @@ -421,7 +450,7 @@ Discarded input sections .debug_macro 0x00000000 0x18a ./Core/Src/syscalls.o .debug_macro 0x00000000 0x16 ./Core/Src/syscalls.o .debug_macro 0x00000000 0xce ./Core/Src/syscalls.o - .debug_line 0x00000000 0x8ac ./Core/Src/syscalls.o + .debug_line 0x00000000 0x8b6 ./Core/Src/syscalls.o .debug_str 0x00000000 0x98c5 ./Core/Src/syscalls.o .comment 0x00000000 0x44 ./Core/Src/syscalls.o .debug_frame 0x00000000 0x244 ./Core/Src/syscalls.o @@ -486,7 +515,7 @@ Discarded input sections .debug_macro 0x00000000 0x103 ./Core/Src/sysmem.o .debug_macro 0x00000000 0x6a ./Core/Src/sysmem.o .debug_macro 0x00000000 0x1df ./Core/Src/sysmem.o - .debug_line 0x00000000 0x588 ./Core/Src/sysmem.o + .debug_line 0x00000000 0x592 ./Core/Src/sysmem.o .debug_str 0x00000000 0x7663 ./Core/Src/sysmem.o .comment 0x00000000 0x44 ./Core/Src/sysmem.o .debug_frame 0x00000000 0x30 ./Core/Src/sysmem.o @@ -654,12 +683,6 @@ Discarded input sections 0x00000000 0x18 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o .text.HAL_GetDEVID 0x00000000 0x18 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o - .text.HAL_GetUIDw0 - 0x00000000 0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o - .text.HAL_GetUIDw1 - 0x00000000 0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o - .text.HAL_GetUIDw2 - 0x00000000 0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o .text.HAL_DBGMCU_EnableDBGStopMode 0x00000000 0x1c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o .text.HAL_DBGMCU_DisableDBGStopMode @@ -890,8 +913,6 @@ Discarded input sections 0x00000000 0xf0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o .text.HAL_DMA_Start 0x00000000 0x9a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o - .text.HAL_DMA_Start_IT - 0x00000000 0x10e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o .text.HAL_DMA_Abort 0x00000000 0xc4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o .text.HAL_DMA_Abort_IT @@ -908,8 +929,6 @@ Discarded input sections 0x00000000 0x18 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o .text.HAL_DMA_GetError 0x00000000 0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o - .text.DMA_SetConfig - 0x00000000 0x80 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o .debug_macro 0x00000000 0xaae ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o .debug_macro 0x00000000 0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o .debug_macro 0x00000000 0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o @@ -1053,7 +1072,7 @@ Discarded input sections .debug_macro 0x00000000 0x67e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o .debug_macro 0x00000000 0xa6 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o .debug_macro 0x00000000 0x42c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o - .debug_line 0x00000000 0x8f8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o + .debug_line 0x00000000 0x900 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o .debug_str 0x00000000 0x7c927 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o .comment 0x00000000 0x44 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o .debug_frame 0x00000000 0xb0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o @@ -1169,7 +1188,7 @@ Discarded input sections .debug_macro 0x00000000 0x67e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o .debug_macro 0x00000000 0xa6 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o .debug_macro 0x00000000 0x42c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o - .debug_line 0x00000000 0xb35 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o + .debug_line 0x00000000 0xb3d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o .debug_str 0x00000000 0x7c767 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o .comment 0x00000000 0x44 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o .debug_frame 0x00000000 0x130 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o @@ -1295,7 +1314,7 @@ Discarded input sections .debug_macro 0x00000000 0x67e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o .debug_macro 0x00000000 0xa6 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o .debug_macro 0x00000000 0x42c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o - .debug_line 0x00000000 0xace ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o + .debug_line 0x00000000 0xad6 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o .debug_str 0x00000000 0x7c7fe ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o .comment 0x00000000 0x44 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o .debug_frame 0x00000000 0x1d4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o @@ -1439,7 +1458,7 @@ Discarded input sections .debug_macro 0x00000000 0x67e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o .debug_macro 0x00000000 0xa6 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o .debug_macro 0x00000000 0x42c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o - .debug_line 0x00000000 0xc43 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o + .debug_line 0x00000000 0xc4b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o .debug_str 0x00000000 0x7c98e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o .comment 0x00000000 0x44 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o .debug_frame 0x00000000 0x2e8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o @@ -1491,8 +1510,6 @@ Discarded input sections .bss 0x00000000 0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o .text.HAL_GPIO_DeInit 0x00000000 0x1b0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o - .text.HAL_GPIO_ReadPin - 0x00000000 0x3a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o .text.HAL_GPIO_WriteMultipleStatePin 0x00000000 0x34 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o .text.HAL_GPIO_TogglePin @@ -1652,7 +1669,7 @@ Discarded input sections .debug_macro 0x00000000 0x67e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o .debug_macro 0x00000000 0xa6 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o .debug_macro 0x00000000 0x42c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o - .debug_line 0x00000000 0x87a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o + .debug_line 0x00000000 0x882 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o .debug_str 0x00000000 0x7c74c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o .comment 0x00000000 0x44 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o .debug_frame 0x00000000 0x138 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o @@ -1784,7 +1801,7 @@ Discarded input sections .debug_macro 0x00000000 0x67e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o .debug_macro 0x00000000 0xa6 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o .debug_macro 0x00000000 0x42c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o - .debug_line 0x00000000 0x937 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o + .debug_line 0x00000000 0x93f ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o .debug_str 0x00000000 0x7c78a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o .comment 0x00000000 0x44 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o .debug_frame 0x00000000 0x19c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o @@ -2542,12 +2559,6 @@ Discarded input sections 0x00000000 0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o .text.HAL_UART_TxHalfCpltCallback 0x00000000 0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o - .text.HAL_UART_RxCpltCallback - 0x00000000 0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o - .text.HAL_UART_RxHalfCpltCallback - 0x00000000 0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o - .text.HAL_UART_ErrorCallback - 0x00000000 0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o .text.HAL_UART_AbortCpltCallback 0x00000000 0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o .text.HAL_UART_AbortTransmitCpltCallback @@ -2580,20 +2591,10 @@ Discarded input sections 0x00000000 0x16 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o .text.UART_Start_Receive_IT 0x00000000 0x248 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o - .text.UART_Start_Receive_DMA - 0x00000000 0x14c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o - .text.UART_EndTxTransfer - 0x00000000 0x80 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o .text.UART_DMATransmitCplt 0x00000000 0x98 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o .text.UART_DMATxHalfCplt 0x00000000 0x1e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o - .text.UART_DMAReceiveCplt - 0x00000000 0x168 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o - .text.UART_DMARxHalfCplt - 0x00000000 0x7e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o - .text.UART_DMAError - 0x00000000 0x86 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o .text.UART_DMAAbortOnError 0x00000000 0x26 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o .text.UART_DMATxAbortCallback @@ -2727,8 +2728,6 @@ Discarded input sections 0x00000000 0x240 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o .text.HAL_UARTEx_ReceiveToIdle_IT 0x00000000 0xc8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o - .text.HAL_UARTEx_ReceiveToIdle_DMA - 0x00000000 0xd0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o .text.HAL_UARTEx_GetRxEventType 0x00000000 0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o .text.UARTEx_Wakeup_AddressConfig @@ -2938,6 +2937,9 @@ Discarded input sections .debug_frame 0x00000000 0xb0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-lock.o) .ARM.attributes 0x00000000 0x2c C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-lock.o) + .text 0x00000000 0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memcpy-stub.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memcpy-stub.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memcpy-stub.o) .text 0x00000000 0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-freer.o) .data 0x00000000 0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-freer.o) .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-freer.o) @@ -3070,7 +3072,7 @@ LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext 0x08000000 g_pfnVectors 0x080000c0 . = ALIGN (0x4) -.text 0x080000c0 0x3eec +.text 0x080000c0 0x4cfc 0x080000c0 . = ALIGN (0x4) *(.text) .text 0x080000c0 0x48 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o @@ -3086,437 +3088,556 @@ LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext 0x080003f0 __aeabi_idiv0 0x080003f0 __aeabi_ldiv0 *(.text*) - .text.main 0x080003f4 0x30 ./Core/Src/main.o - 0x080003f4 main + .text.clamp_i32 + 0x080003f4 0x2e ./Core/Src/main.o + .text.pid_init + 0x08000422 0x52 ./Core/Src/main.o + .text.pid_update_motor + 0x08000474 0x154 ./Core/Src/main.o + .text.main 0x080005c8 0x238 ./Core/Src/main.o + 0x080005c8 main .text.SystemClock_Config - 0x08000424 0x9c ./Core/Src/main.o - 0x08000424 SystemClock_Config + 0x08000800 0x9c ./Core/Src/main.o + 0x08000800 SystemClock_Config .text.MX_TIM1_Init - 0x080004c0 0x1d8 ./Core/Src/main.o + 0x0800089c 0x1d8 ./Core/Src/main.o .text.MX_TIM3_Init - 0x08000698 0xc8 ./Core/Src/main.o + 0x08000a74 0xc8 ./Core/Src/main.o + .text.MX_TIM14_Init + 0x08000b3c 0x48 ./Core/Src/main.o .text.MX_TIM16_Init - 0x08000760 0x54 ./Core/Src/main.o + 0x08000b84 0x54 ./Core/Src/main.o .text.MX_TIM17_Init - 0x080007b4 0x54 ./Core/Src/main.o + 0x08000bd8 0x54 ./Core/Src/main.o .text.MX_USART1_UART_Init - 0x08000808 0x9c ./Core/Src/main.o + 0x08000c2c 0x9c ./Core/Src/main.o .text.MX_USART2_UART_Init - 0x080008a4 0xa0 ./Core/Src/main.o + 0x08000cc8 0xa8 ./Core/Src/main.o .text.MX_DMA_Init - 0x08000944 0x3c ./Core/Src/main.o + 0x08000d70 0x4c ./Core/Src/main.o .text.MX_GPIO_Init - 0x08000980 0x124 ./Core/Src/main.o + 0x08000dbc 0x124 ./Core/Src/main.o .text.HAL_TIM_PeriodElapsedCallback - 0x08000aa4 0xe ./Core/Src/main.o - 0x08000aa4 HAL_TIM_PeriodElapsedCallback + 0x08000ee0 0x144 ./Core/Src/main.o + 0x08000ee0 HAL_TIM_PeriodElapsedCallback + .text.HAL_UARTEx_RxEventCallback + 0x08001024 0x84 ./Core/Src/main.o + 0x08001024 HAL_UARTEx_RxEventCallback .text.Error_Handler - 0x08000ab2 0xc ./Core/Src/main.o - 0x08000ab2 Error_Handler - *fill* 0x08000abe 0x2 + 0x080010a8 0xc ./Core/Src/main.o + 0x080010a8 Error_Handler .text.HAL_MspInit - 0x08000ac0 0x48 ./Core/Src/stm32c0xx_hal_msp.o - 0x08000ac0 HAL_MspInit + 0x080010b4 0x48 ./Core/Src/stm32c0xx_hal_msp.o + 0x080010b4 HAL_MspInit .text.HAL_TIM_Base_MspInit - 0x08000b08 0xb8 ./Core/Src/stm32c0xx_hal_msp.o - 0x08000b08 HAL_TIM_Base_MspInit + 0x080010fc 0xf4 ./Core/Src/stm32c0xx_hal_msp.o + 0x080010fc HAL_TIM_Base_MspInit .text.HAL_TIM_Encoder_MspInit - 0x08000bc0 0xf0 ./Core/Src/stm32c0xx_hal_msp.o - 0x08000bc0 HAL_TIM_Encoder_MspInit + 0x080011f0 0x94 ./Core/Src/stm32c0xx_hal_msp.o + 0x080011f0 HAL_TIM_Encoder_MspInit .text.HAL_TIM_MspPostInit - 0x08000cb0 0xa8 ./Core/Src/stm32c0xx_hal_msp.o - 0x08000cb0 HAL_TIM_MspPostInit + 0x08001284 0xa8 ./Core/Src/stm32c0xx_hal_msp.o + 0x08001284 HAL_TIM_MspPostInit .text.HAL_UART_MspInit - 0x08000d58 0x134 ./Core/Src/stm32c0xx_hal_msp.o - 0x08000d58 HAL_UART_MspInit + 0x0800132c 0x1f0 ./Core/Src/stm32c0xx_hal_msp.o + 0x0800132c HAL_UART_MspInit .text.NMI_Handler - 0x08000e8c 0x8 ./Core/Src/stm32c0xx_it.o - 0x08000e8c NMI_Handler + 0x0800151c 0x8 ./Core/Src/stm32c0xx_it.o + 0x0800151c NMI_Handler .text.HardFault_Handler - 0x08000e94 0x8 ./Core/Src/stm32c0xx_it.o - 0x08000e94 HardFault_Handler + 0x08001524 0x8 ./Core/Src/stm32c0xx_it.o + 0x08001524 HardFault_Handler .text.SVC_Handler - 0x08000e9c 0xa ./Core/Src/stm32c0xx_it.o - 0x08000e9c SVC_Handler + 0x0800152c 0xa ./Core/Src/stm32c0xx_it.o + 0x0800152c SVC_Handler .text.PendSV_Handler - 0x08000ea6 0xa ./Core/Src/stm32c0xx_it.o - 0x08000ea6 PendSV_Handler + 0x08001536 0xa ./Core/Src/stm32c0xx_it.o + 0x08001536 PendSV_Handler .text.SysTick_Handler - 0x08000eb0 0xe ./Core/Src/stm32c0xx_it.o - 0x08000eb0 SysTick_Handler + 0x08001540 0xe ./Core/Src/stm32c0xx_it.o + 0x08001540 SysTick_Handler .text.EXTI4_15_IRQHandler - 0x08000ebe 0x1e ./Core/Src/stm32c0xx_it.o - 0x08000ebe EXTI4_15_IRQHandler + 0x0800154e 0x1e ./Core/Src/stm32c0xx_it.o + 0x0800154e EXTI4_15_IRQHandler .text.DMA1_Channel1_IRQHandler - 0x08000edc 0x18 ./Core/Src/stm32c0xx_it.o - 0x08000edc DMA1_Channel1_IRQHandler + 0x0800156c 0x18 ./Core/Src/stm32c0xx_it.o + 0x0800156c DMA1_Channel1_IRQHandler + .text.DMA1_Channel2_3_IRQHandler + 0x08001584 0x18 ./Core/Src/stm32c0xx_it.o + 0x08001584 DMA1_Channel2_3_IRQHandler + .text.TIM14_IRQHandler + 0x0800159c 0x18 ./Core/Src/stm32c0xx_it.o + 0x0800159c TIM14_IRQHandler .text.TIM16_IRQHandler - 0x08000ef4 0x18 ./Core/Src/stm32c0xx_it.o - 0x08000ef4 TIM16_IRQHandler + 0x080015b4 0x18 ./Core/Src/stm32c0xx_it.o + 0x080015b4 TIM16_IRQHandler .text.TIM17_IRQHandler - 0x08000f0c 0x18 ./Core/Src/stm32c0xx_it.o - 0x08000f0c TIM17_IRQHandler + 0x080015cc 0x18 ./Core/Src/stm32c0xx_it.o + 0x080015cc TIM17_IRQHandler .text.SystemInit - 0x08000f24 0x18 ./Core/Src/system_stm32c0xx.o - 0x08000f24 SystemInit + 0x080015e4 0x18 ./Core/Src/system_stm32c0xx.o + 0x080015e4 SystemInit .text.Reset_Handler - 0x08000f3c 0x50 ./Core/Startup/startup_stm32c051c6tx.o - 0x08000f3c Reset_Handler + 0x080015fc 0x50 ./Core/Startup/startup_stm32c051c6tx.o + 0x080015fc Reset_Handler .text.Default_Handler - 0x08000f8c 0x2 ./Core/Startup/startup_stm32c051c6tx.o - 0x08000f8c TIM1_CC_IRQHandler - 0x08000f8c I2C1_IRQHandler - 0x08000f8c SPI1_IRQHandler - 0x08000f8c EXTI2_3_IRQHandler - 0x08000f8c ADC1_IRQHandler - 0x08000f8c I2C2_IRQHandler - 0x08000f8c RTC_IRQHandler - 0x08000f8c TIM3_IRQHandler - 0x08000f8c RCC_IRQHandler - 0x08000f8c Default_Handler - 0x08000f8c TIM14_IRQHandler - 0x08000f8c EXTI0_1_IRQHandler - 0x08000f8c SPI2_IRQHandler - 0x08000f8c WWDG_IRQHandler - 0x08000f8c TIM2_IRQHandler - 0x08000f8c DMA1_Channel2_3_IRQHandler - 0x08000f8c DMAMUX1_DMA1_CH4_5_IRQHandler - 0x08000f8c USART2_IRQHandler - 0x08000f8c FLASH_IRQHandler - 0x08000f8c USART1_IRQHandler - 0x08000f8c TIM1_BRK_UP_TRG_COM_IRQHandler + 0x0800164c 0x2 ./Core/Startup/startup_stm32c051c6tx.o + 0x0800164c TIM1_CC_IRQHandler + 0x0800164c I2C1_IRQHandler + 0x0800164c SPI1_IRQHandler + 0x0800164c EXTI2_3_IRQHandler + 0x0800164c ADC1_IRQHandler + 0x0800164c I2C2_IRQHandler + 0x0800164c RTC_IRQHandler + 0x0800164c TIM3_IRQHandler + 0x0800164c RCC_IRQHandler + 0x0800164c Default_Handler + 0x0800164c EXTI0_1_IRQHandler + 0x0800164c SPI2_IRQHandler + 0x0800164c WWDG_IRQHandler + 0x0800164c TIM2_IRQHandler + 0x0800164c DMAMUX1_DMA1_CH4_5_IRQHandler + 0x0800164c USART2_IRQHandler + 0x0800164c FLASH_IRQHandler + 0x0800164c USART1_IRQHandler + 0x0800164c TIM1_BRK_UP_TRG_COM_IRQHandler .text.HAL_Init - 0x08000f8e 0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o - 0x08000f8e HAL_Init + 0x0800164e 0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o + 0x0800164e HAL_Init .text.HAL_InitTick - 0x08000fbc 0x94 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o - 0x08000fbc HAL_InitTick + 0x0800167c 0x94 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o + 0x0800167c HAL_InitTick .text.HAL_IncTick - 0x08001050 0x24 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o - 0x08001050 HAL_IncTick + 0x08001710 0x24 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o + 0x08001710 HAL_IncTick .text.HAL_GetTick - 0x08001074 0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o - 0x08001074 HAL_GetTick + 0x08001734 0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o + 0x08001734 HAL_GetTick + .text.HAL_GetUIDw0 + 0x08001748 0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o + 0x08001748 HAL_GetUIDw0 + .text.HAL_GetUIDw1 + 0x0800175c 0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o + 0x0800175c HAL_GetUIDw1 + .text.HAL_GetUIDw2 + 0x08001770 0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o + 0x08001770 HAL_GetUIDw2 .text.__NVIC_EnableIRQ - 0x08001088 0x34 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o + 0x08001784 0x34 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o .text.__NVIC_SetPriority - 0x080010bc 0xdc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o + 0x080017b8 0xdc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o .text.SysTick_Config - 0x08001198 0x48 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o + 0x08001894 0x48 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o .text.HAL_NVIC_SetPriority - 0x080011e0 0x2a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o - 0x080011e0 HAL_NVIC_SetPriority + 0x080018dc 0x2a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o + 0x080018dc HAL_NVIC_SetPriority .text.HAL_NVIC_EnableIRQ - 0x0800120a 0x20 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o - 0x0800120a HAL_NVIC_EnableIRQ + 0x08001906 0x20 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o + 0x08001906 HAL_NVIC_EnableIRQ .text.HAL_SYSTICK_Config - 0x0800122a 0x1a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o - 0x0800122a HAL_SYSTICK_Config + 0x08001926 0x1a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o + 0x08001926 HAL_SYSTICK_Config .text.HAL_DMA_Init - 0x08001244 0x114 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o - 0x08001244 HAL_DMA_Init + 0x08001940 0x114 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o + 0x08001940 HAL_DMA_Init + .text.HAL_DMA_Start_IT + 0x08001a54 0x10e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o + 0x08001a54 HAL_DMA_Start_IT + *fill* 0x08001b62 0x2 .text.HAL_DMA_IRQHandler - 0x08001358 0x164 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o - 0x08001358 HAL_DMA_IRQHandler + 0x08001b64 0x164 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o + 0x08001b64 HAL_DMA_IRQHandler + .text.DMA_SetConfig + 0x08001cc8 0x80 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o .text.DMA_CalcDMAMUXChannelBaseAndMask - 0x080014bc 0x58 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o + 0x08001d48 0x58 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o .text.DMA_CalcDMAMUXRequestGenBaseAndMask - 0x08001514 0x48 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o + 0x08001da0 0x48 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o .text.HAL_GPIO_Init - 0x0800155c 0x2e4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o - 0x0800155c HAL_GPIO_Init + 0x08001de8 0x2e4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o + 0x08001de8 HAL_GPIO_Init + .text.HAL_GPIO_ReadPin + 0x080020cc 0x3a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o + 0x080020cc HAL_GPIO_ReadPin .text.HAL_GPIO_WritePin - 0x08001840 0x3a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o - 0x08001840 HAL_GPIO_WritePin - *fill* 0x0800187a 0x2 + 0x08002106 0x3a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o + 0x08002106 HAL_GPIO_WritePin .text.HAL_GPIO_EXTI_IRQHandler - 0x0800187c 0x54 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o - 0x0800187c HAL_GPIO_EXTI_IRQHandler + 0x08002140 0x54 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o + 0x08002140 HAL_GPIO_EXTI_IRQHandler .text.HAL_GPIO_EXTI_Rising_Callback - 0x080018d0 0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o - 0x080018d0 HAL_GPIO_EXTI_Rising_Callback + 0x08002194 0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o + 0x08002194 HAL_GPIO_EXTI_Rising_Callback .text.HAL_GPIO_EXTI_Falling_Callback - 0x080018e4 0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o - 0x080018e4 HAL_GPIO_EXTI_Falling_Callback + 0x080021a8 0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o + 0x080021a8 HAL_GPIO_EXTI_Falling_Callback .text.HAL_RCC_OscConfig - 0x080018f8 0x3c8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o - 0x080018f8 HAL_RCC_OscConfig + 0x080021bc 0x3c8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o + 0x080021bc HAL_RCC_OscConfig .text.HAL_RCC_ClockConfig - 0x08001cc0 0x214 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o - 0x08001cc0 HAL_RCC_ClockConfig + 0x08002584 0x214 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o + 0x08002584 HAL_RCC_ClockConfig .text.HAL_RCC_GetSysClockFreq - 0x08001ed4 0xa0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o - 0x08001ed4 HAL_RCC_GetSysClockFreq + 0x08002798 0xa0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o + 0x08002798 HAL_RCC_GetSysClockFreq .text.HAL_RCC_GetHCLKFreq - 0x08001f74 0x3c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o - 0x08001f74 HAL_RCC_GetHCLKFreq + 0x08002838 0x3c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o + 0x08002838 HAL_RCC_GetHCLKFreq .text.HAL_RCC_GetPCLK1Freq - 0x08001fb0 0x30 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o - 0x08001fb0 HAL_RCC_GetPCLK1Freq + 0x08002874 0x30 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o + 0x08002874 HAL_RCC_GetPCLK1Freq .text.HAL_RCCEx_PeriphCLKConfig - 0x08001fe0 0x1d8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o - 0x08001fe0 HAL_RCCEx_PeriphCLKConfig + 0x080028a4 0x1d8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o + 0x080028a4 HAL_RCCEx_PeriphCLKConfig .text.HAL_TIM_Base_Init - 0x080021b8 0xb0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o - 0x080021b8 HAL_TIM_Base_Init + 0x08002a7c 0xb0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x08002a7c HAL_TIM_Base_Init .text.HAL_TIM_PWM_Init - 0x08002268 0xb0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o - 0x08002268 HAL_TIM_PWM_Init + 0x08002b2c 0xb0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x08002b2c HAL_TIM_PWM_Init .text.HAL_TIM_PWM_MspInit - 0x08002318 0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o - 0x08002318 HAL_TIM_PWM_MspInit + 0x08002bdc 0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x08002bdc HAL_TIM_PWM_MspInit .text.HAL_TIM_Encoder_Init - 0x08002328 0x150 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o - 0x08002328 HAL_TIM_Encoder_Init + 0x08002bec 0x150 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x08002bec HAL_TIM_Encoder_Init .text.HAL_TIM_IRQHandler - 0x08002478 0x210 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o - 0x08002478 HAL_TIM_IRQHandler + 0x08002d3c 0x210 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x08002d3c HAL_TIM_IRQHandler .text.HAL_TIM_PWM_ConfigChannel - 0x08002688 0x200 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o - 0x08002688 HAL_TIM_PWM_ConfigChannel + 0x08002f4c 0x200 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x08002f4c HAL_TIM_PWM_ConfigChannel .text.HAL_TIM_ConfigClockSource - 0x08002888 0x1ac ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o - 0x08002888 HAL_TIM_ConfigClockSource + 0x0800314c 0x1ac ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x0800314c HAL_TIM_ConfigClockSource .text.HAL_TIM_OC_DelayElapsedCallback - 0x08002a34 0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o - 0x08002a34 HAL_TIM_OC_DelayElapsedCallback + 0x080032f8 0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x080032f8 HAL_TIM_OC_DelayElapsedCallback .text.HAL_TIM_IC_CaptureCallback - 0x08002a44 0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o - 0x08002a44 HAL_TIM_IC_CaptureCallback + 0x08003308 0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x08003308 HAL_TIM_IC_CaptureCallback .text.HAL_TIM_PWM_PulseFinishedCallback - 0x08002a54 0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o - 0x08002a54 HAL_TIM_PWM_PulseFinishedCallback + 0x08003318 0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x08003318 HAL_TIM_PWM_PulseFinishedCallback .text.HAL_TIM_TriggerCallback - 0x08002a64 0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o - 0x08002a64 HAL_TIM_TriggerCallback + 0x08003328 0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x08003328 HAL_TIM_TriggerCallback .text.TIM_Base_SetConfig - 0x08002a74 0xf8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o - 0x08002a74 TIM_Base_SetConfig + 0x08003338 0xf8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x08003338 TIM_Base_SetConfig .text.TIM_OC1_SetConfig - 0x08002b6c 0x100 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x08003430 0x100 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o .text.TIM_OC2_SetConfig - 0x08002c6c 0xfc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o - 0x08002c6c TIM_OC2_SetConfig + 0x08003530 0xfc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x08003530 TIM_OC2_SetConfig .text.TIM_OC3_SetConfig - 0x08002d68 0x104 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x0800362c 0x104 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o .text.TIM_OC4_SetConfig - 0x08002e6c 0xc8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x08003730 0xc8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o .text.TIM_OC5_SetConfig - 0x08002f34 0xb4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + 0x080037f8 0xb4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o .text.TIM_OC6_SetConfig - 0x08002fe8 0xbc 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.gnu.linkonce.armextab.*) - 0x08004088 . = ALIGN (0x4) + 0x08004e98 . = ALIGN (0x4) -.ARM 0x08004088 0x0 - 0x08004088 . = ALIGN (0x4) - 0x08004088 __exidx_start = . +.ARM 0x08004e98 0x0 + 0x08004e98 . = ALIGN (0x4) + 0x08004e98 __exidx_start = . *(.ARM.exidx*) - 0x08004088 __exidx_end = . - 0x08004088 . = ALIGN (0x4) + 0x08004e98 __exidx_end = . + 0x08004e98 . = ALIGN (0x4) -.preinit_array 0x08004088 0x0 - 0x08004088 . = ALIGN (0x4) - 0x08004088 PROVIDE (__preinit_array_start = .) +.preinit_array 0x08004e98 0x0 + 0x08004e98 . = ALIGN (0x4) + 0x08004e98 PROVIDE (__preinit_array_start = .) *(.preinit_array*) - 0x08004088 PROVIDE (__preinit_array_end = .) - 0x08004088 . = ALIGN (0x4) + 0x08004e98 PROVIDE (__preinit_array_end = .) + 0x08004e98 . = ALIGN (0x4) -.init_array 0x08004088 0x4 - 0x08004088 . = ALIGN (0x4) - 0x08004088 PROVIDE (__init_array_start = .) +.init_array 0x08004e98 0x4 + 0x08004e98 . = ALIGN (0x4) + 0x08004e98 PROVIDE (__init_array_start = .) *(SORT_BY_NAME(.init_array.*)) *(.init_array*) - .init_array 0x08004088 0x4 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o - 0x0800408c PROVIDE (__init_array_end = .) - 0x0800408c . = ALIGN (0x4) + .init_array 0x08004e98 0x4 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o + 0x08004e9c PROVIDE (__init_array_end = .) + 0x08004e9c . = ALIGN (0x4) -.fini_array 0x0800408c 0x4 - 0x0800408c . = ALIGN (0x4) +.fini_array 0x08004e9c 0x4 + 0x08004e9c . = ALIGN (0x4) [!provide] PROVIDE (__fini_array_start = .) *(SORT_BY_NAME(.fini_array.*)) *(.fini_array*) - .fini_array 0x0800408c 0x4 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o + .fini_array 0x08004e9c 0x4 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o [!provide] PROVIDE (__fini_array_end = .) - 0x08004090 . = ALIGN (0x4) - 0x08004090 _sidata = LOADADDR (.data) + 0x08004ea0 . = ALIGN (0x4) + 0x08004ea0 _sidata = LOADADDR (.data) -.rel.dyn 0x08004090 0x0 - .rel.iplt 0x08004090 0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o +.rel.dyn 0x08004ea0 0x0 + .rel.iplt 0x08004ea0 0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o -.data 0x20000000 0xc load address 0x08004090 +.data 0x20000000 0x24 load address 0x08004ea0 0x20000000 . = ALIGN (0x4) 0x20000000 _sdata = . *(.data) *(.data*) + .data.msg_buffer1_empty + 0x20000000 0x1 ./Core/Src/main.o + 0x20000000 msg_buffer1_empty + .data.msg_buffer2_empty + 0x20000001 0x1 ./Core/Src/main.o + 0x20000001 msg_buffer2_empty + *fill* 0x20000002 0x2 + .data.kp 0x20000004 0x4 ./Core/Src/main.o + 0x20000004 kp + .data.ki 0x20000008 0x4 ./Core/Src/main.o + 0x20000008 ki + .data.i_min 0x2000000c 0x4 ./Core/Src/main.o + 0x2000000c i_min + .data.i_max 0x20000010 0x4 ./Core/Src/main.o + 0x20000010 i_max + .data.pid_max_step + 0x20000014 0x4 ./Core/Src/main.o + 0x20000014 pid_max_step .data.SystemCoreClock - 0x20000000 0x4 ./Core/Src/system_stm32c0xx.o - 0x20000000 SystemCoreClock + 0x20000018 0x4 ./Core/Src/system_stm32c0xx.o + 0x20000018 SystemCoreClock .data.uwTickPrio - 0x20000004 0x4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o - 0x20000004 uwTickPrio + 0x2000001c 0x4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o + 0x2000001c uwTickPrio .data.uwTickFreq - 0x20000008 0x1 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o - 0x20000008 uwTickFreq + 0x20000020 0x1 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o + 0x20000020 uwTickFreq *(.RamFunc) *(.RamFunc*) - 0x2000000c . = ALIGN (0x4) - *fill* 0x20000009 0x3 - 0x2000000c _edata = . + 0x20000024 . = ALIGN (0x4) + *fill* 0x20000021 0x3 + 0x20000024 _edata = . -.igot.plt 0x2000000c 0x0 load address 0x0800409c - .igot.plt 0x2000000c 0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o - 0x2000000c . = ALIGN (0x4) +.igot.plt 0x20000024 0x0 load address 0x08004ec4 + .igot.plt 0x20000024 0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o + 0x20000024 . = ALIGN (0x4) -.bss 0x2000000c 0x2d4 load address 0x0800409c - 0x2000000c _sbss = . - 0x2000000c __bss_start__ = _sbss +.bss 0x20000024 0x48c load address 0x08004ec4 + 0x20000024 _sbss = . + 0x20000024 __bss_start__ = _sbss *(.bss) - .bss 0x2000000c 0x1c C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o + .bss 0x20000024 0x1c C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o *(.bss*) - .bss.htim1 0x20000028 0x4c ./Core/Src/main.o - 0x20000028 htim1 - .bss.htim3 0x20000074 0x4c ./Core/Src/main.o - 0x20000074 htim3 - .bss.htim16 0x200000c0 0x4c ./Core/Src/main.o - 0x200000c0 htim16 - .bss.htim17 0x2000010c 0x4c ./Core/Src/main.o - 0x2000010c htim17 - .bss.hdma_tim3_up - 0x20000158 0x5c ./Core/Src/main.o - 0x20000158 hdma_tim3_up - .bss.huart1 0x200001b4 0x94 ./Core/Src/main.o - 0x200001b4 huart1 - .bss.huart2 0x20000248 0x94 ./Core/Src/main.o - 0x20000248 huart2 - .bss.uwTick 0x200002dc 0x4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o - 0x200002dc uwTick + .bss.htim1 0x20000040 0x4c ./Core/Src/main.o + 0x20000040 htim1 + .bss.htim3 0x2000008c 0x4c ./Core/Src/main.o + 0x2000008c htim3 + .bss.htim14 0x200000d8 0x4c ./Core/Src/main.o + 0x200000d8 htim14 + .bss.htim16 0x20000124 0x4c ./Core/Src/main.o + 0x20000124 htim16 + .bss.htim17 0x20000170 0x4c ./Core/Src/main.o + 0x20000170 htim17 + .bss.huart1 0x200001bc 0x94 ./Core/Src/main.o + 0x200001bc huart1 + .bss.huart2 0x20000250 0x94 ./Core/Src/main.o + 0x20000250 huart2 + .bss.hdma_usart2_rx + 0x200002e4 0x5c ./Core/Src/main.o + 0x200002e4 hdma_usart2_rx + .bss.hdma_usart2_tx + 0x20000340 0x5c ./Core/Src/main.o + 0x20000340 hdma_usart2_tx + .bss.sw1_pressed + 0x2000039c 0x1 ./Core/Src/main.o + 0x2000039c sw1_pressed + .bss.sw2_pressed + 0x2000039d 0x1 ./Core/Src/main.o + 0x2000039d sw2_pressed + *fill* 0x2000039e 0x2 + .bss.encoder_count_extra + 0x200003a0 0x4 ./Core/Src/main.o + 0x200003a0 encoder_count_extra + .bss.encoder_previous + 0x200003a4 0x2 ./Core/Src/main.o + 0x200003a4 encoder_previous + *fill* 0x200003a6 0x2 + .bss.UUID 0x200003a8 0xc ./Core/Src/main.o + 0x200003a8 UUID + .bss.msg_buffer1 + 0x200003b4 0x40 ./Core/Src/main.o + 0x200003b4 msg_buffer1 + .bss.msg_buffer2 + 0x200003f4 0x40 ./Core/Src/main.o + 0x200003f4 msg_buffer2 + .bss.DMA_buffer + 0x20000434 0x40 ./Core/Src/main.o + 0x20000434 DMA_buffer + .bss.total_count + 0x20000474 0x4 ./Core/Src/main.o + 0x20000474 total_count + .bss.target_count + 0x20000478 0x4 ./Core/Src/main.o + 0x20000478 target_count + .bss.kd 0x2000047c 0x4 ./Core/Src/main.o + 0x2000047c kd + .bss.motor_pid + 0x20000480 0x28 ./Core/Src/main.o + 0x20000480 motor_pid + .bss.motor_cmd + 0x200004a8 0x4 ./Core/Src/main.o + 0x200004a8 motor_cmd + .bss.uwTick 0x200004ac 0x4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o + 0x200004ac uwTick *(COMMON) - 0x200002e0 . = ALIGN (0x4) - 0x200002e0 _ebss = . - 0x200002e0 __bss_end__ = _ebss + 0x200004b0 . = ALIGN (0x4) + 0x200004b0 _ebss = . + 0x200004b0 __bss_end__ = _ebss ._user_heap_stack - 0x200002e0 0x600 load address 0x0800409c - 0x200002e0 . = ALIGN (0x8) + 0x200004b0 0x600 load address 0x08004ec4 + 0x200004b0 . = ALIGN (0x8) [!provide] PROVIDE (end = .) - 0x200002e0 PROVIDE (_end = .) - 0x200004e0 . = (. + _Min_Heap_Size) - *fill* 0x200002e0 0x200 - 0x200008e0 . = (. + _Min_Stack_Size) - *fill* 0x200004e0 0x400 - 0x200008e0 . = ALIGN (0x8) + 0x200004b0 PROVIDE (_end = .) + 0x200006b0 . = (. + _Min_Heap_Size) + *fill* 0x200004b0 0x200 + 0x20000ab0 . = (. + _Min_Stack_Size) + *fill* 0x200006b0 0x400 + 0x20000ab0 . = ALIGN (0x8) /DISCARD/ libc.a(*) @@ -3565,274 +3686,299 @@ LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext .ARM.attributes 0x00000300 0x2c C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-init.o) .ARM.attributes - 0x0000032c 0x1e C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a(_udivsi3.o) + 0x0000032c 0x2c C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memcpy-stub.o) .ARM.attributes - 0x0000034a 0x1e C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a(_divsi3.o) + 0x00000358 0x1e C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a(_udivsi3.o) .ARM.attributes - 0x00000368 0x1e C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a(_dvmd_tls.o) + 0x00000376 0x1e C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a(_divsi3.o) .ARM.attributes - 0x00000386 0x1e C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtn.o + 0x00000394 0x1e C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a(_dvmd_tls.o) + .ARM.attributes + 0x000003b2 0x1e C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtn.o OUTPUT(feeder_mk2.elf elf32-littlearm) LOAD linker stubs LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc.a LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libm.a LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a -.debug_info 0x00000000 0xfde5 - .debug_info 0x00000000 0x17b0 ./Core/Src/main.o - .debug_info 0x000017b0 0x11f1 ./Core/Src/stm32c0xx_hal_msp.o - .debug_info 0x000029a1 0x815 ./Core/Src/stm32c0xx_it.o - .debug_info 0x000031b6 0x36f ./Core/Src/system_stm32c0xx.o - .debug_info 0x00003525 0x30 ./Core/Startup/startup_stm32c051c6tx.o - .debug_info 0x00003555 0x844 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o - .debug_info 0x00003d99 0x88d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o - .debug_info 0x00004626 0x830 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o - .debug_info 0x00004e56 0x5b7 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o - .debug_info 0x0000540d 0x915 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o - .debug_info 0x00005d22 0x551 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o - .debug_info 0x00006273 0x2b65 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o - .debug_info 0x00008dd8 0x1878 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o - .debug_info 0x0000a650 0x4828 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o - .debug_info 0x0000ee78 0xf6d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o +.debug_info 0x00000000 0x104fc + .debug_info 0x00000000 0x1e6f ./Core/Src/main.o + .debug_info 0x00001e6f 0x1215 ./Core/Src/stm32c0xx_hal_msp.o + .debug_info 0x00003084 0x849 ./Core/Src/stm32c0xx_it.o + .debug_info 0x000038cd 0x36f ./Core/Src/system_stm32c0xx.o + .debug_info 0x00003c3c 0x30 ./Core/Startup/startup_stm32c051c6tx.o + .debug_info 0x00003c6c 0x844 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o + .debug_info 0x000044b0 0x88d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o + .debug_info 0x00004d3d 0x830 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o + .debug_info 0x0000556d 0x5b7 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o + .debug_info 0x00005b24 0x915 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o + 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./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o + .comment 0x00000043 0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o 0x44 (size before relaxing) - .comment 0x00000086 0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o + .comment 0x00000043 0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o 0x44 (size before relaxing) - .comment 0x00000086 0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o + .comment 0x00000043 0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o 0x44 (size before relaxing) - .comment 0x00000086 0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + .comment 0x00000043 0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o 0x44 (size before relaxing) - .comment 0x00000086 0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o + .comment 0x00000043 0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o 0x44 (size before relaxing) - .comment 0x00000086 0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o + .comment 0x00000043 0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o 0x44 (size before relaxing) - .comment 0x00000086 0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o + .comment 0x00000043 0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o 0x44 (size before relaxing) -.debug_frame 0x00000000 0x31bc - .debug_frame 0x00000000 0x198 ./Core/Src/main.o - .debug_frame 0x00000198 0x110 ./Core/Src/stm32c0xx_hal_msp.o - .debug_frame 0x000002a8 0x10c ./Core/Src/stm32c0xx_it.o - .debug_frame 0x000003b4 0x4c ./Core/Src/system_stm32c0xx.o - .debug_frame 0x00000400 0x368 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o - .debug_frame 0x00000768 0x33c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o - .debug_frame 0x00000aa4 0x1f0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o - .debug_frame 0x00000c94 0x150 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o - .debug_frame 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C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-init.o) - .debug_frame 0x0000317c 0x20 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a(_udivsi3.o) - .debug_frame 0x0000319c 0x20 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a(_divsi3.o) +.debug_frame 0x00000000 0x3320 + .debug_frame 0x00000000 0x29c ./Core/Src/main.o + .debug_frame 0x0000029c 0x110 ./Core/Src/stm32c0xx_hal_msp.o + .debug_frame 0x000003ac 0x144 ./Core/Src/stm32c0xx_it.o + .debug_frame 0x000004f0 0x4c ./Core/Src/system_stm32c0xx.o + .debug_frame 0x0000053c 0x368 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o + .debug_frame 0x000008a4 0x33c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o + .debug_frame 0x00000be0 0x1f0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o + .debug_frame 0x00000dd0 0x150 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o + .debug_frame 0x00000f20 0x214 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o + .debug_frame 0x00001134 0xac ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o + .debug_frame 0x000011e0 0xf40 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o + .debug_frame 0x00002120 0x620 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o + .debug_frame 0x00002740 0x8d4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o + .debug_frame 0x00003014 0x258 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o + .debug_frame 0x0000326c 0x20 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memset.o) + .debug_frame 0x0000328c 0x2c C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-init.o) + .debug_frame 0x000032b8 0x28 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memcpy-stub.o) + .debug_frame 0x000032e0 0x20 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a(_udivsi3.o) + .debug_frame 0x00003300 0x20 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a(_divsi3.o) .debug_line_str 0x00000000 0x4d diff --git a/code/feeder_mk2.ioc b/code/feeder_mk2.ioc index 16a81e1..ed15e1c 100644 --- a/code/feeder_mk2.ioc +++ b/code/feeder_mk2.ioc @@ -2,25 +2,43 @@ CAD.formats=[] CAD.pinconfig=Dual CAD.provider= -Dma.Request0=TIM3_UP -Dma.RequestsNb=1 -Dma.TIM3_UP.0.Direction=DMA_PERIPH_TO_MEMORY -Dma.TIM3_UP.0.EventEnable=DISABLE -Dma.TIM3_UP.0.Instance=DMA1_Channel1 -Dma.TIM3_UP.0.MemDataAlignment=DMA_MDATAALIGN_HALFWORD -Dma.TIM3_UP.0.MemInc=DMA_MINC_ENABLE -Dma.TIM3_UP.0.Mode=DMA_NORMAL -Dma.TIM3_UP.0.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD -Dma.TIM3_UP.0.PeriphInc=DMA_PINC_DISABLE -Dma.TIM3_UP.0.Polarity=HAL_DMAMUX_REQ_GEN_RISING -Dma.TIM3_UP.0.Priority=DMA_PRIORITY_LOW -Dma.TIM3_UP.0.RequestNumber=1 -Dma.TIM3_UP.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber -Dma.TIM3_UP.0.SignalID=NONE -Dma.TIM3_UP.0.SyncEnable=DISABLE -Dma.TIM3_UP.0.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT -Dma.TIM3_UP.0.SyncRequestNumber=1 -Dma.TIM3_UP.0.SyncSignalID=NONE +Dma.Request0=USART2_RX +Dma.Request1=USART2_TX +Dma.RequestsNb=2 +Dma.USART2_RX.0.Direction=DMA_PERIPH_TO_MEMORY +Dma.USART2_RX.0.EventEnable=DISABLE +Dma.USART2_RX.0.Instance=DMA1_Channel2 +Dma.USART2_RX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE +Dma.USART2_RX.0.MemInc=DMA_MINC_ENABLE +Dma.USART2_RX.0.Mode=DMA_NORMAL +Dma.USART2_RX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE +Dma.USART2_RX.0.PeriphInc=DMA_PINC_DISABLE +Dma.USART2_RX.0.Polarity=HAL_DMAMUX_REQ_GEN_RISING +Dma.USART2_RX.0.Priority=DMA_PRIORITY_MEDIUM +Dma.USART2_RX.0.RequestNumber=1 +Dma.USART2_RX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber +Dma.USART2_RX.0.SignalID=NONE +Dma.USART2_RX.0.SyncEnable=DISABLE +Dma.USART2_RX.0.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT +Dma.USART2_RX.0.SyncRequestNumber=1 +Dma.USART2_RX.0.SyncSignalID=NONE +Dma.USART2_TX.1.Direction=DMA_MEMORY_TO_PERIPH +Dma.USART2_TX.1.EventEnable=DISABLE +Dma.USART2_TX.1.Instance=DMA1_Channel1 +Dma.USART2_TX.1.MemDataAlignment=DMA_MDATAALIGN_BYTE +Dma.USART2_TX.1.MemInc=DMA_MINC_ENABLE +Dma.USART2_TX.1.Mode=DMA_NORMAL +Dma.USART2_TX.1.PeriphDataAlignment=DMA_PDATAALIGN_BYTE +Dma.USART2_TX.1.PeriphInc=DMA_PINC_DISABLE +Dma.USART2_TX.1.Polarity=HAL_DMAMUX_REQ_GEN_RISING +Dma.USART2_TX.1.Priority=DMA_PRIORITY_HIGH +Dma.USART2_TX.1.RequestNumber=1 +Dma.USART2_TX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber +Dma.USART2_TX.1.SignalID=NONE +Dma.USART2_TX.1.SyncEnable=DISABLE +Dma.USART2_TX.1.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT +Dma.USART2_TX.1.SyncRequestNumber=1 +Dma.USART2_TX.1.SyncSignalID=NONE File.Version=6 GPIO.groupedBy=Group By Peripherals KeepUserPlacement=false @@ -77,6 +95,7 @@ Mcu.UserName=STM32C051C6Tx MxCube.Version=6.15.0 MxDb.Version=DB.6.0.150 NVIC.DMA1_Channel1_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true +NVIC.DMA1_Channel2_3_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true NVIC.EXTI4_15_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true NVIC.ForceEnableDMAVector=true NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false @@ -199,7 +218,7 @@ ProjectManager.ToolChainLocation= ProjectManager.UAScriptAfterPath= ProjectManager.UAScriptBeforePath= ProjectManager.UnderRoot=true -ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_TIM1_Init-TIM1-false-HAL-true,5-MX_TIM3_Init-TIM3-false-HAL-true,6-MX_USART1_UART_Init-USART1-false-HAL-true,7-MX_USART2_UART_Init-USART2-false-HAL-true,8-MX_TIM16_Init-TIM16-false-HAL-true,9-MX_TIM17_Init-TIM17-false-HAL-true,0-MX_CORTEX_M0+_Init-CORTEX_M0+-false-HAL-true +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_TIM1_Init-TIM1-false-HAL-true,5-MX_TIM3_Init-TIM3-false-HAL-true,6-MX_USART1_UART_Init-USART1-false-HAL-true,7-MX_USART2_UART_Init-USART2-false-HAL-true,8-MX_TIM16_Init-TIM16-false-HAL-true,9-MX_TIM17_Init-TIM17-false-HAL-true,10-MX_TIM14_Init-TIM14-false-HAL-true,0-MX_CORTEX_M0+_Init-CORTEX_M0+-false-HAL-true RCC.ADCFreq_Value=48000000 RCC.AHBFreq_Value=48000000 RCC.APBFreq_Value=48000000 @@ -256,7 +275,10 @@ TIM3.EncoderMode=TIM_ENCODERMODE_TI12 TIM3.IPParameters=EncoderMode USART1.IPParameters=VirtualMode-Asynchronous USART1.VirtualMode-Asynchronous=VM_ASYNC -USART2.IPParameters=VirtualMode-Asynchronous,VirtualMode-Hardware Flow Control (RS485) +USART2.BaudRate=57600 +USART2.IPParameters=VirtualMode-Asynchronous,VirtualMode-Hardware Flow Control (RS485),BaudRate,TXFIFOThreshold,RXFIFOThreshold +USART2.RXFIFOThreshold=RXFIFO_THRESHOLD_HALFFULL +USART2.TXFIFOThreshold=TXFIFO_THRESHOLD_HALFFULL USART2.VirtualMode-Asynchronous=VM_ASYNC USART2.VirtualMode-Hardware\ Flow\ Control\ (RS485)=VM_ASYNC VP_SYS_VS_Systick.Mode=SysTick diff --git a/pcb/mobo/#auto_saved_files# b/pcb/mobo/#auto_saved_files# deleted file mode 100644 index 8ab9dc7..0000000 --- a/pcb/mobo/#auto_saved_files# +++ /dev/null @@ -1 +0,0 @@ -C:\Users\janik\feeder_mk2\pcb\mobo\_autosave-mobo.kicad_sch diff --git a/pcb/mobo/~mobo.kicad_pcb.lck b/pcb/mobo/~mobo.kicad_pcb.lck deleted file mode 100644 index 64ce498..0000000 --- a/pcb/mobo/~mobo.kicad_pcb.lck +++ /dev/null @@ -1 +0,0 @@ -{"hostname":"SUPERDUPER","username":"janik"} \ No newline at end of file diff --git a/pcb/mobo/~mobo.kicad_sch.lck b/pcb/mobo/~mobo.kicad_sch.lck deleted file mode 100644 index 64ce498..0000000 --- a/pcb/mobo/~mobo.kicad_sch.lck +++ /dev/null @@ -1 +0,0 @@ -{"hostname":"SUPERDUPER","username":"janik"} \ No newline at end of file