C64PSU.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001d8 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 000080fc 080001d8 080001d8 000011d8 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000450 080082d4 080082d4 000092d4 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08008724 08008724 0000a00c 2**0 CONTENTS, READONLY 4 .ARM 00000008 08008724 08008724 00009724 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .preinit_array 00000000 0800872c 0800872c 0000a00c 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 0800872c 0800872c 0000972c 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 7 .fini_array 00000004 08008730 08008730 00009730 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 8 .data 0000000c 20000000 08008734 0000a000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 0000046c 2000000c 08008740 0000a00c 2**2 ALLOC 10 ._user_heap_stack 00000600 20000478 08008740 0000a478 2**0 ALLOC 11 .ARM.attributes 00000030 00000000 00000000 0000a00c 2**0 CONTENTS, READONLY 12 .debug_info 000207c1 00000000 00000000 0000a03c 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 000035a8 00000000 00000000 0002a7fd 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 00001db8 00000000 00000000 0002dda8 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_rnglists 00001746 00000000 00000000 0002fb60 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 0002b98b 00000000 00000000 000312a6 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 00020136 00000000 00000000 0005cc31 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 0013b1c9 00000000 00000000 0007cd67 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000043 00000000 00000000 001b7f30 2**0 CONTENTS, READONLY 20 .debug_frame 000083bc 00000000 00000000 001b7f74 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 21 .debug_line_str 00000049 00000000 00000000 001c0330 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080001d8 <__do_global_dtors_aux>: 80001d8: b510 push {r4, lr} 80001da: 4c05 ldr r4, [pc, #20] @ (80001f0 <__do_global_dtors_aux+0x18>) 80001dc: 7823 ldrb r3, [r4, #0] 80001de: b933 cbnz r3, 80001ee <__do_global_dtors_aux+0x16> 80001e0: 4b04 ldr r3, [pc, #16] @ (80001f4 <__do_global_dtors_aux+0x1c>) 80001e2: b113 cbz r3, 80001ea <__do_global_dtors_aux+0x12> 80001e4: 4804 ldr r0, [pc, #16] @ (80001f8 <__do_global_dtors_aux+0x20>) 80001e6: f3af 8000 nop.w 80001ea: 2301 movs r3, #1 80001ec: 7023 strb r3, [r4, #0] 80001ee: bd10 pop {r4, pc} 80001f0: 2000000c .word 0x2000000c 80001f4: 00000000 .word 0x00000000 80001f8: 080082bc .word 0x080082bc 080001fc : 80001fc: b508 push {r3, lr} 80001fe: 4b03 ldr r3, [pc, #12] @ (800020c ) 8000200: b11b cbz r3, 800020a 8000202: 4903 ldr r1, [pc, #12] @ (8000210 ) 8000204: 4803 ldr r0, [pc, #12] @ (8000214 ) 8000206: f3af 8000 nop.w 800020a: bd08 pop {r3, pc} 800020c: 00000000 .word 0x00000000 8000210: 20000010 .word 0x20000010 8000214: 080082bc .word 0x080082bc 08000218 : 8000218: 4603 mov r3, r0 800021a: f813 2b01 ldrb.w r2, [r3], #1 800021e: 2a00 cmp r2, #0 8000220: d1fb bne.n 800021a 8000222: 1a18 subs r0, r3, r0 8000224: 3801 subs r0, #1 8000226: 4770 bx lr 08000228 <__aeabi_uldivmod>: 8000228: b953 cbnz r3, 8000240 <__aeabi_uldivmod+0x18> 800022a: b94a cbnz r2, 8000240 <__aeabi_uldivmod+0x18> 800022c: 2900 cmp r1, #0 800022e: bf08 it eq 8000230: 2800 cmpeq r0, #0 8000232: bf1c itt ne 8000234: f04f 31ff movne.w r1, #4294967295 8000238: f04f 30ff movne.w r0, #4294967295 800023c: f000 b988 b.w 8000550 <__aeabi_idiv0> 8000240: f1ad 0c08 sub.w ip, sp, #8 8000244: e96d ce04 strd ip, lr, [sp, #-16]! 8000248: f000 f806 bl 8000258 <__udivmoddi4> 800024c: f8dd e004 ldr.w lr, [sp, #4] 8000250: e9dd 2302 ldrd r2, r3, [sp, #8] 8000254: b004 add sp, #16 8000256: 4770 bx lr 08000258 <__udivmoddi4>: 8000258: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 800025c: 9d08 ldr r5, [sp, #32] 800025e: 468e mov lr, r1 8000260: 4604 mov r4, r0 8000262: 4688 mov r8, r1 8000264: 2b00 cmp r3, #0 8000266: d14a bne.n 80002fe <__udivmoddi4+0xa6> 8000268: 428a cmp r2, r1 800026a: 4617 mov r7, r2 800026c: d962 bls.n 8000334 <__udivmoddi4+0xdc> 800026e: fab2 f682 clz r6, r2 8000272: b14e cbz r6, 8000288 <__udivmoddi4+0x30> 8000274: f1c6 0320 rsb r3, r6, #32 8000278: fa01 f806 lsl.w r8, r1, r6 800027c: fa20 f303 lsr.w r3, r0, r3 8000280: 40b7 lsls r7, r6 8000282: ea43 0808 orr.w r8, r3, r8 8000286: 40b4 lsls r4, r6 8000288: ea4f 4e17 mov.w lr, r7, lsr #16 800028c: fa1f fc87 uxth.w ip, r7 8000290: fbb8 f1fe udiv r1, r8, lr 8000294: 0c23 lsrs r3, r4, #16 8000296: fb0e 8811 mls r8, lr, r1, r8 800029a: ea43 4308 orr.w r3, r3, r8, lsl #16 800029e: fb01 f20c mul.w r2, r1, ip 80002a2: 429a cmp r2, r3 80002a4: d909 bls.n 80002ba <__udivmoddi4+0x62> 80002a6: 18fb adds r3, r7, r3 80002a8: f101 30ff add.w r0, r1, #4294967295 80002ac: f080 80ea bcs.w 8000484 <__udivmoddi4+0x22c> 80002b0: 429a cmp r2, r3 80002b2: f240 80e7 bls.w 8000484 <__udivmoddi4+0x22c> 80002b6: 3902 subs r1, #2 80002b8: 443b add r3, r7 80002ba: 1a9a subs r2, r3, r2 80002bc: b2a3 uxth r3, r4 80002be: fbb2 f0fe udiv r0, r2, lr 80002c2: fb0e 2210 mls r2, lr, r0, r2 80002c6: ea43 4302 orr.w r3, r3, r2, lsl #16 80002ca: fb00 fc0c mul.w ip, r0, ip 80002ce: 459c cmp ip, r3 80002d0: d909 bls.n 80002e6 <__udivmoddi4+0x8e> 80002d2: 18fb adds r3, r7, r3 80002d4: f100 32ff add.w r2, r0, #4294967295 80002d8: f080 80d6 bcs.w 8000488 <__udivmoddi4+0x230> 80002dc: 459c cmp ip, r3 80002de: f240 80d3 bls.w 8000488 <__udivmoddi4+0x230> 80002e2: 443b add r3, r7 80002e4: 3802 subs r0, #2 80002e6: ea40 4001 orr.w r0, r0, r1, lsl #16 80002ea: eba3 030c sub.w r3, r3, ip 80002ee: 2100 movs r1, #0 80002f0: b11d cbz r5, 80002fa <__udivmoddi4+0xa2> 80002f2: 40f3 lsrs r3, r6 80002f4: 2200 movs r2, #0 80002f6: e9c5 3200 strd r3, r2, [r5] 80002fa: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80002fe: 428b cmp r3, r1 8000300: d905 bls.n 800030e <__udivmoddi4+0xb6> 8000302: b10d cbz r5, 8000308 <__udivmoddi4+0xb0> 8000304: e9c5 0100 strd r0, r1, [r5] 8000308: 2100 movs r1, #0 800030a: 4608 mov r0, r1 800030c: e7f5 b.n 80002fa <__udivmoddi4+0xa2> 800030e: fab3 f183 clz r1, r3 8000312: 2900 cmp r1, #0 8000314: d146 bne.n 80003a4 <__udivmoddi4+0x14c> 8000316: 4573 cmp r3, lr 8000318: d302 bcc.n 8000320 <__udivmoddi4+0xc8> 800031a: 4282 cmp r2, r0 800031c: f200 8105 bhi.w 800052a <__udivmoddi4+0x2d2> 8000320: 1a84 subs r4, r0, r2 8000322: eb6e 0203 sbc.w r2, lr, r3 8000326: 2001 movs r0, #1 8000328: 4690 mov r8, r2 800032a: 2d00 cmp r5, #0 800032c: d0e5 beq.n 80002fa <__udivmoddi4+0xa2> 800032e: e9c5 4800 strd r4, r8, [r5] 8000332: e7e2 b.n 80002fa <__udivmoddi4+0xa2> 8000334: 2a00 cmp r2, #0 8000336: f000 8090 beq.w 800045a <__udivmoddi4+0x202> 800033a: fab2 f682 clz r6, r2 800033e: 2e00 cmp r6, #0 8000340: f040 80a4 bne.w 800048c <__udivmoddi4+0x234> 8000344: 1a8a subs r2, r1, r2 8000346: 0c03 lsrs r3, r0, #16 8000348: ea4f 4e17 mov.w lr, r7, lsr #16 800034c: b280 uxth r0, r0 800034e: b2bc uxth r4, r7 8000350: 2101 movs r1, #1 8000352: fbb2 fcfe udiv ip, r2, lr 8000356: fb0e 221c mls r2, lr, ip, r2 800035a: ea43 4302 orr.w r3, r3, r2, lsl #16 800035e: fb04 f20c mul.w r2, r4, ip 8000362: 429a cmp r2, r3 8000364: d907 bls.n 8000376 <__udivmoddi4+0x11e> 8000366: 18fb adds r3, r7, r3 8000368: f10c 38ff add.w r8, ip, #4294967295 800036c: d202 bcs.n 8000374 <__udivmoddi4+0x11c> 800036e: 429a cmp r2, r3 8000370: f200 80e0 bhi.w 8000534 <__udivmoddi4+0x2dc> 8000374: 46c4 mov ip, r8 8000376: 1a9b subs r3, r3, r2 8000378: fbb3 f2fe udiv r2, r3, lr 800037c: fb0e 3312 mls r3, lr, r2, r3 8000380: ea40 4303 orr.w r3, r0, r3, lsl #16 8000384: fb02 f404 mul.w r4, r2, r4 8000388: 429c cmp r4, r3 800038a: d907 bls.n 800039c <__udivmoddi4+0x144> 800038c: 18fb adds r3, r7, r3 800038e: f102 30ff add.w r0, r2, #4294967295 8000392: d202 bcs.n 800039a <__udivmoddi4+0x142> 8000394: 429c cmp r4, r3 8000396: f200 80ca bhi.w 800052e <__udivmoddi4+0x2d6> 800039a: 4602 mov r2, r0 800039c: 1b1b subs r3, r3, r4 800039e: ea42 400c orr.w r0, r2, ip, lsl #16 80003a2: e7a5 b.n 80002f0 <__udivmoddi4+0x98> 80003a4: f1c1 0620 rsb r6, r1, #32 80003a8: 408b lsls r3, r1 80003aa: fa22 f706 lsr.w r7, r2, r6 80003ae: 431f orrs r7, r3 80003b0: fa0e f401 lsl.w r4, lr, r1 80003b4: fa20 f306 lsr.w r3, r0, r6 80003b8: fa2e fe06 lsr.w lr, lr, r6 80003bc: ea4f 4917 mov.w r9, r7, lsr #16 80003c0: 4323 orrs r3, r4 80003c2: fa00 f801 lsl.w r8, r0, r1 80003c6: fa1f fc87 uxth.w ip, r7 80003ca: fbbe f0f9 udiv r0, lr, r9 80003ce: 0c1c lsrs r4, r3, #16 80003d0: fb09 ee10 mls lr, r9, r0, lr 80003d4: ea44 440e orr.w r4, r4, lr, lsl #16 80003d8: fb00 fe0c mul.w lr, r0, ip 80003dc: 45a6 cmp lr, r4 80003de: fa02 f201 lsl.w r2, r2, r1 80003e2: d909 bls.n 80003f8 <__udivmoddi4+0x1a0> 80003e4: 193c adds r4, r7, r4 80003e6: f100 3aff add.w sl, r0, #4294967295 80003ea: f080 809c bcs.w 8000526 <__udivmoddi4+0x2ce> 80003ee: 45a6 cmp lr, r4 80003f0: f240 8099 bls.w 8000526 <__udivmoddi4+0x2ce> 80003f4: 3802 subs r0, #2 80003f6: 443c add r4, r7 80003f8: eba4 040e sub.w r4, r4, lr 80003fc: fa1f fe83 uxth.w lr, r3 8000400: fbb4 f3f9 udiv r3, r4, r9 8000404: fb09 4413 mls r4, r9, r3, r4 8000408: ea4e 4404 orr.w r4, lr, r4, lsl #16 800040c: fb03 fc0c mul.w ip, r3, ip 8000410: 45a4 cmp ip, r4 8000412: d908 bls.n 8000426 <__udivmoddi4+0x1ce> 8000414: 193c adds r4, r7, r4 8000416: f103 3eff add.w lr, r3, #4294967295 800041a: f080 8082 bcs.w 8000522 <__udivmoddi4+0x2ca> 800041e: 45a4 cmp ip, r4 8000420: d97f bls.n 8000522 <__udivmoddi4+0x2ca> 8000422: 3b02 subs r3, #2 8000424: 443c add r4, r7 8000426: ea43 4000 orr.w r0, r3, r0, lsl #16 800042a: eba4 040c sub.w r4, r4, ip 800042e: fba0 ec02 umull lr, ip, r0, r2 8000432: 4564 cmp r4, ip 8000434: 4673 mov r3, lr 8000436: 46e1 mov r9, ip 8000438: d362 bcc.n 8000500 <__udivmoddi4+0x2a8> 800043a: d05f beq.n 80004fc <__udivmoddi4+0x2a4> 800043c: b15d cbz r5, 8000456 <__udivmoddi4+0x1fe> 800043e: ebb8 0203 subs.w r2, r8, r3 8000442: eb64 0409 sbc.w r4, r4, r9 8000446: fa04 f606 lsl.w r6, r4, r6 800044a: fa22 f301 lsr.w r3, r2, r1 800044e: 431e orrs r6, r3 8000450: 40cc lsrs r4, r1 8000452: e9c5 6400 strd r6, r4, [r5] 8000456: 2100 movs r1, #0 8000458: e74f b.n 80002fa <__udivmoddi4+0xa2> 800045a: fbb1 fcf2 udiv ip, r1, r2 800045e: 0c01 lsrs r1, r0, #16 8000460: ea41 410e orr.w r1, r1, lr, lsl #16 8000464: b280 uxth r0, r0 8000466: ea40 4201 orr.w r2, r0, r1, lsl #16 800046a: 463b mov r3, r7 800046c: 4638 mov r0, r7 800046e: 463c mov r4, r7 8000470: 46b8 mov r8, r7 8000472: 46be mov lr, r7 8000474: 2620 movs r6, #32 8000476: fbb1 f1f7 udiv r1, r1, r7 800047a: eba2 0208 sub.w r2, r2, r8 800047e: ea41 410c orr.w r1, r1, ip, lsl #16 8000482: e766 b.n 8000352 <__udivmoddi4+0xfa> 8000484: 4601 mov r1, r0 8000486: e718 b.n 80002ba <__udivmoddi4+0x62> 8000488: 4610 mov r0, r2 800048a: e72c b.n 80002e6 <__udivmoddi4+0x8e> 800048c: f1c6 0220 rsb r2, r6, #32 8000490: fa2e f302 lsr.w r3, lr, r2 8000494: 40b7 lsls r7, r6 8000496: 40b1 lsls r1, r6 8000498: fa20 f202 lsr.w r2, r0, r2 800049c: ea4f 4e17 mov.w lr, r7, lsr #16 80004a0: 430a orrs r2, r1 80004a2: fbb3 f8fe udiv r8, r3, lr 80004a6: b2bc uxth r4, r7 80004a8: fb0e 3318 mls r3, lr, r8, r3 80004ac: 0c11 lsrs r1, r2, #16 80004ae: ea41 4103 orr.w r1, r1, r3, lsl #16 80004b2: fb08 f904 mul.w r9, r8, r4 80004b6: 40b0 lsls r0, r6 80004b8: 4589 cmp r9, r1 80004ba: ea4f 4310 mov.w r3, r0, lsr #16 80004be: b280 uxth r0, r0 80004c0: d93e bls.n 8000540 <__udivmoddi4+0x2e8> 80004c2: 1879 adds r1, r7, r1 80004c4: f108 3cff add.w ip, r8, #4294967295 80004c8: d201 bcs.n 80004ce <__udivmoddi4+0x276> 80004ca: 4589 cmp r9, r1 80004cc: d81f bhi.n 800050e <__udivmoddi4+0x2b6> 80004ce: eba1 0109 sub.w r1, r1, r9 80004d2: fbb1 f9fe udiv r9, r1, lr 80004d6: fb09 f804 mul.w r8, r9, r4 80004da: fb0e 1119 mls r1, lr, r9, r1 80004de: b292 uxth r2, r2 80004e0: ea42 4201 orr.w r2, r2, r1, lsl #16 80004e4: 4542 cmp r2, r8 80004e6: d229 bcs.n 800053c <__udivmoddi4+0x2e4> 80004e8: 18ba adds r2, r7, r2 80004ea: f109 31ff add.w r1, r9, #4294967295 80004ee: d2c4 bcs.n 800047a <__udivmoddi4+0x222> 80004f0: 4542 cmp r2, r8 80004f2: d2c2 bcs.n 800047a <__udivmoddi4+0x222> 80004f4: f1a9 0102 sub.w r1, r9, #2 80004f8: 443a add r2, r7 80004fa: e7be b.n 800047a <__udivmoddi4+0x222> 80004fc: 45f0 cmp r8, lr 80004fe: d29d bcs.n 800043c <__udivmoddi4+0x1e4> 8000500: ebbe 0302 subs.w r3, lr, r2 8000504: eb6c 0c07 sbc.w ip, ip, r7 8000508: 3801 subs r0, #1 800050a: 46e1 mov r9, ip 800050c: e796 b.n 800043c <__udivmoddi4+0x1e4> 800050e: eba7 0909 sub.w r9, r7, r9 8000512: 4449 add r1, r9 8000514: f1a8 0c02 sub.w ip, r8, #2 8000518: fbb1 f9fe udiv r9, r1, lr 800051c: fb09 f804 mul.w r8, r9, r4 8000520: e7db b.n 80004da <__udivmoddi4+0x282> 8000522: 4673 mov r3, lr 8000524: e77f b.n 8000426 <__udivmoddi4+0x1ce> 8000526: 4650 mov r0, sl 8000528: e766 b.n 80003f8 <__udivmoddi4+0x1a0> 800052a: 4608 mov r0, r1 800052c: e6fd b.n 800032a <__udivmoddi4+0xd2> 800052e: 443b add r3, r7 8000530: 3a02 subs r2, #2 8000532: e733 b.n 800039c <__udivmoddi4+0x144> 8000534: f1ac 0c02 sub.w ip, ip, #2 8000538: 443b add r3, r7 800053a: e71c b.n 8000376 <__udivmoddi4+0x11e> 800053c: 4649 mov r1, r9 800053e: e79c b.n 800047a <__udivmoddi4+0x222> 8000540: eba1 0109 sub.w r1, r1, r9 8000544: 46c4 mov ip, r8 8000546: fbb1 f9fe udiv r9, r1, lr 800054a: fb09 f804 mul.w r8, r9, r4 800054e: e7c4 b.n 80004da <__udivmoddi4+0x282> 08000550 <__aeabi_idiv0>: 8000550: 4770 bx lr 8000552: bf00 nop 08000554
: /** * @brief The application entry point. * @retval int */ int main(void) { 8000554: b580 push {r7, lr} 8000556: b086 sub sp, #24 8000558: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 800055a: f001 f942 bl 80017e2 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 800055e: f000 f85f bl 8000620 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8000562: f000 fcd3 bl 8000f0c MX_DMA_Init(); 8000566: f000 fc9f bl 8000ea8 MX_TIM1_Init(); 800056a: f000 fbff bl 8000d6c MX_CORDIC_Init(); 800056e: f000 f9cd bl 800090c MX_FMAC_Init(); 8000572: f000 fa53 bl 8000a1c MX_ADC3_Init(); 8000576: f000 f89d bl 80006b4 MX_ADC4_Init(); 800057a: f000 f915 bl 80007a8 MX_COMP5_Init(); 800057e: f000 f979 bl 8000874 MX_COMP7_Init(); 8000582: f000 f99d bl 80008c0 MX_DAC1_Init(); 8000586: f000 f9d5 bl 8000934 MX_DAC4_Init(); 800058a: f000 fa0d bl 80009a8 MX_HRTIM1_Init(); 800058e: f000 fa59 bl 8000a44 MX_USART1_UART_Init(); 8000592: f000 fc3d bl 8000e10 /* USER CODE BEGIN 2 */ HAL_ADCEx_Calibration_Start(&hadc3, ADC_SINGLE_ENDED); 8000596: 217f movs r1, #127 @ 0x7f 8000598: 481a ldr r0, [pc, #104] @ (8000604 ) 800059a: f002 fa61 bl 8002a60 HAL_ADCEx_Calibration_Start(&hadc4, ADC_SINGLE_ENDED); 800059e: 217f movs r1, #127 @ 0x7f 80005a0: 4819 ldr r0, [pc, #100] @ (8000608 ) 80005a2: f002 fa5d bl 8002a60 // HAL_DAC_SetValue(&hdac1, DAC_CHANNEL_2, DAC_ALIGN_12B_R, );//voltage HAL_DAC_SetValue(&hdac4, DAC_CHANNEL_1, DAC_ALIGN_12B_R, 3500);//current 80005a6: f640 53ac movw r3, #3500 @ 0xdac 80005aa: 2200 movs r2, #0 80005ac: 2100 movs r1, #0 80005ae: 4817 ldr r0, [pc, #92] @ (800060c ) 80005b0: f003 f87a bl 80036a8 // HAL_DAC_Start(&hdac1, DAC_CHANNEL_2); HAL_DAC_Start(&hdac4, DAC_CHANNEL_1); //current 80005b4: 2100 movs r1, #0 80005b6: 4815 ldr r0, [pc, #84] @ (800060c ) 80005b8: f003 f80a bl 80035d0 /* Infinite loop */ /* USER CODE BEGIN WHILE */ HAL_HRTIM_WaveformCountStart(&hhrtim1,HRTIM_TIMERID_MASTER|HRTIM_TIMERID_TIMER_A|HRTIM_TIMERID_TIMER_B); 80005bc: f44f 21e0 mov.w r1, #458752 @ 0x70000 80005c0: 4813 ldr r0, [pc, #76] @ (8000610 ) 80005c2: f004 fafe bl 8004bc2 HAL_TIM_Base_Start_IT(&htim1); 80005c6: 4813 ldr r0, [pc, #76] @ (8000614 ) 80005c8: f006 fa1e bl 8006a08 char dtext[20] = "Startup \n\r"; 80005cc: 4a12 ldr r2, [pc, #72] @ (8000618 ) 80005ce: 1d3b adds r3, r7, #4 80005d0: ca07 ldmia r2, {r0, r1, r2} 80005d2: c303 stmia r3!, {r0, r1} 80005d4: 801a strh r2, [r3, #0] 80005d6: 3302 adds r3, #2 80005d8: 0c12 lsrs r2, r2, #16 80005da: 701a strb r2, [r3, #0] 80005dc: f107 030f add.w r3, r7, #15 80005e0: 2200 movs r2, #0 80005e2: 601a str r2, [r3, #0] 80005e4: 605a str r2, [r3, #4] 80005e6: 721a strb r2, [r3, #8] HAL_UART_Transmit(&huart1,(uint8_t *)(dtext),strlen(dtext),10); 80005e8: 1d3b adds r3, r7, #4 80005ea: 4618 mov r0, r3 80005ec: f7ff fe14 bl 8000218 80005f0: 4603 mov r3, r0 80005f2: b29a uxth r2, r3 80005f4: 1d39 adds r1, r7, #4 80005f6: 230a movs r3, #10 80005f8: 4808 ldr r0, [pc, #32] @ (800061c ) 80005fa: f006 ff87 bl 800750c while (1) 80005fe: bf00 nop 8000600: e7fd b.n 80005fe 8000602: bf00 nop 8000604: 20000028 .word 0x20000028 8000608: 20000094 .word 0x20000094 800060c: 20000244 .word 0x20000244 8000610: 20000290 .word 0x20000290 8000614: 2000038c .word 0x2000038c 8000618: 080082d4 .word 0x080082d4 800061c: 200003d8 .word 0x200003d8 08000620 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8000620: b580 push {r7, lr} 8000622: b094 sub sp, #80 @ 0x50 8000624: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8000626: f107 0318 add.w r3, r7, #24 800062a: 2238 movs r2, #56 @ 0x38 800062c: 2100 movs r1, #0 800062e: 4618 mov r0, r3 8000630: f007 fe18 bl 8008264 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000634: 1d3b adds r3, r7, #4 8000636: 2200 movs r2, #0 8000638: 601a str r2, [r3, #0] 800063a: 605a str r2, [r3, #4] 800063c: 609a str r2, [r3, #8] 800063e: 60da str r2, [r3, #12] 8000640: 611a str r2, [r3, #16] /** Configure the main internal regulator output voltage */ HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST); 8000642: 2000 movs r0, #0 8000644: f005 f958 bl 80058f8 /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 8000648: 2301 movs r3, #1 800064a: 61bb str r3, [r7, #24] RCC_OscInitStruct.HSEState = RCC_HSE_ON; 800064c: f44f 3380 mov.w r3, #65536 @ 0x10000 8000650: 61fb str r3, [r7, #28] RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8000652: 2302 movs r3, #2 8000654: 637b str r3, [r7, #52] @ 0x34 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 8000656: 2303 movs r3, #3 8000658: 63bb str r3, [r7, #56] @ 0x38 RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4; 800065a: 2304 movs r3, #4 800065c: 63fb str r3, [r7, #60] @ 0x3c RCC_OscInitStruct.PLL.PLLN = 34; 800065e: 2322 movs r3, #34 @ 0x22 8000660: 643b str r3, [r7, #64] @ 0x40 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 8000662: 2302 movs r3, #2 8000664: 647b str r3, [r7, #68] @ 0x44 RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; 8000666: 2302 movs r3, #2 8000668: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; 800066a: 2302 movs r3, #2 800066c: 64fb str r3, [r7, #76] @ 0x4c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 800066e: f107 0318 add.w r3, r7, #24 8000672: 4618 mov r0, r3 8000674: f005 f9f4 bl 8005a60 8000678: 4603 mov r3, r0 800067a: 2b00 cmp r3, #0 800067c: d001 beq.n 8000682 { Error_Handler(); 800067e: f000 fcff bl 8001080 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8000682: 230f movs r3, #15 8000684: 607b str r3, [r7, #4] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 8000686: 2303 movs r3, #3 8000688: 60bb str r3, [r7, #8] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 800068a: 2300 movs r3, #0 800068c: 60fb str r3, [r7, #12] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 800068e: 2300 movs r3, #0 8000690: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 8000692: 2300 movs r3, #0 8000694: 617b str r3, [r7, #20] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) 8000696: 1d3b adds r3, r7, #4 8000698: 2104 movs r1, #4 800069a: 4618 mov r0, r3 800069c: f005 fcf2 bl 8006084 80006a0: 4603 mov r3, r0 80006a2: 2b00 cmp r3, #0 80006a4: d001 beq.n 80006aa { Error_Handler(); 80006a6: f000 fceb bl 8001080 } } 80006aa: bf00 nop 80006ac: 3750 adds r7, #80 @ 0x50 80006ae: 46bd mov sp, r7 80006b0: bd80 pop {r7, pc} ... 080006b4 : * @brief ADC3 Initialization Function * @param None * @retval None */ static void MX_ADC3_Init(void) { 80006b4: b580 push {r7, lr} 80006b6: b08c sub sp, #48 @ 0x30 80006b8: af00 add r7, sp, #0 /* USER CODE BEGIN ADC3_Init 0 */ /* USER CODE END ADC3_Init 0 */ ADC_MultiModeTypeDef multimode = {0}; 80006ba: f107 0324 add.w r3, r7, #36 @ 0x24 80006be: 2200 movs r2, #0 80006c0: 601a str r2, [r3, #0] 80006c2: 605a str r2, [r3, #4] 80006c4: 609a str r2, [r3, #8] ADC_ChannelConfTypeDef sConfig = {0}; 80006c6: 1d3b adds r3, r7, #4 80006c8: 2220 movs r2, #32 80006ca: 2100 movs r1, #0 80006cc: 4618 mov r0, r3 80006ce: f007 fdc9 bl 8008264 /* USER CODE END ADC3_Init 1 */ /** Common config */ hadc3.Instance = ADC3; 80006d2: 4b32 ldr r3, [pc, #200] @ (800079c ) 80006d4: 4a32 ldr r2, [pc, #200] @ (80007a0 ) 80006d6: 601a str r2, [r3, #0] hadc3.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; 80006d8: 4b30 ldr r3, [pc, #192] @ (800079c ) 80006da: f44f 3240 mov.w r2, #196608 @ 0x30000 80006de: 605a str r2, [r3, #4] hadc3.Init.Resolution = ADC_RESOLUTION_12B; 80006e0: 4b2e ldr r3, [pc, #184] @ (800079c ) 80006e2: 2200 movs r2, #0 80006e4: 609a str r2, [r3, #8] hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT; 80006e6: 4b2d ldr r3, [pc, #180] @ (800079c ) 80006e8: 2200 movs r2, #0 80006ea: 60da str r2, [r3, #12] hadc3.Init.GainCompensation = 0; 80006ec: 4b2b ldr r3, [pc, #172] @ (800079c ) 80006ee: 2200 movs r2, #0 80006f0: 611a str r2, [r3, #16] hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE; 80006f2: 4b2a ldr r3, [pc, #168] @ (800079c ) 80006f4: 2200 movs r2, #0 80006f6: 615a str r2, [r3, #20] hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 80006f8: 4b28 ldr r3, [pc, #160] @ (800079c ) 80006fa: 2204 movs r2, #4 80006fc: 619a str r2, [r3, #24] hadc3.Init.LowPowerAutoWait = DISABLE; 80006fe: 4b27 ldr r3, [pc, #156] @ (800079c ) 8000700: 2200 movs r2, #0 8000702: 771a strb r2, [r3, #28] hadc3.Init.ContinuousConvMode = ENABLE; 8000704: 4b25 ldr r3, [pc, #148] @ (800079c ) 8000706: 2201 movs r2, #1 8000708: 775a strb r2, [r3, #29] hadc3.Init.NbrOfConversion = 1; 800070a: 4b24 ldr r3, [pc, #144] @ (800079c ) 800070c: 2201 movs r2, #1 800070e: 621a str r2, [r3, #32] hadc3.Init.DiscontinuousConvMode = DISABLE; 8000710: 4b22 ldr r3, [pc, #136] @ (800079c ) 8000712: 2200 movs r2, #0 8000714: f883 2024 strb.w r2, [r3, #36] @ 0x24 hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START; 8000718: 4b20 ldr r3, [pc, #128] @ (800079c ) 800071a: 2200 movs r2, #0 800071c: 62da str r2, [r3, #44] @ 0x2c hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 800071e: 4b1f ldr r3, [pc, #124] @ (800079c ) 8000720: 2200 movs r2, #0 8000722: 631a str r2, [r3, #48] @ 0x30 hadc3.Init.DMAContinuousRequests = ENABLE; 8000724: 4b1d ldr r3, [pc, #116] @ (800079c ) 8000726: 2201 movs r2, #1 8000728: f883 2038 strb.w r2, [r3, #56] @ 0x38 hadc3.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN; 800072c: 4b1b ldr r3, [pc, #108] @ (800079c ) 800072e: f44f 5280 mov.w r2, #4096 @ 0x1000 8000732: 63da str r2, [r3, #60] @ 0x3c hadc3.Init.OversamplingMode = DISABLE; 8000734: 4b19 ldr r3, [pc, #100] @ (800079c ) 8000736: 2200 movs r2, #0 8000738: f883 2040 strb.w r2, [r3, #64] @ 0x40 if (HAL_ADC_Init(&hadc3) != HAL_OK) 800073c: 4817 ldr r0, [pc, #92] @ (800079c ) 800073e: f001 fae1 bl 8001d04 8000742: 4603 mov r3, r0 8000744: 2b00 cmp r3, #0 8000746: d001 beq.n 800074c { Error_Handler(); 8000748: f000 fc9a bl 8001080 } /** Configure the ADC multi-mode */ multimode.Mode = ADC_MODE_INDEPENDENT; 800074c: 2300 movs r3, #0 800074e: 627b str r3, [r7, #36] @ 0x24 if (HAL_ADCEx_MultiModeConfigChannel(&hadc3, &multimode) != HAL_OK) 8000750: f107 0324 add.w r3, r7, #36 @ 0x24 8000754: 4619 mov r1, r3 8000756: 4811 ldr r0, [pc, #68] @ (800079c ) 8000758: f002 f9e4 bl 8002b24 800075c: 4603 mov r3, r0 800075e: 2b00 cmp r3, #0 8000760: d001 beq.n 8000766 { Error_Handler(); 8000762: f000 fc8d bl 8001080 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_5; 8000766: 4b0f ldr r3, [pc, #60] @ (80007a4 ) 8000768: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 800076a: 2306 movs r3, #6 800076c: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_247CYCLES_5; 800076e: 2306 movs r3, #6 8000770: 60fb str r3, [r7, #12] sConfig.SingleDiff = ADC_SINGLE_ENDED; 8000772: 237f movs r3, #127 @ 0x7f 8000774: 613b str r3, [r7, #16] sConfig.OffsetNumber = ADC_OFFSET_NONE; 8000776: 2304 movs r3, #4 8000778: 617b str r3, [r7, #20] sConfig.Offset = 0; 800077a: 2300 movs r3, #0 800077c: 61bb str r3, [r7, #24] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 800077e: 1d3b adds r3, r7, #4 8000780: 4619 mov r1, r3 8000782: 4806 ldr r0, [pc, #24] @ (800079c ) 8000784: f001 fc7a bl 800207c 8000788: 4603 mov r3, r0 800078a: 2b00 cmp r3, #0 800078c: d001 beq.n 8000792 { Error_Handler(); 800078e: f000 fc77 bl 8001080 } /* USER CODE BEGIN ADC3_Init 2 */ /* USER CODE END ADC3_Init 2 */ } 8000792: bf00 nop 8000794: 3730 adds r7, #48 @ 0x30 8000796: 46bd mov sp, r7 8000798: bd80 pop {r7, pc} 800079a: bf00 nop 800079c: 20000028 .word 0x20000028 80007a0: 50000400 .word 0x50000400 80007a4: 14f00020 .word 0x14f00020 080007a8 : * @brief ADC4 Initialization Function * @param None * @retval None */ static void MX_ADC4_Init(void) { 80007a8: b580 push {r7, lr} 80007aa: b088 sub sp, #32 80007ac: af00 add r7, sp, #0 /* USER CODE BEGIN ADC4_Init 0 */ /* USER CODE END ADC4_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 80007ae: 463b mov r3, r7 80007b0: 2220 movs r2, #32 80007b2: 2100 movs r1, #0 80007b4: 4618 mov r0, r3 80007b6: f007 fd55 bl 8008264 /* USER CODE END ADC4_Init 1 */ /** Common config */ hadc4.Instance = ADC4; 80007ba: 4b2b ldr r3, [pc, #172] @ (8000868 ) 80007bc: 4a2b ldr r2, [pc, #172] @ (800086c ) 80007be: 601a str r2, [r3, #0] hadc4.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; 80007c0: 4b29 ldr r3, [pc, #164] @ (8000868 ) 80007c2: f44f 3240 mov.w r2, #196608 @ 0x30000 80007c6: 605a str r2, [r3, #4] hadc4.Init.Resolution = ADC_RESOLUTION_12B; 80007c8: 4b27 ldr r3, [pc, #156] @ (8000868 ) 80007ca: 2200 movs r2, #0 80007cc: 609a str r2, [r3, #8] hadc4.Init.DataAlign = ADC_DATAALIGN_RIGHT; 80007ce: 4b26 ldr r3, [pc, #152] @ (8000868 ) 80007d0: 2200 movs r2, #0 80007d2: 60da str r2, [r3, #12] hadc4.Init.GainCompensation = 0; 80007d4: 4b24 ldr r3, [pc, #144] @ (8000868 ) 80007d6: 2200 movs r2, #0 80007d8: 611a str r2, [r3, #16] hadc4.Init.ScanConvMode = ADC_SCAN_DISABLE; 80007da: 4b23 ldr r3, [pc, #140] @ (8000868 ) 80007dc: 2200 movs r2, #0 80007de: 615a str r2, [r3, #20] hadc4.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 80007e0: 4b21 ldr r3, [pc, #132] @ (8000868 ) 80007e2: 2204 movs r2, #4 80007e4: 619a str r2, [r3, #24] hadc4.Init.LowPowerAutoWait = DISABLE; 80007e6: 4b20 ldr r3, [pc, #128] @ (8000868 ) 80007e8: 2200 movs r2, #0 80007ea: 771a strb r2, [r3, #28] hadc4.Init.ContinuousConvMode = ENABLE; 80007ec: 4b1e ldr r3, [pc, #120] @ (8000868 ) 80007ee: 2201 movs r2, #1 80007f0: 775a strb r2, [r3, #29] hadc4.Init.NbrOfConversion = 1; 80007f2: 4b1d ldr r3, [pc, #116] @ (8000868 ) 80007f4: 2201 movs r2, #1 80007f6: 621a str r2, [r3, #32] hadc4.Init.DiscontinuousConvMode = DISABLE; 80007f8: 4b1b ldr r3, [pc, #108] @ (8000868 ) 80007fa: 2200 movs r2, #0 80007fc: f883 2024 strb.w r2, [r3, #36] @ 0x24 hadc4.Init.ExternalTrigConv = ADC_SOFTWARE_START; 8000800: 4b19 ldr r3, [pc, #100] @ (8000868 ) 8000802: 2200 movs r2, #0 8000804: 62da str r2, [r3, #44] @ 0x2c hadc4.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 8000806: 4b18 ldr r3, [pc, #96] @ (8000868 ) 8000808: 2200 movs r2, #0 800080a: 631a str r2, [r3, #48] @ 0x30 hadc4.Init.DMAContinuousRequests = ENABLE; 800080c: 4b16 ldr r3, [pc, #88] @ (8000868 ) 800080e: 2201 movs r2, #1 8000810: f883 2038 strb.w r2, [r3, #56] @ 0x38 hadc4.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN; 8000814: 4b14 ldr r3, [pc, #80] @ (8000868 ) 8000816: f44f 5280 mov.w r2, #4096 @ 0x1000 800081a: 63da str r2, [r3, #60] @ 0x3c hadc4.Init.OversamplingMode = DISABLE; 800081c: 4b12 ldr r3, [pc, #72] @ (8000868 ) 800081e: 2200 movs r2, #0 8000820: f883 2040 strb.w r2, [r3, #64] @ 0x40 if (HAL_ADC_Init(&hadc4) != HAL_OK) 8000824: 4810 ldr r0, [pc, #64] @ (8000868 ) 8000826: f001 fa6d bl 8001d04 800082a: 4603 mov r3, r0 800082c: 2b00 cmp r3, #0 800082e: d001 beq.n 8000834 { Error_Handler(); 8000830: f000 fc26 bl 8001080 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_4; 8000834: 4b0e ldr r3, [pc, #56] @ (8000870 ) 8000836: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_1; 8000838: 2306 movs r3, #6 800083a: 607b str r3, [r7, #4] sConfig.SamplingTime = ADC_SAMPLETIME_247CYCLES_5; 800083c: 2306 movs r3, #6 800083e: 60bb str r3, [r7, #8] sConfig.SingleDiff = ADC_SINGLE_ENDED; 8000840: 237f movs r3, #127 @ 0x7f 8000842: 60fb str r3, [r7, #12] sConfig.OffsetNumber = ADC_OFFSET_NONE; 8000844: 2304 movs r3, #4 8000846: 613b str r3, [r7, #16] sConfig.Offset = 0; 8000848: 2300 movs r3, #0 800084a: 617b str r3, [r7, #20] if (HAL_ADC_ConfigChannel(&hadc4, &sConfig) != HAL_OK) 800084c: 463b mov r3, r7 800084e: 4619 mov r1, r3 8000850: 4805 ldr r0, [pc, #20] @ (8000868 ) 8000852: f001 fc13 bl 800207c 8000856: 4603 mov r3, r0 8000858: 2b00 cmp r3, #0 800085a: d001 beq.n 8000860 { Error_Handler(); 800085c: f000 fc10 bl 8001080 } /* USER CODE BEGIN ADC4_Init 2 */ /* USER CODE END ADC4_Init 2 */ } 8000860: bf00 nop 8000862: 3720 adds r7, #32 8000864: 46bd mov sp, r7 8000866: bd80 pop {r7, pc} 8000868: 20000094 .word 0x20000094 800086c: 50000500 .word 0x50000500 8000870: 10c00010 .word 0x10c00010 08000874 : * @brief COMP5 Initialization Function * @param None * @retval None */ static void MX_COMP5_Init(void) { 8000874: b580 push {r7, lr} 8000876: af00 add r7, sp, #0 /* USER CODE END COMP5_Init 0 */ /* USER CODE BEGIN COMP5_Init 1 */ /* USER CODE END COMP5_Init 1 */ hcomp5.Instance = COMP5; 8000878: 4b0f ldr r3, [pc, #60] @ (80008b8 ) 800087a: 4a10 ldr r2, [pc, #64] @ (80008bc ) 800087c: 601a str r2, [r3, #0] hcomp5.Init.InputPlus = COMP_INPUT_PLUS_IO1; 800087e: 4b0e ldr r3, [pc, #56] @ (80008b8 ) 8000880: 2200 movs r2, #0 8000882: 605a str r2, [r3, #4] hcomp5.Init.InputMinus = COMP_INPUT_MINUS_DAC1_CH2; 8000884: 4b0c ldr r3, [pc, #48] @ (80008b8 ) 8000886: 2250 movs r2, #80 @ 0x50 8000888: 609a str r2, [r3, #8] hcomp5.Init.OutputPol = COMP_OUTPUTPOL_NONINVERTED; 800088a: 4b0b ldr r3, [pc, #44] @ (80008b8 ) 800088c: 2200 movs r2, #0 800088e: 611a str r2, [r3, #16] hcomp5.Init.Hysteresis = COMP_HYSTERESIS_NONE; 8000890: 4b09 ldr r3, [pc, #36] @ (80008b8 ) 8000892: 2200 movs r2, #0 8000894: 60da str r2, [r3, #12] hcomp5.Init.BlankingSrce = COMP_BLANKINGSRC_NONE; 8000896: 4b08 ldr r3, [pc, #32] @ (80008b8 ) 8000898: 2200 movs r2, #0 800089a: 615a str r2, [r3, #20] hcomp5.Init.TriggerMode = COMP_TRIGGERMODE_NONE; 800089c: 4b06 ldr r3, [pc, #24] @ (80008b8 ) 800089e: 2200 movs r2, #0 80008a0: 619a str r2, [r3, #24] if (HAL_COMP_Init(&hcomp5) != HAL_OK) 80008a2: 4805 ldr r0, [pc, #20] @ (80008b8 ) 80008a4: f002 fb96 bl 8002fd4 80008a8: 4603 mov r3, r0 80008aa: 2b00 cmp r3, #0 80008ac: d001 beq.n 80008b2 { Error_Handler(); 80008ae: f000 fbe7 bl 8001080 } /* USER CODE BEGIN COMP5_Init 2 */ /* USER CODE END COMP5_Init 2 */ } 80008b2: bf00 nop 80008b4: bd80 pop {r7, pc} 80008b6: bf00 nop 80008b8: 200001c0 .word 0x200001c0 80008bc: 40010210 .word 0x40010210 080008c0 : * @brief COMP7 Initialization Function * @param None * @retval None */ static void MX_COMP7_Init(void) { 80008c0: b580 push {r7, lr} 80008c2: af00 add r7, sp, #0 /* USER CODE END COMP7_Init 0 */ /* USER CODE BEGIN COMP7_Init 1 */ /* USER CODE END COMP7_Init 1 */ hcomp7.Instance = COMP7; 80008c4: 4b0f ldr r3, [pc, #60] @ (8000904 ) 80008c6: 4a10 ldr r2, [pc, #64] @ (8000908 ) 80008c8: 601a str r2, [r3, #0] hcomp7.Init.InputPlus = COMP_INPUT_PLUS_IO1; 80008ca: 4b0e ldr r3, [pc, #56] @ (8000904 ) 80008cc: 2200 movs r2, #0 80008ce: 605a str r2, [r3, #4] hcomp7.Init.InputMinus = COMP_INPUT_MINUS_DAC4_CH1; 80008d0: 4b0c ldr r3, [pc, #48] @ (8000904 ) 80008d2: 2240 movs r2, #64 @ 0x40 80008d4: 609a str r2, [r3, #8] hcomp7.Init.OutputPol = COMP_OUTPUTPOL_NONINVERTED; 80008d6: 4b0b ldr r3, [pc, #44] @ (8000904 ) 80008d8: 2200 movs r2, #0 80008da: 611a str r2, [r3, #16] hcomp7.Init.Hysteresis = COMP_HYSTERESIS_NONE; 80008dc: 4b09 ldr r3, [pc, #36] @ (8000904 ) 80008de: 2200 movs r2, #0 80008e0: 60da str r2, [r3, #12] hcomp7.Init.BlankingSrce = COMP_BLANKINGSRC_NONE; 80008e2: 4b08 ldr r3, [pc, #32] @ (8000904 ) 80008e4: 2200 movs r2, #0 80008e6: 615a str r2, [r3, #20] hcomp7.Init.TriggerMode = COMP_TRIGGERMODE_NONE; 80008e8: 4b06 ldr r3, [pc, #24] @ (8000904 ) 80008ea: 2200 movs r2, #0 80008ec: 619a str r2, [r3, #24] if (HAL_COMP_Init(&hcomp7) != HAL_OK) 80008ee: 4805 ldr r0, [pc, #20] @ (8000904 ) 80008f0: f002 fb70 bl 8002fd4 80008f4: 4603 mov r3, r0 80008f6: 2b00 cmp r3, #0 80008f8: d001 beq.n 80008fe { Error_Handler(); 80008fa: f000 fbc1 bl 8001080 } /* USER CODE BEGIN COMP7_Init 2 */ /* USER CODE END COMP7_Init 2 */ } 80008fe: bf00 nop 8000900: bd80 pop {r7, pc} 8000902: bf00 nop 8000904: 200001e4 .word 0x200001e4 8000908: 40010218 .word 0x40010218 0800090c : * @brief CORDIC Initialization Function * @param None * @retval None */ static void MX_CORDIC_Init(void) { 800090c: b580 push {r7, lr} 800090e: af00 add r7, sp, #0 /* USER CODE END CORDIC_Init 0 */ /* USER CODE BEGIN CORDIC_Init 1 */ /* USER CODE END CORDIC_Init 1 */ hcordic.Instance = CORDIC; 8000910: 4b06 ldr r3, [pc, #24] @ (800092c ) 8000912: 4a07 ldr r2, [pc, #28] @ (8000930 ) 8000914: 601a str r2, [r3, #0] if (HAL_CORDIC_Init(&hcordic) != HAL_OK) 8000916: 4805 ldr r0, [pc, #20] @ (800092c ) 8000918: f002 fcf6 bl 8003308 800091c: 4603 mov r3, r0 800091e: 2b00 cmp r3, #0 8000920: d001 beq.n 8000926 { Error_Handler(); 8000922: f000 fbad bl 8001080 } /* USER CODE BEGIN CORDIC_Init 2 */ /* USER CODE END CORDIC_Init 2 */ } 8000926: bf00 nop 8000928: bd80 pop {r7, pc} 800092a: bf00 nop 800092c: 20000208 .word 0x20000208 8000930: 40020c00 .word 0x40020c00 08000934 : * @brief DAC1 Initialization Function * @param None * @retval None */ static void MX_DAC1_Init(void) { 8000934: b580 push {r7, lr} 8000936: b08c sub sp, #48 @ 0x30 8000938: af00 add r7, sp, #0 /* USER CODE BEGIN DAC1_Init 0 */ /* USER CODE END DAC1_Init 0 */ DAC_ChannelConfTypeDef sConfig = {0}; 800093a: 463b mov r3, r7 800093c: 2230 movs r2, #48 @ 0x30 800093e: 2100 movs r1, #0 8000940: 4618 mov r0, r3 8000942: f007 fc8f bl 8008264 /* USER CODE END DAC1_Init 1 */ /** DAC Initialization */ hdac1.Instance = DAC1; 8000946: 4b16 ldr r3, [pc, #88] @ (80009a0 ) 8000948: 4a16 ldr r2, [pc, #88] @ (80009a4 ) 800094a: 601a str r2, [r3, #0] if (HAL_DAC_Init(&hdac1) != HAL_OK) 800094c: 4814 ldr r0, [pc, #80] @ (80009a0 ) 800094e: f002 fe1c bl 800358a 8000952: 4603 mov r3, r0 8000954: 2b00 cmp r3, #0 8000956: d001 beq.n 800095c { Error_Handler(); 8000958: f000 fb92 bl 8001080 } /** DAC channel OUT2 config */ sConfig.DAC_HighFrequency = DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC; 800095c: 2302 movs r3, #2 800095e: 603b str r3, [r7, #0] sConfig.DAC_DMADoubleDataMode = DISABLE; 8000960: 2300 movs r3, #0 8000962: 713b strb r3, [r7, #4] sConfig.DAC_SignedFormat = DISABLE; 8000964: 2300 movs r3, #0 8000966: 717b strb r3, [r7, #5] sConfig.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_DISABLE; 8000968: 2300 movs r3, #0 800096a: 60bb str r3, [r7, #8] sConfig.DAC_Trigger = DAC_TRIGGER_NONE; 800096c: 2300 movs r3, #0 800096e: 60fb str r3, [r7, #12] sConfig.DAC_Trigger2 = DAC_TRIGGER_NONE; 8000970: 2300 movs r3, #0 8000972: 613b str r3, [r7, #16] sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_DISABLE; 8000974: 2302 movs r3, #2 8000976: 617b str r3, [r7, #20] sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_INTERNAL; 8000978: 2302 movs r3, #2 800097a: 61bb str r3, [r7, #24] sConfig.DAC_UserTrimming = DAC_TRIMMING_FACTORY; 800097c: 2300 movs r3, #0 800097e: 61fb str r3, [r7, #28] if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_2) != HAL_OK) 8000980: 463b mov r3, r7 8000982: 2210 movs r2, #16 8000984: 4619 mov r1, r3 8000986: 4806 ldr r0, [pc, #24] @ (80009a0 ) 8000988: f002 febc bl 8003704 800098c: 4603 mov r3, r0 800098e: 2b00 cmp r3, #0 8000990: d001 beq.n 8000996 { Error_Handler(); 8000992: f000 fb75 bl 8001080 } /* USER CODE BEGIN DAC1_Init 2 */ /* USER CODE END DAC1_Init 2 */ } 8000996: bf00 nop 8000998: 3730 adds r7, #48 @ 0x30 800099a: 46bd mov sp, r7 800099c: bd80 pop {r7, pc} 800099e: bf00 nop 80009a0: 20000230 .word 0x20000230 80009a4: 50000800 .word 0x50000800 080009a8 : * @brief DAC4 Initialization Function * @param None * @retval None */ static void MX_DAC4_Init(void) { 80009a8: b580 push {r7, lr} 80009aa: b08c sub sp, #48 @ 0x30 80009ac: af00 add r7, sp, #0 /* USER CODE BEGIN DAC4_Init 0 */ /* USER CODE END DAC4_Init 0 */ DAC_ChannelConfTypeDef sConfig = {0}; 80009ae: 463b mov r3, r7 80009b0: 2230 movs r2, #48 @ 0x30 80009b2: 2100 movs r1, #0 80009b4: 4618 mov r0, r3 80009b6: f007 fc55 bl 8008264 /* USER CODE END DAC4_Init 1 */ /** DAC Initialization */ hdac4.Instance = DAC4; 80009ba: 4b16 ldr r3, [pc, #88] @ (8000a14 ) 80009bc: 4a16 ldr r2, [pc, #88] @ (8000a18 ) 80009be: 601a str r2, [r3, #0] if (HAL_DAC_Init(&hdac4) != HAL_OK) 80009c0: 4814 ldr r0, [pc, #80] @ (8000a14 ) 80009c2: f002 fde2 bl 800358a 80009c6: 4603 mov r3, r0 80009c8: 2b00 cmp r3, #0 80009ca: d001 beq.n 80009d0 { Error_Handler(); 80009cc: f000 fb58 bl 8001080 } /** DAC channel OUT1 config */ sConfig.DAC_HighFrequency = DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC; 80009d0: 2302 movs r3, #2 80009d2: 603b str r3, [r7, #0] sConfig.DAC_DMADoubleDataMode = DISABLE; 80009d4: 2300 movs r3, #0 80009d6: 713b strb r3, [r7, #4] sConfig.DAC_SignedFormat = DISABLE; 80009d8: 2300 movs r3, #0 80009da: 717b strb r3, [r7, #5] sConfig.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_DISABLE; 80009dc: 2300 movs r3, #0 80009de: 60bb str r3, [r7, #8] sConfig.DAC_Trigger = DAC_TRIGGER_NONE; 80009e0: 2300 movs r3, #0 80009e2: 60fb str r3, [r7, #12] sConfig.DAC_Trigger2 = DAC_TRIGGER_NONE; 80009e4: 2300 movs r3, #0 80009e6: 613b str r3, [r7, #16] sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_DISABLE; 80009e8: 2302 movs r3, #2 80009ea: 617b str r3, [r7, #20] sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_INTERNAL; 80009ec: 2302 movs r3, #2 80009ee: 61bb str r3, [r7, #24] sConfig.DAC_UserTrimming = DAC_TRIMMING_FACTORY; 80009f0: 2300 movs r3, #0 80009f2: 61fb str r3, [r7, #28] if (HAL_DAC_ConfigChannel(&hdac4, &sConfig, DAC_CHANNEL_1) != HAL_OK) 80009f4: 463b mov r3, r7 80009f6: 2200 movs r2, #0 80009f8: 4619 mov r1, r3 80009fa: 4806 ldr r0, [pc, #24] @ (8000a14 ) 80009fc: f002 fe82 bl 8003704 8000a00: 4603 mov r3, r0 8000a02: 2b00 cmp r3, #0 8000a04: d001 beq.n 8000a0a { Error_Handler(); 8000a06: f000 fb3b bl 8001080 } /* USER CODE BEGIN DAC4_Init 2 */ /* USER CODE END DAC4_Init 2 */ } 8000a0a: bf00 nop 8000a0c: 3730 adds r7, #48 @ 0x30 8000a0e: 46bd mov sp, r7 8000a10: bd80 pop {r7, pc} 8000a12: bf00 nop 8000a14: 20000244 .word 0x20000244 8000a18: 50001400 .word 0x50001400 08000a1c : * @brief FMAC Initialization Function * @param None * @retval None */ static void MX_FMAC_Init(void) { 8000a1c: b580 push {r7, lr} 8000a1e: af00 add r7, sp, #0 /* USER CODE END FMAC_Init 0 */ /* USER CODE BEGIN FMAC_Init 1 */ /* USER CODE END FMAC_Init 1 */ hfmac.Instance = FMAC; 8000a20: 4b06 ldr r3, [pc, #24] @ (8000a3c ) 8000a22: 4a07 ldr r2, [pc, #28] @ (8000a40 ) 8000a24: 601a str r2, [r3, #0] if (HAL_FMAC_Init(&hfmac) != HAL_OK) 8000a26: 4805 ldr r0, [pc, #20] @ (8000a3c ) 8000a28: f003 f9e0 bl 8003dec 8000a2c: 4603 mov r3, r0 8000a2e: 2b00 cmp r3, #0 8000a30: d001 beq.n 8000a36 { Error_Handler(); 8000a32: f000 fb25 bl 8001080 } /* USER CODE BEGIN FMAC_Init 2 */ /* USER CODE END FMAC_Init 2 */ } 8000a36: bf00 nop 8000a38: bd80 pop {r7, pc} 8000a3a: bf00 nop 8000a3c: 20000258 .word 0x20000258 8000a40: 40021400 .word 0x40021400 08000a44 : * @brief HRTIM1 Initialization Function * @param None * @retval None */ static void MX_HRTIM1_Init(void) { 8000a44: b580 push {r7, lr} 8000a46: b0b4 sub sp, #208 @ 0xd0 8000a48: af00 add r7, sp, #0 /* USER CODE BEGIN HRTIM1_Init 0 */ /* USER CODE END HRTIM1_Init 0 */ HRTIM_EventCfgTypeDef pEventCfg = {0}; 8000a4a: f107 03bc add.w r3, r7, #188 @ 0xbc 8000a4e: 2200 movs r2, #0 8000a50: 601a str r2, [r3, #0] 8000a52: 605a str r2, [r3, #4] 8000a54: 609a str r2, [r3, #8] 8000a56: 60da str r2, [r3, #12] 8000a58: 611a str r2, [r3, #16] HRTIM_TimeBaseCfgTypeDef pTimeBaseCfg = {0}; 8000a5a: f107 03ac add.w r3, r7, #172 @ 0xac 8000a5e: 2200 movs r2, #0 8000a60: 601a str r2, [r3, #0] 8000a62: 605a str r2, [r3, #4] 8000a64: 609a str r2, [r3, #8] 8000a66: 60da str r2, [r3, #12] HRTIM_TimerCfgTypeDef pTimerCfg = {0}; 8000a68: f107 034c add.w r3, r7, #76 @ 0x4c 8000a6c: 2260 movs r2, #96 @ 0x60 8000a6e: 2100 movs r1, #0 8000a70: 4618 mov r0, r3 8000a72: f007 fbf7 bl 8008264 HRTIM_TimerCtlTypeDef pTimerCtl = {0}; 8000a76: f107 0330 add.w r3, r7, #48 @ 0x30 8000a7a: 2200 movs r2, #0 8000a7c: 601a str r2, [r3, #0] 8000a7e: 605a str r2, [r3, #4] 8000a80: 609a str r2, [r3, #8] 8000a82: 60da str r2, [r3, #12] 8000a84: 611a str r2, [r3, #16] 8000a86: 615a str r2, [r3, #20] 8000a88: 619a str r2, [r3, #24] HRTIM_CompareCfgTypeDef pCompareCfg = {0}; 8000a8a: f107 0324 add.w r3, r7, #36 @ 0x24 8000a8e: 2200 movs r2, #0 8000a90: 601a str r2, [r3, #0] 8000a92: 605a str r2, [r3, #4] 8000a94: 609a str r2, [r3, #8] HRTIM_OutputCfgTypeDef pOutputCfg = {0}; 8000a96: 1d3b adds r3, r7, #4 8000a98: 2220 movs r2, #32 8000a9a: 2100 movs r1, #0 8000a9c: 4618 mov r0, r3 8000a9e: f007 fbe1 bl 8008264 /* USER CODE BEGIN HRTIM1_Init 1 */ /* USER CODE END HRTIM1_Init 1 */ hhrtim1.Instance = HRTIM1; 8000aa2: 4bb0 ldr r3, [pc, #704] @ (8000d64 ) 8000aa4: 4ab0 ldr r2, [pc, #704] @ (8000d68 ) 8000aa6: 601a str r2, [r3, #0] hhrtim1.Init.HRTIMInterruptResquests = HRTIM_IT_NONE; 8000aa8: 4bae ldr r3, [pc, #696] @ (8000d64 ) 8000aaa: 2200 movs r2, #0 8000aac: 605a str r2, [r3, #4] hhrtim1.Init.SyncOptions = HRTIM_SYNCOPTION_NONE; 8000aae: 4bad ldr r3, [pc, #692] @ (8000d64 ) 8000ab0: 2200 movs r2, #0 8000ab2: 609a str r2, [r3, #8] if (HAL_HRTIM_Init(&hhrtim1) != HAL_OK) 8000ab4: 48ab ldr r0, [pc, #684] @ (8000d64 ) 8000ab6: f003 fbdf bl 8004278 8000aba: 4603 mov r3, r0 8000abc: 2b00 cmp r3, #0 8000abe: d001 beq.n 8000ac4 { Error_Handler(); 8000ac0: f000 fade bl 8001080 } if (HAL_HRTIM_DLLCalibrationStart(&hhrtim1, HRTIM_CALIBRATIONRATE_3) != HAL_OK) 8000ac4: 210c movs r1, #12 8000ac6: 48a7 ldr r0, [pc, #668] @ (8000d64 ) 8000ac8: f003 fca6 bl 8004418 8000acc: 4603 mov r3, r0 8000ace: 2b00 cmp r3, #0 8000ad0: d001 beq.n 8000ad6 { Error_Handler(); 8000ad2: f000 fad5 bl 8001080 } if (HAL_HRTIM_PollForDLLCalibration(&hhrtim1, 10) != HAL_OK) 8000ad6: 210a movs r1, #10 8000ad8: 48a2 ldr r0, [pc, #648] @ (8000d64 ) 8000ada: f003 fcf5 bl 80044c8 8000ade: 4603 mov r3, r0 8000ae0: 2b00 cmp r3, #0 8000ae2: d001 beq.n 8000ae8 { Error_Handler(); 8000ae4: f000 facc bl 8001080 } if (HAL_HRTIM_EventPrescalerConfig(&hhrtim1, HRTIM_EVENTPRESCALER_DIV1) != HAL_OK) 8000ae8: 2100 movs r1, #0 8000aea: 489e ldr r0, [pc, #632] @ (8000d64 ) 8000aec: f003 fd77 bl 80045de 8000af0: 4603 mov r3, r0 8000af2: 2b00 cmp r3, #0 8000af4: d001 beq.n 8000afa { Error_Handler(); 8000af6: f000 fac3 bl 8001080 } pEventCfg.Source = HRTIM_EEV1SRC_COMP2_OUT; 8000afa: 2301 movs r3, #1 8000afc: f8c7 30bc str.w r3, [r7, #188] @ 0xbc pEventCfg.Polarity = HRTIM_EVENTPOLARITY_HIGH; 8000b00: 2300 movs r3, #0 8000b02: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 pEventCfg.Sensitivity = HRTIM_EVENTSENSITIVITY_LEVEL; 8000b06: 2300 movs r3, #0 8000b08: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 pEventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE; 8000b0c: 2300 movs r3, #0 8000b0e: f8c7 30cc str.w r3, [r7, #204] @ 0xcc if (HAL_HRTIM_EventConfig(&hhrtim1, HRTIM_EVENT_1, &pEventCfg) != HAL_OK) 8000b12: f107 03bc add.w r3, r7, #188 @ 0xbc 8000b16: 461a mov r2, r3 8000b18: 2101 movs r1, #1 8000b1a: 4892 ldr r0, [pc, #584] @ (8000d64 ) 8000b1c: f003 fd30 bl 8004580 8000b20: 4603 mov r3, r0 8000b22: 2b00 cmp r3, #0 8000b24: d001 beq.n 8000b2a { Error_Handler(); 8000b26: f000 faab bl 8001080 } pTimeBaseCfg.Period = 0xD480; 8000b2a: f24d 4380 movw r3, #54400 @ 0xd480 8000b2e: f8c7 30ac str.w r3, [r7, #172] @ 0xac pTimeBaseCfg.RepetitionCounter = 0x00; 8000b32: 2300 movs r3, #0 8000b34: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 pTimeBaseCfg.PrescalerRatio = HRTIM_PRESCALERRATIO_MUL32; 8000b38: 2300 movs r3, #0 8000b3a: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 pTimeBaseCfg.Mode = HRTIM_MODE_CONTINUOUS; 8000b3e: 2308 movs r3, #8 8000b40: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 if (HAL_HRTIM_TimeBaseConfig(&hhrtim1, HRTIM_TIMERINDEX_MASTER, &pTimeBaseCfg) != HAL_OK) 8000b44: f107 03ac add.w r3, r7, #172 @ 0xac 8000b48: 461a mov r2, r3 8000b4a: 2106 movs r1, #6 8000b4c: 4885 ldr r0, [pc, #532] @ (8000d64 ) 8000b4e: f003 fcef bl 8004530 8000b52: 4603 mov r3, r0 8000b54: 2b00 cmp r3, #0 8000b56: d001 beq.n 8000b5c { Error_Handler(); 8000b58: f000 fa92 bl 8001080 } pTimerCfg.InterruptRequests = HRTIM_MASTER_IT_NONE; 8000b5c: 2300 movs r3, #0 8000b5e: 64fb str r3, [r7, #76] @ 0x4c pTimerCfg.DMARequests = HRTIM_MASTER_DMA_NONE; 8000b60: 2300 movs r3, #0 8000b62: 653b str r3, [r7, #80] @ 0x50 pTimerCfg.DMASrcAddress = 0x0000; 8000b64: 2300 movs r3, #0 8000b66: 657b str r3, [r7, #84] @ 0x54 pTimerCfg.DMADstAddress = 0x0000; 8000b68: 2300 movs r3, #0 8000b6a: 65bb str r3, [r7, #88] @ 0x58 pTimerCfg.DMASize = 0x1; 8000b6c: 2301 movs r3, #1 8000b6e: 65fb str r3, [r7, #92] @ 0x5c pTimerCfg.HalfModeEnable = HRTIM_HALFMODE_DISABLED; 8000b70: 2300 movs r3, #0 8000b72: 663b str r3, [r7, #96] @ 0x60 pTimerCfg.InterleavedMode = HRTIM_INTERLEAVED_MODE_DISABLED; 8000b74: 2300 movs r3, #0 8000b76: 667b str r3, [r7, #100] @ 0x64 pTimerCfg.StartOnSync = HRTIM_SYNCSTART_DISABLED; 8000b78: 2300 movs r3, #0 8000b7a: 66bb str r3, [r7, #104] @ 0x68 pTimerCfg.ResetOnSync = HRTIM_SYNCRESET_DISABLED; 8000b7c: 2300 movs r3, #0 8000b7e: 66fb str r3, [r7, #108] @ 0x6c pTimerCfg.DACSynchro = HRTIM_DACSYNC_NONE; 8000b80: 2300 movs r3, #0 8000b82: 673b str r3, [r7, #112] @ 0x70 pTimerCfg.PreloadEnable = HRTIM_PRELOAD_ENABLED; 8000b84: f04f 6300 mov.w r3, #134217728 @ 0x8000000 8000b88: 677b str r3, [r7, #116] @ 0x74 pTimerCfg.UpdateGating = HRTIM_UPDATEGATING_INDEPENDENT; 8000b8a: 2300 movs r3, #0 8000b8c: 67bb str r3, [r7, #120] @ 0x78 pTimerCfg.BurstMode = HRTIM_TIMERBURSTMODE_MAINTAINCLOCK; 8000b8e: 2300 movs r3, #0 8000b90: 67fb str r3, [r7, #124] @ 0x7c pTimerCfg.RepetitionUpdate = HRTIM_UPDATEONREPETITION_ENABLED; 8000b92: f04f 5300 mov.w r3, #536870912 @ 0x20000000 8000b96: f8c7 3080 str.w r3, [r7, #128] @ 0x80 pTimerCfg.ReSyncUpdate = HRTIM_TIMERESYNC_UPDATE_UNCONDITIONAL; 8000b9a: 2300 movs r3, #0 8000b9c: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 if (HAL_HRTIM_WaveformTimerConfig(&hhrtim1, HRTIM_TIMERINDEX_MASTER, &pTimerCfg) != HAL_OK) 8000ba0: f107 034c add.w r3, r7, #76 @ 0x4c 8000ba4: 461a mov r2, r3 8000ba6: 2106 movs r1, #6 8000ba8: 486e ldr r0, [pc, #440] @ (8000d64 ) 8000baa: f003 fd51 bl 8004650 8000bae: 4603 mov r3, r0 8000bb0: 2b00 cmp r3, #0 8000bb2: d001 beq.n 8000bb8 { Error_Handler(); 8000bb4: f000 fa64 bl 8001080 } pTimeBaseCfg.RepetitionCounter = 0x0; 8000bb8: 2300 movs r3, #0 8000bba: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 if (HAL_HRTIM_TimeBaseConfig(&hhrtim1, HRTIM_TIMERINDEX_TIMER_A, &pTimeBaseCfg) != HAL_OK) 8000bbe: f107 03ac add.w r3, r7, #172 @ 0xac 8000bc2: 461a mov r2, r3 8000bc4: 2100 movs r1, #0 8000bc6: 4867 ldr r0, [pc, #412] @ (8000d64 ) 8000bc8: f003 fcb2 bl 8004530 8000bcc: 4603 mov r3, r0 8000bce: 2b00 cmp r3, #0 8000bd0: d001 beq.n 8000bd6 { Error_Handler(); 8000bd2: f000 fa55 bl 8001080 } pTimerCtl.UpDownMode = HRTIM_TIMERUPDOWNMODE_UP; 8000bd6: 2300 movs r3, #0 8000bd8: 633b str r3, [r7, #48] @ 0x30 pTimerCtl.GreaterCMP1 = HRTIM_TIMERGTCMP1_GREATER; 8000bda: f44f 3380 mov.w r3, #65536 @ 0x10000 8000bde: 63fb str r3, [r7, #60] @ 0x3c pTimerCtl.DualChannelDacEnable = HRTIM_TIMER_DCDE_DISABLED; 8000be0: 2300 movs r3, #0 8000be2: 64bb str r3, [r7, #72] @ 0x48 if (HAL_HRTIM_WaveformTimerControl(&hhrtim1, HRTIM_TIMERINDEX_TIMER_A, &pTimerCtl) != HAL_OK) 8000be4: f107 0330 add.w r3, r7, #48 @ 0x30 8000be8: 461a mov r2, r3 8000bea: 2100 movs r1, #0 8000bec: 485d ldr r0, [pc, #372] @ (8000d64 ) 8000bee: f003 fdbc bl 800476a 8000bf2: 4603 mov r3, r0 8000bf4: 2b00 cmp r3, #0 8000bf6: d001 beq.n 8000bfc { Error_Handler(); 8000bf8: f000 fa42 bl 8001080 } pTimerCfg.InterruptRequests = HRTIM_TIM_IT_NONE; 8000bfc: 2300 movs r3, #0 8000bfe: 64fb str r3, [r7, #76] @ 0x4c pTimerCfg.DMARequests = HRTIM_TIM_DMA_NONE; 8000c00: 2300 movs r3, #0 8000c02: 653b str r3, [r7, #80] @ 0x50 pTimerCfg.RepetitionUpdate = HRTIM_UPDATEONREPETITION_DISABLED; 8000c04: 2300 movs r3, #0 8000c06: f8c7 3080 str.w r3, [r7, #128] @ 0x80 pTimerCfg.PushPull = HRTIM_TIMPUSHPULLMODE_DISABLED; 8000c0a: 2300 movs r3, #0 8000c0c: f8c7 3084 str.w r3, [r7, #132] @ 0x84 pTimerCfg.FaultEnable = HRTIM_TIMFAULTENABLE_NONE; 8000c10: 2300 movs r3, #0 8000c12: f8c7 3088 str.w r3, [r7, #136] @ 0x88 pTimerCfg.FaultLock = HRTIM_TIMFAULTLOCK_READWRITE; 8000c16: 2300 movs r3, #0 8000c18: f8c7 308c str.w r3, [r7, #140] @ 0x8c pTimerCfg.DeadTimeInsertion = HRTIM_TIMDEADTIMEINSERTION_DISABLED; 8000c1c: 2300 movs r3, #0 8000c1e: f8c7 3090 str.w r3, [r7, #144] @ 0x90 pTimerCfg.DelayedProtectionMode = HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED; 8000c22: 2300 movs r3, #0 8000c24: f8c7 3094 str.w r3, [r7, #148] @ 0x94 pTimerCfg.UpdateTrigger = HRTIM_TIMUPDATETRIGGER_NONE; 8000c28: 2300 movs r3, #0 8000c2a: f8c7 309c str.w r3, [r7, #156] @ 0x9c pTimerCfg.ResetTrigger = HRTIM_TIMRESETTRIGGER_NONE; 8000c2e: 2300 movs r3, #0 8000c30: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 pTimerCfg.ResetUpdate = HRTIM_TIMUPDATEONRESET_ENABLED; 8000c34: f44f 2380 mov.w r3, #262144 @ 0x40000 8000c38: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 if (HAL_HRTIM_WaveformTimerConfig(&hhrtim1, HRTIM_TIMERINDEX_TIMER_A, &pTimerCfg) != HAL_OK) 8000c3c: f107 034c add.w r3, r7, #76 @ 0x4c 8000c40: 461a mov r2, r3 8000c42: 2100 movs r1, #0 8000c44: 4847 ldr r0, [pc, #284] @ (8000d64 ) 8000c46: f003 fd03 bl 8004650 8000c4a: 4603 mov r3, r0 8000c4c: 2b00 cmp r3, #0 8000c4e: d001 beq.n 8000c54 { Error_Handler(); 8000c50: f000 fa16 bl 8001080 } if (HAL_HRTIM_WaveformTimerConfig(&hhrtim1, HRTIM_TIMERINDEX_TIMER_B, &pTimerCfg) != HAL_OK) 8000c54: f107 034c add.w r3, r7, #76 @ 0x4c 8000c58: 461a mov r2, r3 8000c5a: 2101 movs r1, #1 8000c5c: 4841 ldr r0, [pc, #260] @ (8000d64 ) 8000c5e: f003 fcf7 bl 8004650 8000c62: 4603 mov r3, r0 8000c64: 2b00 cmp r3, #0 8000c66: d001 beq.n 8000c6c { Error_Handler(); 8000c68: f000 fa0a bl 8001080 } pCompareCfg.CompareValue = 0x0; 8000c6c: 2300 movs r3, #0 8000c6e: 627b str r3, [r7, #36] @ 0x24 if (HAL_HRTIM_WaveformCompareConfig(&hhrtim1, HRTIM_TIMERINDEX_TIMER_A, HRTIM_COMPAREUNIT_1, &pCompareCfg) != HAL_OK) 8000c70: f107 0324 add.w r3, r7, #36 @ 0x24 8000c74: 2201 movs r2, #1 8000c76: 2100 movs r1, #0 8000c78: 483a ldr r0, [pc, #232] @ (8000d64 ) 8000c7a: f003 fda9 bl 80047d0 8000c7e: 4603 mov r3, r0 8000c80: 2b00 cmp r3, #0 8000c82: d001 beq.n 8000c88 { Error_Handler(); 8000c84: f000 f9fc bl 8001080 } pOutputCfg.Polarity = HRTIM_OUTPUTPOLARITY_LOW; 8000c88: 2302 movs r3, #2 8000c8a: 607b str r3, [r7, #4] pOutputCfg.SetSource = HRTIM_OUTPUTSET_TIMPER; 8000c8c: 2304 movs r3, #4 8000c8e: 60bb str r3, [r7, #8] pOutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP1; 8000c90: 2308 movs r3, #8 8000c92: 60fb str r3, [r7, #12] pOutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE; 8000c94: 2300 movs r3, #0 8000c96: 613b str r3, [r7, #16] pOutputCfg.IdleLevel = HRTIM_OUTPUTIDLELEVEL_ACTIVE; 8000c98: 2308 movs r3, #8 8000c9a: 617b str r3, [r7, #20] pOutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE; 8000c9c: 2300 movs r3, #0 8000c9e: 61bb str r3, [r7, #24] pOutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED; 8000ca0: 2300 movs r3, #0 8000ca2: 61fb str r3, [r7, #28] pOutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR; 8000ca4: 2300 movs r3, #0 8000ca6: 623b str r3, [r7, #32] if (HAL_HRTIM_WaveformOutputConfig(&hhrtim1, HRTIM_TIMERINDEX_TIMER_A, HRTIM_OUTPUT_TA1, &pOutputCfg) != HAL_OK) 8000ca8: 1d3b adds r3, r7, #4 8000caa: 2201 movs r2, #1 8000cac: 2100 movs r1, #0 8000cae: 482d ldr r0, [pc, #180] @ (8000d64 ) 8000cb0: f003 fefc bl 8004aac 8000cb4: 4603 mov r3, r0 8000cb6: 2b00 cmp r3, #0 8000cb8: d001 beq.n 8000cbe { Error_Handler(); 8000cba: f000 f9e1 bl 8001080 } if (HAL_HRTIM_WaveformOutputConfig(&hhrtim1, HRTIM_TIMERINDEX_TIMER_B, HRTIM_OUTPUT_TB1, &pOutputCfg) != HAL_OK) 8000cbe: 1d3b adds r3, r7, #4 8000cc0: 2204 movs r2, #4 8000cc2: 2101 movs r1, #1 8000cc4: 4827 ldr r0, [pc, #156] @ (8000d64 ) 8000cc6: f003 fef1 bl 8004aac 8000cca: 4603 mov r3, r0 8000ccc: 2b00 cmp r3, #0 8000cce: d001 beq.n 8000cd4 { Error_Handler(); 8000cd0: f000 f9d6 bl 8001080 } pOutputCfg.Polarity = HRTIM_OUTPUTPOLARITY_HIGH; 8000cd4: 2300 movs r3, #0 8000cd6: 607b str r3, [r7, #4] pOutputCfg.IdleLevel = HRTIM_OUTPUTIDLELEVEL_INACTIVE; 8000cd8: 2300 movs r3, #0 8000cda: 617b str r3, [r7, #20] if (HAL_HRTIM_WaveformOutputConfig(&hhrtim1, HRTIM_TIMERINDEX_TIMER_A, HRTIM_OUTPUT_TA2, &pOutputCfg) != HAL_OK) 8000cdc: 1d3b adds r3, r7, #4 8000cde: 2202 movs r2, #2 8000ce0: 2100 movs r1, #0 8000ce2: 4820 ldr r0, [pc, #128] @ (8000d64 ) 8000ce4: f003 fee2 bl 8004aac 8000ce8: 4603 mov r3, r0 8000cea: 2b00 cmp r3, #0 8000cec: d001 beq.n 8000cf2 { Error_Handler(); 8000cee: f000 f9c7 bl 8001080 } if (HAL_HRTIM_WaveformOutputConfig(&hhrtim1, HRTIM_TIMERINDEX_TIMER_B, HRTIM_OUTPUT_TB2, &pOutputCfg) != HAL_OK) 8000cf2: 1d3b adds r3, r7, #4 8000cf4: 2208 movs r2, #8 8000cf6: 2101 movs r1, #1 8000cf8: 481a ldr r0, [pc, #104] @ (8000d64 ) 8000cfa: f003 fed7 bl 8004aac 8000cfe: 4603 mov r3, r0 8000d00: 2b00 cmp r3, #0 8000d02: d001 beq.n 8000d08 { Error_Handler(); 8000d04: f000 f9bc bl 8001080 } pTimeBaseCfg.RepetitionCounter = 0x00; 8000d08: 2300 movs r3, #0 8000d0a: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 if (HAL_HRTIM_TimeBaseConfig(&hhrtim1, HRTIM_TIMERINDEX_TIMER_B, &pTimeBaseCfg) != HAL_OK) 8000d0e: f107 03ac add.w r3, r7, #172 @ 0xac 8000d12: 461a mov r2, r3 8000d14: 2101 movs r1, #1 8000d16: 4813 ldr r0, [pc, #76] @ (8000d64 ) 8000d18: f003 fc0a bl 8004530 8000d1c: 4603 mov r3, r0 8000d1e: 2b00 cmp r3, #0 8000d20: d001 beq.n 8000d26 { Error_Handler(); 8000d22: f000 f9ad bl 8001080 } if (HAL_HRTIM_WaveformTimerControl(&hhrtim1, HRTIM_TIMERINDEX_TIMER_B, &pTimerCtl) != HAL_OK) 8000d26: f107 0330 add.w r3, r7, #48 @ 0x30 8000d2a: 461a mov r2, r3 8000d2c: 2101 movs r1, #1 8000d2e: 480d ldr r0, [pc, #52] @ (8000d64 ) 8000d30: f003 fd1b bl 800476a 8000d34: 4603 mov r3, r0 8000d36: 2b00 cmp r3, #0 8000d38: d001 beq.n 8000d3e { Error_Handler(); 8000d3a: f000 f9a1 bl 8001080 } if (HAL_HRTIM_WaveformCompareConfig(&hhrtim1, HRTIM_TIMERINDEX_TIMER_B, HRTIM_COMPAREUNIT_1, &pCompareCfg) != HAL_OK) 8000d3e: f107 0324 add.w r3, r7, #36 @ 0x24 8000d42: 2201 movs r2, #1 8000d44: 2101 movs r1, #1 8000d46: 4807 ldr r0, [pc, #28] @ (8000d64 ) 8000d48: f003 fd42 bl 80047d0 8000d4c: 4603 mov r3, r0 8000d4e: 2b00 cmp r3, #0 8000d50: d001 beq.n 8000d56 { Error_Handler(); 8000d52: f000 f995 bl 8001080 } /* USER CODE BEGIN HRTIM1_Init 2 */ /* USER CODE END HRTIM1_Init 2 */ HAL_HRTIM_MspPostInit(&hhrtim1); 8000d56: 4803 ldr r0, [pc, #12] @ (8000d64 ) 8000d58: f000 fbce bl 80014f8 } 8000d5c: bf00 nop 8000d5e: 37d0 adds r7, #208 @ 0xd0 8000d60: 46bd mov sp, r7 8000d62: bd80 pop {r7, pc} 8000d64: 20000290 .word 0x20000290 8000d68: 40016800 .word 0x40016800 08000d6c : * @brief TIM1 Initialization Function * @param None * @retval None */ static void MX_TIM1_Init(void) { 8000d6c: b580 push {r7, lr} 8000d6e: b088 sub sp, #32 8000d70: af00 add r7, sp, #0 /* USER CODE BEGIN TIM1_Init 0 */ /* USER CODE END TIM1_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 8000d72: f107 0310 add.w r3, r7, #16 8000d76: 2200 movs r2, #0 8000d78: 601a str r2, [r3, #0] 8000d7a: 605a str r2, [r3, #4] 8000d7c: 609a str r2, [r3, #8] 8000d7e: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 8000d80: 1d3b adds r3, r7, #4 8000d82: 2200 movs r2, #0 8000d84: 601a str r2, [r3, #0] 8000d86: 605a str r2, [r3, #4] 8000d88: 609a str r2, [r3, #8] /* USER CODE BEGIN TIM1_Init 1 */ /* USER CODE END TIM1_Init 1 */ htim1.Instance = TIM1; 8000d8a: 4b1f ldr r3, [pc, #124] @ (8000e08 ) 8000d8c: 4a1f ldr r2, [pc, #124] @ (8000e0c ) 8000d8e: 601a str r2, [r3, #0] htim1.Init.Prescaler = 170-1; 8000d90: 4b1d ldr r3, [pc, #116] @ (8000e08 ) 8000d92: 22a9 movs r2, #169 @ 0xa9 8000d94: 605a str r2, [r3, #4] htim1.Init.CounterMode = TIM_COUNTERMODE_UP; 8000d96: 4b1c ldr r3, [pc, #112] @ (8000e08 ) 8000d98: 2200 movs r2, #0 8000d9a: 609a str r2, [r3, #8] htim1.Init.Period = 20; 8000d9c: 4b1a ldr r3, [pc, #104] @ (8000e08 ) 8000d9e: 2214 movs r2, #20 8000da0: 60da str r2, [r3, #12] htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8000da2: 4b19 ldr r3, [pc, #100] @ (8000e08 ) 8000da4: 2200 movs r2, #0 8000da6: 611a str r2, [r3, #16] htim1.Init.RepetitionCounter = 0; 8000da8: 4b17 ldr r3, [pc, #92] @ (8000e08 ) 8000daa: 2200 movs r2, #0 8000dac: 615a str r2, [r3, #20] htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8000dae: 4b16 ldr r3, [pc, #88] @ (8000e08 ) 8000db0: 2200 movs r2, #0 8000db2: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim1) != HAL_OK) 8000db4: 4814 ldr r0, [pc, #80] @ (8000e08 ) 8000db6: f005 fdcf bl 8006958 8000dba: 4603 mov r3, r0 8000dbc: 2b00 cmp r3, #0 8000dbe: d001 beq.n 8000dc4 { Error_Handler(); 8000dc0: f000 f95e bl 8001080 } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 8000dc4: f44f 5380 mov.w r3, #4096 @ 0x1000 8000dc8: 613b str r3, [r7, #16] if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK) 8000dca: f107 0310 add.w r3, r7, #16 8000dce: 4619 mov r1, r3 8000dd0: 480d ldr r0, [pc, #52] @ (8000e08 ) 8000dd2: f005 ffe1 bl 8006d98 8000dd6: 4603 mov r3, r0 8000dd8: 2b00 cmp r3, #0 8000dda: d001 beq.n 8000de0 { Error_Handler(); 8000ddc: f000 f950 bl 8001080 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8000de0: 2300 movs r3, #0 8000de2: 607b str r3, [r7, #4] sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; 8000de4: 2300 movs r3, #0 8000de6: 60bb str r3, [r7, #8] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8000de8: 2300 movs r3, #0 8000dea: 60fb str r3, [r7, #12] if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK) 8000dec: 1d3b adds r3, r7, #4 8000dee: 4619 mov r1, r3 8000df0: 4805 ldr r0, [pc, #20] @ (8000e08 ) 8000df2: f006 fa5f bl 80072b4 8000df6: 4603 mov r3, r0 8000df8: 2b00 cmp r3, #0 8000dfa: d001 beq.n 8000e00 { Error_Handler(); 8000dfc: f000 f940 bl 8001080 } /* USER CODE BEGIN TIM1_Init 2 */ /* USER CODE END TIM1_Init 2 */ } 8000e00: bf00 nop 8000e02: 3720 adds r7, #32 8000e04: 46bd mov sp, r7 8000e06: bd80 pop {r7, pc} 8000e08: 2000038c .word 0x2000038c 8000e0c: 40012c00 .word 0x40012c00 08000e10 : * @brief USART1 Initialization Function * @param None * @retval None */ static void MX_USART1_UART_Init(void) { 8000e10: b580 push {r7, lr} 8000e12: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 8000e14: 4b22 ldr r3, [pc, #136] @ (8000ea0 ) 8000e16: 4a23 ldr r2, [pc, #140] @ (8000ea4 ) 8000e18: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 8000e1a: 4b21 ldr r3, [pc, #132] @ (8000ea0 ) 8000e1c: f44f 32e1 mov.w r2, #115200 @ 0x1c200 8000e20: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 8000e22: 4b1f ldr r3, [pc, #124] @ (8000ea0 ) 8000e24: 2200 movs r2, #0 8000e26: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 8000e28: 4b1d ldr r3, [pc, #116] @ (8000ea0 ) 8000e2a: 2200 movs r2, #0 8000e2c: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 8000e2e: 4b1c ldr r3, [pc, #112] @ (8000ea0 ) 8000e30: 2200 movs r2, #0 8000e32: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 8000e34: 4b1a ldr r3, [pc, #104] @ (8000ea0 ) 8000e36: 220c movs r2, #12 8000e38: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8000e3a: 4b19 ldr r3, [pc, #100] @ (8000ea0 ) 8000e3c: 2200 movs r2, #0 8000e3e: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 8000e40: 4b17 ldr r3, [pc, #92] @ (8000ea0 ) 8000e42: 2200 movs r2, #0 8000e44: 61da str r2, [r3, #28] huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 8000e46: 4b16 ldr r3, [pc, #88] @ (8000ea0 ) 8000e48: 2200 movs r2, #0 8000e4a: 621a str r2, [r3, #32] huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; 8000e4c: 4b14 ldr r3, [pc, #80] @ (8000ea0 ) 8000e4e: 2200 movs r2, #0 8000e50: 625a str r2, [r3, #36] @ 0x24 huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 8000e52: 4b13 ldr r3, [pc, #76] @ (8000ea0 ) 8000e54: 2200 movs r2, #0 8000e56: 629a str r2, [r3, #40] @ 0x28 if (HAL_UART_Init(&huart1) != HAL_OK) 8000e58: 4811 ldr r0, [pc, #68] @ (8000ea0 ) 8000e5a: f006 fb07 bl 800746c 8000e5e: 4603 mov r3, r0 8000e60: 2b00 cmp r3, #0 8000e62: d001 beq.n 8000e68 { Error_Handler(); 8000e64: f000 f90c bl 8001080 } if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 8000e68: 2100 movs r1, #0 8000e6a: 480d ldr r0, [pc, #52] @ (8000ea0 ) 8000e6c: f007 f930 bl 80080d0 8000e70: 4603 mov r3, r0 8000e72: 2b00 cmp r3, #0 8000e74: d001 beq.n 8000e7a { Error_Handler(); 8000e76: f000 f903 bl 8001080 } if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 8000e7a: 2100 movs r1, #0 8000e7c: 4808 ldr r0, [pc, #32] @ (8000ea0 ) 8000e7e: f007 f965 bl 800814c 8000e82: 4603 mov r3, r0 8000e84: 2b00 cmp r3, #0 8000e86: d001 beq.n 8000e8c { Error_Handler(); 8000e88: f000 f8fa bl 8001080 } if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK) 8000e8c: 4804 ldr r0, [pc, #16] @ (8000ea0 ) 8000e8e: f007 f8e6 bl 800805e 8000e92: 4603 mov r3, r0 8000e94: 2b00 cmp r3, #0 8000e96: d001 beq.n 8000e9c { Error_Handler(); 8000e98: f000 f8f2 bl 8001080 } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 8000e9c: bf00 nop 8000e9e: bd80 pop {r7, pc} 8000ea0: 200003d8 .word 0x200003d8 8000ea4: 40013800 .word 0x40013800 08000ea8 : /** * Enable DMA controller clock */ static void MX_DMA_Init(void) { 8000ea8: b580 push {r7, lr} 8000eaa: b082 sub sp, #8 8000eac: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMAMUX1_CLK_ENABLE(); 8000eae: 4b16 ldr r3, [pc, #88] @ (8000f08 ) 8000eb0: 6c9b ldr r3, [r3, #72] @ 0x48 8000eb2: 4a15 ldr r2, [pc, #84] @ (8000f08 ) 8000eb4: f043 0304 orr.w r3, r3, #4 8000eb8: 6493 str r3, [r2, #72] @ 0x48 8000eba: 4b13 ldr r3, [pc, #76] @ (8000f08 ) 8000ebc: 6c9b ldr r3, [r3, #72] @ 0x48 8000ebe: f003 0304 and.w r3, r3, #4 8000ec2: 607b str r3, [r7, #4] 8000ec4: 687b ldr r3, [r7, #4] __HAL_RCC_DMA1_CLK_ENABLE(); 8000ec6: 4b10 ldr r3, [pc, #64] @ (8000f08 ) 8000ec8: 6c9b ldr r3, [r3, #72] @ 0x48 8000eca: 4a0f ldr r2, [pc, #60] @ (8000f08 ) 8000ecc: f043 0301 orr.w r3, r3, #1 8000ed0: 6493 str r3, [r2, #72] @ 0x48 8000ed2: 4b0d ldr r3, [pc, #52] @ (8000f08 ) 8000ed4: 6c9b ldr r3, [r3, #72] @ 0x48 8000ed6: f003 0301 and.w r3, r3, #1 8000eda: 603b str r3, [r7, #0] 8000edc: 683b ldr r3, [r7, #0] /* DMA interrupt init */ /* DMA1_Channel1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0); 8000ede: 2200 movs r2, #0 8000ee0: 2100 movs r1, #0 8000ee2: 200b movs r0, #11 8000ee4: f002 fb1d bl 8003522 HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); 8000ee8: 200b movs r0, #11 8000eea: f002 fb34 bl 8003556 /* DMA1_Channel2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel2_IRQn, 0, 0); 8000eee: 2200 movs r2, #0 8000ef0: 2100 movs r1, #0 8000ef2: 200c movs r0, #12 8000ef4: f002 fb15 bl 8003522 HAL_NVIC_EnableIRQ(DMA1_Channel2_IRQn); 8000ef8: 200c movs r0, #12 8000efa: f002 fb2c bl 8003556 } 8000efe: bf00 nop 8000f00: 3708 adds r7, #8 8000f02: 46bd mov sp, r7 8000f04: bd80 pop {r7, pc} 8000f06: bf00 nop 8000f08: 40021000 .word 0x40021000 08000f0c : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 8000f0c: b580 push {r7, lr} 8000f0e: b088 sub sp, #32 8000f10: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000f12: f107 030c add.w r3, r7, #12 8000f16: 2200 movs r2, #0 8000f18: 601a str r2, [r3, #0] 8000f1a: 605a str r2, [r3, #4] 8000f1c: 609a str r2, [r3, #8] 8000f1e: 60da str r2, [r3, #12] 8000f20: 611a str r2, [r3, #16] /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOF_CLK_ENABLE(); 8000f22: 4b1e ldr r3, [pc, #120] @ (8000f9c ) 8000f24: 6cdb ldr r3, [r3, #76] @ 0x4c 8000f26: 4a1d ldr r2, [pc, #116] @ (8000f9c ) 8000f28: f043 0320 orr.w r3, r3, #32 8000f2c: 64d3 str r3, [r2, #76] @ 0x4c 8000f2e: 4b1b ldr r3, [pc, #108] @ (8000f9c ) 8000f30: 6cdb ldr r3, [r3, #76] @ 0x4c 8000f32: f003 0320 and.w r3, r3, #32 8000f36: 60bb str r3, [r7, #8] 8000f38: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); 8000f3a: 4b18 ldr r3, [pc, #96] @ (8000f9c ) 8000f3c: 6cdb ldr r3, [r3, #76] @ 0x4c 8000f3e: 4a17 ldr r2, [pc, #92] @ (8000f9c ) 8000f40: f043 0302 orr.w r3, r3, #2 8000f44: 64d3 str r3, [r2, #76] @ 0x4c 8000f46: 4b15 ldr r3, [pc, #84] @ (8000f9c ) 8000f48: 6cdb ldr r3, [r3, #76] @ 0x4c 8000f4a: f003 0302 and.w r3, r3, #2 8000f4e: 607b str r3, [r7, #4] 8000f50: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOA_CLK_ENABLE(); 8000f52: 4b12 ldr r3, [pc, #72] @ (8000f9c ) 8000f54: 6cdb ldr r3, [r3, #76] @ 0x4c 8000f56: 4a11 ldr r2, [pc, #68] @ (8000f9c ) 8000f58: f043 0301 orr.w r3, r3, #1 8000f5c: 64d3 str r3, [r2, #76] @ 0x4c 8000f5e: 4b0f ldr r3, [pc, #60] @ (8000f9c ) 8000f60: 6cdb ldr r3, [r3, #76] @ 0x4c 8000f62: f003 0301 and.w r3, r3, #1 8000f66: 603b str r3, [r7, #0] 8000f68: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, ENABLE_DRVA_Pin|ENABLE_DRVB_Pin, GPIO_PIN_RESET); 8000f6a: 2200 movs r2, #0 8000f6c: f44f 51c0 mov.w r1, #6144 @ 0x1800 8000f70: 480b ldr r0, [pc, #44] @ (8000fa0 ) 8000f72: f003 f969 bl 8004248 /*Configure GPIO pins : ENABLE_DRVA_Pin ENABLE_DRVB_Pin */ GPIO_InitStruct.Pin = ENABLE_DRVA_Pin|ENABLE_DRVB_Pin; 8000f76: f44f 53c0 mov.w r3, #6144 @ 0x1800 8000f7a: 60fb str r3, [r7, #12] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000f7c: 2301 movs r3, #1 8000f7e: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 8000f80: 2302 movs r3, #2 8000f82: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000f84: 2300 movs r3, #0 8000f86: 61bb str r3, [r7, #24] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8000f88: f107 030c add.w r3, r7, #12 8000f8c: 4619 mov r1, r3 8000f8e: 4804 ldr r0, [pc, #16] @ (8000fa0 ) 8000f90: f002 ffd8 bl 8003f44 /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } 8000f94: bf00 nop 8000f96: 3720 adds r7, #32 8000f98: 46bd mov sp, r7 8000f9a: bd80 pop {r7, pc} 8000f9c: 40021000 .word 0x40021000 8000fa0: 48000400 .word 0x48000400 08000fa4 : /* USER CODE BEGIN 4 */ void HAL_TIM_PeriodElapsedCallback (TIM_HandleTypeDef * htim) { 8000fa4: b580 push {r7, lr} 8000fa6: b082 sub sp, #8 8000fa8: af00 add r7, sp, #0 8000faa: 6078 str r0, [r7, #4] if (htim == &htim1) // 50khz timer 8000fac: 687b ldr r3, [r7, #4] 8000fae: 4a2e ldr r2, [pc, #184] @ (8001068 ) 8000fb0: 4293 cmp r3, r2 8000fb2: d154 bne.n 800105e { time++; // current time in 20us increments; -> 1000 = one period 8000fb4: 4b2d ldr r3, [pc, #180] @ (800106c ) 8000fb6: 881b ldrh r3, [r3, #0] 8000fb8: 3301 adds r3, #1 8000fba: b29a uxth r2, r3 8000fbc: 4b2b ldr r3, [pc, #172] @ (800106c ) 8000fbe: 801a strh r2, [r3, #0] if (time >=1000) time = 0; 8000fc0: 4b2a ldr r3, [pc, #168] @ (800106c ) 8000fc2: 881b ldrh r3, [r3, #0] 8000fc4: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8000fc8: d302 bcc.n 8000fd0 8000fca: 4b28 ldr r3, [pc, #160] @ (800106c ) 8000fcc: 2200 movs r2, #0 8000fce: 801a strh r2, [r3, #0] if ((time >= 0) && (time < 500)) 8000fd0: 4b26 ldr r3, [pc, #152] @ (800106c ) 8000fd2: 881b ldrh r3, [r3, #0] 8000fd4: f5b3 7ffa cmp.w r3, #500 @ 0x1f4 8000fd8: d221 bcs.n 800101e { // positive half // set hrtim->A with pwm_sine[time] //HRTIM1->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].CMP1xR = pwm_sine[time]; HRTIM1->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].CMP1xR = 0; 8000fda: 4b25 ldr r3, [pc, #148] @ (8001070 ) 8000fdc: 2200 movs r2, #0 8000fde: f8c3 209c str.w r2, [r3, #156] @ 0x9c HRTIM1->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].CMP1xR = pwm_sine[time]; 8000fe2: 4b22 ldr r3, [pc, #136] @ (800106c ) 8000fe4: 881b ldrh r3, [r3, #0] 8000fe6: 461a mov r2, r3 8000fe8: 4b22 ldr r3, [pc, #136] @ (8001074 ) 8000fea: f833 2012 ldrh.w r2, [r3, r2, lsl #1] 8000fee: 4b20 ldr r3, [pc, #128] @ (8001070 ) 8000ff0: f8c3 211c str.w r2, [r3, #284] @ 0x11c HAL_HRTIM_WaveformOutputStop(&hhrtim1,HRTIM_OUTPUT_TB1|HRTIM_OUTPUT_TA2); 8000ff4: 2106 movs r1, #6 8000ff6: 4820 ldr r0, [pc, #128] @ (8001078 ) 8000ff8: f003 fdb6 bl 8004b68 HAL_HRTIM_WaveformOutputStart(&hhrtim1,HRTIM_OUTPUT_TA1|HRTIM_OUTPUT_TB2); 8000ffc: 2109 movs r1, #9 8000ffe: 481e ldr r0, [pc, #120] @ (8001078 ) 8001000: f003 fd85 bl 8004b0e HAL_GPIO_WritePin(ENABLE_DRVA_GPIO_Port,ENABLE_DRVA_Pin,GPIO_PIN_SET); 8001004: 2201 movs r2, #1 8001006: f44f 6100 mov.w r1, #2048 @ 0x800 800100a: 481c ldr r0, [pc, #112] @ (800107c ) 800100c: f003 f91c bl 8004248 HAL_GPIO_WritePin(ENABLE_DRVB_GPIO_Port,ENABLE_DRVB_Pin,GPIO_PIN_SET); 8001010: 2201 movs r2, #1 8001012: f44f 5180 mov.w r1, #4096 @ 0x1000 8001016: 4819 ldr r0, [pc, #100] @ (800107c ) 8001018: f003 f916 bl 8004248 HAL_HRTIM_WaveformOutputStop(&hhrtim1,HRTIM_OUTPUT_TA1|HRTIM_OUTPUT_TB2); HAL_HRTIM_WaveformOutputStart(&hhrtim1,HRTIM_OUTPUT_TB1|HRTIM_OUTPUT_TA2); } } } 800101c: e01f b.n 800105e else if ((time >= 500) && (time < 1000)) 800101e: 4b13 ldr r3, [pc, #76] @ (800106c ) 8001020: 881b ldrh r3, [r3, #0] 8001022: f5b3 7ffa cmp.w r3, #500 @ 0x1f4 8001026: d31a bcc.n 800105e 8001028: 4b10 ldr r3, [pc, #64] @ (800106c ) 800102a: 881b ldrh r3, [r3, #0] 800102c: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8001030: d215 bcs.n 800105e HRTIM1->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].CMP1xR = 0; 8001032: 4b0f ldr r3, [pc, #60] @ (8001070 ) 8001034: 2200 movs r2, #0 8001036: f8c3 211c str.w r2, [r3, #284] @ 0x11c HRTIM1->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].CMP1xR = pwm_sine[time-500]; 800103a: 4b0c ldr r3, [pc, #48] @ (800106c ) 800103c: 881b ldrh r3, [r3, #0] 800103e: f5a3 73fa sub.w r3, r3, #500 @ 0x1f4 8001042: 4a0c ldr r2, [pc, #48] @ (8001074 ) 8001044: f832 2013 ldrh.w r2, [r2, r3, lsl #1] 8001048: 4b09 ldr r3, [pc, #36] @ (8001070 ) 800104a: f8c3 209c str.w r2, [r3, #156] @ 0x9c HAL_HRTIM_WaveformOutputStop(&hhrtim1,HRTIM_OUTPUT_TA1|HRTIM_OUTPUT_TB2); 800104e: 2109 movs r1, #9 8001050: 4809 ldr r0, [pc, #36] @ (8001078 ) 8001052: f003 fd89 bl 8004b68 HAL_HRTIM_WaveformOutputStart(&hhrtim1,HRTIM_OUTPUT_TB1|HRTIM_OUTPUT_TA2); 8001056: 2106 movs r1, #6 8001058: 4807 ldr r0, [pc, #28] @ (8001078 ) 800105a: f003 fd58 bl 8004b0e } 800105e: bf00 nop 8001060: 3708 adds r7, #8 8001062: 46bd mov sp, r7 8001064: bd80 pop {r7, pc} 8001066: bf00 nop 8001068: 2000038c .word 0x2000038c 800106c: 2000046c .word 0x2000046c 8001070: 40016800 .word 0x40016800 8001074: 080082fc .word 0x080082fc 8001078: 20000290 .word 0x20000290 800107c: 48000400 .word 0x48000400 08001080 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8001080: b580 push {r7, lr} 8001082: b086 sub sp, #24 8001084: af00 add r7, sp, #0 /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ char etext[20] = "Error \n\r"; 8001086: 4a0d ldr r2, [pc, #52] @ (80010bc ) 8001088: 1d3b adds r3, r7, #4 800108a: ca07 ldmia r2, {r0, r1, r2} 800108c: c303 stmia r3!, {r0, r1} 800108e: 701a strb r2, [r3, #0] 8001090: f107 030d add.w r3, r7, #13 8001094: 2200 movs r2, #0 8001096: 601a str r2, [r3, #0] 8001098: 605a str r2, [r3, #4] 800109a: f8c3 2007 str.w r2, [r3, #7] HAL_UART_Transmit(&huart1,(uint8_t *)(etext),strlen(etext),10); 800109e: 1d3b adds r3, r7, #4 80010a0: 4618 mov r0, r3 80010a2: f7ff f8b9 bl 8000218 80010a6: 4603 mov r3, r0 80010a8: b29a uxth r2, r3 80010aa: 1d39 adds r1, r7, #4 80010ac: 230a movs r3, #10 80010ae: 4804 ldr r0, [pc, #16] @ (80010c0 ) 80010b0: f006 fa2c bl 800750c \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 80010b4: b672 cpsid i } 80010b6: bf00 nop __disable_irq(); while (1) 80010b8: bf00 nop 80010ba: e7fd b.n 80010b8 80010bc: 080082e8 .word 0x080082e8 80010c0: 200003d8 .word 0x200003d8 080010c4 : void HAL_HRTIM_MspPostInit(HRTIM_HandleTypeDef *hhrtim); /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 80010c4: b580 push {r7, lr} 80010c6: b082 sub sp, #8 80010c8: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 80010ca: 4b11 ldr r3, [pc, #68] @ (8001110 ) 80010cc: 6e1b ldr r3, [r3, #96] @ 0x60 80010ce: 4a10 ldr r2, [pc, #64] @ (8001110 ) 80010d0: f043 0301 orr.w r3, r3, #1 80010d4: 6613 str r3, [r2, #96] @ 0x60 80010d6: 4b0e ldr r3, [pc, #56] @ (8001110 ) 80010d8: 6e1b ldr r3, [r3, #96] @ 0x60 80010da: f003 0301 and.w r3, r3, #1 80010de: 607b str r3, [r7, #4] 80010e0: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 80010e2: 4b0b ldr r3, [pc, #44] @ (8001110 ) 80010e4: 6d9b ldr r3, [r3, #88] @ 0x58 80010e6: 4a0a ldr r2, [pc, #40] @ (8001110 ) 80010e8: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80010ec: 6593 str r3, [r2, #88] @ 0x58 80010ee: 4b08 ldr r3, [pc, #32] @ (8001110 ) 80010f0: 6d9b ldr r3, [r3, #88] @ 0x58 80010f2: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80010f6: 603b str r3, [r7, #0] 80010f8: 683b ldr r3, [r7, #0] /* System interrupt init*/ /** Configure the internal voltage reference buffer high impedance mode */ HAL_SYSCFG_VREFBUF_HighImpedanceConfig(SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE); 80010fa: 2002 movs r0, #2 80010fc: f000 fbe2 bl 80018c4 /** Disable the Internal Voltage Reference buffer */ HAL_SYSCFG_DisableVREFBUF(); 8001100: f000 fbf4 bl 80018ec /** Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral */ HAL_PWREx_DisableUCPDDeadBattery(); 8001104: f004 fc9c bl 8005a40 /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8001108: bf00 nop 800110a: 3708 adds r7, #8 800110c: 46bd mov sp, r7 800110e: bd80 pop {r7, pc} 8001110: 40021000 .word 0x40021000 08001114 : * This function configures the hardware resources used in this example * @param hadc: ADC handle pointer * @retval None */ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { 8001114: b580 push {r7, lr} 8001116: b0a0 sub sp, #128 @ 0x80 8001118: af00 add r7, sp, #0 800111a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800111c: f107 036c add.w r3, r7, #108 @ 0x6c 8001120: 2200 movs r2, #0 8001122: 601a str r2, [r3, #0] 8001124: 605a str r2, [r3, #4] 8001126: 609a str r2, [r3, #8] 8001128: 60da str r2, [r3, #12] 800112a: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 800112c: f107 0318 add.w r3, r7, #24 8001130: 2254 movs r2, #84 @ 0x54 8001132: 2100 movs r1, #0 8001134: 4618 mov r0, r3 8001136: f007 f895 bl 8008264 if(hadc->Instance==ADC3) 800113a: 687b ldr r3, [r7, #4] 800113c: 681b ldr r3, [r3, #0] 800113e: 4a70 ldr r2, [pc, #448] @ (8001300 ) 8001140: 4293 cmp r3, r2 8001142: d16a bne.n 800121a /* USER CODE END ADC3_MspInit 0 */ /** Initializes the peripherals clocks */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC345; 8001144: f44f 3380 mov.w r3, #65536 @ 0x10000 8001148: 61bb str r3, [r7, #24] PeriphClkInit.Adc345ClockSelection = RCC_ADC345CLKSOURCE_SYSCLK; 800114a: f04f 4300 mov.w r3, #2147483648 @ 0x80000000 800114e: 663b str r3, [r7, #96] @ 0x60 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 8001150: f107 0318 add.w r3, r7, #24 8001154: 4618 mov r0, r3 8001156: f005 f9b1 bl 80064bc 800115a: 4603 mov r3, r0 800115c: 2b00 cmp r3, #0 800115e: d001 beq.n 8001164 { Error_Handler(); 8001160: f7ff ff8e bl 8001080 } /* Peripheral clock enable */ HAL_RCC_ADC345_CLK_ENABLED++; 8001164: 4b67 ldr r3, [pc, #412] @ (8001304 ) 8001166: 681b ldr r3, [r3, #0] 8001168: 3301 adds r3, #1 800116a: 4a66 ldr r2, [pc, #408] @ (8001304 ) 800116c: 6013 str r3, [r2, #0] if(HAL_RCC_ADC345_CLK_ENABLED==1){ 800116e: 4b65 ldr r3, [pc, #404] @ (8001304 ) 8001170: 681b ldr r3, [r3, #0] 8001172: 2b01 cmp r3, #1 8001174: d10b bne.n 800118e __HAL_RCC_ADC345_CLK_ENABLE(); 8001176: 4b64 ldr r3, [pc, #400] @ (8001308 ) 8001178: 6cdb ldr r3, [r3, #76] @ 0x4c 800117a: 4a63 ldr r2, [pc, #396] @ (8001308 ) 800117c: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8001180: 64d3 str r3, [r2, #76] @ 0x4c 8001182: 4b61 ldr r3, [pc, #388] @ (8001308 ) 8001184: 6cdb ldr r3, [r3, #76] @ 0x4c 8001186: f403 4380 and.w r3, r3, #16384 @ 0x4000 800118a: 617b str r3, [r7, #20] 800118c: 697b ldr r3, [r7, #20] } __HAL_RCC_GPIOB_CLK_ENABLE(); 800118e: 4b5e ldr r3, [pc, #376] @ (8001308 ) 8001190: 6cdb ldr r3, [r3, #76] @ 0x4c 8001192: 4a5d ldr r2, [pc, #372] @ (8001308 ) 8001194: f043 0302 orr.w r3, r3, #2 8001198: 64d3 str r3, [r2, #76] @ 0x4c 800119a: 4b5b ldr r3, [pc, #364] @ (8001308 ) 800119c: 6cdb ldr r3, [r3, #76] @ 0x4c 800119e: f003 0302 and.w r3, r3, #2 80011a2: 613b str r3, [r7, #16] 80011a4: 693b ldr r3, [r7, #16] /**ADC3 GPIO Configuration PB13 ------> ADC3_IN5 */ GPIO_InitStruct.Pin = VOLTAGE_Pin; 80011a6: f44f 5300 mov.w r3, #8192 @ 0x2000 80011aa: 66fb str r3, [r7, #108] @ 0x6c GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 80011ac: 2303 movs r3, #3 80011ae: 673b str r3, [r7, #112] @ 0x70 GPIO_InitStruct.Pull = GPIO_NOPULL; 80011b0: 2300 movs r3, #0 80011b2: 677b str r3, [r7, #116] @ 0x74 HAL_GPIO_Init(VOLTAGE_GPIO_Port, &GPIO_InitStruct); 80011b4: f107 036c add.w r3, r7, #108 @ 0x6c 80011b8: 4619 mov r1, r3 80011ba: 4854 ldr r0, [pc, #336] @ (800130c ) 80011bc: f002 fec2 bl 8003f44 /* ADC3 DMA Init */ /* ADC3 Init */ hdma_adc3.Instance = DMA1_Channel1; 80011c0: 4b53 ldr r3, [pc, #332] @ (8001310 ) 80011c2: 4a54 ldr r2, [pc, #336] @ (8001314 ) 80011c4: 601a str r2, [r3, #0] hdma_adc3.Init.Request = DMA_REQUEST_ADC3; 80011c6: 4b52 ldr r3, [pc, #328] @ (8001310 ) 80011c8: 2225 movs r2, #37 @ 0x25 80011ca: 605a str r2, [r3, #4] hdma_adc3.Init.Direction = DMA_PERIPH_TO_MEMORY; 80011cc: 4b50 ldr r3, [pc, #320] @ (8001310 ) 80011ce: 2200 movs r2, #0 80011d0: 609a str r2, [r3, #8] hdma_adc3.Init.PeriphInc = DMA_PINC_DISABLE; 80011d2: 4b4f ldr r3, [pc, #316] @ (8001310 ) 80011d4: 2200 movs r2, #0 80011d6: 60da str r2, [r3, #12] hdma_adc3.Init.MemInc = DMA_MINC_ENABLE; 80011d8: 4b4d ldr r3, [pc, #308] @ (8001310 ) 80011da: 2280 movs r2, #128 @ 0x80 80011dc: 611a str r2, [r3, #16] hdma_adc3.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 80011de: 4b4c ldr r3, [pc, #304] @ (8001310 ) 80011e0: f44f 7280 mov.w r2, #256 @ 0x100 80011e4: 615a str r2, [r3, #20] hdma_adc3.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 80011e6: 4b4a ldr r3, [pc, #296] @ (8001310 ) 80011e8: f44f 6280 mov.w r2, #1024 @ 0x400 80011ec: 619a str r2, [r3, #24] hdma_adc3.Init.Mode = DMA_CIRCULAR; 80011ee: 4b48 ldr r3, [pc, #288] @ (8001310 ) 80011f0: 2220 movs r2, #32 80011f2: 61da str r2, [r3, #28] hdma_adc3.Init.Priority = DMA_PRIORITY_HIGH; 80011f4: 4b46 ldr r3, [pc, #280] @ (8001310 ) 80011f6: f44f 5200 mov.w r2, #8192 @ 0x2000 80011fa: 621a str r2, [r3, #32] if (HAL_DMA_Init(&hdma_adc3) != HAL_OK) 80011fc: 4844 ldr r0, [pc, #272] @ (8001310 ) 80011fe: f002 fc3b bl 8003a78 8001202: 4603 mov r3, r0 8001204: 2b00 cmp r3, #0 8001206: d001 beq.n 800120c { Error_Handler(); 8001208: f7ff ff3a bl 8001080 } __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc3); 800120c: 687b ldr r3, [r7, #4] 800120e: 4a40 ldr r2, [pc, #256] @ (8001310 ) 8001210: 655a str r2, [r3, #84] @ 0x54 8001212: 4a3f ldr r2, [pc, #252] @ (8001310 ) 8001214: 687b ldr r3, [r7, #4] 8001216: 6293 str r3, [r2, #40] @ 0x28 /* USER CODE BEGIN ADC4_MspInit 1 */ /* USER CODE END ADC4_MspInit 1 */ } } 8001218: e06e b.n 80012f8 else if(hadc->Instance==ADC4) 800121a: 687b ldr r3, [r7, #4] 800121c: 681b ldr r3, [r3, #0] 800121e: 4a3e ldr r2, [pc, #248] @ (8001318 ) 8001220: 4293 cmp r3, r2 8001222: d169 bne.n 80012f8 PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC345; 8001224: f44f 3380 mov.w r3, #65536 @ 0x10000 8001228: 61bb str r3, [r7, #24] PeriphClkInit.Adc345ClockSelection = RCC_ADC345CLKSOURCE_SYSCLK; 800122a: f04f 4300 mov.w r3, #2147483648 @ 0x80000000 800122e: 663b str r3, [r7, #96] @ 0x60 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 8001230: f107 0318 add.w r3, r7, #24 8001234: 4618 mov r0, r3 8001236: f005 f941 bl 80064bc 800123a: 4603 mov r3, r0 800123c: 2b00 cmp r3, #0 800123e: d001 beq.n 8001244 Error_Handler(); 8001240: f7ff ff1e bl 8001080 HAL_RCC_ADC345_CLK_ENABLED++; 8001244: 4b2f ldr r3, [pc, #188] @ (8001304 ) 8001246: 681b ldr r3, [r3, #0] 8001248: 3301 adds r3, #1 800124a: 4a2e ldr r2, [pc, #184] @ (8001304 ) 800124c: 6013 str r3, [r2, #0] if(HAL_RCC_ADC345_CLK_ENABLED==1){ 800124e: 4b2d ldr r3, [pc, #180] @ (8001304 ) 8001250: 681b ldr r3, [r3, #0] 8001252: 2b01 cmp r3, #1 8001254: d10b bne.n 800126e __HAL_RCC_ADC345_CLK_ENABLE(); 8001256: 4b2c ldr r3, [pc, #176] @ (8001308 ) 8001258: 6cdb ldr r3, [r3, #76] @ 0x4c 800125a: 4a2b ldr r2, [pc, #172] @ (8001308 ) 800125c: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8001260: 64d3 str r3, [r2, #76] @ 0x4c 8001262: 4b29 ldr r3, [pc, #164] @ (8001308 ) 8001264: 6cdb ldr r3, [r3, #76] @ 0x4c 8001266: f403 4380 and.w r3, r3, #16384 @ 0x4000 800126a: 60fb str r3, [r7, #12] 800126c: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOB_CLK_ENABLE(); 800126e: 4b26 ldr r3, [pc, #152] @ (8001308 ) 8001270: 6cdb ldr r3, [r3, #76] @ 0x4c 8001272: 4a25 ldr r2, [pc, #148] @ (8001308 ) 8001274: f043 0302 orr.w r3, r3, #2 8001278: 64d3 str r3, [r2, #76] @ 0x4c 800127a: 4b23 ldr r3, [pc, #140] @ (8001308 ) 800127c: 6cdb ldr r3, [r3, #76] @ 0x4c 800127e: f003 0302 and.w r3, r3, #2 8001282: 60bb str r3, [r7, #8] 8001284: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = CURRENT_Pin; 8001286: f44f 4380 mov.w r3, #16384 @ 0x4000 800128a: 66fb str r3, [r7, #108] @ 0x6c GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 800128c: 2303 movs r3, #3 800128e: 673b str r3, [r7, #112] @ 0x70 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001290: 2300 movs r3, #0 8001292: 677b str r3, [r7, #116] @ 0x74 HAL_GPIO_Init(CURRENT_GPIO_Port, &GPIO_InitStruct); 8001294: f107 036c add.w r3, r7, #108 @ 0x6c 8001298: 4619 mov r1, r3 800129a: 481c ldr r0, [pc, #112] @ (800130c ) 800129c: f002 fe52 bl 8003f44 hdma_adc4.Instance = DMA1_Channel2; 80012a0: 4b1e ldr r3, [pc, #120] @ (800131c ) 80012a2: 4a1f ldr r2, [pc, #124] @ (8001320 ) 80012a4: 601a str r2, [r3, #0] hdma_adc4.Init.Request = DMA_REQUEST_ADC4; 80012a6: 4b1d ldr r3, [pc, #116] @ (800131c ) 80012a8: 2226 movs r2, #38 @ 0x26 80012aa: 605a str r2, [r3, #4] hdma_adc4.Init.Direction = DMA_PERIPH_TO_MEMORY; 80012ac: 4b1b ldr r3, [pc, #108] @ (800131c ) 80012ae: 2200 movs r2, #0 80012b0: 609a str r2, [r3, #8] hdma_adc4.Init.PeriphInc = DMA_PINC_DISABLE; 80012b2: 4b1a ldr r3, [pc, #104] @ (800131c ) 80012b4: 2200 movs r2, #0 80012b6: 60da str r2, [r3, #12] hdma_adc4.Init.MemInc = DMA_MINC_ENABLE; 80012b8: 4b18 ldr r3, [pc, #96] @ (800131c ) 80012ba: 2280 movs r2, #128 @ 0x80 80012bc: 611a str r2, [r3, #16] hdma_adc4.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 80012be: 4b17 ldr r3, [pc, #92] @ (800131c ) 80012c0: f44f 7280 mov.w r2, #256 @ 0x100 80012c4: 615a str r2, [r3, #20] hdma_adc4.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 80012c6: 4b15 ldr r3, [pc, #84] @ (800131c ) 80012c8: f44f 6280 mov.w r2, #1024 @ 0x400 80012cc: 619a str r2, [r3, #24] hdma_adc4.Init.Mode = DMA_CIRCULAR; 80012ce: 4b13 ldr r3, [pc, #76] @ (800131c ) 80012d0: 2220 movs r2, #32 80012d2: 61da str r2, [r3, #28] hdma_adc4.Init.Priority = DMA_PRIORITY_VERY_HIGH; 80012d4: 4b11 ldr r3, [pc, #68] @ (800131c ) 80012d6: f44f 5240 mov.w r2, #12288 @ 0x3000 80012da: 621a str r2, [r3, #32] if (HAL_DMA_Init(&hdma_adc4) != HAL_OK) 80012dc: 480f ldr r0, [pc, #60] @ (800131c ) 80012de: f002 fbcb bl 8003a78 80012e2: 4603 mov r3, r0 80012e4: 2b00 cmp r3, #0 80012e6: d001 beq.n 80012ec Error_Handler(); 80012e8: f7ff feca bl 8001080 __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc4); 80012ec: 687b ldr r3, [r7, #4] 80012ee: 4a0b ldr r2, [pc, #44] @ (800131c ) 80012f0: 655a str r2, [r3, #84] @ 0x54 80012f2: 4a0a ldr r2, [pc, #40] @ (800131c ) 80012f4: 687b ldr r3, [r7, #4] 80012f6: 6293 str r3, [r2, #40] @ 0x28 } 80012f8: bf00 nop 80012fa: 3780 adds r7, #128 @ 0x80 80012fc: 46bd mov sp, r7 80012fe: bd80 pop {r7, pc} 8001300: 50000400 .word 0x50000400 8001304: 20000470 .word 0x20000470 8001308: 40021000 .word 0x40021000 800130c: 48000400 .word 0x48000400 8001310: 20000100 .word 0x20000100 8001314: 40020008 .word 0x40020008 8001318: 50000500 .word 0x50000500 800131c: 20000160 .word 0x20000160 8001320: 4002001c .word 0x4002001c 08001324 : * This function configures the hardware resources used in this example * @param hcomp: COMP handle pointer * @retval None */ void HAL_COMP_MspInit(COMP_HandleTypeDef* hcomp) { 8001324: b580 push {r7, lr} 8001326: b08a sub sp, #40 @ 0x28 8001328: af00 add r7, sp, #0 800132a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800132c: f107 0314 add.w r3, r7, #20 8001330: 2200 movs r2, #0 8001332: 601a str r2, [r3, #0] 8001334: 605a str r2, [r3, #4] 8001336: 609a str r2, [r3, #8] 8001338: 60da str r2, [r3, #12] 800133a: 611a str r2, [r3, #16] if(hcomp->Instance==COMP5) 800133c: 687b ldr r3, [r7, #4] 800133e: 681b ldr r3, [r3, #0] 8001340: 4a1f ldr r2, [pc, #124] @ (80013c0 ) 8001342: 4293 cmp r3, r2 8001344: d119 bne.n 800137a { /* USER CODE BEGIN COMP5_MspInit 0 */ /* USER CODE END COMP5_MspInit 0 */ __HAL_RCC_GPIOB_CLK_ENABLE(); 8001346: 4b1f ldr r3, [pc, #124] @ (80013c4 ) 8001348: 6cdb ldr r3, [r3, #76] @ 0x4c 800134a: 4a1e ldr r2, [pc, #120] @ (80013c4 ) 800134c: f043 0302 orr.w r3, r3, #2 8001350: 64d3 str r3, [r2, #76] @ 0x4c 8001352: 4b1c ldr r3, [pc, #112] @ (80013c4 ) 8001354: 6cdb ldr r3, [r3, #76] @ 0x4c 8001356: f003 0302 and.w r3, r3, #2 800135a: 613b str r3, [r7, #16] 800135c: 693b ldr r3, [r7, #16] /**COMP5 GPIO Configuration PB13 ------> COMP5_INP */ GPIO_InitStruct.Pin = VOLTAGE_Pin; 800135e: f44f 5300 mov.w r3, #8192 @ 0x2000 8001362: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8001364: 2303 movs r3, #3 8001366: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001368: 2300 movs r3, #0 800136a: 61fb str r3, [r7, #28] HAL_GPIO_Init(VOLTAGE_GPIO_Port, &GPIO_InitStruct); 800136c: f107 0314 add.w r3, r7, #20 8001370: 4619 mov r1, r3 8001372: 4815 ldr r0, [pc, #84] @ (80013c8 ) 8001374: f002 fde6 bl 8003f44 /* USER CODE BEGIN COMP7_MspInit 1 */ /* USER CODE END COMP7_MspInit 1 */ } } 8001378: e01d b.n 80013b6 else if(hcomp->Instance==COMP7) 800137a: 687b ldr r3, [r7, #4] 800137c: 681b ldr r3, [r3, #0] 800137e: 4a13 ldr r2, [pc, #76] @ (80013cc ) 8001380: 4293 cmp r3, r2 8001382: d118 bne.n 80013b6 __HAL_RCC_GPIOB_CLK_ENABLE(); 8001384: 4b0f ldr r3, [pc, #60] @ (80013c4 ) 8001386: 6cdb ldr r3, [r3, #76] @ 0x4c 8001388: 4a0e ldr r2, [pc, #56] @ (80013c4 ) 800138a: f043 0302 orr.w r3, r3, #2 800138e: 64d3 str r3, [r2, #76] @ 0x4c 8001390: 4b0c ldr r3, [pc, #48] @ (80013c4 ) 8001392: 6cdb ldr r3, [r3, #76] @ 0x4c 8001394: f003 0302 and.w r3, r3, #2 8001398: 60fb str r3, [r7, #12] 800139a: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = CURRENT_Pin; 800139c: f44f 4380 mov.w r3, #16384 @ 0x4000 80013a0: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 80013a2: 2303 movs r3, #3 80013a4: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80013a6: 2300 movs r3, #0 80013a8: 61fb str r3, [r7, #28] HAL_GPIO_Init(CURRENT_GPIO_Port, &GPIO_InitStruct); 80013aa: f107 0314 add.w r3, r7, #20 80013ae: 4619 mov r1, r3 80013b0: 4805 ldr r0, [pc, #20] @ (80013c8 ) 80013b2: f002 fdc7 bl 8003f44 } 80013b6: bf00 nop 80013b8: 3728 adds r7, #40 @ 0x28 80013ba: 46bd mov sp, r7 80013bc: bd80 pop {r7, pc} 80013be: bf00 nop 80013c0: 40010210 .word 0x40010210 80013c4: 40021000 .word 0x40021000 80013c8: 48000400 .word 0x48000400 80013cc: 40010218 .word 0x40010218 080013d0 : * This function configures the hardware resources used in this example * @param hcordic: CORDIC handle pointer * @retval None */ void HAL_CORDIC_MspInit(CORDIC_HandleTypeDef* hcordic) { 80013d0: b480 push {r7} 80013d2: b085 sub sp, #20 80013d4: af00 add r7, sp, #0 80013d6: 6078 str r0, [r7, #4] if(hcordic->Instance==CORDIC) 80013d8: 687b ldr r3, [r7, #4] 80013da: 681b ldr r3, [r3, #0] 80013dc: 4a0a ldr r2, [pc, #40] @ (8001408 ) 80013de: 4293 cmp r3, r2 80013e0: d10b bne.n 80013fa { /* USER CODE BEGIN CORDIC_MspInit 0 */ /* USER CODE END CORDIC_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_CORDIC_CLK_ENABLE(); 80013e2: 4b0a ldr r3, [pc, #40] @ (800140c ) 80013e4: 6c9b ldr r3, [r3, #72] @ 0x48 80013e6: 4a09 ldr r2, [pc, #36] @ (800140c ) 80013e8: f043 0308 orr.w r3, r3, #8 80013ec: 6493 str r3, [r2, #72] @ 0x48 80013ee: 4b07 ldr r3, [pc, #28] @ (800140c ) 80013f0: 6c9b ldr r3, [r3, #72] @ 0x48 80013f2: f003 0308 and.w r3, r3, #8 80013f6: 60fb str r3, [r7, #12] 80013f8: 68fb ldr r3, [r7, #12] /* USER CODE END CORDIC_MspInit 1 */ } } 80013fa: bf00 nop 80013fc: 3714 adds r7, #20 80013fe: 46bd mov sp, r7 8001400: f85d 7b04 ldr.w r7, [sp], #4 8001404: 4770 bx lr 8001406: bf00 nop 8001408: 40020c00 .word 0x40020c00 800140c: 40021000 .word 0x40021000 08001410 : * This function configures the hardware resources used in this example * @param hdac: DAC handle pointer * @retval None */ void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) { 8001410: b480 push {r7} 8001412: b085 sub sp, #20 8001414: af00 add r7, sp, #0 8001416: 6078 str r0, [r7, #4] if(hdac->Instance==DAC1) 8001418: 687b ldr r3, [r7, #4] 800141a: 681b ldr r3, [r3, #0] 800141c: 4a13 ldr r2, [pc, #76] @ (800146c ) 800141e: 4293 cmp r3, r2 8001420: d10c bne.n 800143c { /* USER CODE BEGIN DAC1_MspInit 0 */ /* USER CODE END DAC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_DAC1_CLK_ENABLE(); 8001422: 4b13 ldr r3, [pc, #76] @ (8001470 ) 8001424: 6cdb ldr r3, [r3, #76] @ 0x4c 8001426: 4a12 ldr r2, [pc, #72] @ (8001470 ) 8001428: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800142c: 64d3 str r3, [r2, #76] @ 0x4c 800142e: 4b10 ldr r3, [pc, #64] @ (8001470 ) 8001430: 6cdb ldr r3, [r3, #76] @ 0x4c 8001432: f403 3380 and.w r3, r3, #65536 @ 0x10000 8001436: 60fb str r3, [r7, #12] 8001438: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN DAC4_MspInit 1 */ /* USER CODE END DAC4_MspInit 1 */ } } 800143a: e010 b.n 800145e else if(hdac->Instance==DAC4) 800143c: 687b ldr r3, [r7, #4] 800143e: 681b ldr r3, [r3, #0] 8001440: 4a0c ldr r2, [pc, #48] @ (8001474 ) 8001442: 4293 cmp r3, r2 8001444: d10b bne.n 800145e __HAL_RCC_DAC4_CLK_ENABLE(); 8001446: 4b0a ldr r3, [pc, #40] @ (8001470 ) 8001448: 6cdb ldr r3, [r3, #76] @ 0x4c 800144a: 4a09 ldr r2, [pc, #36] @ (8001470 ) 800144c: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8001450: 64d3 str r3, [r2, #76] @ 0x4c 8001452: 4b07 ldr r3, [pc, #28] @ (8001470 ) 8001454: 6cdb ldr r3, [r3, #76] @ 0x4c 8001456: f403 2300 and.w r3, r3, #524288 @ 0x80000 800145a: 60bb str r3, [r7, #8] 800145c: 68bb ldr r3, [r7, #8] } 800145e: bf00 nop 8001460: 3714 adds r7, #20 8001462: 46bd mov sp, r7 8001464: f85d 7b04 ldr.w r7, [sp], #4 8001468: 4770 bx lr 800146a: bf00 nop 800146c: 50000800 .word 0x50000800 8001470: 40021000 .word 0x40021000 8001474: 50001400 .word 0x50001400 08001478 : * This function configures the hardware resources used in this example * @param hfmac: FMAC handle pointer * @retval None */ void HAL_FMAC_MspInit(FMAC_HandleTypeDef* hfmac) { 8001478: b480 push {r7} 800147a: b085 sub sp, #20 800147c: af00 add r7, sp, #0 800147e: 6078 str r0, [r7, #4] if(hfmac->Instance==FMAC) 8001480: 687b ldr r3, [r7, #4] 8001482: 681b ldr r3, [r3, #0] 8001484: 4a0a ldr r2, [pc, #40] @ (80014b0 ) 8001486: 4293 cmp r3, r2 8001488: d10b bne.n 80014a2 { /* USER CODE BEGIN FMAC_MspInit 0 */ /* USER CODE END FMAC_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_FMAC_CLK_ENABLE(); 800148a: 4b0a ldr r3, [pc, #40] @ (80014b4 ) 800148c: 6c9b ldr r3, [r3, #72] @ 0x48 800148e: 4a09 ldr r2, [pc, #36] @ (80014b4 ) 8001490: f043 0310 orr.w r3, r3, #16 8001494: 6493 str r3, [r2, #72] @ 0x48 8001496: 4b07 ldr r3, [pc, #28] @ (80014b4 ) 8001498: 6c9b ldr r3, [r3, #72] @ 0x48 800149a: f003 0310 and.w r3, r3, #16 800149e: 60fb str r3, [r7, #12] 80014a0: 68fb ldr r3, [r7, #12] /* USER CODE END FMAC_MspInit 1 */ } } 80014a2: bf00 nop 80014a4: 3714 adds r7, #20 80014a6: 46bd mov sp, r7 80014a8: f85d 7b04 ldr.w r7, [sp], #4 80014ac: 4770 bx lr 80014ae: bf00 nop 80014b0: 40021400 .word 0x40021400 80014b4: 40021000 .word 0x40021000 080014b8 : * This function configures the hardware resources used in this example * @param hhrtim: HRTIM handle pointer * @retval None */ void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef* hhrtim) { 80014b8: b480 push {r7} 80014ba: b085 sub sp, #20 80014bc: af00 add r7, sp, #0 80014be: 6078 str r0, [r7, #4] if(hhrtim->Instance==HRTIM1) 80014c0: 687b ldr r3, [r7, #4] 80014c2: 681b ldr r3, [r3, #0] 80014c4: 4a0a ldr r2, [pc, #40] @ (80014f0 ) 80014c6: 4293 cmp r3, r2 80014c8: d10b bne.n 80014e2 { /* USER CODE BEGIN HRTIM1_MspInit 0 */ /* USER CODE END HRTIM1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_HRTIM1_CLK_ENABLE(); 80014ca: 4b0a ldr r3, [pc, #40] @ (80014f4 ) 80014cc: 6e1b ldr r3, [r3, #96] @ 0x60 80014ce: 4a09 ldr r2, [pc, #36] @ (80014f4 ) 80014d0: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 80014d4: 6613 str r3, [r2, #96] @ 0x60 80014d6: 4b07 ldr r3, [pc, #28] @ (80014f4 ) 80014d8: 6e1b ldr r3, [r3, #96] @ 0x60 80014da: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 80014de: 60fb str r3, [r7, #12] 80014e0: 68fb ldr r3, [r7, #12] /* USER CODE END HRTIM1_MspInit 1 */ } } 80014e2: bf00 nop 80014e4: 3714 adds r7, #20 80014e6: 46bd mov sp, r7 80014e8: f85d 7b04 ldr.w r7, [sp], #4 80014ec: 4770 bx lr 80014ee: bf00 nop 80014f0: 40016800 .word 0x40016800 80014f4: 40021000 .word 0x40021000 080014f8 : void HAL_HRTIM_MspPostInit(HRTIM_HandleTypeDef* hhrtim) { 80014f8: b580 push {r7, lr} 80014fa: b088 sub sp, #32 80014fc: af00 add r7, sp, #0 80014fe: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001500: f107 030c add.w r3, r7, #12 8001504: 2200 movs r2, #0 8001506: 601a str r2, [r3, #0] 8001508: 605a str r2, [r3, #4] 800150a: 609a str r2, [r3, #8] 800150c: 60da str r2, [r3, #12] 800150e: 611a str r2, [r3, #16] if(hhrtim->Instance==HRTIM1) 8001510: 687b ldr r3, [r7, #4] 8001512: 681b ldr r3, [r3, #0] 8001514: 4a12 ldr r2, [pc, #72] @ (8001560 ) 8001516: 4293 cmp r3, r2 8001518: d11d bne.n 8001556 { /* USER CODE BEGIN HRTIM1_MspPostInit 0 */ /* USER CODE END HRTIM1_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 800151a: 4b12 ldr r3, [pc, #72] @ (8001564 ) 800151c: 6cdb ldr r3, [r3, #76] @ 0x4c 800151e: 4a11 ldr r2, [pc, #68] @ (8001564 ) 8001520: f043 0301 orr.w r3, r3, #1 8001524: 64d3 str r3, [r2, #76] @ 0x4c 8001526: 4b0f ldr r3, [pc, #60] @ (8001564 ) 8001528: 6cdb ldr r3, [r3, #76] @ 0x4c 800152a: f003 0301 and.w r3, r3, #1 800152e: 60bb str r3, [r7, #8] 8001530: 68bb ldr r3, [r7, #8] PA8 ------> HRTIM1_CHA1 PA9 ------> HRTIM1_CHA2 PA10 ------> HRTIM1_CHB1 PA11 ------> HRTIM1_CHB2 */ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11; 8001532: f44f 6370 mov.w r3, #3840 @ 0xf00 8001536: 60fb str r3, [r7, #12] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001538: 2302 movs r3, #2 800153a: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; 800153c: 2300 movs r3, #0 800153e: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001540: 2303 movs r3, #3 8001542: 61bb str r3, [r7, #24] GPIO_InitStruct.Alternate = GPIO_AF13_HRTIM1; 8001544: 230d movs r3, #13 8001546: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001548: f107 030c add.w r3, r7, #12 800154c: 4619 mov r1, r3 800154e: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8001552: f002 fcf7 bl 8003f44 /* USER CODE BEGIN HRTIM1_MspPostInit 1 */ /* USER CODE END HRTIM1_MspPostInit 1 */ } } 8001556: bf00 nop 8001558: 3720 adds r7, #32 800155a: 46bd mov sp, r7 800155c: bd80 pop {r7, pc} 800155e: bf00 nop 8001560: 40016800 .word 0x40016800 8001564: 40021000 .word 0x40021000 08001568 : * This function configures the hardware resources used in this example * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { 8001568: b580 push {r7, lr} 800156a: b084 sub sp, #16 800156c: af00 add r7, sp, #0 800156e: 6078 str r0, [r7, #4] if(htim_base->Instance==TIM1) 8001570: 687b ldr r3, [r7, #4] 8001572: 681b ldr r3, [r3, #0] 8001574: 4a19 ldr r2, [pc, #100] @ (80015dc ) 8001576: 4293 cmp r3, r2 8001578: d12b bne.n 80015d2 { /* USER CODE BEGIN TIM1_MspInit 0 */ /* USER CODE END TIM1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM1_CLK_ENABLE(); 800157a: 4b19 ldr r3, [pc, #100] @ (80015e0 ) 800157c: 6e1b ldr r3, [r3, #96] @ 0x60 800157e: 4a18 ldr r2, [pc, #96] @ (80015e0 ) 8001580: f443 6300 orr.w r3, r3, #2048 @ 0x800 8001584: 6613 str r3, [r2, #96] @ 0x60 8001586: 4b16 ldr r3, [pc, #88] @ (80015e0 ) 8001588: 6e1b ldr r3, [r3, #96] @ 0x60 800158a: f403 6300 and.w r3, r3, #2048 @ 0x800 800158e: 60fb str r3, [r7, #12] 8001590: 68fb ldr r3, [r7, #12] /* TIM1 interrupt Init */ HAL_NVIC_SetPriority(TIM1_BRK_TIM15_IRQn, 0, 0); 8001592: 2200 movs r2, #0 8001594: 2100 movs r1, #0 8001596: 2018 movs r0, #24 8001598: f001 ffc3 bl 8003522 HAL_NVIC_EnableIRQ(TIM1_BRK_TIM15_IRQn); 800159c: 2018 movs r0, #24 800159e: f001 ffda bl 8003556 HAL_NVIC_SetPriority(TIM1_UP_TIM16_IRQn, 0, 0); 80015a2: 2200 movs r2, #0 80015a4: 2100 movs r1, #0 80015a6: 2019 movs r0, #25 80015a8: f001 ffbb bl 8003522 HAL_NVIC_EnableIRQ(TIM1_UP_TIM16_IRQn); 80015ac: 2019 movs r0, #25 80015ae: f001 ffd2 bl 8003556 HAL_NVIC_SetPriority(TIM1_TRG_COM_TIM17_IRQn, 0, 0); 80015b2: 2200 movs r2, #0 80015b4: 2100 movs r1, #0 80015b6: 201a movs r0, #26 80015b8: f001 ffb3 bl 8003522 HAL_NVIC_EnableIRQ(TIM1_TRG_COM_TIM17_IRQn); 80015bc: 201a movs r0, #26 80015be: f001 ffca bl 8003556 HAL_NVIC_SetPriority(TIM1_CC_IRQn, 0, 0); 80015c2: 2200 movs r2, #0 80015c4: 2100 movs r1, #0 80015c6: 201b movs r0, #27 80015c8: f001 ffab bl 8003522 HAL_NVIC_EnableIRQ(TIM1_CC_IRQn); 80015cc: 201b movs r0, #27 80015ce: f001 ffc2 bl 8003556 /* USER CODE END TIM1_MspInit 1 */ } } 80015d2: bf00 nop 80015d4: 3710 adds r7, #16 80015d6: 46bd mov sp, r7 80015d8: bd80 pop {r7, pc} 80015da: bf00 nop 80015dc: 40012c00 .word 0x40012c00 80015e0: 40021000 .word 0x40021000 080015e4 : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { 80015e4: b580 push {r7, lr} 80015e6: b09e sub sp, #120 @ 0x78 80015e8: af00 add r7, sp, #0 80015ea: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80015ec: f107 0364 add.w r3, r7, #100 @ 0x64 80015f0: 2200 movs r2, #0 80015f2: 601a str r2, [r3, #0] 80015f4: 605a str r2, [r3, #4] 80015f6: 609a str r2, [r3, #8] 80015f8: 60da str r2, [r3, #12] 80015fa: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 80015fc: f107 0310 add.w r3, r7, #16 8001600: 2254 movs r2, #84 @ 0x54 8001602: 2100 movs r1, #0 8001604: 4618 mov r0, r3 8001606: f006 fe2d bl 8008264 if(huart->Instance==USART1) 800160a: 687b ldr r3, [r7, #4] 800160c: 681b ldr r3, [r3, #0] 800160e: 4a1e ldr r2, [pc, #120] @ (8001688 ) 8001610: 4293 cmp r3, r2 8001612: d135 bne.n 8001680 /* USER CODE END USART1_MspInit 0 */ /** Initializes the peripherals clocks */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1; 8001614: 2301 movs r3, #1 8001616: 613b str r3, [r7, #16] PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; 8001618: 2300 movs r3, #0 800161a: 617b str r3, [r7, #20] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 800161c: f107 0310 add.w r3, r7, #16 8001620: 4618 mov r0, r3 8001622: f004 ff4b bl 80064bc 8001626: 4603 mov r3, r0 8001628: 2b00 cmp r3, #0 800162a: d001 beq.n 8001630 { Error_Handler(); 800162c: f7ff fd28 bl 8001080 } /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); 8001630: 4b16 ldr r3, [pc, #88] @ (800168c ) 8001632: 6e1b ldr r3, [r3, #96] @ 0x60 8001634: 4a15 ldr r2, [pc, #84] @ (800168c ) 8001636: f443 4380 orr.w r3, r3, #16384 @ 0x4000 800163a: 6613 str r3, [r2, #96] @ 0x60 800163c: 4b13 ldr r3, [pc, #76] @ (800168c ) 800163e: 6e1b ldr r3, [r3, #96] @ 0x60 8001640: f403 4380 and.w r3, r3, #16384 @ 0x4000 8001644: 60fb str r3, [r7, #12] 8001646: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOB_CLK_ENABLE(); 8001648: 4b10 ldr r3, [pc, #64] @ (800168c ) 800164a: 6cdb ldr r3, [r3, #76] @ 0x4c 800164c: 4a0f ldr r2, [pc, #60] @ (800168c ) 800164e: f043 0302 orr.w r3, r3, #2 8001652: 64d3 str r3, [r2, #76] @ 0x4c 8001654: 4b0d ldr r3, [pc, #52] @ (800168c ) 8001656: 6cdb ldr r3, [r3, #76] @ 0x4c 8001658: f003 0302 and.w r3, r3, #2 800165c: 60bb str r3, [r7, #8] 800165e: 68bb ldr r3, [r7, #8] /**USART1 GPIO Configuration PB6 ------> USART1_TX PB7 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; 8001660: 23c0 movs r3, #192 @ 0xc0 8001662: 667b str r3, [r7, #100] @ 0x64 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001664: 2302 movs r3, #2 8001666: 66bb str r3, [r7, #104] @ 0x68 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001668: 2300 movs r3, #0 800166a: 66fb str r3, [r7, #108] @ 0x6c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800166c: 2300 movs r3, #0 800166e: 673b str r3, [r7, #112] @ 0x70 GPIO_InitStruct.Alternate = GPIO_AF7_USART1; 8001670: 2307 movs r3, #7 8001672: 677b str r3, [r7, #116] @ 0x74 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8001674: f107 0364 add.w r3, r7, #100 @ 0x64 8001678: 4619 mov r1, r3 800167a: 4805 ldr r0, [pc, #20] @ (8001690 ) 800167c: f002 fc62 bl 8003f44 /* USER CODE END USART1_MspInit 1 */ } } 8001680: bf00 nop 8001682: 3778 adds r7, #120 @ 0x78 8001684: 46bd mov sp, r7 8001686: bd80 pop {r7, pc} 8001688: 40013800 .word 0x40013800 800168c: 40021000 .word 0x40021000 8001690: 48000400 .word 0x48000400 08001694 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8001694: b480 push {r7} 8001696: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8001698: bf00 nop 800169a: e7fd b.n 8001698 0800169c : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 800169c: b480 push {r7} 800169e: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 80016a0: bf00 nop 80016a2: e7fd b.n 80016a0 080016a4 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 80016a4: b480 push {r7} 80016a6: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 80016a8: bf00 nop 80016aa: e7fd b.n 80016a8 080016ac : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 80016ac: b480 push {r7} 80016ae: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 80016b0: bf00 nop 80016b2: e7fd b.n 80016b0 080016b4 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 80016b4: b480 push {r7} 80016b6: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 80016b8: bf00 nop 80016ba: e7fd b.n 80016b8 080016bc : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 80016bc: b480 push {r7} 80016be: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 80016c0: bf00 nop 80016c2: 46bd mov sp, r7 80016c4: f85d 7b04 ldr.w r7, [sp], #4 80016c8: 4770 bx lr 080016ca : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 80016ca: b480 push {r7} 80016cc: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 80016ce: bf00 nop 80016d0: 46bd mov sp, r7 80016d2: f85d 7b04 ldr.w r7, [sp], #4 80016d6: 4770 bx lr 080016d8 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 80016d8: b480 push {r7} 80016da: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 80016dc: bf00 nop 80016de: 46bd mov sp, r7 80016e0: f85d 7b04 ldr.w r7, [sp], #4 80016e4: 4770 bx lr 080016e6 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 80016e6: b580 push {r7, lr} 80016e8: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 80016ea: f000 f8cd bl 8001888 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 80016ee: bf00 nop 80016f0: bd80 pop {r7, pc} ... 080016f4 : /** * @brief This function handles DMA1 channel1 global interrupt. */ void DMA1_Channel1_IRQHandler(void) { 80016f4: b580 push {r7, lr} 80016f6: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */ /* USER CODE END DMA1_Channel1_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc3); 80016f8: 4802 ldr r0, [pc, #8] @ (8001704 ) 80016fa: f002 fa65 bl 8003bc8 /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */ /* USER CODE END DMA1_Channel1_IRQn 1 */ } 80016fe: bf00 nop 8001700: bd80 pop {r7, pc} 8001702: bf00 nop 8001704: 20000100 .word 0x20000100 08001708 : /** * @brief This function handles DMA1 channel2 global interrupt. */ void DMA1_Channel2_IRQHandler(void) { 8001708: b580 push {r7, lr} 800170a: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Channel2_IRQn 0 */ /* USER CODE END DMA1_Channel2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc4); 800170c: 4802 ldr r0, [pc, #8] @ (8001718 ) 800170e: f002 fa5b bl 8003bc8 /* USER CODE BEGIN DMA1_Channel2_IRQn 1 */ /* USER CODE END DMA1_Channel2_IRQn 1 */ } 8001712: bf00 nop 8001714: bd80 pop {r7, pc} 8001716: bf00 nop 8001718: 20000160 .word 0x20000160 0800171c : /** * @brief This function handles TIM1 break interrupt and TIM15 global interrupt. */ void TIM1_BRK_TIM15_IRQHandler(void) { 800171c: b580 push {r7, lr} 800171e: af00 add r7, sp, #0 /* USER CODE BEGIN TIM1_BRK_TIM15_IRQn 0 */ /* USER CODE END TIM1_BRK_TIM15_IRQn 0 */ HAL_TIM_IRQHandler(&htim1); 8001720: 4802 ldr r0, [pc, #8] @ (800172c ) 8001722: f005 f9e9 bl 8006af8 /* USER CODE BEGIN TIM1_BRK_TIM15_IRQn 1 */ /* USER CODE END TIM1_BRK_TIM15_IRQn 1 */ } 8001726: bf00 nop 8001728: bd80 pop {r7, pc} 800172a: bf00 nop 800172c: 2000038c .word 0x2000038c 08001730 : /** * @brief This function handles TIM1 update interrupt and TIM16 global interrupt. */ void TIM1_UP_TIM16_IRQHandler(void) { 8001730: b580 push {r7, lr} 8001732: af00 add r7, sp, #0 /* USER CODE BEGIN TIM1_UP_TIM16_IRQn 0 */ /* USER CODE END TIM1_UP_TIM16_IRQn 0 */ HAL_TIM_IRQHandler(&htim1); 8001734: 4802 ldr r0, [pc, #8] @ (8001740 ) 8001736: f005 f9df bl 8006af8 /* USER CODE BEGIN TIM1_UP_TIM16_IRQn 1 */ /* USER CODE END TIM1_UP_TIM16_IRQn 1 */ } 800173a: bf00 nop 800173c: bd80 pop {r7, pc} 800173e: bf00 nop 8001740: 2000038c .word 0x2000038c 08001744 : /** * @brief This function handles TIM1 trigger and commutation interrupts and TIM17 global interrupt. */ void TIM1_TRG_COM_TIM17_IRQHandler(void) { 8001744: b580 push {r7, lr} 8001746: af00 add r7, sp, #0 /* USER CODE BEGIN TIM1_TRG_COM_TIM17_IRQn 0 */ /* USER CODE END TIM1_TRG_COM_TIM17_IRQn 0 */ HAL_TIM_IRQHandler(&htim1); 8001748: 4802 ldr r0, [pc, #8] @ (8001754 ) 800174a: f005 f9d5 bl 8006af8 /* USER CODE BEGIN TIM1_TRG_COM_TIM17_IRQn 1 */ /* USER CODE END TIM1_TRG_COM_TIM17_IRQn 1 */ } 800174e: bf00 nop 8001750: bd80 pop {r7, pc} 8001752: bf00 nop 8001754: 2000038c .word 0x2000038c 08001758 : /** * @brief This function handles TIM1 capture compare interrupt. */ void TIM1_CC_IRQHandler(void) { 8001758: b580 push {r7, lr} 800175a: af00 add r7, sp, #0 /* USER CODE BEGIN TIM1_CC_IRQn 0 */ /* USER CODE END TIM1_CC_IRQn 0 */ HAL_TIM_IRQHandler(&htim1); 800175c: 4802 ldr r0, [pc, #8] @ (8001768 ) 800175e: f005 f9cb bl 8006af8 /* USER CODE BEGIN TIM1_CC_IRQn 1 */ /* USER CODE END TIM1_CC_IRQn 1 */ } 8001762: bf00 nop 8001764: bd80 pop {r7, pc} 8001766: bf00 nop 8001768: 2000038c .word 0x2000038c 0800176c : * @param None * @retval None */ void SystemInit(void) { 800176c: b480 push {r7} 800176e: af00 add r7, sp, #0 /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ 8001770: 4b06 ldr r3, [pc, #24] @ (800178c ) 8001772: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8001776: 4a05 ldr r2, [pc, #20] @ (800178c ) 8001778: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 800177c: f8c2 3088 str.w r3, [r2, #136] @ 0x88 /* Configure the Vector Table location add offset address ------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #endif /* USER_VECT_TAB_ADDRESS */ } 8001780: bf00 nop 8001782: 46bd mov sp, r7 8001784: f85d 7b04 ldr.w r7, [sp], #4 8001788: 4770 bx lr 800178a: bf00 nop 800178c: e000ed00 .word 0xe000ed00 08001790 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr r0, =_estack 8001790: 480d ldr r0, [pc, #52] @ (80017c8 ) mov sp, r0 /* set stack pointer */ 8001792: 4685 mov sp, r0 /* Call the clock system initialization function.*/ bl SystemInit 8001794: f7ff ffea bl 800176c /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8001798: 480c ldr r0, [pc, #48] @ (80017cc ) ldr r1, =_edata 800179a: 490d ldr r1, [pc, #52] @ (80017d0 ) ldr r2, =_sidata 800179c: 4a0d ldr r2, [pc, #52] @ (80017d4 ) movs r3, #0 800179e: 2300 movs r3, #0 b LoopCopyDataInit 80017a0: e002 b.n 80017a8 080017a2 : CopyDataInit: ldr r4, [r2, r3] 80017a2: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 80017a4: 50c4 str r4, [r0, r3] adds r3, r3, #4 80017a6: 3304 adds r3, #4 080017a8 : LoopCopyDataInit: adds r4, r0, r3 80017a8: 18c4 adds r4, r0, r3 cmp r4, r1 80017aa: 428c cmp r4, r1 bcc CopyDataInit 80017ac: d3f9 bcc.n 80017a2 /* Zero fill the bss segment. */ ldr r2, =_sbss 80017ae: 4a0a ldr r2, [pc, #40] @ (80017d8 ) ldr r4, =_ebss 80017b0: 4c0a ldr r4, [pc, #40] @ (80017dc ) movs r3, #0 80017b2: 2300 movs r3, #0 b LoopFillZerobss 80017b4: e001 b.n 80017ba 080017b6 : FillZerobss: str r3, [r2] 80017b6: 6013 str r3, [r2, #0] adds r2, r2, #4 80017b8: 3204 adds r2, #4 080017ba : LoopFillZerobss: cmp r2, r4 80017ba: 42a2 cmp r2, r4 bcc FillZerobss 80017bc: d3fb bcc.n 80017b6 /* Call static constructors */ bl __libc_init_array 80017be: f006 fd59 bl 8008274 <__libc_init_array> /* Call the application's entry point.*/ bl main 80017c2: f7fe fec7 bl 8000554
080017c6 : LoopForever: b LoopForever 80017c6: e7fe b.n 80017c6 ldr r0, =_estack 80017c8: 20020000 .word 0x20020000 ldr r0, =_sdata 80017cc: 20000000 .word 0x20000000 ldr r1, =_edata 80017d0: 2000000c .word 0x2000000c ldr r2, =_sidata 80017d4: 08008734 .word 0x08008734 ldr r2, =_sbss 80017d8: 2000000c .word 0x2000000c ldr r4, =_ebss 80017dc: 20000478 .word 0x20000478 080017e0 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 80017e0: e7fe b.n 80017e0 080017e2 : * each 1ms in the SysTick_Handler() interrupt handler. * * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 80017e2: b580 push {r7, lr} 80017e4: b082 sub sp, #8 80017e6: af00 add r7, sp, #0 HAL_StatusTypeDef status = HAL_OK; 80017e8: 2300 movs r3, #0 80017ea: 71fb strb r3, [r7, #7] #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 80017ec: 2003 movs r0, #3 80017ee: f001 fe8d bl 800350c /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */ if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) 80017f2: 200f movs r0, #15 80017f4: f000 f80e bl 8001814 80017f8: 4603 mov r3, r0 80017fa: 2b00 cmp r3, #0 80017fc: d002 beq.n 8001804 { status = HAL_ERROR; 80017fe: 2301 movs r3, #1 8001800: 71fb strb r3, [r7, #7] 8001802: e001 b.n 8001808 } else { /* Init the low level hardware */ HAL_MspInit(); 8001804: f7ff fc5e bl 80010c4 } /* Return function status */ return status; 8001808: 79fb ldrb r3, [r7, #7] } 800180a: 4618 mov r0, r3 800180c: 3708 adds r7, #8 800180e: 46bd mov sp, r7 8001810: bd80 pop {r7, pc} ... 08001814 : * implementation in user file. * @param TickPriority: Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8001814: b580 push {r7, lr} 8001816: b084 sub sp, #16 8001818: af00 add r7, sp, #0 800181a: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800181c: 2300 movs r3, #0 800181e: 73fb strb r3, [r7, #15] if (uwTickFreq != 0U) 8001820: 4b16 ldr r3, [pc, #88] @ (800187c ) 8001822: 681b ldr r3, [r3, #0] 8001824: 2b00 cmp r3, #0 8001826: d022 beq.n 800186e { /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U) 8001828: 4b15 ldr r3, [pc, #84] @ (8001880 ) 800182a: 681a ldr r2, [r3, #0] 800182c: 4b13 ldr r3, [pc, #76] @ (800187c ) 800182e: 681b ldr r3, [r3, #0] 8001830: f44f 717a mov.w r1, #1000 @ 0x3e8 8001834: fbb1 f3f3 udiv r3, r1, r3 8001838: fbb2 f3f3 udiv r3, r2, r3 800183c: 4618 mov r0, r3 800183e: f001 fe98 bl 8003572 8001842: 4603 mov r3, r0 8001844: 2b00 cmp r3, #0 8001846: d10f bne.n 8001868 { /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8001848: 687b ldr r3, [r7, #4] 800184a: 2b0f cmp r3, #15 800184c: d809 bhi.n 8001862 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 800184e: 2200 movs r2, #0 8001850: 6879 ldr r1, [r7, #4] 8001852: f04f 30ff mov.w r0, #4294967295 8001856: f001 fe64 bl 8003522 uwTickPrio = TickPriority; 800185a: 4a0a ldr r2, [pc, #40] @ (8001884 ) 800185c: 687b ldr r3, [r7, #4] 800185e: 6013 str r3, [r2, #0] 8001860: e007 b.n 8001872 } else { status = HAL_ERROR; 8001862: 2301 movs r3, #1 8001864: 73fb strb r3, [r7, #15] 8001866: e004 b.n 8001872 } } else { status = HAL_ERROR; 8001868: 2301 movs r3, #1 800186a: 73fb strb r3, [r7, #15] 800186c: e001 b.n 8001872 } } else { status = HAL_ERROR; 800186e: 2301 movs r3, #1 8001870: 73fb strb r3, [r7, #15] } /* Return function status */ return status; 8001872: 7bfb ldrb r3, [r7, #15] } 8001874: 4618 mov r0, r3 8001876: 3710 adds r7, #16 8001878: 46bd mov sp, r7 800187a: bd80 pop {r7, pc} 800187c: 20000008 .word 0x20000008 8001880: 20000000 .word 0x20000000 8001884: 20000004 .word 0x20000004 08001888 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8001888: b480 push {r7} 800188a: af00 add r7, sp, #0 uwTick += uwTickFreq; 800188c: 4b05 ldr r3, [pc, #20] @ (80018a4 ) 800188e: 681a ldr r2, [r3, #0] 8001890: 4b05 ldr r3, [pc, #20] @ (80018a8 ) 8001892: 681b ldr r3, [r3, #0] 8001894: 4413 add r3, r2 8001896: 4a03 ldr r2, [pc, #12] @ (80018a4 ) 8001898: 6013 str r3, [r2, #0] } 800189a: bf00 nop 800189c: 46bd mov sp, r7 800189e: f85d 7b04 ldr.w r7, [sp], #4 80018a2: 4770 bx lr 80018a4: 20000474 .word 0x20000474 80018a8: 20000008 .word 0x20000008 080018ac : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 80018ac: b480 push {r7} 80018ae: af00 add r7, sp, #0 return uwTick; 80018b0: 4b03 ldr r3, [pc, #12] @ (80018c0 ) 80018b2: 681b ldr r3, [r3, #0] } 80018b4: 4618 mov r0, r3 80018b6: 46bd mov sp, r7 80018b8: f85d 7b04 ldr.w r7, [sp], #4 80018bc: 4770 bx lr 80018be: bf00 nop 80018c0: 20000474 .word 0x20000474 080018c4 : * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output. * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance. * @retval None */ void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode) { 80018c4: b480 push {r7} 80018c6: b083 sub sp, #12 80018c8: af00 add r7, sp, #0 80018ca: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode)); MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode); 80018cc: 4b06 ldr r3, [pc, #24] @ (80018e8 ) 80018ce: 681b ldr r3, [r3, #0] 80018d0: f023 0202 bic.w r2, r3, #2 80018d4: 4904 ldr r1, [pc, #16] @ (80018e8 ) 80018d6: 687b ldr r3, [r7, #4] 80018d8: 4313 orrs r3, r2 80018da: 600b str r3, [r1, #0] } 80018dc: bf00 nop 80018de: 370c adds r7, #12 80018e0: 46bd mov sp, r7 80018e2: f85d 7b04 ldr.w r7, [sp], #4 80018e6: 4770 bx lr 80018e8: 40010030 .word 0x40010030 080018ec : * @brief Disable the Internal Voltage Reference buffer (VREFBUF). * * @retval None */ void HAL_SYSCFG_DisableVREFBUF(void) { 80018ec: b480 push {r7} 80018ee: af00 add r7, sp, #0 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); 80018f0: 4b05 ldr r3, [pc, #20] @ (8001908 ) 80018f2: 681b ldr r3, [r3, #0] 80018f4: 4a04 ldr r2, [pc, #16] @ (8001908 ) 80018f6: f023 0301 bic.w r3, r3, #1 80018fa: 6013 str r3, [r2, #0] } 80018fc: bf00 nop 80018fe: 46bd mov sp, r7 8001900: f85d 7b04 ldr.w r7, [sp], #4 8001904: 4770 bx lr 8001906: bf00 nop 8001908: 40010030 .word 0x40010030 0800190c : * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 * @retval None */ __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock) { 800190c: b480 push {r7} 800190e: b083 sub sp, #12 8001910: af00 add r7, sp, #0 8001912: 6078 str r0, [r7, #4] 8001914: 6039 str r1, [r7, #0] MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock); 8001916: 687b ldr r3, [r7, #4] 8001918: 689b ldr r3, [r3, #8] 800191a: f423 127c bic.w r2, r3, #4128768 @ 0x3f0000 800191e: 683b ldr r3, [r7, #0] 8001920: 431a orrs r2, r3 8001922: 687b ldr r3, [r7, #4] 8001924: 609a str r2, [r3, #8] } 8001926: bf00 nop 8001928: 370c adds r7, #12 800192a: 46bd mov sp, r7 800192c: f85d 7b04 ldr.w r7, [sp], #4 8001930: 4770 bx lr 08001932 : * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT * @retval None */ __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) { 8001932: b480 push {r7} 8001934: b083 sub sp, #12 8001936: af00 add r7, sp, #0 8001938: 6078 str r0, [r7, #4] 800193a: 6039 str r1, [r7, #0] MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL, PathInternal); 800193c: 687b ldr r3, [r7, #4] 800193e: 689b ldr r3, [r3, #8] 8001940: f023 72e0 bic.w r2, r3, #29360128 @ 0x1c00000 8001944: 683b ldr r3, [r7, #0] 8001946: 431a orrs r2, r3 8001948: 687b ldr r3, [r7, #4] 800194a: 609a str r2, [r3, #8] } 800194c: bf00 nop 800194e: 370c adds r7, #12 8001950: 46bd mov sp, r7 8001952: f85d 7b04 ldr.w r7, [sp], #4 8001956: 4770 bx lr 08001958 : * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT */ __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON) { 8001958: b480 push {r7} 800195a: b083 sub sp, #12 800195c: af00 add r7, sp, #0 800195e: 6078 str r0, [r7, #4] return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL)); 8001960: 687b ldr r3, [r7, #4] 8001962: 689b ldr r3, [r3, #8] 8001964: f003 73e0 and.w r3, r3, #29360128 @ 0x1c00000 } 8001968: 4618 mov r0, r3 800196a: 370c adds r7, #12 800196c: 46bd mov sp, r7 800196e: f85d 7b04 ldr.w r7, [sp], #4 8001972: 4770 bx lr 08001974 : * (fADC) to convert in 12-bit resolution.\n * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None */ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel) { 8001974: b480 push {r7} 8001976: b087 sub sp, #28 8001978: af00 add r7, sp, #0 800197a: 60f8 str r0, [r7, #12] 800197c: 60b9 str r1, [r7, #8] 800197e: 607a str r2, [r7, #4] 8001980: 603b str r3, [r7, #0] __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 8001982: 68fb ldr r3, [r7, #12] 8001984: 3360 adds r3, #96 @ 0x60 8001986: 461a mov r2, r3 8001988: 68bb ldr r3, [r7, #8] 800198a: 009b lsls r3, r3, #2 800198c: 4413 add r3, r2 800198e: 617b str r3, [r7, #20] MODIFY_REG(*preg, 8001990: 697b ldr r3, [r7, #20] 8001992: 681a ldr r2, [r3, #0] 8001994: 4b08 ldr r3, [pc, #32] @ (80019b8 ) 8001996: 4013 ands r3, r2 8001998: 687a ldr r2, [r7, #4] 800199a: f002 41f8 and.w r1, r2, #2080374784 @ 0x7c000000 800199e: 683a ldr r2, [r7, #0] 80019a0: 430a orrs r2, r1 80019a2: 4313 orrs r3, r2 80019a4: f043 4200 orr.w r2, r3, #2147483648 @ 0x80000000 80019a8: 697b ldr r3, [r7, #20] 80019aa: 601a str r2, [r3, #0] ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1, ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel); } 80019ac: bf00 nop 80019ae: 371c adds r7, #28 80019b0: 46bd mov sp, r7 80019b2: f85d 7b04 ldr.w r7, [sp], #4 80019b6: 4770 bx lr 80019b8: 03fff000 .word 0x03fff000 080019bc : * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(const ADC_TypeDef *ADCx, uint32_t Offsety) { 80019bc: b480 push {r7} 80019be: b085 sub sp, #20 80019c0: af00 add r7, sp, #0 80019c2: 6078 str r0, [r7, #4] 80019c4: 6039 str r1, [r7, #0] const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 80019c6: 687b ldr r3, [r7, #4] 80019c8: 3360 adds r3, #96 @ 0x60 80019ca: 461a mov r2, r3 80019cc: 683b ldr r3, [r7, #0] 80019ce: 009b lsls r3, r3, #2 80019d0: 4413 add r3, r2 80019d2: 60fb str r3, [r7, #12] return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); 80019d4: 68fb ldr r3, [r7, #12] 80019d6: 681b ldr r3, [r3, #0] 80019d8: f003 43f8 and.w r3, r3, #2080374784 @ 0x7c000000 } 80019dc: 4618 mov r0, r3 80019de: 3714 adds r7, #20 80019e0: 46bd mov sp, r7 80019e2: f85d 7b04 ldr.w r7, [sp], #4 80019e6: 4770 bx lr 080019e8 : * @arg @ref LL_ADC_OFFSET_DISABLE * @arg @ref LL_ADC_OFFSET_ENABLE * @retval None */ __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState) { 80019e8: b480 push {r7} 80019ea: b087 sub sp, #28 80019ec: af00 add r7, sp, #0 80019ee: 60f8 str r0, [r7, #12] 80019f0: 60b9 str r1, [r7, #8] 80019f2: 607a str r2, [r7, #4] __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 80019f4: 68fb ldr r3, [r7, #12] 80019f6: 3360 adds r3, #96 @ 0x60 80019f8: 461a mov r2, r3 80019fa: 68bb ldr r3, [r7, #8] 80019fc: 009b lsls r3, r3, #2 80019fe: 4413 add r3, r2 8001a00: 617b str r3, [r7, #20] MODIFY_REG(*preg, 8001a02: 697b ldr r3, [r7, #20] 8001a04: 681b ldr r3, [r3, #0] 8001a06: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000 8001a0a: 687b ldr r3, [r7, #4] 8001a0c: 431a orrs r2, r3 8001a0e: 697b ldr r3, [r7, #20] 8001a10: 601a str r2, [r3, #0] ADC_OFR1_OFFSET1_EN, OffsetState); } 8001a12: bf00 nop 8001a14: 371c adds r7, #28 8001a16: 46bd mov sp, r7 8001a18: f85d 7b04 ldr.w r7, [sp], #4 8001a1c: 4770 bx lr 08001a1e : * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE * @retval None */ __STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign) { 8001a1e: b480 push {r7} 8001a20: b087 sub sp, #28 8001a22: af00 add r7, sp, #0 8001a24: 60f8 str r0, [r7, #12] 8001a26: 60b9 str r1, [r7, #8] 8001a28: 607a str r2, [r7, #4] __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 8001a2a: 68fb ldr r3, [r7, #12] 8001a2c: 3360 adds r3, #96 @ 0x60 8001a2e: 461a mov r2, r3 8001a30: 68bb ldr r3, [r7, #8] 8001a32: 009b lsls r3, r3, #2 8001a34: 4413 add r3, r2 8001a36: 617b str r3, [r7, #20] MODIFY_REG(*preg, 8001a38: 697b ldr r3, [r7, #20] 8001a3a: 681b ldr r3, [r3, #0] 8001a3c: f023 7280 bic.w r2, r3, #16777216 @ 0x1000000 8001a40: 687b ldr r3, [r7, #4] 8001a42: 431a orrs r2, r3 8001a44: 697b ldr r3, [r7, #20] 8001a46: 601a str r2, [r3, #0] ADC_OFR1_OFFSETPOS, OffsetSign); } 8001a48: bf00 nop 8001a4a: 371c adds r7, #28 8001a4c: 46bd mov sp, r7 8001a4e: f85d 7b04 ldr.w r7, [sp], #4 8001a52: 4770 bx lr 08001a54 : * @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE * @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE * @retval None */ __STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSaturation) { 8001a54: b480 push {r7} 8001a56: b087 sub sp, #28 8001a58: af00 add r7, sp, #0 8001a5a: 60f8 str r0, [r7, #12] 8001a5c: 60b9 str r1, [r7, #8] 8001a5e: 607a str r2, [r7, #4] __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 8001a60: 68fb ldr r3, [r7, #12] 8001a62: 3360 adds r3, #96 @ 0x60 8001a64: 461a mov r2, r3 8001a66: 68bb ldr r3, [r7, #8] 8001a68: 009b lsls r3, r3, #2 8001a6a: 4413 add r3, r2 8001a6c: 617b str r3, [r7, #20] MODIFY_REG(*preg, 8001a6e: 697b ldr r3, [r7, #20] 8001a70: 681b ldr r3, [r3, #0] 8001a72: f023 7200 bic.w r2, r3, #33554432 @ 0x2000000 8001a76: 687b ldr r3, [r7, #4] 8001a78: 431a orrs r2, r3 8001a7a: 697b ldr r3, [r7, #20] 8001a7c: 601a str r2, [r3, #0] ADC_OFR1_SATEN, OffsetSaturation); } 8001a7e: bf00 nop 8001a80: 371c adds r7, #28 8001a82: 46bd mov sp, r7 8001a84: f85d 7b04 ldr.w r7, [sp], #4 8001a88: 4770 bx lr 08001a8a : * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 * @retval None */ __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef *ADCx, uint32_t SamplingTimeCommonConfig) { 8001a8a: b480 push {r7} 8001a8c: b083 sub sp, #12 8001a8e: af00 add r7, sp, #0 8001a90: 6078 str r0, [r7, #4] 8001a92: 6039 str r1, [r7, #0] MODIFY_REG(ADCx->SMPR1, ADC_SMPR1_SMPPLUS, SamplingTimeCommonConfig); 8001a94: 687b ldr r3, [r7, #4] 8001a96: 695b ldr r3, [r3, #20] 8001a98: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000 8001a9c: 683b ldr r3, [r7, #0] 8001a9e: 431a orrs r2, r3 8001aa0: 687b ldr r3, [r7, #4] 8001aa2: 615a str r2, [r3, #20] } 8001aa4: bf00 nop 8001aa6: 370c adds r7, #12 8001aa8: 46bd mov sp, r7 8001aaa: f85d 7b04 ldr.w r7, [sp], #4 8001aae: 4770 bx lr 08001ab0 : * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles * (fADC) to convert in 12-bit resolution.\n * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) { 8001ab0: b480 push {r7} 8001ab2: b087 sub sp, #28 8001ab4: af00 add r7, sp, #0 8001ab6: 60f8 str r0, [r7, #12] 8001ab8: 60b9 str r1, [r7, #8] 8001aba: 607a str r2, [r7, #4] /* Set bits with content of parameter "Channel" with bits position */ /* in register and register position depending on parameter "Rank". */ /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, 8001abc: 68fb ldr r3, [r7, #12] 8001abe: 3330 adds r3, #48 @ 0x30 8001ac0: 461a mov r2, r3 8001ac2: 68bb ldr r3, [r7, #8] 8001ac4: 0a1b lsrs r3, r3, #8 8001ac6: 009b lsls r3, r3, #2 8001ac8: f003 030c and.w r3, r3, #12 8001acc: 4413 add r3, r2 8001ace: 617b str r3, [r7, #20] ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); MODIFY_REG(*preg, 8001ad0: 697b ldr r3, [r7, #20] 8001ad2: 681a ldr r2, [r3, #0] 8001ad4: 68bb ldr r3, [r7, #8] 8001ad6: f003 031f and.w r3, r3, #31 8001ada: 211f movs r1, #31 8001adc: fa01 f303 lsl.w r3, r1, r3 8001ae0: 43db mvns r3, r3 8001ae2: 401a ands r2, r3 8001ae4: 687b ldr r3, [r7, #4] 8001ae6: 0e9b lsrs r3, r3, #26 8001ae8: f003 011f and.w r1, r3, #31 8001aec: 68bb ldr r3, [r7, #8] 8001aee: f003 031f and.w r3, r3, #31 8001af2: fa01 f303 lsl.w r3, r1, r3 8001af6: 431a orrs r2, r3 8001af8: 697b ldr r3, [r7, #20] 8001afa: 601a str r2, [r3, #0] ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); } 8001afc: bf00 nop 8001afe: 371c adds r7, #28 8001b00: 46bd mov sp, r7 8001b02: f85d 7b04 ldr.w r7, [sp], #4 8001b06: 4770 bx lr 08001b08 : * can be replaced by 3.5 ADC clock cycles. * Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig(). * @retval None */ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime) { 8001b08: b480 push {r7} 8001b0a: b087 sub sp, #28 8001b0c: af00 add r7, sp, #0 8001b0e: 60f8 str r0, [r7, #12] 8001b10: 60b9 str r1, [r7, #8] 8001b12: 607a str r2, [r7, #4] /* Set bits with content of parameter "SamplingTime" with bits position */ /* in register and register position depending on parameter "Channel". */ /* Parameter "Channel" is used with masks because containing */ /* other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, 8001b14: 68fb ldr r3, [r7, #12] 8001b16: 3314 adds r3, #20 8001b18: 461a mov r2, r3 8001b1a: 68bb ldr r3, [r7, #8] 8001b1c: 0e5b lsrs r3, r3, #25 8001b1e: 009b lsls r3, r3, #2 8001b20: f003 0304 and.w r3, r3, #4 8001b24: 4413 add r3, r2 8001b26: 617b str r3, [r7, #20] ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); MODIFY_REG(*preg, 8001b28: 697b ldr r3, [r7, #20] 8001b2a: 681a ldr r2, [r3, #0] 8001b2c: 68bb ldr r3, [r7, #8] 8001b2e: 0d1b lsrs r3, r3, #20 8001b30: f003 031f and.w r3, r3, #31 8001b34: 2107 movs r1, #7 8001b36: fa01 f303 lsl.w r3, r1, r3 8001b3a: 43db mvns r3, r3 8001b3c: 401a ands r2, r3 8001b3e: 68bb ldr r3, [r7, #8] 8001b40: 0d1b lsrs r3, r3, #20 8001b42: f003 031f and.w r3, r3, #31 8001b46: 6879 ldr r1, [r7, #4] 8001b48: fa01 f303 lsl.w r3, r1, r3 8001b4c: 431a orrs r2, r3 8001b4e: 697b ldr r3, [r7, #20] 8001b50: 601a str r2, [r3, #0] ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS), SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)); } 8001b52: bf00 nop 8001b54: 371c adds r7, #28 8001b56: 46bd mov sp, r7 8001b58: f85d 7b04 ldr.w r7, [sp], #4 8001b5c: 4770 bx lr ... 08001b60 : * @arg @ref LL_ADC_SINGLE_ENDED * @arg @ref LL_ADC_DIFFERENTIAL_ENDED * @retval None */ __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff) { 8001b60: b480 push {r7} 8001b62: b085 sub sp, #20 8001b64: af00 add r7, sp, #0 8001b66: 60f8 str r0, [r7, #12] 8001b68: 60b9 str r1, [r7, #8] 8001b6a: 607a str r2, [r7, #4] /* Bits of channels in single or differential mode are set only for */ /* differential mode (for single mode, mask of bits allowed to be set is */ /* shifted out of range of bits of channels in single or differential mode. */ MODIFY_REG(ADCx->DIFSEL, 8001b6c: 68fb ldr r3, [r7, #12] 8001b6e: f8d3 20b0 ldr.w r2, [r3, #176] @ 0xb0 8001b72: 68bb ldr r3, [r7, #8] 8001b74: f3c3 0312 ubfx r3, r3, #0, #19 8001b78: 43db mvns r3, r3 8001b7a: 401a ands r2, r3 8001b7c: 687b ldr r3, [r7, #4] 8001b7e: f003 0318 and.w r3, r3, #24 8001b82: 4908 ldr r1, [pc, #32] @ (8001ba4 ) 8001b84: 40d9 lsrs r1, r3 8001b86: 68bb ldr r3, [r7, #8] 8001b88: 400b ands r3, r1 8001b8a: f3c3 0312 ubfx r3, r3, #0, #19 8001b8e: 431a orrs r2, r3 8001b90: 68fb ldr r3, [r7, #12] 8001b92: f8c3 20b0 str.w r2, [r3, #176] @ 0xb0 Channel & ADC_SINGLEDIFF_CHANNEL_MASK, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK))); } 8001b96: bf00 nop 8001b98: 3714 adds r7, #20 8001b9a: 46bd mov sp, r7 8001b9c: f85d 7b04 ldr.w r7, [sp], #4 8001ba0: 4770 bx lr 8001ba2: bf00 nop 8001ba4: 0007ffff .word 0x0007ffff 08001ba8 : * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx) { 8001ba8: b480 push {r7} 8001baa: b083 sub sp, #12 8001bac: af00 add r7, sp, #0 8001bae: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS)); 8001bb0: 687b ldr r3, [r7, #4] 8001bb2: 689b ldr r3, [r3, #8] 8001bb4: f023 4320 bic.w r3, r3, #2684354560 @ 0xa0000000 8001bb8: f023 033f bic.w r3, r3, #63 @ 0x3f 8001bbc: 687a ldr r2, [r7, #4] 8001bbe: 6093 str r3, [r2, #8] } 8001bc0: bf00 nop 8001bc2: 370c adds r7, #12 8001bc4: 46bd mov sp, r7 8001bc6: f85d 7b04 ldr.w r7, [sp], #4 8001bca: 4770 bx lr 08001bcc : * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled * @param ADCx ADC instance * @retval 0: deep power down is disabled, 1: deep power down is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef *ADCx) { 8001bcc: b480 push {r7} 8001bce: b083 sub sp, #12 8001bd0: af00 add r7, sp, #0 8001bd2: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL); 8001bd4: 687b ldr r3, [r7, #4] 8001bd6: 689b ldr r3, [r3, #8] 8001bd8: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8001bdc: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8001be0: d101 bne.n 8001be6 8001be2: 2301 movs r3, #1 8001be4: e000 b.n 8001be8 8001be6: 2300 movs r3, #0 } 8001be8: 4618 mov r0, r3 8001bea: 370c adds r7, #12 8001bec: 46bd mov sp, r7 8001bee: f85d 7b04 ldr.w r7, [sp], #4 8001bf2: 4770 bx lr 08001bf4 : * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx) { 8001bf4: b480 push {r7} 8001bf6: b083 sub sp, #12 8001bf8: af00 add r7, sp, #0 8001bfa: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 8001bfc: 687b ldr r3, [r7, #4] 8001bfe: 689b ldr r3, [r3, #8] 8001c00: f023 4310 bic.w r3, r3, #2415919104 @ 0x90000000 8001c04: f023 033f bic.w r3, r3, #63 @ 0x3f 8001c08: f043 5280 orr.w r2, r3, #268435456 @ 0x10000000 8001c0c: 687b ldr r3, [r7, #4] 8001c0e: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADVREGEN); } 8001c10: bf00 nop 8001c12: 370c adds r7, #12 8001c14: 46bd mov sp, r7 8001c16: f85d 7b04 ldr.w r7, [sp], #4 8001c1a: 4770 bx lr 08001c1c : * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled * @param ADCx ADC instance * @retval 0: internal regulator is disabled, 1: internal regulator is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx) { 8001c1c: b480 push {r7} 8001c1e: b083 sub sp, #12 8001c20: af00 add r7, sp, #0 8001c22: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); 8001c24: 687b ldr r3, [r7, #4] 8001c26: 689b ldr r3, [r3, #8] 8001c28: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8001c2c: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8001c30: d101 bne.n 8001c36 8001c32: 2301 movs r3, #1 8001c34: e000 b.n 8001c38 8001c36: 2300 movs r3, #0 } 8001c38: 4618 mov r0, r3 8001c3a: 370c adds r7, #12 8001c3c: 46bd mov sp, r7 8001c3e: f85d 7b04 ldr.w r7, [sp], #4 8001c42: 4770 bx lr 08001c44 : * @rmtoll CR ADDIS LL_ADC_Disable * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) { 8001c44: b480 push {r7} 8001c46: b083 sub sp, #12 8001c48: af00 add r7, sp, #0 8001c4a: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 8001c4c: 687b ldr r3, [r7, #4] 8001c4e: 689b ldr r3, [r3, #8] 8001c50: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 8001c54: f023 033f bic.w r3, r3, #63 @ 0x3f 8001c58: f043 0202 orr.w r2, r3, #2 8001c5c: 687b ldr r3, [r7, #4] 8001c5e: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADDIS); } 8001c60: bf00 nop 8001c62: 370c adds r7, #12 8001c64: 46bd mov sp, r7 8001c66: f85d 7b04 ldr.w r7, [sp], #4 8001c6a: 4770 bx lr 08001c6c : * @rmtoll CR ADEN LL_ADC_IsEnabled * @param ADCx ADC instance * @retval 0: ADC is disabled, 1: ADC is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx) { 8001c6c: b480 push {r7} 8001c6e: b083 sub sp, #12 8001c70: af00 add r7, sp, #0 8001c72: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 8001c74: 687b ldr r3, [r7, #4] 8001c76: 689b ldr r3, [r3, #8] 8001c78: f003 0301 and.w r3, r3, #1 8001c7c: 2b01 cmp r3, #1 8001c7e: d101 bne.n 8001c84 8001c80: 2301 movs r3, #1 8001c82: e000 b.n 8001c86 8001c84: 2300 movs r3, #0 } 8001c86: 4618 mov r0, r3 8001c88: 370c adds r7, #12 8001c8a: 46bd mov sp, r7 8001c8c: f85d 7b04 ldr.w r7, [sp], #4 8001c90: 4770 bx lr 08001c92 : * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing * @param ADCx ADC instance * @retval 0: no ADC disable command on going. */ __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx) { 8001c92: b480 push {r7} 8001c94: b083 sub sp, #12 8001c96: af00 add r7, sp, #0 8001c98: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL); 8001c9a: 687b ldr r3, [r7, #4] 8001c9c: 689b ldr r3, [r3, #8] 8001c9e: f003 0302 and.w r3, r3, #2 8001ca2: 2b02 cmp r3, #2 8001ca4: d101 bne.n 8001caa 8001ca6: 2301 movs r3, #1 8001ca8: e000 b.n 8001cac 8001caa: 2300 movs r3, #0 } 8001cac: 4618 mov r0, r3 8001cae: 370c adds r7, #12 8001cb0: 46bd mov sp, r7 8001cb2: f85d 7b04 ldr.w r7, [sp], #4 8001cb6: 4770 bx lr 08001cb8 : * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group regular. */ __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx) { 8001cb8: b480 push {r7} 8001cba: b083 sub sp, #12 8001cbc: af00 add r7, sp, #0 8001cbe: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 8001cc0: 687b ldr r3, [r7, #4] 8001cc2: 689b ldr r3, [r3, #8] 8001cc4: f003 0304 and.w r3, r3, #4 8001cc8: 2b04 cmp r3, #4 8001cca: d101 bne.n 8001cd0 8001ccc: 2301 movs r3, #1 8001cce: e000 b.n 8001cd2 8001cd0: 2300 movs r3, #0 } 8001cd2: 4618 mov r0, r3 8001cd4: 370c adds r7, #12 8001cd6: 46bd mov sp, r7 8001cd8: f85d 7b04 ldr.w r7, [sp], #4 8001cdc: 4770 bx lr 08001cde : * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group injected. */ __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef *ADCx) { 8001cde: b480 push {r7} 8001ce0: b083 sub sp, #12 8001ce2: af00 add r7, sp, #0 8001ce4: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL); 8001ce6: 687b ldr r3, [r7, #4] 8001ce8: 689b ldr r3, [r3, #8] 8001cea: f003 0308 and.w r3, r3, #8 8001cee: 2b08 cmp r3, #8 8001cf0: d101 bne.n 8001cf6 8001cf2: 2301 movs r3, #1 8001cf4: e000 b.n 8001cf8 8001cf6: 2300 movs r3, #0 } 8001cf8: 4618 mov r0, r3 8001cfa: 370c adds r7, #12 8001cfc: 46bd mov sp, r7 8001cfe: f85d 7b04 ldr.w r7, [sp], #4 8001d02: 4770 bx lr 08001d04 : * without disabling the other ADCs. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) { 8001d04: b590 push {r4, r7, lr} 8001d06: b089 sub sp, #36 @ 0x24 8001d08: af00 add r7, sp, #0 8001d0a: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8001d0c: 2300 movs r3, #0 8001d0e: 77fb strb r3, [r7, #31] uint32_t tmp_cfgr; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; __IO uint32_t wait_loop_index = 0UL; 8001d10: 2300 movs r3, #0 8001d12: 60fb str r3, [r7, #12] /* Check ADC handle */ if (hadc == NULL) 8001d14: 687b ldr r3, [r7, #4] 8001d16: 2b00 cmp r3, #0 8001d18: d101 bne.n 8001d1e { return HAL_ERROR; 8001d1a: 2301 movs r3, #1 8001d1c: e1a9 b.n 8002072 assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode)); if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 8001d1e: 687b ldr r3, [r7, #4] 8001d20: 695b ldr r3, [r3, #20] 8001d22: 2b00 cmp r3, #0 /* DISCEN and CONT bits cannot be set at the same time */ assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE))); /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 8001d24: 687b ldr r3, [r7, #4] 8001d26: 6ddb ldr r3, [r3, #92] @ 0x5c 8001d28: 2b00 cmp r3, #0 8001d2a: d109 bne.n 8001d40 /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 8001d2c: 6878 ldr r0, [r7, #4] 8001d2e: f7ff f9f1 bl 8001114 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 8001d32: 687b ldr r3, [r7, #4] 8001d34: 2200 movs r2, #0 8001d36: 661a str r2, [r3, #96] @ 0x60 /* Initialize Lock */ hadc->Lock = HAL_UNLOCKED; 8001d38: 687b ldr r3, [r7, #4] 8001d3a: 2200 movs r2, #0 8001d3c: f883 2058 strb.w r2, [r3, #88] @ 0x58 } /* - Exit from deep-power-down mode and ADC voltage regulator enable */ if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL) 8001d40: 687b ldr r3, [r7, #4] 8001d42: 681b ldr r3, [r3, #0] 8001d44: 4618 mov r0, r3 8001d46: f7ff ff41 bl 8001bcc 8001d4a: 4603 mov r3, r0 8001d4c: 2b00 cmp r3, #0 8001d4e: d004 beq.n 8001d5a { /* Disable ADC deep power down mode */ LL_ADC_DisableDeepPowerDown(hadc->Instance); 8001d50: 687b ldr r3, [r7, #4] 8001d52: 681b ldr r3, [r3, #0] 8001d54: 4618 mov r0, r3 8001d56: f7ff ff27 bl 8001ba8 /* System was in deep power down mode, calibration must be relaunched or a previously saved calibration factor re-applied once the ADC voltage regulator is enabled */ } if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) 8001d5a: 687b ldr r3, [r7, #4] 8001d5c: 681b ldr r3, [r3, #0] 8001d5e: 4618 mov r0, r3 8001d60: f7ff ff5c bl 8001c1c 8001d64: 4603 mov r3, r0 8001d66: 2b00 cmp r3, #0 8001d68: d115 bne.n 8001d96 { /* Enable ADC internal voltage regulator */ LL_ADC_EnableInternalRegulator(hadc->Instance); 8001d6a: 687b ldr r3, [r7, #4] 8001d6c: 681b ldr r3, [r3, #0] 8001d6e: 4618 mov r0, r3 8001d70: f7ff ff40 bl 8001bf4 /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 8001d74: 4b9c ldr r3, [pc, #624] @ (8001fe8 ) 8001d76: 681b ldr r3, [r3, #0] 8001d78: 099b lsrs r3, r3, #6 8001d7a: 4a9c ldr r2, [pc, #624] @ (8001fec ) 8001d7c: fba2 2303 umull r2, r3, r2, r3 8001d80: 099b lsrs r3, r3, #6 8001d82: 3301 adds r3, #1 8001d84: 005b lsls r3, r3, #1 8001d86: 60fb str r3, [r7, #12] while (wait_loop_index != 0UL) 8001d88: e002 b.n 8001d90 { wait_loop_index--; 8001d8a: 68fb ldr r3, [r7, #12] 8001d8c: 3b01 subs r3, #1 8001d8e: 60fb str r3, [r7, #12] while (wait_loop_index != 0UL) 8001d90: 68fb ldr r3, [r7, #12] 8001d92: 2b00 cmp r3, #0 8001d94: d1f9 bne.n 8001d8a } /* Verification that ADC voltage regulator is correctly enabled, whether */ /* or not ADC is coming from state reset (if any potential problem of */ /* clocking, voltage regulator would not be enabled). */ if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) 8001d96: 687b ldr r3, [r7, #4] 8001d98: 681b ldr r3, [r3, #0] 8001d9a: 4618 mov r0, r3 8001d9c: f7ff ff3e bl 8001c1c 8001da0: 4603 mov r3, r0 8001da2: 2b00 cmp r3, #0 8001da4: d10d bne.n 8001dc2 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8001da6: 687b ldr r3, [r7, #4] 8001da8: 6ddb ldr r3, [r3, #92] @ 0x5c 8001daa: f043 0210 orr.w r2, r3, #16 8001dae: 687b ldr r3, [r7, #4] 8001db0: 65da str r2, [r3, #92] @ 0x5c /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8001db2: 687b ldr r3, [r7, #4] 8001db4: 6e1b ldr r3, [r3, #96] @ 0x60 8001db6: f043 0201 orr.w r2, r3, #1 8001dba: 687b ldr r3, [r7, #4] 8001dbc: 661a str r2, [r3, #96] @ 0x60 tmp_hal_status = HAL_ERROR; 8001dbe: 2301 movs r3, #1 8001dc0: 77fb strb r3, [r7, #31] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed and if there is no conversion on going on regular */ /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */ /* called to update a parameter on the fly). */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); 8001dc2: 687b ldr r3, [r7, #4] 8001dc4: 681b ldr r3, [r3, #0] 8001dc6: 4618 mov r0, r3 8001dc8: f7ff ff76 bl 8001cb8 8001dcc: 6178 str r0, [r7, #20] if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) 8001dce: 687b ldr r3, [r7, #4] 8001dd0: 6ddb ldr r3, [r3, #92] @ 0x5c 8001dd2: f003 0310 and.w r3, r3, #16 8001dd6: 2b00 cmp r3, #0 8001dd8: f040 8142 bne.w 8002060 && (tmp_adc_is_conversion_on_going_regular == 0UL) 8001ddc: 697b ldr r3, [r7, #20] 8001dde: 2b00 cmp r3, #0 8001de0: f040 813e bne.w 8002060 ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8001de4: 687b ldr r3, [r7, #4] 8001de6: 6ddb ldr r3, [r3, #92] @ 0x5c 8001de8: f423 7381 bic.w r3, r3, #258 @ 0x102 8001dec: f043 0202 orr.w r2, r3, #2 8001df0: 687b ldr r3, [r7, #4] 8001df2: 65da str r2, [r3, #92] @ 0x5c /* Configuration of common ADC parameters */ /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - clock configuration */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 8001df4: 687b ldr r3, [r7, #4] 8001df6: 681b ldr r3, [r3, #0] 8001df8: 4618 mov r0, r3 8001dfa: f7ff ff37 bl 8001c6c 8001dfe: 4603 mov r3, r0 8001e00: 2b00 cmp r3, #0 8001e02: d141 bne.n 8001e88 { if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 8001e04: 687b ldr r3, [r7, #4] 8001e06: 681b ldr r3, [r3, #0] 8001e08: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 8001e0c: d004 beq.n 8001e18 8001e0e: 687b ldr r3, [r7, #4] 8001e10: 681b ldr r3, [r3, #0] 8001e12: 4a77 ldr r2, [pc, #476] @ (8001ff0 ) 8001e14: 4293 cmp r3, r2 8001e16: d10f bne.n 8001e38 8001e18: f04f 40a0 mov.w r0, #1342177280 @ 0x50000000 8001e1c: f7ff ff26 bl 8001c6c 8001e20: 4604 mov r4, r0 8001e22: 4873 ldr r0, [pc, #460] @ (8001ff0 ) 8001e24: f7ff ff22 bl 8001c6c 8001e28: 4603 mov r3, r0 8001e2a: 4323 orrs r3, r4 8001e2c: 2b00 cmp r3, #0 8001e2e: bf0c ite eq 8001e30: 2301 moveq r3, #1 8001e32: 2300 movne r3, #0 8001e34: b2db uxtb r3, r3 8001e36: e012 b.n 8001e5e 8001e38: 486e ldr r0, [pc, #440] @ (8001ff4 ) 8001e3a: f7ff ff17 bl 8001c6c 8001e3e: 4604 mov r4, r0 8001e40: 486d ldr r0, [pc, #436] @ (8001ff8 ) 8001e42: f7ff ff13 bl 8001c6c 8001e46: 4603 mov r3, r0 8001e48: 431c orrs r4, r3 8001e4a: 486c ldr r0, [pc, #432] @ (8001ffc ) 8001e4c: f7ff ff0e bl 8001c6c 8001e50: 4603 mov r3, r0 8001e52: 4323 orrs r3, r4 8001e54: 2b00 cmp r3, #0 8001e56: bf0c ite eq 8001e58: 2301 moveq r3, #1 8001e5a: 2300 movne r3, #0 8001e5c: b2db uxtb r3, r3 8001e5e: 2b00 cmp r3, #0 8001e60: d012 beq.n 8001e88 /* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */ /* HAL_ADCEx_MultiModeConfigChannel() ) */ /* - internal measurement paths: Vbat, temperature sensor, Vref */ /* (set into HAL_ADC_ConfigChannel() or */ /* HAL_ADCEx_InjectedConfigChannel() ) */ LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler); 8001e62: 687b ldr r3, [r7, #4] 8001e64: 681b ldr r3, [r3, #0] 8001e66: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 8001e6a: d004 beq.n 8001e76 8001e6c: 687b ldr r3, [r7, #4] 8001e6e: 681b ldr r3, [r3, #0] 8001e70: 4a5f ldr r2, [pc, #380] @ (8001ff0 ) 8001e72: 4293 cmp r3, r2 8001e74: d101 bne.n 8001e7a 8001e76: 4a62 ldr r2, [pc, #392] @ (8002000 ) 8001e78: e000 b.n 8001e7c 8001e7a: 4a62 ldr r2, [pc, #392] @ (8002004 ) 8001e7c: 687b ldr r3, [r7, #4] 8001e7e: 685b ldr r3, [r3, #4] 8001e80: 4619 mov r1, r3 8001e82: 4610 mov r0, r2 8001e84: f7ff fd42 bl 800190c /* - external trigger polarity Init.ExternalTrigConvEdge */ /* - continuous conversion mode Init.ContinuousConvMode */ /* - overrun Init.Overrun */ /* - discontinuous mode Init.DiscontinuousConvMode */ /* - discontinuous mode channel count Init.NbrOfDiscConversion */ tmp_cfgr = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8001e88: 687b ldr r3, [r7, #4] 8001e8a: 7f5b ldrb r3, [r3, #29] 8001e8c: 035a lsls r2, r3, #13 hadc->Init.Overrun | 8001e8e: 687b ldr r3, [r7, #4] 8001e90: 6bdb ldr r3, [r3, #60] @ 0x3c tmp_cfgr = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8001e92: 431a orrs r2, r3 hadc->Init.DataAlign | 8001e94: 687b ldr r3, [r7, #4] 8001e96: 68db ldr r3, [r3, #12] hadc->Init.Overrun | 8001e98: 431a orrs r2, r3 hadc->Init.Resolution | 8001e9a: 687b ldr r3, [r7, #4] 8001e9c: 689b ldr r3, [r3, #8] hadc->Init.DataAlign | 8001e9e: 431a orrs r2, r3 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); 8001ea0: 687b ldr r3, [r7, #4] 8001ea2: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 8001ea6: 041b lsls r3, r3, #16 tmp_cfgr = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8001ea8: 4313 orrs r3, r2 8001eaa: 61bb str r3, [r7, #24] if (hadc->Init.DiscontinuousConvMode == ENABLE) 8001eac: 687b ldr r3, [r7, #4] 8001eae: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 8001eb2: 2b01 cmp r3, #1 8001eb4: d106 bne.n 8001ec4 { tmp_cfgr |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion); 8001eb6: 687b ldr r3, [r7, #4] 8001eb8: 6a9b ldr r3, [r3, #40] @ 0x28 8001eba: 3b01 subs r3, #1 8001ebc: 045b lsls r3, r3, #17 8001ebe: 69ba ldr r2, [r7, #24] 8001ec0: 4313 orrs r3, r2 8001ec2: 61bb str r3, [r7, #24] /* Enable external trigger if trigger selection is different of software */ /* start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigConvEdge "trigger edge none" equivalent to */ /* software start. */ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) 8001ec4: 687b ldr r3, [r7, #4] 8001ec6: 6adb ldr r3, [r3, #44] @ 0x2c 8001ec8: 2b00 cmp r3, #0 8001eca: d009 beq.n 8001ee0 { tmp_cfgr |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) 8001ecc: 687b ldr r3, [r7, #4] 8001ece: 6adb ldr r3, [r3, #44] @ 0x2c 8001ed0: f403 7278 and.w r2, r3, #992 @ 0x3e0 | hadc->Init.ExternalTrigConvEdge 8001ed4: 687b ldr r3, [r7, #4] 8001ed6: 6b1b ldr r3, [r3, #48] @ 0x30 8001ed8: 4313 orrs r3, r2 tmp_cfgr |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) 8001eda: 69ba ldr r2, [r7, #24] 8001edc: 4313 orrs r3, r2 8001ede: 61bb str r3, [r7, #24] ); } /* Update Configuration Register CFGR */ MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmp_cfgr); 8001ee0: 687b ldr r3, [r7, #4] 8001ee2: 681b ldr r3, [r3, #0] 8001ee4: 68da ldr r2, [r3, #12] 8001ee6: 4b48 ldr r3, [pc, #288] @ (8002008 ) 8001ee8: 4013 ands r3, r2 8001eea: 687a ldr r2, [r7, #4] 8001eec: 6812 ldr r2, [r2, #0] 8001eee: 69b9 ldr r1, [r7, #24] 8001ef0: 430b orrs r3, r1 8001ef2: 60d3 str r3, [r2, #12] /* Configuration of sampling mode */ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, hadc->Init.SamplingMode); 8001ef4: 687b ldr r3, [r7, #4] 8001ef6: 681b ldr r3, [r3, #0] 8001ef8: 691b ldr r3, [r3, #16] 8001efa: f023 6140 bic.w r1, r3, #201326592 @ 0xc000000 8001efe: 687b ldr r3, [r7, #4] 8001f00: 6b5a ldr r2, [r3, #52] @ 0x34 8001f02: 687b ldr r3, [r7, #4] 8001f04: 681b ldr r3, [r3, #0] 8001f06: 430a orrs r2, r1 8001f08: 611a str r2, [r3, #16] /* conversion on going on regular and injected groups: */ /* - Gain Compensation Init.GainCompensation */ /* - DMA continuous request Init.DMAContinuousRequests */ /* - LowPowerAutoWait feature Init.LowPowerAutoWait */ /* - Oversampling parameters Init.Oversampling */ tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); 8001f0a: 687b ldr r3, [r7, #4] 8001f0c: 681b ldr r3, [r3, #0] 8001f0e: 4618 mov r0, r3 8001f10: f7ff fee5 bl 8001cde 8001f14: 6138 str r0, [r7, #16] if ((tmp_adc_is_conversion_on_going_regular == 0UL) 8001f16: 697b ldr r3, [r7, #20] 8001f18: 2b00 cmp r3, #0 8001f1a: d17f bne.n 800201c && (tmp_adc_is_conversion_on_going_injected == 0UL) 8001f1c: 693b ldr r3, [r7, #16] 8001f1e: 2b00 cmp r3, #0 8001f20: d17c bne.n 800201c ) { tmp_cfgr = (ADC_CFGR_DFSDM(hadc) | ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | 8001f22: 687b ldr r3, [r7, #4] 8001f24: 7f1b ldrb r3, [r3, #28] tmp_cfgr = (ADC_CFGR_DFSDM(hadc) | 8001f26: 039a lsls r2, r3, #14 ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests)); 8001f28: 687b ldr r3, [r7, #4] 8001f2a: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 8001f2e: 005b lsls r3, r3, #1 tmp_cfgr = (ADC_CFGR_DFSDM(hadc) | 8001f30: 4313 orrs r3, r2 8001f32: 61bb str r3, [r7, #24] MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmp_cfgr); 8001f34: 687b ldr r3, [r7, #4] 8001f36: 681b ldr r3, [r3, #0] 8001f38: 68db ldr r3, [r3, #12] 8001f3a: f423 4380 bic.w r3, r3, #16384 @ 0x4000 8001f3e: f023 0302 bic.w r3, r3, #2 8001f42: 687a ldr r2, [r7, #4] 8001f44: 6812 ldr r2, [r2, #0] 8001f46: 69b9 ldr r1, [r7, #24] 8001f48: 430b orrs r3, r1 8001f4a: 60d3 str r3, [r2, #12] if (hadc->Init.GainCompensation != 0UL) 8001f4c: 687b ldr r3, [r7, #4] 8001f4e: 691b ldr r3, [r3, #16] 8001f50: 2b00 cmp r3, #0 8001f52: d017 beq.n 8001f84 { SET_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP); 8001f54: 687b ldr r3, [r7, #4] 8001f56: 681b ldr r3, [r3, #0] 8001f58: 691a ldr r2, [r3, #16] 8001f5a: 687b ldr r3, [r7, #4] 8001f5c: 681b ldr r3, [r3, #0] 8001f5e: f442 3280 orr.w r2, r2, #65536 @ 0x10000 8001f62: 611a str r2, [r3, #16] MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, hadc->Init.GainCompensation); 8001f64: 687b ldr r3, [r7, #4] 8001f66: 681b ldr r3, [r3, #0] 8001f68: f8d3 30c0 ldr.w r3, [r3, #192] @ 0xc0 8001f6c: f423 537f bic.w r3, r3, #16320 @ 0x3fc0 8001f70: f023 033f bic.w r3, r3, #63 @ 0x3f 8001f74: 687a ldr r2, [r7, #4] 8001f76: 6911 ldr r1, [r2, #16] 8001f78: 687a ldr r2, [r7, #4] 8001f7a: 6812 ldr r2, [r2, #0] 8001f7c: 430b orrs r3, r1 8001f7e: f8c2 30c0 str.w r3, [r2, #192] @ 0xc0 8001f82: e013 b.n 8001fac } else { CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP); 8001f84: 687b ldr r3, [r7, #4] 8001f86: 681b ldr r3, [r3, #0] 8001f88: 691a ldr r2, [r3, #16] 8001f8a: 687b ldr r3, [r7, #4] 8001f8c: 681b ldr r3, [r3, #0] 8001f8e: f422 3280 bic.w r2, r2, #65536 @ 0x10000 8001f92: 611a str r2, [r3, #16] MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, 0UL); 8001f94: 687b ldr r3, [r7, #4] 8001f96: 681b ldr r3, [r3, #0] 8001f98: f8d3 30c0 ldr.w r3, [r3, #192] @ 0xc0 8001f9c: 687a ldr r2, [r7, #4] 8001f9e: 6812 ldr r2, [r2, #0] 8001fa0: f423 537f bic.w r3, r3, #16320 @ 0x3fc0 8001fa4: f023 033f bic.w r3, r3, #63 @ 0x3f 8001fa8: f8c2 30c0 str.w r3, [r2, #192] @ 0xc0 } if (hadc->Init.OversamplingMode == ENABLE) 8001fac: 687b ldr r3, [r7, #4] 8001fae: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 8001fb2: 2b01 cmp r3, #1 8001fb4: d12a bne.n 800200c /* Configuration of Oversampler: */ /* - Oversampling Ratio */ /* - Right bit shift */ /* - Triggered mode */ /* - Oversampling mode (continued/resumed) */ MODIFY_REG(hadc->Instance->CFGR2, 8001fb6: 687b ldr r3, [r7, #4] 8001fb8: 681b ldr r3, [r3, #0] 8001fba: 691b ldr r3, [r3, #16] 8001fbc: f423 63ff bic.w r3, r3, #2040 @ 0x7f8 8001fc0: f023 0304 bic.w r3, r3, #4 8001fc4: 687a ldr r2, [r7, #4] 8001fc6: 6c51 ldr r1, [r2, #68] @ 0x44 8001fc8: 687a ldr r2, [r7, #4] 8001fca: 6c92 ldr r2, [r2, #72] @ 0x48 8001fcc: 4311 orrs r1, r2 8001fce: 687a ldr r2, [r7, #4] 8001fd0: 6cd2 ldr r2, [r2, #76] @ 0x4c 8001fd2: 4311 orrs r1, r2 8001fd4: 687a ldr r2, [r7, #4] 8001fd6: 6d12 ldr r2, [r2, #80] @ 0x50 8001fd8: 430a orrs r2, r1 8001fda: 431a orrs r2, r3 8001fdc: 687b ldr r3, [r7, #4] 8001fde: 681b ldr r3, [r3, #0] 8001fe0: f042 0201 orr.w r2, r2, #1 8001fe4: 611a str r2, [r3, #16] 8001fe6: e019 b.n 800201c 8001fe8: 20000000 .word 0x20000000 8001fec: 053e2d63 .word 0x053e2d63 8001ff0: 50000100 .word 0x50000100 8001ff4: 50000400 .word 0x50000400 8001ff8: 50000500 .word 0x50000500 8001ffc: 50000600 .word 0x50000600 8002000: 50000300 .word 0x50000300 8002004: 50000700 .word 0x50000700 8002008: fff04007 .word 0xfff04007 ); } else { /* Disable ADC oversampling scope on ADC group regular */ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE); 800200c: 687b ldr r3, [r7, #4] 800200e: 681b ldr r3, [r3, #0] 8002010: 691a ldr r2, [r3, #16] 8002012: 687b ldr r3, [r7, #4] 8002014: 681b ldr r3, [r3, #0] 8002016: f022 0201 bic.w r2, r2, #1 800201a: 611a str r2, [r3, #16] /* Note: Scan mode is not present by hardware on this device, but */ /* emulated by software for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion". */ if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) 800201c: 687b ldr r3, [r7, #4] 800201e: 695b ldr r3, [r3, #20] 8002020: 2b01 cmp r3, #1 8002022: d10c bne.n 800203e { /* Set number of ranks in regular group sequencer */ MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1)); 8002024: 687b ldr r3, [r7, #4] 8002026: 681b ldr r3, [r3, #0] 8002028: 6b1b ldr r3, [r3, #48] @ 0x30 800202a: f023 010f bic.w r1, r3, #15 800202e: 687b ldr r3, [r7, #4] 8002030: 6a1b ldr r3, [r3, #32] 8002032: 1e5a subs r2, r3, #1 8002034: 687b ldr r3, [r7, #4] 8002036: 681b ldr r3, [r3, #0] 8002038: 430a orrs r2, r1 800203a: 631a str r2, [r3, #48] @ 0x30 800203c: e007 b.n 800204e } else { CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L); 800203e: 687b ldr r3, [r7, #4] 8002040: 681b ldr r3, [r3, #0] 8002042: 6b1a ldr r2, [r3, #48] @ 0x30 8002044: 687b ldr r3, [r7, #4] 8002046: 681b ldr r3, [r3, #0] 8002048: f022 020f bic.w r2, r2, #15 800204c: 631a str r2, [r3, #48] @ 0x30 } /* Initialize the ADC state */ /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); 800204e: 687b ldr r3, [r7, #4] 8002050: 6ddb ldr r3, [r3, #92] @ 0x5c 8002052: f023 0303 bic.w r3, r3, #3 8002056: f043 0201 orr.w r2, r3, #1 800205a: 687b ldr r3, [r7, #4] 800205c: 65da str r2, [r3, #92] @ 0x5c 800205e: e007 b.n 8002070 } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8002060: 687b ldr r3, [r7, #4] 8002062: 6ddb ldr r3, [r3, #92] @ 0x5c 8002064: f043 0210 orr.w r2, r3, #16 8002068: 687b ldr r3, [r7, #4] 800206a: 65da str r2, [r3, #92] @ 0x5c tmp_hal_status = HAL_ERROR; 800206c: 2301 movs r3, #1 800206e: 77fb strb r3, [r7, #31] } /* Return function status */ return tmp_hal_status; 8002070: 7ffb ldrb r3, [r7, #31] } 8002072: 4618 mov r0, r3 8002074: 3724 adds r7, #36 @ 0x24 8002076: 46bd mov sp, r7 8002078: bd90 pop {r4, r7, pc} 800207a: bf00 nop 0800207c : * @param hadc ADC handle * @param pConfig Structure of ADC channel assigned to ADC group regular. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig) { 800207c: b580 push {r7, lr} 800207e: b0b6 sub sp, #216 @ 0xd8 8002080: af00 add r7, sp, #0 8002082: 6078 str r0, [r7, #4] 8002084: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8002086: 2300 movs r3, #0 8002088: f887 30d7 strb.w r3, [r7, #215] @ 0xd7 uint32_t tmpOffsetShifted; uint32_t tmp_config_internal_channel; __IO uint32_t wait_loop_index = 0UL; 800208c: 2300 movs r3, #0 800208e: 60fb str r3, [r7, #12] { assert_param(IS_ADC_DIFF_CHANNEL(hadc, pConfig->Channel)); } /* Process locked */ __HAL_LOCK(hadc); 8002090: 687b ldr r3, [r7, #4] 8002092: f893 3058 ldrb.w r3, [r3, #88] @ 0x58 8002096: 2b01 cmp r3, #1 8002098: d102 bne.n 80020a0 800209a: 2302 movs r3, #2 800209c: f000 bc13 b.w 80028c6 80020a0: 687b ldr r3, [r7, #4] 80020a2: 2201 movs r2, #1 80020a4: f883 2058 strb.w r2, [r3, #88] @ 0x58 /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel number */ /* - Channel rank */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) 80020a8: 687b ldr r3, [r7, #4] 80020aa: 681b ldr r3, [r3, #0] 80020ac: 4618 mov r0, r3 80020ae: f7ff fe03 bl 8001cb8 80020b2: 4603 mov r3, r0 80020b4: 2b00 cmp r3, #0 80020b6: f040 83f3 bne.w 80028a0 { /* Set ADC group regular sequence: channel on the selected scan sequence rank */ LL_ADC_REG_SetSequencerRanks(hadc->Instance, pConfig->Rank, pConfig->Channel); 80020ba: 687b ldr r3, [r7, #4] 80020bc: 6818 ldr r0, [r3, #0] 80020be: 683b ldr r3, [r7, #0] 80020c0: 6859 ldr r1, [r3, #4] 80020c2: 683b ldr r3, [r7, #0] 80020c4: 681b ldr r3, [r3, #0] 80020c6: 461a mov r2, r3 80020c8: f7ff fcf2 bl 8001ab0 /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel sampling time */ /* - Channel offset */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); 80020cc: 687b ldr r3, [r7, #4] 80020ce: 681b ldr r3, [r3, #0] 80020d0: 4618 mov r0, r3 80020d2: f7ff fdf1 bl 8001cb8 80020d6: f8c7 00d0 str.w r0, [r7, #208] @ 0xd0 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); 80020da: 687b ldr r3, [r7, #4] 80020dc: 681b ldr r3, [r3, #0] 80020de: 4618 mov r0, r3 80020e0: f7ff fdfd bl 8001cde 80020e4: f8c7 00cc str.w r0, [r7, #204] @ 0xcc if ((tmp_adc_is_conversion_on_going_regular == 0UL) 80020e8: f8d7 30d0 ldr.w r3, [r7, #208] @ 0xd0 80020ec: 2b00 cmp r3, #0 80020ee: f040 81d9 bne.w 80024a4 && (tmp_adc_is_conversion_on_going_injected == 0UL) 80020f2: f8d7 30cc ldr.w r3, [r7, #204] @ 0xcc 80020f6: 2b00 cmp r3, #0 80020f8: f040 81d4 bne.w 80024a4 ) { /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */ if (pConfig->SamplingTime == ADC_SAMPLETIME_3CYCLES_5) 80020fc: 683b ldr r3, [r7, #0] 80020fe: 689b ldr r3, [r3, #8] 8002100: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8002104: d10f bne.n 8002126 { /* Set sampling time of the selected ADC channel */ LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, LL_ADC_SAMPLINGTIME_2CYCLES_5); 8002106: 687b ldr r3, [r7, #4] 8002108: 6818 ldr r0, [r3, #0] 800210a: 683b ldr r3, [r7, #0] 800210c: 681b ldr r3, [r3, #0] 800210e: 2200 movs r2, #0 8002110: 4619 mov r1, r3 8002112: f7ff fcf9 bl 8001b08 /* Set ADC sampling time common configuration */ LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5); 8002116: 687b ldr r3, [r7, #4] 8002118: 681b ldr r3, [r3, #0] 800211a: f04f 4100 mov.w r1, #2147483648 @ 0x80000000 800211e: 4618 mov r0, r3 8002120: f7ff fcb3 bl 8001a8a 8002124: e00e b.n 8002144 } else { /* Set sampling time of the selected ADC channel */ LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, pConfig->SamplingTime); 8002126: 687b ldr r3, [r7, #4] 8002128: 6818 ldr r0, [r3, #0] 800212a: 683b ldr r3, [r7, #0] 800212c: 6819 ldr r1, [r3, #0] 800212e: 683b ldr r3, [r7, #0] 8002130: 689b ldr r3, [r3, #8] 8002132: 461a mov r2, r3 8002134: f7ff fce8 bl 8001b08 /* Set ADC sampling time common configuration */ LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT); 8002138: 687b ldr r3, [r7, #4] 800213a: 681b ldr r3, [r3, #0] 800213c: 2100 movs r1, #0 800213e: 4618 mov r0, r3 8002140: f7ff fca3 bl 8001a8a /* Configure the offset: offset enable/disable, channel, offset value */ /* Shift the offset with respect to the selected ADC resolution. */ /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)pConfig->Offset); 8002144: 683b ldr r3, [r7, #0] 8002146: 695a ldr r2, [r3, #20] 8002148: 687b ldr r3, [r7, #4] 800214a: 681b ldr r3, [r3, #0] 800214c: 68db ldr r3, [r3, #12] 800214e: 08db lsrs r3, r3, #3 8002150: f003 0303 and.w r3, r3, #3 8002154: 005b lsls r3, r3, #1 8002156: fa02 f303 lsl.w r3, r2, r3 800215a: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 if (pConfig->OffsetNumber != ADC_OFFSET_NONE) 800215e: 683b ldr r3, [r7, #0] 8002160: 691b ldr r3, [r3, #16] 8002162: 2b04 cmp r3, #4 8002164: d022 beq.n 80021ac { /* Set ADC selected offset number */ LL_ADC_SetOffset(hadc->Instance, pConfig->OffsetNumber, pConfig->Channel, tmpOffsetShifted); 8002166: 687b ldr r3, [r7, #4] 8002168: 6818 ldr r0, [r3, #0] 800216a: 683b ldr r3, [r7, #0] 800216c: 6919 ldr r1, [r3, #16] 800216e: 683b ldr r3, [r7, #0] 8002170: 681a ldr r2, [r3, #0] 8002172: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8 8002176: f7ff fbfd bl 8001974 assert_param(IS_ADC_OFFSET_SIGN(pConfig->OffsetSign)); assert_param(IS_FUNCTIONAL_STATE(pConfig->OffsetSaturation)); /* Set ADC selected offset sign & saturation */ LL_ADC_SetOffsetSign(hadc->Instance, pConfig->OffsetNumber, pConfig->OffsetSign); 800217a: 687b ldr r3, [r7, #4] 800217c: 6818 ldr r0, [r3, #0] 800217e: 683b ldr r3, [r7, #0] 8002180: 6919 ldr r1, [r3, #16] 8002182: 683b ldr r3, [r7, #0] 8002184: 699b ldr r3, [r3, #24] 8002186: 461a mov r2, r3 8002188: f7ff fc49 bl 8001a1e LL_ADC_SetOffsetSaturation(hadc->Instance, pConfig->OffsetNumber, 800218c: 687b ldr r3, [r7, #4] 800218e: 6818 ldr r0, [r3, #0] 8002190: 683b ldr r3, [r7, #0] 8002192: 6919 ldr r1, [r3, #16] (pConfig->OffsetSaturation == ENABLE) ? 8002194: 683b ldr r3, [r7, #0] 8002196: 7f1b ldrb r3, [r3, #28] LL_ADC_SetOffsetSaturation(hadc->Instance, pConfig->OffsetNumber, 8002198: 2b01 cmp r3, #1 800219a: d102 bne.n 80021a2 800219c: f04f 7300 mov.w r3, #33554432 @ 0x2000000 80021a0: e000 b.n 80021a4 80021a2: 2300 movs r3, #0 80021a4: 461a mov r2, r3 80021a6: f7ff fc55 bl 8001a54 80021aa: e17b b.n 80024a4 } else { /* Scan each offset register to check if the selected channel is targeted. */ /* If this is the case, the corresponding offset number is disabled. */ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) 80021ac: 687b ldr r3, [r7, #4] 80021ae: 681b ldr r3, [r3, #0] 80021b0: 2100 movs r1, #0 80021b2: 4618 mov r0, r3 80021b4: f7ff fc02 bl 80019bc 80021b8: 4603 mov r3, r0 80021ba: f3c3 0312 ubfx r3, r3, #0, #19 80021be: 2b00 cmp r3, #0 80021c0: d10a bne.n 80021d8 80021c2: 687b ldr r3, [r7, #4] 80021c4: 681b ldr r3, [r3, #0] 80021c6: 2100 movs r1, #0 80021c8: 4618 mov r0, r3 80021ca: f7ff fbf7 bl 80019bc 80021ce: 4603 mov r3, r0 80021d0: 0e9b lsrs r3, r3, #26 80021d2: f003 021f and.w r2, r3, #31 80021d6: e01e b.n 8002216 80021d8: 687b ldr r3, [r7, #4] 80021da: 681b ldr r3, [r3, #0] 80021dc: 2100 movs r1, #0 80021de: 4618 mov r0, r3 80021e0: f7ff fbec bl 80019bc 80021e4: 4603 mov r3, r0 80021e6: f8c7 30bc str.w r3, [r7, #188] @ 0xbc uint32_t result; #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80021ea: f8d7 30bc ldr.w r3, [r7, #188] @ 0xbc 80021ee: fa93 f3a3 rbit r3, r3 80021f2: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return result; 80021f6: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0 80021fa: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 optimisations using the logic "value was passed to __builtin_clz, so it is non-zero". ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a single CLZ instruction. */ if (value == 0U) 80021fe: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8 8002202: 2b00 cmp r3, #0 8002204: d101 bne.n 800220a { return 32U; 8002206: 2320 movs r3, #32 8002208: e004 b.n 8002214 } return __builtin_clz(value); 800220a: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8 800220e: fab3 f383 clz r3, r3 8002212: b2db uxtb r3, r3 8002214: 461a mov r2, r3 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) 8002216: 683b ldr r3, [r7, #0] 8002218: 681b ldr r3, [r3, #0] 800221a: f3c3 0312 ubfx r3, r3, #0, #19 800221e: 2b00 cmp r3, #0 8002220: d105 bne.n 800222e 8002222: 683b ldr r3, [r7, #0] 8002224: 681b ldr r3, [r3, #0] 8002226: 0e9b lsrs r3, r3, #26 8002228: f003 031f and.w r3, r3, #31 800222c: e018 b.n 8002260 800222e: 683b ldr r3, [r7, #0] 8002230: 681b ldr r3, [r3, #0] 8002232: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8002236: f8d7 30b0 ldr.w r3, [r7, #176] @ 0xb0 800223a: fa93 f3a3 rbit r3, r3 800223e: f8c7 30ac str.w r3, [r7, #172] @ 0xac return result; 8002242: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8002246: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 if (value == 0U) 800224a: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 800224e: 2b00 cmp r3, #0 8002250: d101 bne.n 8002256 return 32U; 8002252: 2320 movs r3, #32 8002254: e004 b.n 8002260 return __builtin_clz(value); 8002256: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 800225a: fab3 f383 clz r3, r3 800225e: b2db uxtb r3, r3 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) 8002260: 429a cmp r2, r3 8002262: d106 bne.n 8002272 { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE); 8002264: 687b ldr r3, [r7, #4] 8002266: 681b ldr r3, [r3, #0] 8002268: 2200 movs r2, #0 800226a: 2100 movs r1, #0 800226c: 4618 mov r0, r3 800226e: f7ff fbbb bl 80019e8 } if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) 8002272: 687b ldr r3, [r7, #4] 8002274: 681b ldr r3, [r3, #0] 8002276: 2101 movs r1, #1 8002278: 4618 mov r0, r3 800227a: f7ff fb9f bl 80019bc 800227e: 4603 mov r3, r0 8002280: f3c3 0312 ubfx r3, r3, #0, #19 8002284: 2b00 cmp r3, #0 8002286: d10a bne.n 800229e 8002288: 687b ldr r3, [r7, #4] 800228a: 681b ldr r3, [r3, #0] 800228c: 2101 movs r1, #1 800228e: 4618 mov r0, r3 8002290: f7ff fb94 bl 80019bc 8002294: 4603 mov r3, r0 8002296: 0e9b lsrs r3, r3, #26 8002298: f003 021f and.w r2, r3, #31 800229c: e01e b.n 80022dc 800229e: 687b ldr r3, [r7, #4] 80022a0: 681b ldr r3, [r3, #0] 80022a2: 2101 movs r1, #1 80022a4: 4618 mov r0, r3 80022a6: f7ff fb89 bl 80019bc 80022aa: 4603 mov r3, r0 80022ac: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80022b0: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4 80022b4: fa93 f3a3 rbit r3, r3 80022b8: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 return result; 80022bc: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 80022c0: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 if (value == 0U) 80022c4: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 80022c8: 2b00 cmp r3, #0 80022ca: d101 bne.n 80022d0 return 32U; 80022cc: 2320 movs r3, #32 80022ce: e004 b.n 80022da return __builtin_clz(value); 80022d0: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 80022d4: fab3 f383 clz r3, r3 80022d8: b2db uxtb r3, r3 80022da: 461a mov r2, r3 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) 80022dc: 683b ldr r3, [r7, #0] 80022de: 681b ldr r3, [r3, #0] 80022e0: f3c3 0312 ubfx r3, r3, #0, #19 80022e4: 2b00 cmp r3, #0 80022e6: d105 bne.n 80022f4 80022e8: 683b ldr r3, [r7, #0] 80022ea: 681b ldr r3, [r3, #0] 80022ec: 0e9b lsrs r3, r3, #26 80022ee: f003 031f and.w r3, r3, #31 80022f2: e018 b.n 8002326 80022f4: 683b ldr r3, [r7, #0] 80022f6: 681b ldr r3, [r3, #0] 80022f8: f8c7 3098 str.w r3, [r7, #152] @ 0x98 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80022fc: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 8002300: fa93 f3a3 rbit r3, r3 8002304: f8c7 3094 str.w r3, [r7, #148] @ 0x94 return result; 8002308: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94 800230c: f8c7 309c str.w r3, [r7, #156] @ 0x9c if (value == 0U) 8002310: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 8002314: 2b00 cmp r3, #0 8002316: d101 bne.n 800231c return 32U; 8002318: 2320 movs r3, #32 800231a: e004 b.n 8002326 return __builtin_clz(value); 800231c: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 8002320: fab3 f383 clz r3, r3 8002324: b2db uxtb r3, r3 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) 8002326: 429a cmp r2, r3 8002328: d106 bne.n 8002338 { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE); 800232a: 687b ldr r3, [r7, #4] 800232c: 681b ldr r3, [r3, #0] 800232e: 2200 movs r2, #0 8002330: 2101 movs r1, #1 8002332: 4618 mov r0, r3 8002334: f7ff fb58 bl 80019e8 } if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) 8002338: 687b ldr r3, [r7, #4] 800233a: 681b ldr r3, [r3, #0] 800233c: 2102 movs r1, #2 800233e: 4618 mov r0, r3 8002340: f7ff fb3c bl 80019bc 8002344: 4603 mov r3, r0 8002346: f3c3 0312 ubfx r3, r3, #0, #19 800234a: 2b00 cmp r3, #0 800234c: d10a bne.n 8002364 800234e: 687b ldr r3, [r7, #4] 8002350: 681b ldr r3, [r3, #0] 8002352: 2102 movs r1, #2 8002354: 4618 mov r0, r3 8002356: f7ff fb31 bl 80019bc 800235a: 4603 mov r3, r0 800235c: 0e9b lsrs r3, r3, #26 800235e: f003 021f and.w r2, r3, #31 8002362: e01e b.n 80023a2 8002364: 687b ldr r3, [r7, #4] 8002366: 681b ldr r3, [r3, #0] 8002368: 2102 movs r1, #2 800236a: 4618 mov r0, r3 800236c: f7ff fb26 bl 80019bc 8002370: 4603 mov r3, r0 8002372: f8c7 308c str.w r3, [r7, #140] @ 0x8c __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8002376: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 800237a: fa93 f3a3 rbit r3, r3 800237e: f8c7 3088 str.w r3, [r7, #136] @ 0x88 return result; 8002382: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 8002386: f8c7 3090 str.w r3, [r7, #144] @ 0x90 if (value == 0U) 800238a: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 800238e: 2b00 cmp r3, #0 8002390: d101 bne.n 8002396 return 32U; 8002392: 2320 movs r3, #32 8002394: e004 b.n 80023a0 return __builtin_clz(value); 8002396: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 800239a: fab3 f383 clz r3, r3 800239e: b2db uxtb r3, r3 80023a0: 461a mov r2, r3 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) 80023a2: 683b ldr r3, [r7, #0] 80023a4: 681b ldr r3, [r3, #0] 80023a6: f3c3 0312 ubfx r3, r3, #0, #19 80023aa: 2b00 cmp r3, #0 80023ac: d105 bne.n 80023ba 80023ae: 683b ldr r3, [r7, #0] 80023b0: 681b ldr r3, [r3, #0] 80023b2: 0e9b lsrs r3, r3, #26 80023b4: f003 031f and.w r3, r3, #31 80023b8: e016 b.n 80023e8 80023ba: 683b ldr r3, [r7, #0] 80023bc: 681b ldr r3, [r3, #0] 80023be: f8c7 3080 str.w r3, [r7, #128] @ 0x80 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80023c2: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 80023c6: fa93 f3a3 rbit r3, r3 80023ca: 67fb str r3, [r7, #124] @ 0x7c return result; 80023cc: 6ffb ldr r3, [r7, #124] @ 0x7c 80023ce: f8c7 3084 str.w r3, [r7, #132] @ 0x84 if (value == 0U) 80023d2: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 80023d6: 2b00 cmp r3, #0 80023d8: d101 bne.n 80023de return 32U; 80023da: 2320 movs r3, #32 80023dc: e004 b.n 80023e8 return __builtin_clz(value); 80023de: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 80023e2: fab3 f383 clz r3, r3 80023e6: b2db uxtb r3, r3 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) 80023e8: 429a cmp r2, r3 80023ea: d106 bne.n 80023fa { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE); 80023ec: 687b ldr r3, [r7, #4] 80023ee: 681b ldr r3, [r3, #0] 80023f0: 2200 movs r2, #0 80023f2: 2102 movs r1, #2 80023f4: 4618 mov r0, r3 80023f6: f7ff faf7 bl 80019e8 } if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) 80023fa: 687b ldr r3, [r7, #4] 80023fc: 681b ldr r3, [r3, #0] 80023fe: 2103 movs r1, #3 8002400: 4618 mov r0, r3 8002402: f7ff fadb bl 80019bc 8002406: 4603 mov r3, r0 8002408: f3c3 0312 ubfx r3, r3, #0, #19 800240c: 2b00 cmp r3, #0 800240e: d10a bne.n 8002426 8002410: 687b ldr r3, [r7, #4] 8002412: 681b ldr r3, [r3, #0] 8002414: 2103 movs r1, #3 8002416: 4618 mov r0, r3 8002418: f7ff fad0 bl 80019bc 800241c: 4603 mov r3, r0 800241e: 0e9b lsrs r3, r3, #26 8002420: f003 021f and.w r2, r3, #31 8002424: e017 b.n 8002456 8002426: 687b ldr r3, [r7, #4] 8002428: 681b ldr r3, [r3, #0] 800242a: 2103 movs r1, #3 800242c: 4618 mov r0, r3 800242e: f7ff fac5 bl 80019bc 8002432: 4603 mov r3, r0 8002434: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8002436: 6f7b ldr r3, [r7, #116] @ 0x74 8002438: fa93 f3a3 rbit r3, r3 800243c: 673b str r3, [r7, #112] @ 0x70 return result; 800243e: 6f3b ldr r3, [r7, #112] @ 0x70 8002440: 67bb str r3, [r7, #120] @ 0x78 if (value == 0U) 8002442: 6fbb ldr r3, [r7, #120] @ 0x78 8002444: 2b00 cmp r3, #0 8002446: d101 bne.n 800244c return 32U; 8002448: 2320 movs r3, #32 800244a: e003 b.n 8002454 return __builtin_clz(value); 800244c: 6fbb ldr r3, [r7, #120] @ 0x78 800244e: fab3 f383 clz r3, r3 8002452: b2db uxtb r3, r3 8002454: 461a mov r2, r3 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) 8002456: 683b ldr r3, [r7, #0] 8002458: 681b ldr r3, [r3, #0] 800245a: f3c3 0312 ubfx r3, r3, #0, #19 800245e: 2b00 cmp r3, #0 8002460: d105 bne.n 800246e 8002462: 683b ldr r3, [r7, #0] 8002464: 681b ldr r3, [r3, #0] 8002466: 0e9b lsrs r3, r3, #26 8002468: f003 031f and.w r3, r3, #31 800246c: e011 b.n 8002492 800246e: 683b ldr r3, [r7, #0] 8002470: 681b ldr r3, [r3, #0] 8002472: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8002474: 6ebb ldr r3, [r7, #104] @ 0x68 8002476: fa93 f3a3 rbit r3, r3 800247a: 667b str r3, [r7, #100] @ 0x64 return result; 800247c: 6e7b ldr r3, [r7, #100] @ 0x64 800247e: 66fb str r3, [r7, #108] @ 0x6c if (value == 0U) 8002480: 6efb ldr r3, [r7, #108] @ 0x6c 8002482: 2b00 cmp r3, #0 8002484: d101 bne.n 800248a return 32U; 8002486: 2320 movs r3, #32 8002488: e003 b.n 8002492 return __builtin_clz(value); 800248a: 6efb ldr r3, [r7, #108] @ 0x6c 800248c: fab3 f383 clz r3, r3 8002490: b2db uxtb r3, r3 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) 8002492: 429a cmp r2, r3 8002494: d106 bne.n 80024a4 { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE); 8002496: 687b ldr r3, [r7, #4] 8002498: 681b ldr r3, [r3, #0] 800249a: 2200 movs r2, #0 800249c: 2103 movs r1, #3 800249e: 4618 mov r0, r3 80024a0: f7ff faa2 bl 80019e8 } /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - Single or differential mode */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 80024a4: 687b ldr r3, [r7, #4] 80024a6: 681b ldr r3, [r3, #0] 80024a8: 4618 mov r0, r3 80024aa: f7ff fbdf bl 8001c6c 80024ae: 4603 mov r3, r0 80024b0: 2b00 cmp r3, #0 80024b2: f040 813d bne.w 8002730 { /* Set mode single-ended or differential input of the selected ADC channel */ LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfig->Channel, pConfig->SingleDiff); 80024b6: 687b ldr r3, [r7, #4] 80024b8: 6818 ldr r0, [r3, #0] 80024ba: 683b ldr r3, [r7, #0] 80024bc: 6819 ldr r1, [r3, #0] 80024be: 683b ldr r3, [r7, #0] 80024c0: 68db ldr r3, [r3, #12] 80024c2: 461a mov r2, r3 80024c4: f7ff fb4c bl 8001b60 /* Configuration of differential mode */ if (pConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED) 80024c8: 683b ldr r3, [r7, #0] 80024ca: 68db ldr r3, [r3, #12] 80024cc: 4aa2 ldr r2, [pc, #648] @ (8002758 ) 80024ce: 4293 cmp r3, r2 80024d0: f040 812e bne.w 8002730 { /* Set sampling time of the selected ADC channel */ /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */ LL_ADC_SetChannelSamplingTime(hadc->Instance, 80024d4: 687b ldr r3, [r7, #4] 80024d6: 6818 ldr r0, [r3, #0] (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL( 80024d8: 683b ldr r3, [r7, #0] 80024da: 681b ldr r3, [r3, #0] 80024dc: f3c3 0312 ubfx r3, r3, #0, #19 80024e0: 2b00 cmp r3, #0 80024e2: d10b bne.n 80024fc 80024e4: 683b ldr r3, [r7, #0] 80024e6: 681b ldr r3, [r3, #0] 80024e8: 0e9b lsrs r3, r3, #26 80024ea: 3301 adds r3, #1 80024ec: f003 031f and.w r3, r3, #31 80024f0: 2b09 cmp r3, #9 80024f2: bf94 ite ls 80024f4: 2301 movls r3, #1 80024f6: 2300 movhi r3, #0 80024f8: b2db uxtb r3, r3 80024fa: e019 b.n 8002530 80024fc: 683b ldr r3, [r7, #0] 80024fe: 681b ldr r3, [r3, #0] 8002500: 65fb str r3, [r7, #92] @ 0x5c __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8002502: 6dfb ldr r3, [r7, #92] @ 0x5c 8002504: fa93 f3a3 rbit r3, r3 8002508: 65bb str r3, [r7, #88] @ 0x58 return result; 800250a: 6dbb ldr r3, [r7, #88] @ 0x58 800250c: 663b str r3, [r7, #96] @ 0x60 if (value == 0U) 800250e: 6e3b ldr r3, [r7, #96] @ 0x60 8002510: 2b00 cmp r3, #0 8002512: d101 bne.n 8002518 return 32U; 8002514: 2320 movs r3, #32 8002516: e003 b.n 8002520 return __builtin_clz(value); 8002518: 6e3b ldr r3, [r7, #96] @ 0x60 800251a: fab3 f383 clz r3, r3 800251e: b2db uxtb r3, r3 8002520: 3301 adds r3, #1 8002522: f003 031f and.w r3, r3, #31 8002526: 2b09 cmp r3, #9 8002528: bf94 ite ls 800252a: 2301 movls r3, #1 800252c: 2300 movhi r3, #0 800252e: b2db uxtb r3, r3 LL_ADC_SetChannelSamplingTime(hadc->Instance, 8002530: 2b00 cmp r3, #0 8002532: d079 beq.n 8002628 (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL( 8002534: 683b ldr r3, [r7, #0] 8002536: 681b ldr r3, [r3, #0] 8002538: f3c3 0312 ubfx r3, r3, #0, #19 800253c: 2b00 cmp r3, #0 800253e: d107 bne.n 8002550 8002540: 683b ldr r3, [r7, #0] 8002542: 681b ldr r3, [r3, #0] 8002544: 0e9b lsrs r3, r3, #26 8002546: 3301 adds r3, #1 8002548: 069b lsls r3, r3, #26 800254a: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 800254e: e015 b.n 800257c 8002550: 683b ldr r3, [r7, #0] 8002552: 681b ldr r3, [r3, #0] 8002554: 653b str r3, [r7, #80] @ 0x50 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8002556: 6d3b ldr r3, [r7, #80] @ 0x50 8002558: fa93 f3a3 rbit r3, r3 800255c: 64fb str r3, [r7, #76] @ 0x4c return result; 800255e: 6cfb ldr r3, [r7, #76] @ 0x4c 8002560: 657b str r3, [r7, #84] @ 0x54 if (value == 0U) 8002562: 6d7b ldr r3, [r7, #84] @ 0x54 8002564: 2b00 cmp r3, #0 8002566: d101 bne.n 800256c return 32U; 8002568: 2320 movs r3, #32 800256a: e003 b.n 8002574 return __builtin_clz(value); 800256c: 6d7b ldr r3, [r7, #84] @ 0x54 800256e: fab3 f383 clz r3, r3 8002572: b2db uxtb r3, r3 8002574: 3301 adds r3, #1 8002576: 069b lsls r3, r3, #26 8002578: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 800257c: 683b ldr r3, [r7, #0] 800257e: 681b ldr r3, [r3, #0] 8002580: f3c3 0312 ubfx r3, r3, #0, #19 8002584: 2b00 cmp r3, #0 8002586: d109 bne.n 800259c 8002588: 683b ldr r3, [r7, #0] 800258a: 681b ldr r3, [r3, #0] 800258c: 0e9b lsrs r3, r3, #26 800258e: 3301 adds r3, #1 8002590: f003 031f and.w r3, r3, #31 8002594: 2101 movs r1, #1 8002596: fa01 f303 lsl.w r3, r1, r3 800259a: e017 b.n 80025cc 800259c: 683b ldr r3, [r7, #0] 800259e: 681b ldr r3, [r3, #0] 80025a0: 647b str r3, [r7, #68] @ 0x44 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80025a2: 6c7b ldr r3, [r7, #68] @ 0x44 80025a4: fa93 f3a3 rbit r3, r3 80025a8: 643b str r3, [r7, #64] @ 0x40 return result; 80025aa: 6c3b ldr r3, [r7, #64] @ 0x40 80025ac: 64bb str r3, [r7, #72] @ 0x48 if (value == 0U) 80025ae: 6cbb ldr r3, [r7, #72] @ 0x48 80025b0: 2b00 cmp r3, #0 80025b2: d101 bne.n 80025b8 return 32U; 80025b4: 2320 movs r3, #32 80025b6: e003 b.n 80025c0 return __builtin_clz(value); 80025b8: 6cbb ldr r3, [r7, #72] @ 0x48 80025ba: fab3 f383 clz r3, r3 80025be: b2db uxtb r3, r3 80025c0: 3301 adds r3, #1 80025c2: f003 031f and.w r3, r3, #31 80025c6: 2101 movs r1, #1 80025c8: fa01 f303 lsl.w r3, r1, r3 80025cc: ea42 0103 orr.w r1, r2, r3 80025d0: 683b ldr r3, [r7, #0] 80025d2: 681b ldr r3, [r3, #0] 80025d4: f3c3 0312 ubfx r3, r3, #0, #19 80025d8: 2b00 cmp r3, #0 80025da: d10a bne.n 80025f2 80025dc: 683b ldr r3, [r7, #0] 80025de: 681b ldr r3, [r3, #0] 80025e0: 0e9b lsrs r3, r3, #26 80025e2: 3301 adds r3, #1 80025e4: f003 021f and.w r2, r3, #31 80025e8: 4613 mov r3, r2 80025ea: 005b lsls r3, r3, #1 80025ec: 4413 add r3, r2 80025ee: 051b lsls r3, r3, #20 80025f0: e018 b.n 8002624 80025f2: 683b ldr r3, [r7, #0] 80025f4: 681b ldr r3, [r3, #0] 80025f6: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80025f8: 6bbb ldr r3, [r7, #56] @ 0x38 80025fa: fa93 f3a3 rbit r3, r3 80025fe: 637b str r3, [r7, #52] @ 0x34 return result; 8002600: 6b7b ldr r3, [r7, #52] @ 0x34 8002602: 63fb str r3, [r7, #60] @ 0x3c if (value == 0U) 8002604: 6bfb ldr r3, [r7, #60] @ 0x3c 8002606: 2b00 cmp r3, #0 8002608: d101 bne.n 800260e return 32U; 800260a: 2320 movs r3, #32 800260c: e003 b.n 8002616 return __builtin_clz(value); 800260e: 6bfb ldr r3, [r7, #60] @ 0x3c 8002610: fab3 f383 clz r3, r3 8002614: b2db uxtb r3, r3 8002616: 3301 adds r3, #1 8002618: f003 021f and.w r2, r3, #31 800261c: 4613 mov r3, r2 800261e: 005b lsls r3, r3, #1 8002620: 4413 add r3, r2 8002622: 051b lsls r3, r3, #20 LL_ADC_SetChannelSamplingTime(hadc->Instance, 8002624: 430b orrs r3, r1 8002626: e07e b.n 8002726 (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL( 8002628: 683b ldr r3, [r7, #0] 800262a: 681b ldr r3, [r3, #0] 800262c: f3c3 0312 ubfx r3, r3, #0, #19 8002630: 2b00 cmp r3, #0 8002632: d107 bne.n 8002644 8002634: 683b ldr r3, [r7, #0] 8002636: 681b ldr r3, [r3, #0] 8002638: 0e9b lsrs r3, r3, #26 800263a: 3301 adds r3, #1 800263c: 069b lsls r3, r3, #26 800263e: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8002642: e015 b.n 8002670 8002644: 683b ldr r3, [r7, #0] 8002646: 681b ldr r3, [r3, #0] 8002648: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 800264a: 6afb ldr r3, [r7, #44] @ 0x2c 800264c: fa93 f3a3 rbit r3, r3 8002650: 62bb str r3, [r7, #40] @ 0x28 return result; 8002652: 6abb ldr r3, [r7, #40] @ 0x28 8002654: 633b str r3, [r7, #48] @ 0x30 if (value == 0U) 8002656: 6b3b ldr r3, [r7, #48] @ 0x30 8002658: 2b00 cmp r3, #0 800265a: d101 bne.n 8002660 return 32U; 800265c: 2320 movs r3, #32 800265e: e003 b.n 8002668 return __builtin_clz(value); 8002660: 6b3b ldr r3, [r7, #48] @ 0x30 8002662: fab3 f383 clz r3, r3 8002666: b2db uxtb r3, r3 8002668: 3301 adds r3, #1 800266a: 069b lsls r3, r3, #26 800266c: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8002670: 683b ldr r3, [r7, #0] 8002672: 681b ldr r3, [r3, #0] 8002674: f3c3 0312 ubfx r3, r3, #0, #19 8002678: 2b00 cmp r3, #0 800267a: d109 bne.n 8002690 800267c: 683b ldr r3, [r7, #0] 800267e: 681b ldr r3, [r3, #0] 8002680: 0e9b lsrs r3, r3, #26 8002682: 3301 adds r3, #1 8002684: f003 031f and.w r3, r3, #31 8002688: 2101 movs r1, #1 800268a: fa01 f303 lsl.w r3, r1, r3 800268e: e017 b.n 80026c0 8002690: 683b ldr r3, [r7, #0] 8002692: 681b ldr r3, [r3, #0] 8002694: 623b str r3, [r7, #32] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8002696: 6a3b ldr r3, [r7, #32] 8002698: fa93 f3a3 rbit r3, r3 800269c: 61fb str r3, [r7, #28] return result; 800269e: 69fb ldr r3, [r7, #28] 80026a0: 627b str r3, [r7, #36] @ 0x24 if (value == 0U) 80026a2: 6a7b ldr r3, [r7, #36] @ 0x24 80026a4: 2b00 cmp r3, #0 80026a6: d101 bne.n 80026ac return 32U; 80026a8: 2320 movs r3, #32 80026aa: e003 b.n 80026b4 return __builtin_clz(value); 80026ac: 6a7b ldr r3, [r7, #36] @ 0x24 80026ae: fab3 f383 clz r3, r3 80026b2: b2db uxtb r3, r3 80026b4: 3301 adds r3, #1 80026b6: f003 031f and.w r3, r3, #31 80026ba: 2101 movs r1, #1 80026bc: fa01 f303 lsl.w r3, r1, r3 80026c0: ea42 0103 orr.w r1, r2, r3 80026c4: 683b ldr r3, [r7, #0] 80026c6: 681b ldr r3, [r3, #0] 80026c8: f3c3 0312 ubfx r3, r3, #0, #19 80026cc: 2b00 cmp r3, #0 80026ce: d10d bne.n 80026ec 80026d0: 683b ldr r3, [r7, #0] 80026d2: 681b ldr r3, [r3, #0] 80026d4: 0e9b lsrs r3, r3, #26 80026d6: 3301 adds r3, #1 80026d8: f003 021f and.w r2, r3, #31 80026dc: 4613 mov r3, r2 80026de: 005b lsls r3, r3, #1 80026e0: 4413 add r3, r2 80026e2: 3b1e subs r3, #30 80026e4: 051b lsls r3, r3, #20 80026e6: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 80026ea: e01b b.n 8002724 80026ec: 683b ldr r3, [r7, #0] 80026ee: 681b ldr r3, [r3, #0] 80026f0: 617b str r3, [r7, #20] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80026f2: 697b ldr r3, [r7, #20] 80026f4: fa93 f3a3 rbit r3, r3 80026f8: 613b str r3, [r7, #16] return result; 80026fa: 693b ldr r3, [r7, #16] 80026fc: 61bb str r3, [r7, #24] if (value == 0U) 80026fe: 69bb ldr r3, [r7, #24] 8002700: 2b00 cmp r3, #0 8002702: d101 bne.n 8002708 return 32U; 8002704: 2320 movs r3, #32 8002706: e003 b.n 8002710 return __builtin_clz(value); 8002708: 69bb ldr r3, [r7, #24] 800270a: fab3 f383 clz r3, r3 800270e: b2db uxtb r3, r3 8002710: 3301 adds r3, #1 8002712: f003 021f and.w r2, r3, #31 8002716: 4613 mov r3, r2 8002718: 005b lsls r3, r3, #1 800271a: 4413 add r3, r2 800271c: 3b1e subs r3, #30 800271e: 051b lsls r3, r3, #20 8002720: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 LL_ADC_SetChannelSamplingTime(hadc->Instance, 8002724: 430b orrs r3, r1 (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)pConfig->Channel) + 1UL) & 0x1FUL)), pConfig->SamplingTime); 8002726: 683a ldr r2, [r7, #0] 8002728: 6892 ldr r2, [r2, #8] LL_ADC_SetChannelSamplingTime(hadc->Instance, 800272a: 4619 mov r1, r3 800272c: f7ff f9ec bl 8001b08 /* If internal channel selected, enable dedicated internal buffers and */ /* paths. */ /* Note: these internal measurement paths can be disabled using */ /* HAL_ADC_DeInit(). */ if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel)) 8002730: 683b ldr r3, [r7, #0] 8002732: 681a ldr r2, [r3, #0] 8002734: 4b09 ldr r3, [pc, #36] @ (800275c ) 8002736: 4013 ands r3, r2 8002738: 2b00 cmp r3, #0 800273a: f000 80be beq.w 80028ba { tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); 800273e: 687b ldr r3, [r7, #4] 8002740: 681b ldr r3, [r3, #0] 8002742: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 8002746: d004 beq.n 8002752 8002748: 687b ldr r3, [r7, #4] 800274a: 681b ldr r3, [r3, #0] 800274c: 4a04 ldr r2, [pc, #16] @ (8002760 ) 800274e: 4293 cmp r3, r2 8002750: d10a bne.n 8002768 8002752: 4b04 ldr r3, [pc, #16] @ (8002764 ) 8002754: e009 b.n 800276a 8002756: bf00 nop 8002758: 407f0000 .word 0x407f0000 800275c: 80080000 .word 0x80080000 8002760: 50000100 .word 0x50000100 8002764: 50000300 .word 0x50000300 8002768: 4b59 ldr r3, [pc, #356] @ (80028d0 ) 800276a: 4618 mov r0, r3 800276c: f7ff f8f4 bl 8001958 8002770: f8c7 00c4 str.w r0, [r7, #196] @ 0xc4 /* If the requested internal measurement path has already been enabled, */ /* bypass the configuration processing. */ if (((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC1) || (pConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC5)) 8002774: 683b ldr r3, [r7, #0] 8002776: 681b ldr r3, [r3, #0] 8002778: 4a56 ldr r2, [pc, #344] @ (80028d4 ) 800277a: 4293 cmp r3, r2 800277c: d004 beq.n 8002788 800277e: 683b ldr r3, [r7, #0] 8002780: 681b ldr r3, [r3, #0] 8002782: 4a55 ldr r2, [pc, #340] @ (80028d8 ) 8002784: 4293 cmp r3, r2 8002786: d13a bne.n 80027fe && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) 8002788: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4 800278c: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8002790: 2b00 cmp r3, #0 8002792: d134 bne.n 80027fe { if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) 8002794: 687b ldr r3, [r7, #4] 8002796: 681b ldr r3, [r3, #0] 8002798: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800279c: d005 beq.n 80027aa 800279e: 687b ldr r3, [r7, #4] 80027a0: 681b ldr r3, [r3, #0] 80027a2: 4a4e ldr r2, [pc, #312] @ (80028dc ) 80027a4: 4293 cmp r3, r2 80027a6: f040 8085 bne.w 80028b4 { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), 80027aa: 687b ldr r3, [r7, #4] 80027ac: 681b ldr r3, [r3, #0] 80027ae: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 80027b2: d004 beq.n 80027be 80027b4: 687b ldr r3, [r7, #4] 80027b6: 681b ldr r3, [r3, #0] 80027b8: 4a49 ldr r2, [pc, #292] @ (80028e0 ) 80027ba: 4293 cmp r3, r2 80027bc: d101 bne.n 80027c2 80027be: 4a49 ldr r2, [pc, #292] @ (80028e4 ) 80027c0: e000 b.n 80027c4 80027c2: 4a43 ldr r2, [pc, #268] @ (80028d0 ) 80027c4: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4 80027c8: f443 0300 orr.w r3, r3, #8388608 @ 0x800000 80027cc: 4619 mov r1, r3 80027ce: 4610 mov r0, r2 80027d0: f7ff f8af bl 8001932 /* Delay for temperature sensor stabilization time */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 80027d4: 4b44 ldr r3, [pc, #272] @ (80028e8 ) 80027d6: 681b ldr r3, [r3, #0] 80027d8: 099b lsrs r3, r3, #6 80027da: 4a44 ldr r2, [pc, #272] @ (80028ec ) 80027dc: fba2 2303 umull r2, r3, r2, r3 80027e0: 099b lsrs r3, r3, #6 80027e2: 1c5a adds r2, r3, #1 80027e4: 4613 mov r3, r2 80027e6: 005b lsls r3, r3, #1 80027e8: 4413 add r3, r2 80027ea: 009b lsls r3, r3, #2 80027ec: 60fb str r3, [r7, #12] while (wait_loop_index != 0UL) 80027ee: e002 b.n 80027f6 { wait_loop_index--; 80027f0: 68fb ldr r3, [r7, #12] 80027f2: 3b01 subs r3, #1 80027f4: 60fb str r3, [r7, #12] while (wait_loop_index != 0UL) 80027f6: 68fb ldr r3, [r7, #12] 80027f8: 2b00 cmp r3, #0 80027fa: d1f9 bne.n 80027f0 if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) 80027fc: e05a b.n 80028b4 } } } else if ((pConfig->Channel == ADC_CHANNEL_VBAT) 80027fe: 683b ldr r3, [r7, #0] 8002800: 681b ldr r3, [r3, #0] 8002802: 4a3b ldr r2, [pc, #236] @ (80028f0 ) 8002804: 4293 cmp r3, r2 8002806: d125 bne.n 8002854 && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) 8002808: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4 800280c: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8002810: 2b00 cmp r3, #0 8002812: d11f bne.n 8002854 { if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) 8002814: 687b ldr r3, [r7, #4] 8002816: 681b ldr r3, [r3, #0] 8002818: 4a31 ldr r2, [pc, #196] @ (80028e0 ) 800281a: 4293 cmp r3, r2 800281c: d104 bne.n 8002828 800281e: 687b ldr r3, [r7, #4] 8002820: 681b ldr r3, [r3, #0] 8002822: 4a34 ldr r2, [pc, #208] @ (80028f4 ) 8002824: 4293 cmp r3, r2 8002826: d047 beq.n 80028b8 { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), 8002828: 687b ldr r3, [r7, #4] 800282a: 681b ldr r3, [r3, #0] 800282c: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 8002830: d004 beq.n 800283c 8002832: 687b ldr r3, [r7, #4] 8002834: 681b ldr r3, [r3, #0] 8002836: 4a2a ldr r2, [pc, #168] @ (80028e0 ) 8002838: 4293 cmp r3, r2 800283a: d101 bne.n 8002840 800283c: 4a29 ldr r2, [pc, #164] @ (80028e4 ) 800283e: e000 b.n 8002842 8002840: 4a23 ldr r2, [pc, #140] @ (80028d0 ) 8002842: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4 8002846: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 800284a: 4619 mov r1, r3 800284c: 4610 mov r0, r2 800284e: f7ff f870 bl 8001932 if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) 8002852: e031 b.n 80028b8 LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel); } } else if ((pConfig->Channel == ADC_CHANNEL_VREFINT) 8002854: 683b ldr r3, [r7, #0] 8002856: 681b ldr r3, [r3, #0] 8002858: 4a27 ldr r2, [pc, #156] @ (80028f8 ) 800285a: 4293 cmp r3, r2 800285c: d12d bne.n 80028ba && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) 800285e: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4 8002862: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8002866: 2b00 cmp r3, #0 8002868: d127 bne.n 80028ba { if (ADC_VREFINT_INSTANCE(hadc)) 800286a: 687b ldr r3, [r7, #4] 800286c: 681b ldr r3, [r3, #0] 800286e: 4a1c ldr r2, [pc, #112] @ (80028e0 ) 8002870: 4293 cmp r3, r2 8002872: d022 beq.n 80028ba { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), 8002874: 687b ldr r3, [r7, #4] 8002876: 681b ldr r3, [r3, #0] 8002878: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800287c: d004 beq.n 8002888 800287e: 687b ldr r3, [r7, #4] 8002880: 681b ldr r3, [r3, #0] 8002882: 4a17 ldr r2, [pc, #92] @ (80028e0 ) 8002884: 4293 cmp r3, r2 8002886: d101 bne.n 800288c 8002888: 4a16 ldr r2, [pc, #88] @ (80028e4 ) 800288a: e000 b.n 800288e 800288c: 4a10 ldr r2, [pc, #64] @ (80028d0 ) 800288e: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4 8002892: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 8002896: 4619 mov r1, r3 8002898: 4610 mov r0, r2 800289a: f7ff f84a bl 8001932 800289e: e00c b.n 80028ba /* channel could be done on neither of the channel configuration structure */ /* parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 80028a0: 687b ldr r3, [r7, #4] 80028a2: 6ddb ldr r3, [r3, #92] @ 0x5c 80028a4: f043 0220 orr.w r2, r3, #32 80028a8: 687b ldr r3, [r7, #4] 80028aa: 65da str r2, [r3, #92] @ 0x5c tmp_hal_status = HAL_ERROR; 80028ac: 2301 movs r3, #1 80028ae: f887 30d7 strb.w r3, [r7, #215] @ 0xd7 80028b2: e002 b.n 80028ba if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) 80028b4: bf00 nop 80028b6: e000 b.n 80028ba if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) 80028b8: bf00 nop } /* Process unlocked */ __HAL_UNLOCK(hadc); 80028ba: 687b ldr r3, [r7, #4] 80028bc: 2200 movs r2, #0 80028be: f883 2058 strb.w r2, [r3, #88] @ 0x58 /* Return function status */ return tmp_hal_status; 80028c2: f897 30d7 ldrb.w r3, [r7, #215] @ 0xd7 } 80028c6: 4618 mov r0, r3 80028c8: 37d8 adds r7, #216 @ 0xd8 80028ca: 46bd mov sp, r7 80028cc: bd80 pop {r7, pc} 80028ce: bf00 nop 80028d0: 50000700 .word 0x50000700 80028d4: c3210000 .word 0xc3210000 80028d8: 90c00010 .word 0x90c00010 80028dc: 50000600 .word 0x50000600 80028e0: 50000100 .word 0x50000100 80028e4: 50000300 .word 0x50000300 80028e8: 20000000 .word 0x20000000 80028ec: 053e2d63 .word 0x053e2d63 80028f0: c7520000 .word 0xc7520000 80028f4: 50000500 .word 0x50000500 80028f8: cb840000 .word 0xcb840000 080028fc : * stopped. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc) { 80028fc: b580 push {r7, lr} 80028fe: b084 sub sp, #16 8002900: af00 add r7, sp, #0 8002902: 6078 str r0, [r7, #4] uint32_t tickstart; const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance); 8002904: 687b ldr r3, [r7, #4] 8002906: 681b ldr r3, [r3, #0] 8002908: 4618 mov r0, r3 800290a: f7ff f9c2 bl 8001c92 800290e: 60f8 str r0, [r7, #12] /* Verification if ADC is not already disabled: */ /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ /* disabled. */ if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) 8002910: 687b ldr r3, [r7, #4] 8002912: 681b ldr r3, [r3, #0] 8002914: 4618 mov r0, r3 8002916: f7ff f9a9 bl 8001c6c 800291a: 4603 mov r3, r0 800291c: 2b00 cmp r3, #0 800291e: d047 beq.n 80029b0 && (tmp_adc_is_disable_on_going == 0UL) 8002920: 68fb ldr r3, [r7, #12] 8002922: 2b00 cmp r3, #0 8002924: d144 bne.n 80029b0 ) { /* Check if conditions to disable the ADC are fulfilled */ if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN) 8002926: 687b ldr r3, [r7, #4] 8002928: 681b ldr r3, [r3, #0] 800292a: 689b ldr r3, [r3, #8] 800292c: f003 030d and.w r3, r3, #13 8002930: 2b01 cmp r3, #1 8002932: d10c bne.n 800294e { /* Disable the ADC peripheral */ LL_ADC_Disable(hadc->Instance); 8002934: 687b ldr r3, [r7, #4] 8002936: 681b ldr r3, [r3, #0] 8002938: 4618 mov r0, r3 800293a: f7ff f983 bl 8001c44 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); 800293e: 687b ldr r3, [r7, #4] 8002940: 681b ldr r3, [r3, #0] 8002942: 2203 movs r2, #3 8002944: 601a str r2, [r3, #0] return HAL_ERROR; } /* Wait for ADC effectively disabled */ /* Get tick count */ tickstart = HAL_GetTick(); 8002946: f7fe ffb1 bl 80018ac 800294a: 60b8 str r0, [r7, #8] while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 800294c: e029 b.n 80029a2 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800294e: 687b ldr r3, [r7, #4] 8002950: 6ddb ldr r3, [r3, #92] @ 0x5c 8002952: f043 0210 orr.w r2, r3, #16 8002956: 687b ldr r3, [r7, #4] 8002958: 65da str r2, [r3, #92] @ 0x5c SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800295a: 687b ldr r3, [r7, #4] 800295c: 6e1b ldr r3, [r3, #96] @ 0x60 800295e: f043 0201 orr.w r2, r3, #1 8002962: 687b ldr r3, [r7, #4] 8002964: 661a str r2, [r3, #96] @ 0x60 return HAL_ERROR; 8002966: 2301 movs r3, #1 8002968: e023 b.n 80029b2 { if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 800296a: f7fe ff9f bl 80018ac 800296e: 4602 mov r2, r0 8002970: 68bb ldr r3, [r7, #8] 8002972: 1ad3 subs r3, r2, r3 8002974: 2b02 cmp r3, #2 8002976: d914 bls.n 80029a2 { /* New check to avoid false timeout detection in case of preemption */ if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 8002978: 687b ldr r3, [r7, #4] 800297a: 681b ldr r3, [r3, #0] 800297c: 689b ldr r3, [r3, #8] 800297e: f003 0301 and.w r3, r3, #1 8002982: 2b00 cmp r3, #0 8002984: d00d beq.n 80029a2 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8002986: 687b ldr r3, [r7, #4] 8002988: 6ddb ldr r3, [r3, #92] @ 0x5c 800298a: f043 0210 orr.w r2, r3, #16 800298e: 687b ldr r3, [r7, #4] 8002990: 65da str r2, [r3, #92] @ 0x5c /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8002992: 687b ldr r3, [r7, #4] 8002994: 6e1b ldr r3, [r3, #96] @ 0x60 8002996: f043 0201 orr.w r2, r3, #1 800299a: 687b ldr r3, [r7, #4] 800299c: 661a str r2, [r3, #96] @ 0x60 return HAL_ERROR; 800299e: 2301 movs r3, #1 80029a0: e007 b.n 80029b2 while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 80029a2: 687b ldr r3, [r7, #4] 80029a4: 681b ldr r3, [r3, #0] 80029a6: 689b ldr r3, [r3, #8] 80029a8: f003 0301 and.w r3, r3, #1 80029ac: 2b00 cmp r3, #0 80029ae: d1dc bne.n 800296a } } } /* Return HAL status */ return HAL_OK; 80029b0: 2300 movs r3, #0 } 80029b2: 4618 mov r0, r3 80029b4: 3710 adds r7, #16 80029b6: 46bd mov sp, r7 80029b8: bd80 pop {r7, pc} 080029ba : { 80029ba: b480 push {r7} 80029bc: b083 sub sp, #12 80029be: af00 add r7, sp, #0 80029c0: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 80029c2: 687b ldr r3, [r7, #4] 80029c4: 689b ldr r3, [r3, #8] 80029c6: f003 0301 and.w r3, r3, #1 80029ca: 2b01 cmp r3, #1 80029cc: d101 bne.n 80029d2 80029ce: 2301 movs r3, #1 80029d0: e000 b.n 80029d4 80029d2: 2300 movs r3, #0 } 80029d4: 4618 mov r0, r3 80029d6: 370c adds r7, #12 80029d8: 46bd mov sp, r7 80029da: f85d 7b04 ldr.w r7, [sp], #4 80029de: 4770 bx lr 080029e0 : { 80029e0: b480 push {r7} 80029e2: b083 sub sp, #12 80029e4: af00 add r7, sp, #0 80029e6: 6078 str r0, [r7, #4] 80029e8: 6039 str r1, [r7, #0] MODIFY_REG(ADCx->CR, 80029ea: 687b ldr r3, [r7, #4] 80029ec: 689b ldr r3, [r3, #8] 80029ee: f023 4340 bic.w r3, r3, #3221225472 @ 0xc0000000 80029f2: f023 033f bic.w r3, r3, #63 @ 0x3f 80029f6: 683a ldr r2, [r7, #0] 80029f8: f002 4280 and.w r2, r2, #1073741824 @ 0x40000000 80029fc: 4313 orrs r3, r2 80029fe: f043 4200 orr.w r2, r3, #2147483648 @ 0x80000000 8002a02: 687b ldr r3, [r7, #4] 8002a04: 609a str r2, [r3, #8] } 8002a06: bf00 nop 8002a08: 370c adds r7, #12 8002a0a: 46bd mov sp, r7 8002a0c: f85d 7b04 ldr.w r7, [sp], #4 8002a10: 4770 bx lr 08002a12 : { 8002a12: b480 push {r7} 8002a14: b083 sub sp, #12 8002a16: af00 add r7, sp, #0 8002a18: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL); 8002a1a: 687b ldr r3, [r7, #4] 8002a1c: 689b ldr r3, [r3, #8] 8002a1e: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8002a22: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8002a26: d101 bne.n 8002a2c 8002a28: 2301 movs r3, #1 8002a2a: e000 b.n 8002a2e 8002a2c: 2300 movs r3, #0 } 8002a2e: 4618 mov r0, r3 8002a30: 370c adds r7, #12 8002a32: 46bd mov sp, r7 8002a34: f85d 7b04 ldr.w r7, [sp], #4 8002a38: 4770 bx lr 08002a3a : { 8002a3a: b480 push {r7} 8002a3c: b083 sub sp, #12 8002a3e: af00 add r7, sp, #0 8002a40: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 8002a42: 687b ldr r3, [r7, #4] 8002a44: 689b ldr r3, [r3, #8] 8002a46: f003 0304 and.w r3, r3, #4 8002a4a: 2b04 cmp r3, #4 8002a4c: d101 bne.n 8002a52 8002a4e: 2301 movs r3, #1 8002a50: e000 b.n 8002a54 8002a52: 2300 movs r3, #0 } 8002a54: 4618 mov r0, r3 8002a56: 370c adds r7, #12 8002a58: 46bd mov sp, r7 8002a5a: f85d 7b04 ldr.w r7, [sp], #4 8002a5e: 4770 bx lr 08002a60 : * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff) { 8002a60: b580 push {r7, lr} 8002a62: b084 sub sp, #16 8002a64: af00 add r7, sp, #0 8002a66: 6078 str r0, [r7, #4] 8002a68: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status; __IO uint32_t wait_loop_index = 0UL; 8002a6a: 2300 movs r3, #0 8002a6c: 60bb str r3, [r7, #8] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); /* Process locked */ __HAL_LOCK(hadc); 8002a6e: 687b ldr r3, [r7, #4] 8002a70: f893 3058 ldrb.w r3, [r3, #88] @ 0x58 8002a74: 2b01 cmp r3, #1 8002a76: d101 bne.n 8002a7c 8002a78: 2302 movs r3, #2 8002a7a: e04d b.n 8002b18 8002a7c: 687b ldr r3, [r7, #4] 8002a7e: 2201 movs r2, #1 8002a80: f883 2058 strb.w r2, [r3, #88] @ 0x58 /* Calibration prerequisite: ADC must be disabled. */ /* Disable the ADC (if not already disabled) */ tmp_hal_status = ADC_Disable(hadc); 8002a84: 6878 ldr r0, [r7, #4] 8002a86: f7ff ff39 bl 80028fc 8002a8a: 4603 mov r3, r0 8002a8c: 73fb strb r3, [r7, #15] /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) 8002a8e: 7bfb ldrb r3, [r7, #15] 8002a90: 2b00 cmp r3, #0 8002a92: d136 bne.n 8002b02 { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8002a94: 687b ldr r3, [r7, #4] 8002a96: 6ddb ldr r3, [r3, #92] @ 0x5c 8002a98: f423 5388 bic.w r3, r3, #4352 @ 0x1100 8002a9c: f023 0302 bic.w r3, r3, #2 8002aa0: f043 0202 orr.w r2, r3, #2 8002aa4: 687b ldr r3, [r7, #4] 8002aa6: 65da str r2, [r3, #92] @ 0x5c HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); /* Start ADC calibration in mode single-ended or differential */ LL_ADC_StartCalibration(hadc->Instance, SingleDiff); 8002aa8: 687b ldr r3, [r7, #4] 8002aaa: 681b ldr r3, [r3, #0] 8002aac: 6839 ldr r1, [r7, #0] 8002aae: 4618 mov r0, r3 8002ab0: f7ff ff96 bl 80029e0 /* Wait for calibration completion */ while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) 8002ab4: e014 b.n 8002ae0 { wait_loop_index++; 8002ab6: 68bb ldr r3, [r7, #8] 8002ab8: 3301 adds r3, #1 8002aba: 60bb str r3, [r7, #8] if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT) 8002abc: 68bb ldr r3, [r7, #8] 8002abe: 4a18 ldr r2, [pc, #96] @ (8002b20 ) 8002ac0: 4293 cmp r3, r2 8002ac2: d90d bls.n 8002ae0 { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 8002ac4: 687b ldr r3, [r7, #4] 8002ac6: 6ddb ldr r3, [r3, #92] @ 0x5c 8002ac8: f023 0312 bic.w r3, r3, #18 8002acc: f043 0210 orr.w r2, r3, #16 8002ad0: 687b ldr r3, [r7, #4] 8002ad2: 65da str r2, [r3, #92] @ 0x5c HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 8002ad4: 687b ldr r3, [r7, #4] 8002ad6: 2200 movs r2, #0 8002ad8: f883 2058 strb.w r2, [r3, #88] @ 0x58 return HAL_ERROR; 8002adc: 2301 movs r3, #1 8002ade: e01b b.n 8002b18 while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) 8002ae0: 687b ldr r3, [r7, #4] 8002ae2: 681b ldr r3, [r3, #0] 8002ae4: 4618 mov r0, r3 8002ae6: f7ff ff94 bl 8002a12 8002aea: 4603 mov r3, r0 8002aec: 2b00 cmp r3, #0 8002aee: d1e2 bne.n 8002ab6 } } /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8002af0: 687b ldr r3, [r7, #4] 8002af2: 6ddb ldr r3, [r3, #92] @ 0x5c 8002af4: f023 0303 bic.w r3, r3, #3 8002af8: f043 0201 orr.w r2, r3, #1 8002afc: 687b ldr r3, [r7, #4] 8002afe: 65da str r2, [r3, #92] @ 0x5c 8002b00: e005 b.n 8002b0e HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } else { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8002b02: 687b ldr r3, [r7, #4] 8002b04: 6ddb ldr r3, [r3, #92] @ 0x5c 8002b06: f043 0210 orr.w r2, r3, #16 8002b0a: 687b ldr r3, [r7, #4] 8002b0c: 65da str r2, [r3, #92] @ 0x5c /* Note: No need to update variable "tmp_hal_status" here: already set */ /* to state "HAL_ERROR" by function disabling the ADC. */ } /* Process unlocked */ __HAL_UNLOCK(hadc); 8002b0e: 687b ldr r3, [r7, #4] 8002b10: 2200 movs r2, #0 8002b12: f883 2058 strb.w r2, [r3, #88] @ 0x58 /* Return function status */ return tmp_hal_status; 8002b16: 7bfb ldrb r3, [r7, #15] } 8002b18: 4618 mov r0, r3 8002b1a: 3710 adds r7, #16 8002b1c: 46bd mov sp, r7 8002b1e: bd80 pop {r7, pc} 8002b20: 0004de01 .word 0x0004de01 08002b24 : * @param hadc Master ADC handle * @param pMultimode Structure of ADC multimode configuration * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, const ADC_MultiModeTypeDef *pMultimode) { 8002b24: b590 push {r4, r7, lr} 8002b26: b0a1 sub sp, #132 @ 0x84 8002b28: af00 add r7, sp, #0 8002b2a: 6078 str r0, [r7, #4] 8002b2c: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8002b2e: 2300 movs r3, #0 8002b30: f887 307f strb.w r3, [r7, #127] @ 0x7f assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(pMultimode->DMAAccessMode)); assert_param(IS_ADC_SAMPLING_DELAY(pMultimode->TwoSamplingDelay)); } /* Process locked */ __HAL_LOCK(hadc); 8002b34: 687b ldr r3, [r7, #4] 8002b36: f893 3058 ldrb.w r3, [r3, #88] @ 0x58 8002b3a: 2b01 cmp r3, #1 8002b3c: d101 bne.n 8002b42 8002b3e: 2302 movs r3, #2 8002b40: e0e7 b.n 8002d12 8002b42: 687b ldr r3, [r7, #4] 8002b44: 2201 movs r2, #1 8002b46: f883 2058 strb.w r2, [r3, #88] @ 0x58 /* Temporary handle minimum initialization */ __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave); 8002b4a: 2300 movs r3, #0 8002b4c: 667b str r3, [r7, #100] @ 0x64 ADC_CLEAR_ERRORCODE(&tmp_hadc_slave); 8002b4e: 2300 movs r3, #0 8002b50: 66bb str r3, [r7, #104] @ 0x68 ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave); 8002b52: 687b ldr r3, [r7, #4] 8002b54: 681b ldr r3, [r3, #0] 8002b56: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 8002b5a: d102 bne.n 8002b62 8002b5c: 4b6f ldr r3, [pc, #444] @ (8002d1c ) 8002b5e: 60bb str r3, [r7, #8] 8002b60: e009 b.n 8002b76 8002b62: 687b ldr r3, [r7, #4] 8002b64: 681b ldr r3, [r3, #0] 8002b66: 4a6e ldr r2, [pc, #440] @ (8002d20 ) 8002b68: 4293 cmp r3, r2 8002b6a: d102 bne.n 8002b72 8002b6c: 4b6d ldr r3, [pc, #436] @ (8002d24 ) 8002b6e: 60bb str r3, [r7, #8] 8002b70: e001 b.n 8002b76 8002b72: 2300 movs r3, #0 8002b74: 60bb str r3, [r7, #8] if (tmp_hadc_slave.Instance == NULL) 8002b76: 68bb ldr r3, [r7, #8] 8002b78: 2b00 cmp r3, #0 8002b7a: d10b bne.n 8002b94 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8002b7c: 687b ldr r3, [r7, #4] 8002b7e: 6ddb ldr r3, [r3, #92] @ 0x5c 8002b80: f043 0220 orr.w r2, r3, #32 8002b84: 687b ldr r3, [r7, #4] 8002b86: 65da str r2, [r3, #92] @ 0x5c /* Process unlocked */ __HAL_UNLOCK(hadc); 8002b88: 687b ldr r3, [r7, #4] 8002b8a: 2200 movs r2, #0 8002b8c: f883 2058 strb.w r2, [r3, #88] @ 0x58 return HAL_ERROR; 8002b90: 2301 movs r3, #1 8002b92: e0be b.n 8002d12 /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Multimode DMA configuration */ /* - Multimode DMA mode */ tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance); 8002b94: 68bb ldr r3, [r7, #8] 8002b96: 4618 mov r0, r3 8002b98: f7ff ff4f bl 8002a3a 8002b9c: 67b8 str r0, [r7, #120] @ 0x78 if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) 8002b9e: 687b ldr r3, [r7, #4] 8002ba0: 681b ldr r3, [r3, #0] 8002ba2: 4618 mov r0, r3 8002ba4: f7ff ff49 bl 8002a3a 8002ba8: 4603 mov r3, r0 8002baa: 2b00 cmp r3, #0 8002bac: f040 80a0 bne.w 8002cf0 && (tmp_hadc_slave_conversion_on_going == 0UL)) 8002bb0: 6fbb ldr r3, [r7, #120] @ 0x78 8002bb2: 2b00 cmp r3, #0 8002bb4: f040 809c bne.w 8002cf0 { /* Pointer to the common control register */ tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); 8002bb8: 687b ldr r3, [r7, #4] 8002bba: 681b ldr r3, [r3, #0] 8002bbc: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 8002bc0: d004 beq.n 8002bcc 8002bc2: 687b ldr r3, [r7, #4] 8002bc4: 681b ldr r3, [r3, #0] 8002bc6: 4a55 ldr r2, [pc, #340] @ (8002d1c ) 8002bc8: 4293 cmp r3, r2 8002bca: d101 bne.n 8002bd0 8002bcc: 4b56 ldr r3, [pc, #344] @ (8002d28 ) 8002bce: e000 b.n 8002bd2 8002bd0: 4b56 ldr r3, [pc, #344] @ (8002d2c ) 8002bd2: 677b str r3, [r7, #116] @ 0x74 /* If multimode is selected, configure all multimode parameters. */ /* Otherwise, reset multimode parameters (can be used in case of */ /* transition from multimode to independent mode). */ if (pMultimode->Mode != ADC_MODE_INDEPENDENT) 8002bd4: 683b ldr r3, [r7, #0] 8002bd6: 681b ldr r3, [r3, #0] 8002bd8: 2b00 cmp r3, #0 8002bda: d04b beq.n 8002c74 { MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, 8002bdc: 6f7b ldr r3, [r7, #116] @ 0x74 8002bde: 689b ldr r3, [r3, #8] 8002be0: f423 4260 bic.w r2, r3, #57344 @ 0xe000 8002be4: 683b ldr r3, [r7, #0] 8002be6: 6859 ldr r1, [r3, #4] 8002be8: 687b ldr r3, [r7, #4] 8002bea: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 8002bee: 035b lsls r3, r3, #13 8002bf0: 430b orrs r3, r1 8002bf2: 431a orrs r2, r3 8002bf4: 6f7b ldr r3, [r7, #116] @ 0x74 8002bf6: 609a str r2, [r3, #8] /* from 1 to 10 clock cycles for 10 bits, */ /* from 1 to 8 clock cycles for 8 bits */ /* from 1 to 6 clock cycles for 6 bits */ /* If a higher delay is selected, it will be clipped to maximum delay */ /* range */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 8002bf8: 687b ldr r3, [r7, #4] 8002bfa: 681b ldr r3, [r3, #0] 8002bfc: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 8002c00: d004 beq.n 8002c0c 8002c02: 687b ldr r3, [r7, #4] 8002c04: 681b ldr r3, [r3, #0] 8002c06: 4a45 ldr r2, [pc, #276] @ (8002d1c ) 8002c08: 4293 cmp r3, r2 8002c0a: d10f bne.n 8002c2c 8002c0c: f04f 40a0 mov.w r0, #1342177280 @ 0x50000000 8002c10: f7ff fed3 bl 80029ba 8002c14: 4604 mov r4, r0 8002c16: 4841 ldr r0, [pc, #260] @ (8002d1c ) 8002c18: f7ff fecf bl 80029ba 8002c1c: 4603 mov r3, r0 8002c1e: 4323 orrs r3, r4 8002c20: 2b00 cmp r3, #0 8002c22: bf0c ite eq 8002c24: 2301 moveq r3, #1 8002c26: 2300 movne r3, #0 8002c28: b2db uxtb r3, r3 8002c2a: e012 b.n 8002c52 8002c2c: 483c ldr r0, [pc, #240] @ (8002d20 ) 8002c2e: f7ff fec4 bl 80029ba 8002c32: 4604 mov r4, r0 8002c34: 483b ldr r0, [pc, #236] @ (8002d24 ) 8002c36: f7ff fec0 bl 80029ba 8002c3a: 4603 mov r3, r0 8002c3c: 431c orrs r4, r3 8002c3e: 483c ldr r0, [pc, #240] @ (8002d30 ) 8002c40: f7ff febb bl 80029ba 8002c44: 4603 mov r3, r0 8002c46: 4323 orrs r3, r4 8002c48: 2b00 cmp r3, #0 8002c4a: bf0c ite eq 8002c4c: 2301 moveq r3, #1 8002c4e: 2300 movne r3, #0 8002c50: b2db uxtb r3, r3 8002c52: 2b00 cmp r3, #0 8002c54: d056 beq.n 8002d04 { MODIFY_REG(tmpADC_Common->CCR, 8002c56: 6f7b ldr r3, [r7, #116] @ 0x74 8002c58: 689b ldr r3, [r3, #8] 8002c5a: f423 6371 bic.w r3, r3, #3856 @ 0xf10 8002c5e: f023 030f bic.w r3, r3, #15 8002c62: 683a ldr r2, [r7, #0] 8002c64: 6811 ldr r1, [r2, #0] 8002c66: 683a ldr r2, [r7, #0] 8002c68: 6892 ldr r2, [r2, #8] 8002c6a: 430a orrs r2, r1 8002c6c: 431a orrs r2, r3 8002c6e: 6f7b ldr r3, [r7, #116] @ 0x74 8002c70: 609a str r2, [r3, #8] if (pMultimode->Mode != ADC_MODE_INDEPENDENT) 8002c72: e047 b.n 8002d04 ); } } else /* ADC_MODE_INDEPENDENT */ { CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG); 8002c74: 6f7b ldr r3, [r7, #116] @ 0x74 8002c76: 689b ldr r3, [r3, #8] 8002c78: f423 4260 bic.w r2, r3, #57344 @ 0xe000 8002c7c: 6f7b ldr r3, [r7, #116] @ 0x74 8002c7e: 609a str r2, [r3, #8] /* Parameters that can be updated only when ADC is disabled: */ /* - Multimode mode selection */ /* - Multimode delay */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 8002c80: 687b ldr r3, [r7, #4] 8002c82: 681b ldr r3, [r3, #0] 8002c84: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 8002c88: d004 beq.n 8002c94 8002c8a: 687b ldr r3, [r7, #4] 8002c8c: 681b ldr r3, [r3, #0] 8002c8e: 4a23 ldr r2, [pc, #140] @ (8002d1c ) 8002c90: 4293 cmp r3, r2 8002c92: d10f bne.n 8002cb4 8002c94: f04f 40a0 mov.w r0, #1342177280 @ 0x50000000 8002c98: f7ff fe8f bl 80029ba 8002c9c: 4604 mov r4, r0 8002c9e: 481f ldr r0, [pc, #124] @ (8002d1c ) 8002ca0: f7ff fe8b bl 80029ba 8002ca4: 4603 mov r3, r0 8002ca6: 4323 orrs r3, r4 8002ca8: 2b00 cmp r3, #0 8002caa: bf0c ite eq 8002cac: 2301 moveq r3, #1 8002cae: 2300 movne r3, #0 8002cb0: b2db uxtb r3, r3 8002cb2: e012 b.n 8002cda 8002cb4: 481a ldr r0, [pc, #104] @ (8002d20 ) 8002cb6: f7ff fe80 bl 80029ba 8002cba: 4604 mov r4, r0 8002cbc: 4819 ldr r0, [pc, #100] @ (8002d24 ) 8002cbe: f7ff fe7c bl 80029ba 8002cc2: 4603 mov r3, r0 8002cc4: 431c orrs r4, r3 8002cc6: 481a ldr r0, [pc, #104] @ (8002d30 ) 8002cc8: f7ff fe77 bl 80029ba 8002ccc: 4603 mov r3, r0 8002cce: 4323 orrs r3, r4 8002cd0: 2b00 cmp r3, #0 8002cd2: bf0c ite eq 8002cd4: 2301 moveq r3, #1 8002cd6: 2300 movne r3, #0 8002cd8: b2db uxtb r3, r3 8002cda: 2b00 cmp r3, #0 8002cdc: d012 beq.n 8002d04 { CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY); 8002cde: 6f7b ldr r3, [r7, #116] @ 0x74 8002ce0: 689b ldr r3, [r3, #8] 8002ce2: f423 6371 bic.w r3, r3, #3856 @ 0xf10 8002ce6: f023 030f bic.w r3, r3, #15 8002cea: 6f7a ldr r2, [r7, #116] @ 0x74 8002cec: 6093 str r3, [r2, #8] if (pMultimode->Mode != ADC_MODE_INDEPENDENT) 8002cee: e009 b.n 8002d04 /* If one of the ADC sharing the same common group is enabled, no update */ /* could be done on neither of the multimode structure parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8002cf0: 687b ldr r3, [r7, #4] 8002cf2: 6ddb ldr r3, [r3, #92] @ 0x5c 8002cf4: f043 0220 orr.w r2, r3, #32 8002cf8: 687b ldr r3, [r7, #4] 8002cfa: 65da str r2, [r3, #92] @ 0x5c tmp_hal_status = HAL_ERROR; 8002cfc: 2301 movs r3, #1 8002cfe: f887 307f strb.w r3, [r7, #127] @ 0x7f 8002d02: e000 b.n 8002d06 if (pMultimode->Mode != ADC_MODE_INDEPENDENT) 8002d04: bf00 nop } /* Process unlocked */ __HAL_UNLOCK(hadc); 8002d06: 687b ldr r3, [r7, #4] 8002d08: 2200 movs r2, #0 8002d0a: f883 2058 strb.w r2, [r3, #88] @ 0x58 /* Return function status */ return tmp_hal_status; 8002d0e: f897 307f ldrb.w r3, [r7, #127] @ 0x7f } 8002d12: 4618 mov r0, r3 8002d14: 3784 adds r7, #132 @ 0x84 8002d16: 46bd mov sp, r7 8002d18: bd90 pop {r4, r7, pc} 8002d1a: bf00 nop 8002d1c: 50000100 .word 0x50000100 8002d20: 50000400 .word 0x50000400 8002d24: 50000500 .word 0x50000500 8002d28: 50000300 .word 0x50000300 8002d2c: 50000700 .word 0x50000700 8002d30: 50000600 .word 0x50000600 08002d34 : * @note (*): Available in some devices * @note Please check each device line mapping for EXTI Line availability * @retval None */ __STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) { 8002d34: b480 push {r7} 8002d36: b083 sub sp, #12 8002d38: af00 add r7, sp, #0 8002d3a: 6078 str r0, [r7, #4] SET_BIT(EXTI->IMR1, ExtiLine); 8002d3c: 4b05 ldr r3, [pc, #20] @ (8002d54 ) 8002d3e: 681a ldr r2, [r3, #0] 8002d40: 4904 ldr r1, [pc, #16] @ (8002d54 ) 8002d42: 687b ldr r3, [r7, #4] 8002d44: 4313 orrs r3, r2 8002d46: 600b str r3, [r1, #0] } 8002d48: bf00 nop 8002d4a: 370c adds r7, #12 8002d4c: 46bd mov sp, r7 8002d4e: f85d 7b04 ldr.w r7, [sp], #4 8002d52: 4770 bx lr 8002d54: 40010400 .word 0x40010400 08002d58 : * @arg @ref LL_EXTI_LINE_ALL_32_63 * @note (*): Available in some devices * @retval None */ __STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine) { 8002d58: b480 push {r7} 8002d5a: b083 sub sp, #12 8002d5c: af00 add r7, sp, #0 8002d5e: 6078 str r0, [r7, #4] SET_BIT(EXTI->IMR2, ExtiLine); 8002d60: 4b05 ldr r3, [pc, #20] @ (8002d78 ) 8002d62: 6a1a ldr r2, [r3, #32] 8002d64: 4904 ldr r1, [pc, #16] @ (8002d78 ) 8002d66: 687b ldr r3, [r7, #4] 8002d68: 4313 orrs r3, r2 8002d6a: 620b str r3, [r1, #32] } 8002d6c: bf00 nop 8002d6e: 370c adds r7, #12 8002d70: 46bd mov sp, r7 8002d72: f85d 7b04 ldr.w r7, [sp], #4 8002d76: 4770 bx lr 8002d78: 40010400 .word 0x40010400 08002d7c : * @note (*): Available in some devices * @note Please check each device line mapping for EXTI Line availability * @retval None */ __STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) { 8002d7c: b480 push {r7} 8002d7e: b083 sub sp, #12 8002d80: af00 add r7, sp, #0 8002d82: 6078 str r0, [r7, #4] CLEAR_BIT(EXTI->IMR1, ExtiLine); 8002d84: 4b06 ldr r3, [pc, #24] @ (8002da0 ) 8002d86: 681a ldr r2, [r3, #0] 8002d88: 687b ldr r3, [r7, #4] 8002d8a: 43db mvns r3, r3 8002d8c: 4904 ldr r1, [pc, #16] @ (8002da0 ) 8002d8e: 4013 ands r3, r2 8002d90: 600b str r3, [r1, #0] } 8002d92: bf00 nop 8002d94: 370c adds r7, #12 8002d96: 46bd mov sp, r7 8002d98: f85d 7b04 ldr.w r7, [sp], #4 8002d9c: 4770 bx lr 8002d9e: bf00 nop 8002da0: 40010400 .word 0x40010400 08002da4 : * @arg @ref LL_EXTI_LINE_ALL_32_63 * @note (*): Available in some devices * @retval None */ __STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine) { 8002da4: b480 push {r7} 8002da6: b083 sub sp, #12 8002da8: af00 add r7, sp, #0 8002daa: 6078 str r0, [r7, #4] CLEAR_BIT(EXTI->IMR2, ExtiLine); 8002dac: 4b06 ldr r3, [pc, #24] @ (8002dc8 ) 8002dae: 6a1a ldr r2, [r3, #32] 8002db0: 687b ldr r3, [r7, #4] 8002db2: 43db mvns r3, r3 8002db4: 4904 ldr r1, [pc, #16] @ (8002dc8 ) 8002db6: 4013 ands r3, r2 8002db8: 620b str r3, [r1, #32] } 8002dba: bf00 nop 8002dbc: 370c adds r7, #12 8002dbe: 46bd mov sp, r7 8002dc0: f85d 7b04 ldr.w r7, [sp], #4 8002dc4: 4770 bx lr 8002dc6: bf00 nop 8002dc8: 40010400 .word 0x40010400 08002dcc : * @note (*): Available in some devices * @note Please check each device line mapping for EXTI Line availability * @retval None */ __STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) { 8002dcc: b480 push {r7} 8002dce: b083 sub sp, #12 8002dd0: af00 add r7, sp, #0 8002dd2: 6078 str r0, [r7, #4] SET_BIT(EXTI->EMR1, ExtiLine); 8002dd4: 4b05 ldr r3, [pc, #20] @ (8002dec ) 8002dd6: 685a ldr r2, [r3, #4] 8002dd8: 4904 ldr r1, [pc, #16] @ (8002dec ) 8002dda: 687b ldr r3, [r7, #4] 8002ddc: 4313 orrs r3, r2 8002dde: 604b str r3, [r1, #4] } 8002de0: bf00 nop 8002de2: 370c adds r7, #12 8002de4: 46bd mov sp, r7 8002de6: f85d 7b04 ldr.w r7, [sp], #4 8002dea: 4770 bx lr 8002dec: 40010400 .word 0x40010400 08002df0 : * @arg @ref LL_EXTI_LINE_ALL_32_63 * @note (*): Available in some devices * @retval None */ __STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine) { 8002df0: b480 push {r7} 8002df2: b083 sub sp, #12 8002df4: af00 add r7, sp, #0 8002df6: 6078 str r0, [r7, #4] SET_BIT(EXTI->EMR2, ExtiLine); 8002df8: 4b05 ldr r3, [pc, #20] @ (8002e10 ) 8002dfa: 6a5a ldr r2, [r3, #36] @ 0x24 8002dfc: 4904 ldr r1, [pc, #16] @ (8002e10 ) 8002dfe: 687b ldr r3, [r7, #4] 8002e00: 4313 orrs r3, r2 8002e02: 624b str r3, [r1, #36] @ 0x24 } 8002e04: bf00 nop 8002e06: 370c adds r7, #12 8002e08: 46bd mov sp, r7 8002e0a: f85d 7b04 ldr.w r7, [sp], #4 8002e0e: 4770 bx lr 8002e10: 40010400 .word 0x40010400 08002e14 : * @note (*): Available in some devices * @note Please check each device line mapping for EXTI Line availability * @retval None */ __STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) { 8002e14: b480 push {r7} 8002e16: b083 sub sp, #12 8002e18: af00 add r7, sp, #0 8002e1a: 6078 str r0, [r7, #4] CLEAR_BIT(EXTI->EMR1, ExtiLine); 8002e1c: 4b06 ldr r3, [pc, #24] @ (8002e38 ) 8002e1e: 685a ldr r2, [r3, #4] 8002e20: 687b ldr r3, [r7, #4] 8002e22: 43db mvns r3, r3 8002e24: 4904 ldr r1, [pc, #16] @ (8002e38 ) 8002e26: 4013 ands r3, r2 8002e28: 604b str r3, [r1, #4] } 8002e2a: bf00 nop 8002e2c: 370c adds r7, #12 8002e2e: 46bd mov sp, r7 8002e30: f85d 7b04 ldr.w r7, [sp], #4 8002e34: 4770 bx lr 8002e36: bf00 nop 8002e38: 40010400 .word 0x40010400 08002e3c : * @arg @ref LL_EXTI_LINE_ALL_32_63 * @note (*): Available in some devices * @retval None */ __STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine) { 8002e3c: b480 push {r7} 8002e3e: b083 sub sp, #12 8002e40: af00 add r7, sp, #0 8002e42: 6078 str r0, [r7, #4] CLEAR_BIT(EXTI->EMR2, ExtiLine); 8002e44: 4b06 ldr r3, [pc, #24] @ (8002e60 ) 8002e46: 6a5a ldr r2, [r3, #36] @ 0x24 8002e48: 687b ldr r3, [r7, #4] 8002e4a: 43db mvns r3, r3 8002e4c: 4904 ldr r1, [pc, #16] @ (8002e60 ) 8002e4e: 4013 ands r3, r2 8002e50: 624b str r3, [r1, #36] @ 0x24 } 8002e52: bf00 nop 8002e54: 370c adds r7, #12 8002e56: 46bd mov sp, r7 8002e58: f85d 7b04 ldr.w r7, [sp], #4 8002e5c: 4770 bx lr 8002e5e: bf00 nop 8002e60: 40010400 .word 0x40010400 08002e64 : * @note (*): Available in some devices * @note Please check each device line mapping for EXTI Line availability * @retval None */ __STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) { 8002e64: b480 push {r7} 8002e66: b083 sub sp, #12 8002e68: af00 add r7, sp, #0 8002e6a: 6078 str r0, [r7, #4] SET_BIT(EXTI->RTSR1, ExtiLine); 8002e6c: 4b05 ldr r3, [pc, #20] @ (8002e84 ) 8002e6e: 689a ldr r2, [r3, #8] 8002e70: 4904 ldr r1, [pc, #16] @ (8002e84 ) 8002e72: 687b ldr r3, [r7, #4] 8002e74: 4313 orrs r3, r2 8002e76: 608b str r3, [r1, #8] } 8002e78: bf00 nop 8002e7a: 370c adds r7, #12 8002e7c: 46bd mov sp, r7 8002e7e: f85d 7b04 ldr.w r7, [sp], #4 8002e82: 4770 bx lr 8002e84: 40010400 .word 0x40010400 08002e88 : * @arg @ref LL_EXTI_LINE_41 * @note (*): Available in some devices * @retval None */ __STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine) { 8002e88: b480 push {r7} 8002e8a: b083 sub sp, #12 8002e8c: af00 add r7, sp, #0 8002e8e: 6078 str r0, [r7, #4] SET_BIT(EXTI->RTSR2, ExtiLine); 8002e90: 4b05 ldr r3, [pc, #20] @ (8002ea8 ) 8002e92: 6a9a ldr r2, [r3, #40] @ 0x28 8002e94: 4904 ldr r1, [pc, #16] @ (8002ea8 ) 8002e96: 687b ldr r3, [r7, #4] 8002e98: 4313 orrs r3, r2 8002e9a: 628b str r3, [r1, #40] @ 0x28 } 8002e9c: bf00 nop 8002e9e: 370c adds r7, #12 8002ea0: 46bd mov sp, r7 8002ea2: f85d 7b04 ldr.w r7, [sp], #4 8002ea6: 4770 bx lr 8002ea8: 40010400 .word 0x40010400 08002eac : * @note (*): Available in some devices * @note Please check each device line mapping for EXTI Line availability * @retval None */ __STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) { 8002eac: b480 push {r7} 8002eae: b083 sub sp, #12 8002eb0: af00 add r7, sp, #0 8002eb2: 6078 str r0, [r7, #4] CLEAR_BIT(EXTI->RTSR1, ExtiLine); 8002eb4: 4b06 ldr r3, [pc, #24] @ (8002ed0 ) 8002eb6: 689a ldr r2, [r3, #8] 8002eb8: 687b ldr r3, [r7, #4] 8002eba: 43db mvns r3, r3 8002ebc: 4904 ldr r1, [pc, #16] @ (8002ed0 ) 8002ebe: 4013 ands r3, r2 8002ec0: 608b str r3, [r1, #8] } 8002ec2: bf00 nop 8002ec4: 370c adds r7, #12 8002ec6: 46bd mov sp, r7 8002ec8: f85d 7b04 ldr.w r7, [sp], #4 8002ecc: 4770 bx lr 8002ece: bf00 nop 8002ed0: 40010400 .word 0x40010400 08002ed4 : * @arg @ref LL_EXTI_LINE_41 * @note (*): Available in some devices * @retval None */ __STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine) { 8002ed4: b480 push {r7} 8002ed6: b083 sub sp, #12 8002ed8: af00 add r7, sp, #0 8002eda: 6078 str r0, [r7, #4] CLEAR_BIT(EXTI->RTSR2, ExtiLine); 8002edc: 4b06 ldr r3, [pc, #24] @ (8002ef8 ) 8002ede: 6a9a ldr r2, [r3, #40] @ 0x28 8002ee0: 687b ldr r3, [r7, #4] 8002ee2: 43db mvns r3, r3 8002ee4: 4904 ldr r1, [pc, #16] @ (8002ef8 ) 8002ee6: 4013 ands r3, r2 8002ee8: 628b str r3, [r1, #40] @ 0x28 } 8002eea: bf00 nop 8002eec: 370c adds r7, #12 8002eee: 46bd mov sp, r7 8002ef0: f85d 7b04 ldr.w r7, [sp], #4 8002ef4: 4770 bx lr 8002ef6: bf00 nop 8002ef8: 40010400 .word 0x40010400 08002efc : * @note (*): Available in some devices * @note Please check each device line mapping for EXTI Line availability * @retval None */ __STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) { 8002efc: b480 push {r7} 8002efe: b083 sub sp, #12 8002f00: af00 add r7, sp, #0 8002f02: 6078 str r0, [r7, #4] SET_BIT(EXTI->FTSR1, ExtiLine); 8002f04: 4b05 ldr r3, [pc, #20] @ (8002f1c ) 8002f06: 68da ldr r2, [r3, #12] 8002f08: 4904 ldr r1, [pc, #16] @ (8002f1c ) 8002f0a: 687b ldr r3, [r7, #4] 8002f0c: 4313 orrs r3, r2 8002f0e: 60cb str r3, [r1, #12] } 8002f10: bf00 nop 8002f12: 370c adds r7, #12 8002f14: 46bd mov sp, r7 8002f16: f85d 7b04 ldr.w r7, [sp], #4 8002f1a: 4770 bx lr 8002f1c: 40010400 .word 0x40010400 08002f20 : * @arg @ref LL_EXTI_LINE_41 * @note (*): Available in some devices * @retval None */ __STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine) { 8002f20: b480 push {r7} 8002f22: b083 sub sp, #12 8002f24: af00 add r7, sp, #0 8002f26: 6078 str r0, [r7, #4] SET_BIT(EXTI->FTSR2, ExtiLine); 8002f28: 4b05 ldr r3, [pc, #20] @ (8002f40 ) 8002f2a: 6ada ldr r2, [r3, #44] @ 0x2c 8002f2c: 4904 ldr r1, [pc, #16] @ (8002f40 ) 8002f2e: 687b ldr r3, [r7, #4] 8002f30: 4313 orrs r3, r2 8002f32: 62cb str r3, [r1, #44] @ 0x2c } 8002f34: bf00 nop 8002f36: 370c adds r7, #12 8002f38: 46bd mov sp, r7 8002f3a: f85d 7b04 ldr.w r7, [sp], #4 8002f3e: 4770 bx lr 8002f40: 40010400 .word 0x40010400 08002f44 : * @note (*): Available in some devices * @note Please check each device line mapping for EXTI Line availability * @retval None */ __STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) { 8002f44: b480 push {r7} 8002f46: b083 sub sp, #12 8002f48: af00 add r7, sp, #0 8002f4a: 6078 str r0, [r7, #4] CLEAR_BIT(EXTI->FTSR1, ExtiLine); 8002f4c: 4b06 ldr r3, [pc, #24] @ (8002f68 ) 8002f4e: 68da ldr r2, [r3, #12] 8002f50: 687b ldr r3, [r7, #4] 8002f52: 43db mvns r3, r3 8002f54: 4904 ldr r1, [pc, #16] @ (8002f68 ) 8002f56: 4013 ands r3, r2 8002f58: 60cb str r3, [r1, #12] } 8002f5a: bf00 nop 8002f5c: 370c adds r7, #12 8002f5e: 46bd mov sp, r7 8002f60: f85d 7b04 ldr.w r7, [sp], #4 8002f64: 4770 bx lr 8002f66: bf00 nop 8002f68: 40010400 .word 0x40010400 08002f6c : * @arg @ref LL_EXTI_LINE_41 * @note (*): Available in some devices * @retval None */ __STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine) { 8002f6c: b480 push {r7} 8002f6e: b083 sub sp, #12 8002f70: af00 add r7, sp, #0 8002f72: 6078 str r0, [r7, #4] CLEAR_BIT(EXTI->FTSR2, ExtiLine); 8002f74: 4b06 ldr r3, [pc, #24] @ (8002f90 ) 8002f76: 6ada ldr r2, [r3, #44] @ 0x2c 8002f78: 687b ldr r3, [r7, #4] 8002f7a: 43db mvns r3, r3 8002f7c: 4904 ldr r1, [pc, #16] @ (8002f90 ) 8002f7e: 4013 ands r3, r2 8002f80: 62cb str r3, [r1, #44] @ 0x2c } 8002f82: bf00 nop 8002f84: 370c adds r7, #12 8002f86: 46bd mov sp, r7 8002f88: f85d 7b04 ldr.w r7, [sp], #4 8002f8c: 4770 bx lr 8002f8e: bf00 nop 8002f90: 40010400 .word 0x40010400 08002f94 : * @note (*): Available in some devices * @note Please check each device line mapping for EXTI Line availability * @retval None */ __STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine) { 8002f94: b480 push {r7} 8002f96: b083 sub sp, #12 8002f98: af00 add r7, sp, #0 8002f9a: 6078 str r0, [r7, #4] WRITE_REG(EXTI->PR1, ExtiLine); 8002f9c: 4a04 ldr r2, [pc, #16] @ (8002fb0 ) 8002f9e: 687b ldr r3, [r7, #4] 8002fa0: 6153 str r3, [r2, #20] } 8002fa2: bf00 nop 8002fa4: 370c adds r7, #12 8002fa6: 46bd mov sp, r7 8002fa8: f85d 7b04 ldr.w r7, [sp], #4 8002fac: 4770 bx lr 8002fae: bf00 nop 8002fb0: 40010400 .word 0x40010400 08002fb4 : * @arg @ref LL_EXTI_LINE_41 * @note (*): Available in some devices * @retval None */ __STATIC_INLINE void LL_EXTI_ClearFlag_32_63(uint32_t ExtiLine) { 8002fb4: b480 push {r7} 8002fb6: b083 sub sp, #12 8002fb8: af00 add r7, sp, #0 8002fba: 6078 str r0, [r7, #4] WRITE_REG(EXTI->PR2, ExtiLine); 8002fbc: 4a04 ldr r2, [pc, #16] @ (8002fd0 ) 8002fbe: 687b ldr r3, [r7, #4] 8002fc0: 6353 str r3, [r2, #52] @ 0x34 } 8002fc2: bf00 nop 8002fc4: 370c adds r7, #12 8002fc6: 46bd mov sp, r7 8002fc8: f85d 7b04 ldr.w r7, [sp], #4 8002fcc: 4770 bx lr 8002fce: bf00 nop 8002fd0: 40010400 .word 0x40010400 08002fd4 : * To unlock the configuration, perform a system reset. * @param hcomp COMP handle * @retval HAL status */ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) { 8002fd4: b580 push {r7, lr} 8002fd6: b088 sub sp, #32 8002fd8: af00 add r7, sp, #0 8002fda: 6078 str r0, [r7, #4] uint32_t tmp_csr; uint32_t exti_line; uint32_t comp_voltage_scaler_initialized; /* Value "0" if comparator voltage scaler is not initialized */ __IO uint32_t wait_loop_index = 0UL; 8002fdc: 2300 movs r3, #0 8002fde: 60fb str r3, [r7, #12] HAL_StatusTypeDef status = HAL_OK; 8002fe0: 2300 movs r3, #0 8002fe2: 77fb strb r3, [r7, #31] /* Check the COMP handle allocation and lock status */ if (hcomp == NULL) 8002fe4: 687b ldr r3, [r7, #4] 8002fe6: 2b00 cmp r3, #0 8002fe8: d102 bne.n 8002ff0 { status = HAL_ERROR; 8002fea: 2301 movs r3, #1 8002fec: 77fb strb r3, [r7, #31] 8002fee: e181 b.n 80032f4 } else if (__HAL_COMP_IS_LOCKED(hcomp)) 8002ff0: 687b ldr r3, [r7, #4] 8002ff2: 681b ldr r3, [r3, #0] 8002ff4: 681b ldr r3, [r3, #0] 8002ff6: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8002ffa: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8002ffe: d102 bne.n 8003006 { status = HAL_ERROR; 8003000: 2301 movs r3, #1 8003002: 77fb strb r3, [r7, #31] 8003004: e176 b.n 80032f4 assert_param(IS_COMP_OUTPUTPOL(hcomp->Init.OutputPol)); assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis)); assert_param(IS_COMP_BLANKINGSRC_INSTANCE(hcomp->Instance, hcomp->Init.BlankingSrce)); assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode)); if (hcomp->State == HAL_COMP_STATE_RESET) 8003006: 687b ldr r3, [r7, #4] 8003008: 7f5b ldrb r3, [r3, #29] 800300a: b2db uxtb r3, r3 800300c: 2b00 cmp r3, #0 800300e: d108 bne.n 8003022 { /* Allocate lock resource and initialize it */ hcomp->Lock = HAL_UNLOCKED; 8003010: 687b ldr r3, [r7, #4] 8003012: 2200 movs r2, #0 8003014: 771a strb r2, [r3, #28] /* Set COMP error code to none */ COMP_CLEAR_ERRORCODE(hcomp); 8003016: 687b ldr r3, [r7, #4] 8003018: 2200 movs r2, #0 800301a: 621a str r2, [r3, #32] #else /* Init the low level hardware */ /* Note: Internal control clock of the comparators must */ /* be enabled in "HAL_COMP_MspInit()" */ /* using "__HAL_RCC_SYSCFG_CLK_ENABLE()". */ HAL_COMP_MspInit(hcomp); 800301c: 6878 ldr r0, [r7, #4] 800301e: f7fe f981 bl 8001324 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ } /* Memorize voltage scaler state before initialization */ comp_voltage_scaler_initialized = READ_BIT(hcomp->Instance->CSR, COMP_CSR_SCALEN); 8003022: 687b ldr r3, [r7, #4] 8003024: 681b ldr r3, [r3, #0] 8003026: 681b ldr r3, [r3, #0] 8003028: f403 0300 and.w r3, r3, #8388608 @ 0x800000 800302c: 61bb str r3, [r7, #24] /* Set COMP parameters */ tmp_csr = (hcomp->Init.InputMinus 800302e: 687b ldr r3, [r7, #4] 8003030: 689a ldr r2, [r3, #8] | hcomp->Init.InputPlus 8003032: 687b ldr r3, [r7, #4] 8003034: 685b ldr r3, [r3, #4] 8003036: 431a orrs r2, r3 | hcomp->Init.BlankingSrce 8003038: 687b ldr r3, [r7, #4] 800303a: 695b ldr r3, [r3, #20] 800303c: 431a orrs r2, r3 | hcomp->Init.Hysteresis 800303e: 687b ldr r3, [r7, #4] 8003040: 68db ldr r3, [r3, #12] 8003042: 431a orrs r2, r3 | hcomp->Init.OutputPol 8003044: 687b ldr r3, [r7, #4] 8003046: 691b ldr r3, [r3, #16] tmp_csr = (hcomp->Init.InputMinus 8003048: 4313 orrs r3, r2 800304a: 617b str r3, [r7, #20] ); /* Set parameters in COMP register */ /* Note: Update all bits except read-only, lock and enable bits */ MODIFY_REG(hcomp->Instance->CSR, 800304c: 687b ldr r3, [r7, #4] 800304e: 681b ldr r3, [r3, #0] 8003050: 681a ldr r2, [r3, #0] 8003052: 4b90 ldr r3, [pc, #576] @ (8003294 ) 8003054: 4013 ands r3, r2 8003056: 687a ldr r2, [r7, #4] 8003058: 6812 ldr r2, [r2, #0] 800305a: 6979 ldr r1, [r7, #20] 800305c: 430b orrs r3, r1 800305e: 6013 str r3, [r2, #0] tmp_csr ); /* Delay for COMP scaler bridge voltage stabilization */ /* Apply the delay if voltage scaler bridge is required and not already enabled */ if ((READ_BIT(hcomp->Instance->CSR, COMP_CSR_SCALEN) != 0UL) && 8003060: 687b ldr r3, [r7, #4] 8003062: 681b ldr r3, [r3, #0] 8003064: 681b ldr r3, [r3, #0] 8003066: f403 0300 and.w r3, r3, #8388608 @ 0x800000 800306a: 2b00 cmp r3, #0 800306c: d016 beq.n 800309c 800306e: 69bb ldr r3, [r7, #24] 8003070: 2b00 cmp r3, #0 8003072: d113 bne.n 800309c { /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((COMP_DELAY_VOLTAGE_SCALER_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 8003074: 4b88 ldr r3, [pc, #544] @ (8003298 ) 8003076: 681b ldr r3, [r3, #0] 8003078: 099b lsrs r3, r3, #6 800307a: 4a88 ldr r2, [pc, #544] @ (800329c ) 800307c: fba2 2303 umull r2, r3, r2, r3 8003080: 099b lsrs r3, r3, #6 8003082: 1c5a adds r2, r3, #1 8003084: 4613 mov r3, r2 8003086: 009b lsls r3, r3, #2 8003088: 4413 add r3, r2 800308a: 009b lsls r3, r3, #2 800308c: 60fb str r3, [r7, #12] while (wait_loop_index != 0UL) 800308e: e002 b.n 8003096 { wait_loop_index--; 8003090: 68fb ldr r3, [r7, #12] 8003092: 3b01 subs r3, #1 8003094: 60fb str r3, [r7, #12] while (wait_loop_index != 0UL) 8003096: 68fb ldr r3, [r7, #12] 8003098: 2b00 cmp r3, #0 800309a: d1f9 bne.n 8003090 } } /* Get the EXTI line corresponding to the selected COMP instance */ exti_line = COMP_GET_EXTI_LINE(hcomp->Instance); 800309c: 687b ldr r3, [r7, #4] 800309e: 681b ldr r3, [r3, #0] 80030a0: 4a7f ldr r2, [pc, #508] @ (80032a0 ) 80030a2: 4293 cmp r3, r2 80030a4: d028 beq.n 80030f8 80030a6: 687b ldr r3, [r7, #4] 80030a8: 681b ldr r3, [r3, #0] 80030aa: 4a7e ldr r2, [pc, #504] @ (80032a4 ) 80030ac: 4293 cmp r3, r2 80030ae: d020 beq.n 80030f2 80030b0: 687b ldr r3, [r7, #4] 80030b2: 681b ldr r3, [r3, #0] 80030b4: 4a7c ldr r2, [pc, #496] @ (80032a8 ) 80030b6: 4293 cmp r3, r2 80030b8: d018 beq.n 80030ec 80030ba: 687b ldr r3, [r7, #4] 80030bc: 681b ldr r3, [r3, #0] 80030be: 4a7b ldr r2, [pc, #492] @ (80032ac ) 80030c0: 4293 cmp r3, r2 80030c2: d010 beq.n 80030e6 80030c4: 687b ldr r3, [r7, #4] 80030c6: 681b ldr r3, [r3, #0] 80030c8: 4a79 ldr r2, [pc, #484] @ (80032b0 ) 80030ca: 4293 cmp r3, r2 80030cc: d008 beq.n 80030e0 80030ce: 687b ldr r3, [r7, #4] 80030d0: 681b ldr r3, [r3, #0] 80030d2: 4a78 ldr r2, [pc, #480] @ (80032b4 ) 80030d4: 4293 cmp r3, r2 80030d6: d101 bne.n 80030dc 80030d8: 2301 movs r3, #1 80030da: e00f b.n 80030fc 80030dc: 2302 movs r3, #2 80030de: e00d b.n 80030fc 80030e0: f04f 4300 mov.w r3, #2147483648 @ 0x80000000 80030e4: e00a b.n 80030fc 80030e6: f04f 4380 mov.w r3, #1073741824 @ 0x40000000 80030ea: e007 b.n 80030fc 80030ec: f04f 5300 mov.w r3, #536870912 @ 0x20000000 80030f0: e004 b.n 80030fc 80030f2: f44f 0380 mov.w r3, #4194304 @ 0x400000 80030f6: e001 b.n 80030fc 80030f8: f44f 1300 mov.w r3, #2097152 @ 0x200000 80030fc: 613b str r3, [r7, #16] /* Manage EXTI settings */ if ((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != 0UL) 80030fe: 687b ldr r3, [r7, #4] 8003100: 699b ldr r3, [r3, #24] 8003102: f003 0303 and.w r3, r3, #3 8003106: 2b00 cmp r3, #0 8003108: f000 80b6 beq.w 8003278 { /* Configure EXTI rising edge */ if ((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != 0UL) 800310c: 687b ldr r3, [r7, #4] 800310e: 699b ldr r3, [r3, #24] 8003110: f003 0310 and.w r3, r3, #16 8003114: 2b00 cmp r3, #0 8003116: d011 beq.n 800313c { #if defined(COMP7) if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7)) 8003118: 687b ldr r3, [r7, #4] 800311a: 681b ldr r3, [r3, #0] 800311c: 4a65 ldr r2, [pc, #404] @ (80032b4 ) 800311e: 4293 cmp r3, r2 8003120: d004 beq.n 800312c 8003122: 687b ldr r3, [r7, #4] 8003124: 681b ldr r3, [r3, #0] 8003126: 4a64 ldr r2, [pc, #400] @ (80032b8 ) 8003128: 4293 cmp r3, r2 800312a: d103 bne.n 8003134 { LL_EXTI_EnableRisingTrig_32_63(exti_line); 800312c: 6938 ldr r0, [r7, #16] 800312e: f7ff feab bl 8002e88 8003132: e014 b.n 800315e } else { LL_EXTI_EnableRisingTrig_0_31(exti_line); 8003134: 6938 ldr r0, [r7, #16] 8003136: f7ff fe95 bl 8002e64 800313a: e010 b.n 800315e #endif /* COMP7 */ } else { #if defined(COMP7) if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7)) 800313c: 687b ldr r3, [r7, #4] 800313e: 681b ldr r3, [r3, #0] 8003140: 4a5c ldr r2, [pc, #368] @ (80032b4 ) 8003142: 4293 cmp r3, r2 8003144: d004 beq.n 8003150 8003146: 687b ldr r3, [r7, #4] 8003148: 681b ldr r3, [r3, #0] 800314a: 4a5b ldr r2, [pc, #364] @ (80032b8 ) 800314c: 4293 cmp r3, r2 800314e: d103 bne.n 8003158 { LL_EXTI_DisableRisingTrig_32_63(exti_line); 8003150: 6938 ldr r0, [r7, #16] 8003152: f7ff febf bl 8002ed4 8003156: e002 b.n 800315e } else { LL_EXTI_DisableRisingTrig_0_31(exti_line); 8003158: 6938 ldr r0, [r7, #16] 800315a: f7ff fea7 bl 8002eac LL_EXTI_DisableRisingTrig_0_31(exti_line); #endif /* COMP7 */ } /* Configure EXTI falling edge */ if ((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != 0UL) 800315e: 687b ldr r3, [r7, #4] 8003160: 699b ldr r3, [r3, #24] 8003162: f003 0320 and.w r3, r3, #32 8003166: 2b00 cmp r3, #0 8003168: d011 beq.n 800318e { #if defined(COMP7) if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7)) 800316a: 687b ldr r3, [r7, #4] 800316c: 681b ldr r3, [r3, #0] 800316e: 4a51 ldr r2, [pc, #324] @ (80032b4 ) 8003170: 4293 cmp r3, r2 8003172: d004 beq.n 800317e 8003174: 687b ldr r3, [r7, #4] 8003176: 681b ldr r3, [r3, #0] 8003178: 4a4f ldr r2, [pc, #316] @ (80032b8 ) 800317a: 4293 cmp r3, r2 800317c: d103 bne.n 8003186 { LL_EXTI_EnableFallingTrig_32_63(exti_line); 800317e: 6938 ldr r0, [r7, #16] 8003180: f7ff fece bl 8002f20 8003184: e014 b.n 80031b0 } else { LL_EXTI_EnableFallingTrig_0_31(exti_line); 8003186: 6938 ldr r0, [r7, #16] 8003188: f7ff feb8 bl 8002efc 800318c: e010 b.n 80031b0 #endif /* COMP7 */ } else { #if defined(COMP7) if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7)) 800318e: 687b ldr r3, [r7, #4] 8003190: 681b ldr r3, [r3, #0] 8003192: 4a48 ldr r2, [pc, #288] @ (80032b4 ) 8003194: 4293 cmp r3, r2 8003196: d004 beq.n 80031a2 8003198: 687b ldr r3, [r7, #4] 800319a: 681b ldr r3, [r3, #0] 800319c: 4a46 ldr r2, [pc, #280] @ (80032b8 ) 800319e: 4293 cmp r3, r2 80031a0: d103 bne.n 80031aa { LL_EXTI_DisableFallingTrig_32_63(exti_line); 80031a2: 6938 ldr r0, [r7, #16] 80031a4: f7ff fee2 bl 8002f6c 80031a8: e002 b.n 80031b0 } else { LL_EXTI_DisableFallingTrig_0_31(exti_line); 80031aa: 6938 ldr r0, [r7, #16] 80031ac: f7ff feca bl 8002f44 #endif /* COMP7 */ } /* Clear COMP EXTI pending bit (if any) */ #if defined(COMP7) if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7)) 80031b0: 687b ldr r3, [r7, #4] 80031b2: 681b ldr r3, [r3, #0] 80031b4: 4a3f ldr r2, [pc, #252] @ (80032b4 ) 80031b6: 4293 cmp r3, r2 80031b8: d004 beq.n 80031c4 80031ba: 687b ldr r3, [r7, #4] 80031bc: 681b ldr r3, [r3, #0] 80031be: 4a3e ldr r2, [pc, #248] @ (80032b8 ) 80031c0: 4293 cmp r3, r2 80031c2: d103 bne.n 80031cc { LL_EXTI_ClearFlag_32_63(exti_line); 80031c4: 6938 ldr r0, [r7, #16] 80031c6: f7ff fef5 bl 8002fb4 80031ca: e002 b.n 80031d2 } else { LL_EXTI_ClearFlag_0_31(exti_line); 80031cc: 6938 ldr r0, [r7, #16] 80031ce: f7ff fee1 bl 8002f94 #else LL_EXTI_ClearFlag_0_31(exti_line); #endif /* COMP7 */ /* Configure EXTI event mode */ if ((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL) 80031d2: 687b ldr r3, [r7, #4] 80031d4: 699b ldr r3, [r3, #24] 80031d6: f003 0302 and.w r3, r3, #2 80031da: 2b00 cmp r3, #0 80031dc: d011 beq.n 8003202 { #if defined(COMP7) if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7)) 80031de: 687b ldr r3, [r7, #4] 80031e0: 681b ldr r3, [r3, #0] 80031e2: 4a34 ldr r2, [pc, #208] @ (80032b4 ) 80031e4: 4293 cmp r3, r2 80031e6: d004 beq.n 80031f2 80031e8: 687b ldr r3, [r7, #4] 80031ea: 681b ldr r3, [r3, #0] 80031ec: 4a32 ldr r2, [pc, #200] @ (80032b8 ) 80031ee: 4293 cmp r3, r2 80031f0: d103 bne.n 80031fa { LL_EXTI_EnableEvent_32_63(exti_line); 80031f2: 6938 ldr r0, [r7, #16] 80031f4: f7ff fdfc bl 8002df0 80031f8: e014 b.n 8003224 } else { LL_EXTI_EnableEvent_0_31(exti_line); 80031fa: 6938 ldr r0, [r7, #16] 80031fc: f7ff fde6 bl 8002dcc 8003200: e010 b.n 8003224 #endif /* COMP7 */ } else { #if defined(COMP7) if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7)) 8003202: 687b ldr r3, [r7, #4] 8003204: 681b ldr r3, [r3, #0] 8003206: 4a2b ldr r2, [pc, #172] @ (80032b4 ) 8003208: 4293 cmp r3, r2 800320a: d004 beq.n 8003216 800320c: 687b ldr r3, [r7, #4] 800320e: 681b ldr r3, [r3, #0] 8003210: 4a29 ldr r2, [pc, #164] @ (80032b8 ) 8003212: 4293 cmp r3, r2 8003214: d103 bne.n 800321e { LL_EXTI_DisableEvent_32_63(exti_line); 8003216: 6938 ldr r0, [r7, #16] 8003218: f7ff fe10 bl 8002e3c 800321c: e002 b.n 8003224 } else { LL_EXTI_DisableEvent_0_31(exti_line); 800321e: 6938 ldr r0, [r7, #16] 8003220: f7ff fdf8 bl 8002e14 LL_EXTI_DisableEvent_0_31(exti_line); #endif /* COMP7 */ } /* Configure EXTI interrupt mode */ if ((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL) 8003224: 687b ldr r3, [r7, #4] 8003226: 699b ldr r3, [r3, #24] 8003228: f003 0301 and.w r3, r3, #1 800322c: 2b00 cmp r3, #0 800322e: d011 beq.n 8003254 { #if defined(COMP7) if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7)) 8003230: 687b ldr r3, [r7, #4] 8003232: 681b ldr r3, [r3, #0] 8003234: 4a1f ldr r2, [pc, #124] @ (80032b4 ) 8003236: 4293 cmp r3, r2 8003238: d004 beq.n 8003244 800323a: 687b ldr r3, [r7, #4] 800323c: 681b ldr r3, [r3, #0] 800323e: 4a1e ldr r2, [pc, #120] @ (80032b8 ) 8003240: 4293 cmp r3, r2 8003242: d103 bne.n 800324c { LL_EXTI_EnableIT_32_63(exti_line); 8003244: 6938 ldr r0, [r7, #16] 8003246: f7ff fd87 bl 8002d58 800324a: e04b b.n 80032e4 } else { LL_EXTI_EnableIT_0_31(exti_line); 800324c: 6938 ldr r0, [r7, #16] 800324e: f7ff fd71 bl 8002d34 8003252: e047 b.n 80032e4 #endif /* COMP7 */ } else { #if defined(COMP7) if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7)) 8003254: 687b ldr r3, [r7, #4] 8003256: 681b ldr r3, [r3, #0] 8003258: 4a16 ldr r2, [pc, #88] @ (80032b4 ) 800325a: 4293 cmp r3, r2 800325c: d004 beq.n 8003268 800325e: 687b ldr r3, [r7, #4] 8003260: 681b ldr r3, [r3, #0] 8003262: 4a15 ldr r2, [pc, #84] @ (80032b8 ) 8003264: 4293 cmp r3, r2 8003266: d103 bne.n 8003270 { LL_EXTI_DisableIT_32_63(exti_line); 8003268: 6938 ldr r0, [r7, #16] 800326a: f7ff fd9b bl 8002da4 800326e: e039 b.n 80032e4 } else { LL_EXTI_DisableIT_0_31(exti_line); 8003270: 6938 ldr r0, [r7, #16] 8003272: f7ff fd83 bl 8002d7c 8003276: e035 b.n 80032e4 } else { /* Disable EXTI event mode */ #if defined(COMP7) if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7)) 8003278: 687b ldr r3, [r7, #4] 800327a: 681b ldr r3, [r3, #0] 800327c: 4a0d ldr r2, [pc, #52] @ (80032b4 ) 800327e: 4293 cmp r3, r2 8003280: d004 beq.n 800328c 8003282: 687b ldr r3, [r7, #4] 8003284: 681b ldr r3, [r3, #0] 8003286: 4a0c ldr r2, [pc, #48] @ (80032b8 ) 8003288: 4293 cmp r3, r2 800328a: d117 bne.n 80032bc { LL_EXTI_DisableEvent_32_63(exti_line); 800328c: 6938 ldr r0, [r7, #16] 800328e: f7ff fdd5 bl 8002e3c 8003292: e016 b.n 80032c2 8003294: ff007e0f .word 0xff007e0f 8003298: 20000000 .word 0x20000000 800329c: 053e2d63 .word 0x053e2d63 80032a0: 40010200 .word 0x40010200 80032a4: 40010204 .word 0x40010204 80032a8: 40010208 .word 0x40010208 80032ac: 4001020c .word 0x4001020c 80032b0: 40010210 .word 0x40010210 80032b4: 40010214 .word 0x40010214 80032b8: 40010218 .word 0x40010218 } else { LL_EXTI_DisableEvent_0_31(exti_line); 80032bc: 6938 ldr r0, [r7, #16] 80032be: f7ff fda9 bl 8002e14 LL_EXTI_DisableEvent_0_31(exti_line); #endif /* COMP7 */ /* Disable EXTI interrupt mode */ #if defined(COMP7) if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7)) 80032c2: 687b ldr r3, [r7, #4] 80032c4: 681b ldr r3, [r3, #0] 80032c6: 4a0e ldr r2, [pc, #56] @ (8003300 ) 80032c8: 4293 cmp r3, r2 80032ca: d004 beq.n 80032d6 80032cc: 687b ldr r3, [r7, #4] 80032ce: 681b ldr r3, [r3, #0] 80032d0: 4a0c ldr r2, [pc, #48] @ (8003304 ) 80032d2: 4293 cmp r3, r2 80032d4: d103 bne.n 80032de { LL_EXTI_DisableIT_32_63(exti_line); 80032d6: 6938 ldr r0, [r7, #16] 80032d8: f7ff fd64 bl 8002da4 80032dc: e002 b.n 80032e4 } else { LL_EXTI_DisableIT_0_31(exti_line); 80032de: 6938 ldr r0, [r7, #16] 80032e0: f7ff fd4c bl 8002d7c } /* Set HAL COMP handle state */ /* Note: Transition from state reset to state ready, */ /* otherwise (coming from state ready or busy) no state update. */ if (hcomp->State == HAL_COMP_STATE_RESET) 80032e4: 687b ldr r3, [r7, #4] 80032e6: 7f5b ldrb r3, [r3, #29] 80032e8: b2db uxtb r3, r3 80032ea: 2b00 cmp r3, #0 80032ec: d102 bne.n 80032f4 { hcomp->State = HAL_COMP_STATE_READY; 80032ee: 687b ldr r3, [r7, #4] 80032f0: 2201 movs r2, #1 80032f2: 775a strb r2, [r3, #29] } } return status; 80032f4: 7ffb ldrb r3, [r7, #31] } 80032f6: 4618 mov r0, r3 80032f8: 3720 adds r7, #32 80032fa: 46bd mov sp, r7 80032fc: bd80 pop {r7, pc} 80032fe: bf00 nop 8003300: 40010214 .word 0x40010214 8003304: 40010218 .word 0x40010218 08003308 : * @brief Initialize the CORDIC peripheral and the associated handle. * @param hcordic pointer to a CORDIC_HandleTypeDef structure. * @retval HAL status */ HAL_StatusTypeDef HAL_CORDIC_Init(CORDIC_HandleTypeDef *hcordic) { 8003308: b580 push {r7, lr} 800330a: b082 sub sp, #8 800330c: af00 add r7, sp, #0 800330e: 6078 str r0, [r7, #4] /* Check the CORDIC handle allocation */ if (hcordic == NULL) 8003310: 687b ldr r3, [r7, #4] 8003312: 2b00 cmp r3, #0 8003314: d101 bne.n 800331a { /* Return error status */ return HAL_ERROR; 8003316: 2301 movs r3, #1 8003318: e023 b.n 8003362 /* Initialize the low level hardware */ hcordic->MspInitCallback(hcordic); } #else if (hcordic->State == HAL_CORDIC_STATE_RESET) 800331a: 687b ldr r3, [r7, #4] 800331c: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 8003320: b2db uxtb r3, r3 8003322: 2b00 cmp r3, #0 8003324: d106 bne.n 8003334 { /* Allocate lock resource and initialize it */ hcordic->Lock = HAL_UNLOCKED; 8003326: 687b ldr r3, [r7, #4] 8003328: 2200 movs r2, #0 800332a: f883 2020 strb.w r2, [r3, #32] /* Initialize the low level hardware */ HAL_CORDIC_MspInit(hcordic); 800332e: 6878 ldr r0, [r7, #4] 8003330: f7fe f84e bl 80013d0 } #endif /* (USE_HAL_CORDIC_REGISTER_CALLBACKS) */ /* Set CORDIC error code to none */ hcordic->ErrorCode = HAL_CORDIC_ERROR_NONE; 8003334: 687b ldr r3, [r7, #4] 8003336: 2200 movs r2, #0 8003338: 625a str r2, [r3, #36] @ 0x24 /* Reset pInBuff and pOutBuff */ hcordic->pInBuff = NULL; 800333a: 687b ldr r3, [r7, #4] 800333c: 2200 movs r2, #0 800333e: 605a str r2, [r3, #4] hcordic->pOutBuff = NULL; 8003340: 687b ldr r3, [r7, #4] 8003342: 2200 movs r2, #0 8003344: 609a str r2, [r3, #8] /* Reset NbCalcToOrder and NbCalcToGet */ hcordic->NbCalcToOrder = 0U; 8003346: 687b ldr r3, [r7, #4] 8003348: 2200 movs r2, #0 800334a: 60da str r2, [r3, #12] hcordic->NbCalcToGet = 0U; 800334c: 687b ldr r3, [r7, #4] 800334e: 2200 movs r2, #0 8003350: 611a str r2, [r3, #16] /* Reset DMADirection */ hcordic->DMADirection = CORDIC_DMA_DIR_NONE; 8003352: 687b ldr r3, [r7, #4] 8003354: 2200 movs r2, #0 8003356: 615a str r2, [r3, #20] /* Change CORDIC peripheral state */ hcordic->State = HAL_CORDIC_STATE_READY; 8003358: 687b ldr r3, [r7, #4] 800335a: 2201 movs r2, #1 800335c: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Return function status */ return HAL_OK; 8003360: 2300 movs r3, #0 } 8003362: 4618 mov r0, r3 8003364: 3708 adds r7, #8 8003366: 46bd mov sp, r7 8003368: bd80 pop {r7, pc} ... 0800336c <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 800336c: b480 push {r7} 800336e: b085 sub sp, #20 8003370: af00 add r7, sp, #0 8003372: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8003374: 687b ldr r3, [r7, #4] 8003376: f003 0307 and.w r3, r3, #7 800337a: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 800337c: 4b0c ldr r3, [pc, #48] @ (80033b0 <__NVIC_SetPriorityGrouping+0x44>) 800337e: 68db ldr r3, [r3, #12] 8003380: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8003382: 68ba ldr r2, [r7, #8] 8003384: f64f 03ff movw r3, #63743 @ 0xf8ff 8003388: 4013 ands r3, r2 800338a: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 800338c: 68fb ldr r3, [r7, #12] 800338e: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8003390: 68bb ldr r3, [r7, #8] 8003392: 4313 orrs r3, r2 reg_value = (reg_value | 8003394: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 8003398: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800339c: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 800339e: 4a04 ldr r2, [pc, #16] @ (80033b0 <__NVIC_SetPriorityGrouping+0x44>) 80033a0: 68bb ldr r3, [r7, #8] 80033a2: 60d3 str r3, [r2, #12] } 80033a4: bf00 nop 80033a6: 3714 adds r7, #20 80033a8: 46bd mov sp, r7 80033aa: f85d 7b04 ldr.w r7, [sp], #4 80033ae: 4770 bx lr 80033b0: e000ed00 .word 0xe000ed00 080033b4 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 80033b4: b480 push {r7} 80033b6: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 80033b8: 4b04 ldr r3, [pc, #16] @ (80033cc <__NVIC_GetPriorityGrouping+0x18>) 80033ba: 68db ldr r3, [r3, #12] 80033bc: 0a1b lsrs r3, r3, #8 80033be: f003 0307 and.w r3, r3, #7 } 80033c2: 4618 mov r0, r3 80033c4: 46bd mov sp, r7 80033c6: f85d 7b04 ldr.w r7, [sp], #4 80033ca: 4770 bx lr 80033cc: e000ed00 .word 0xe000ed00 080033d0 <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 80033d0: b480 push {r7} 80033d2: b083 sub sp, #12 80033d4: af00 add r7, sp, #0 80033d6: 4603 mov r3, r0 80033d8: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 80033da: f997 3007 ldrsb.w r3, [r7, #7] 80033de: 2b00 cmp r3, #0 80033e0: db0b blt.n 80033fa <__NVIC_EnableIRQ+0x2a> { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 80033e2: 79fb ldrb r3, [r7, #7] 80033e4: f003 021f and.w r2, r3, #31 80033e8: 4907 ldr r1, [pc, #28] @ (8003408 <__NVIC_EnableIRQ+0x38>) 80033ea: f997 3007 ldrsb.w r3, [r7, #7] 80033ee: 095b lsrs r3, r3, #5 80033f0: 2001 movs r0, #1 80033f2: fa00 f202 lsl.w r2, r0, r2 80033f6: f841 2023 str.w r2, [r1, r3, lsl #2] __COMPILER_BARRIER(); } } 80033fa: bf00 nop 80033fc: 370c adds r7, #12 80033fe: 46bd mov sp, r7 8003400: f85d 7b04 ldr.w r7, [sp], #4 8003404: 4770 bx lr 8003406: bf00 nop 8003408: e000e100 .word 0xe000e100 0800340c <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 800340c: b480 push {r7} 800340e: b083 sub sp, #12 8003410: af00 add r7, sp, #0 8003412: 4603 mov r3, r0 8003414: 6039 str r1, [r7, #0] 8003416: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8003418: f997 3007 ldrsb.w r3, [r7, #7] 800341c: 2b00 cmp r3, #0 800341e: db0a blt.n 8003436 <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8003420: 683b ldr r3, [r7, #0] 8003422: b2da uxtb r2, r3 8003424: 490c ldr r1, [pc, #48] @ (8003458 <__NVIC_SetPriority+0x4c>) 8003426: f997 3007 ldrsb.w r3, [r7, #7] 800342a: 0112 lsls r2, r2, #4 800342c: b2d2 uxtb r2, r2 800342e: 440b add r3, r1 8003430: f883 2300 strb.w r2, [r3, #768] @ 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8003434: e00a b.n 800344c <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8003436: 683b ldr r3, [r7, #0] 8003438: b2da uxtb r2, r3 800343a: 4908 ldr r1, [pc, #32] @ (800345c <__NVIC_SetPriority+0x50>) 800343c: 79fb ldrb r3, [r7, #7] 800343e: f003 030f and.w r3, r3, #15 8003442: 3b04 subs r3, #4 8003444: 0112 lsls r2, r2, #4 8003446: b2d2 uxtb r2, r2 8003448: 440b add r3, r1 800344a: 761a strb r2, [r3, #24] } 800344c: bf00 nop 800344e: 370c adds r7, #12 8003450: 46bd mov sp, r7 8003452: f85d 7b04 ldr.w r7, [sp], #4 8003456: 4770 bx lr 8003458: e000e100 .word 0xe000e100 800345c: e000ed00 .word 0xe000ed00 08003460 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 8003460: b480 push {r7} 8003462: b089 sub sp, #36 @ 0x24 8003464: af00 add r7, sp, #0 8003466: 60f8 str r0, [r7, #12] 8003468: 60b9 str r1, [r7, #8] 800346a: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 800346c: 68fb ldr r3, [r7, #12] 800346e: f003 0307 and.w r3, r3, #7 8003472: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8003474: 69fb ldr r3, [r7, #28] 8003476: f1c3 0307 rsb r3, r3, #7 800347a: 2b04 cmp r3, #4 800347c: bf28 it cs 800347e: 2304 movcs r3, #4 8003480: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8003482: 69fb ldr r3, [r7, #28] 8003484: 3304 adds r3, #4 8003486: 2b06 cmp r3, #6 8003488: d902 bls.n 8003490 800348a: 69fb ldr r3, [r7, #28] 800348c: 3b03 subs r3, #3 800348e: e000 b.n 8003492 8003490: 2300 movs r3, #0 8003492: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8003494: f04f 32ff mov.w r2, #4294967295 8003498: 69bb ldr r3, [r7, #24] 800349a: fa02 f303 lsl.w r3, r2, r3 800349e: 43da mvns r2, r3 80034a0: 68bb ldr r3, [r7, #8] 80034a2: 401a ands r2, r3 80034a4: 697b ldr r3, [r7, #20] 80034a6: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 80034a8: f04f 31ff mov.w r1, #4294967295 80034ac: 697b ldr r3, [r7, #20] 80034ae: fa01 f303 lsl.w r3, r1, r3 80034b2: 43d9 mvns r1, r3 80034b4: 687b ldr r3, [r7, #4] 80034b6: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80034b8: 4313 orrs r3, r2 ); } 80034ba: 4618 mov r0, r3 80034bc: 3724 adds r7, #36 @ 0x24 80034be: 46bd mov sp, r7 80034c0: f85d 7b04 ldr.w r7, [sp], #4 80034c4: 4770 bx lr ... 080034c8 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 80034c8: b580 push {r7, lr} 80034ca: b082 sub sp, #8 80034cc: af00 add r7, sp, #0 80034ce: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 80034d0: 687b ldr r3, [r7, #4] 80034d2: 3b01 subs r3, #1 80034d4: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 80034d8: d301 bcc.n 80034de { return (1UL); /* Reload value impossible */ 80034da: 2301 movs r3, #1 80034dc: e00f b.n 80034fe } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 80034de: 4a0a ldr r2, [pc, #40] @ (8003508 ) 80034e0: 687b ldr r3, [r7, #4] 80034e2: 3b01 subs r3, #1 80034e4: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 80034e6: 210f movs r1, #15 80034e8: f04f 30ff mov.w r0, #4294967295 80034ec: f7ff ff8e bl 800340c <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 80034f0: 4b05 ldr r3, [pc, #20] @ (8003508 ) 80034f2: 2200 movs r2, #0 80034f4: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 80034f6: 4b04 ldr r3, [pc, #16] @ (8003508 ) 80034f8: 2207 movs r2, #7 80034fa: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 80034fc: 2300 movs r3, #0 } 80034fe: 4618 mov r0, r3 8003500: 3708 adds r7, #8 8003502: 46bd mov sp, r7 8003504: bd80 pop {r7, pc} 8003506: bf00 nop 8003508: e000e010 .word 0xe000e010 0800350c : * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 800350c: b580 push {r7, lr} 800350e: b082 sub sp, #8 8003510: af00 add r7, sp, #0 8003512: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8003514: 6878 ldr r0, [r7, #4] 8003516: f7ff ff29 bl 800336c <__NVIC_SetPriorityGrouping> } 800351a: bf00 nop 800351c: 3708 adds r7, #8 800351e: 46bd mov sp, r7 8003520: bd80 pop {r7, pc} 08003522 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8003522: b580 push {r7, lr} 8003524: b086 sub sp, #24 8003526: af00 add r7, sp, #0 8003528: 4603 mov r3, r0 800352a: 60b9 str r1, [r7, #8] 800352c: 607a str r2, [r7, #4] 800352e: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8003530: f7ff ff40 bl 80033b4 <__NVIC_GetPriorityGrouping> 8003534: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8003536: 687a ldr r2, [r7, #4] 8003538: 68b9 ldr r1, [r7, #8] 800353a: 6978 ldr r0, [r7, #20] 800353c: f7ff ff90 bl 8003460 8003540: 4602 mov r2, r0 8003542: f997 300f ldrsb.w r3, [r7, #15] 8003546: 4611 mov r1, r2 8003548: 4618 mov r0, r3 800354a: f7ff ff5f bl 800340c <__NVIC_SetPriority> } 800354e: bf00 nop 8003550: 3718 adds r7, #24 8003552: 46bd mov sp, r7 8003554: bd80 pop {r7, pc} 08003556 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8003556: b580 push {r7, lr} 8003558: b082 sub sp, #8 800355a: af00 add r7, sp, #0 800355c: 4603 mov r3, r0 800355e: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 8003560: f997 3007 ldrsb.w r3, [r7, #7] 8003564: 4618 mov r0, r3 8003566: f7ff ff33 bl 80033d0 <__NVIC_EnableIRQ> } 800356a: bf00 nop 800356c: 3708 adds r7, #8 800356e: 46bd mov sp, r7 8003570: bd80 pop {r7, pc} 08003572 : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8003572: b580 push {r7, lr} 8003574: b082 sub sp, #8 8003576: af00 add r7, sp, #0 8003578: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 800357a: 6878 ldr r0, [r7, #4] 800357c: f7ff ffa4 bl 80034c8 8003580: 4603 mov r3, r0 } 8003582: 4618 mov r0, r3 8003584: 3708 adds r7, #8 8003586: 46bd mov sp, r7 8003588: bd80 pop {r7, pc} 0800358a : * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac) { 800358a: b580 push {r7, lr} 800358c: b082 sub sp, #8 800358e: af00 add r7, sp, #0 8003590: 6078 str r0, [r7, #4] /* Check the DAC peripheral handle */ if (hdac == NULL) 8003592: 687b ldr r3, [r7, #4] 8003594: 2b00 cmp r3, #0 8003596: d101 bne.n 800359c { return HAL_ERROR; 8003598: 2301 movs r3, #1 800359a: e014 b.n 80035c6 } /* Check the parameters */ assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance)); if (hdac->State == HAL_DAC_STATE_RESET) 800359c: 687b ldr r3, [r7, #4] 800359e: 791b ldrb r3, [r3, #4] 80035a0: b2db uxtb r3, r3 80035a2: 2b00 cmp r3, #0 80035a4: d105 bne.n 80035b2 hdac->MspInitCallback = HAL_DAC_MspInit; } #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ /* Allocate lock resource and initialize it */ hdac->Lock = HAL_UNLOCKED; 80035a6: 687b ldr r3, [r7, #4] 80035a8: 2200 movs r2, #0 80035aa: 715a strb r2, [r3, #5] #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) /* Init the low level hardware */ hdac->MspInitCallback(hdac); #else /* Init the low level hardware */ HAL_DAC_MspInit(hdac); 80035ac: 6878 ldr r0, [r7, #4] 80035ae: f7fd ff2f bl 8001410 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } /* Initialize the DAC state*/ hdac->State = HAL_DAC_STATE_BUSY; 80035b2: 687b ldr r3, [r7, #4] 80035b4: 2202 movs r2, #2 80035b6: 711a strb r2, [r3, #4] /* Set DAC error code to none */ hdac->ErrorCode = HAL_DAC_ERROR_NONE; 80035b8: 687b ldr r3, [r7, #4] 80035ba: 2200 movs r2, #0 80035bc: 611a str r2, [r3, #16] /* Initialize the DAC state*/ hdac->State = HAL_DAC_STATE_READY; 80035be: 687b ldr r3, [r7, #4] 80035c0: 2201 movs r2, #1 80035c2: 711a strb r2, [r3, #4] /* Return function status */ return HAL_OK; 80035c4: 2300 movs r3, #0 } 80035c6: 4618 mov r0, r3 80035c8: 3708 adds r7, #8 80035ca: 46bd mov sp, r7 80035cc: bd80 pop {r7, pc} ... 080035d0 : * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) { 80035d0: b480 push {r7} 80035d2: b085 sub sp, #20 80035d4: af00 add r7, sp, #0 80035d6: 6078 str r0, [r7, #4] 80035d8: 6039 str r1, [r7, #0] __IO uint32_t wait_loop_index; /* Check the DAC peripheral handle */ if (hdac == NULL) 80035da: 687b ldr r3, [r7, #4] 80035dc: 2b00 cmp r3, #0 80035de: d101 bne.n 80035e4 { return HAL_ERROR; 80035e0: 2301 movs r3, #1 80035e2: e056 b.n 8003692 /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); /* Process locked */ __HAL_LOCK(hdac); 80035e4: 687b ldr r3, [r7, #4] 80035e6: 795b ldrb r3, [r3, #5] 80035e8: 2b01 cmp r3, #1 80035ea: d101 bne.n 80035f0 80035ec: 2302 movs r3, #2 80035ee: e050 b.n 8003692 80035f0: 687b ldr r3, [r7, #4] 80035f2: 2201 movs r2, #1 80035f4: 715a strb r2, [r3, #5] /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; 80035f6: 687b ldr r3, [r7, #4] 80035f8: 2202 movs r2, #2 80035fa: 711a strb r2, [r3, #4] /* Enable the Peripheral */ __HAL_DAC_ENABLE(hdac, Channel); 80035fc: 687b ldr r3, [r7, #4] 80035fe: 681b ldr r3, [r3, #0] 8003600: 6819 ldr r1, [r3, #0] 8003602: 683b ldr r3, [r7, #0] 8003604: f003 0310 and.w r3, r3, #16 8003608: 2201 movs r2, #1 800360a: 409a lsls r2, r3 800360c: 687b ldr r3, [r7, #4] 800360e: 681b ldr r3, [r3, #0] 8003610: 430a orrs r2, r1 8003612: 601a str r2, [r3, #0] /* Ensure minimum wait before using peripheral after enabling it */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed 32 */ /* bits register capacity and handle low frequency. */ wait_loop_index = ((DAC_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 8003614: 4b22 ldr r3, [pc, #136] @ (80036a0 ) 8003616: 681b ldr r3, [r3, #0] 8003618: 099b lsrs r3, r3, #6 800361a: 4a22 ldr r2, [pc, #136] @ (80036a4 ) 800361c: fba2 2303 umull r2, r3, r2, r3 8003620: 099b lsrs r3, r3, #6 8003622: 3301 adds r3, #1 8003624: 60fb str r3, [r7, #12] while (wait_loop_index != 0UL) 8003626: e002 b.n 800362e { wait_loop_index--; 8003628: 68fb ldr r3, [r7, #12] 800362a: 3b01 subs r3, #1 800362c: 60fb str r3, [r7, #12] while (wait_loop_index != 0UL) 800362e: 68fb ldr r3, [r7, #12] 8003630: 2b00 cmp r3, #0 8003632: d1f9 bne.n 8003628 } if (Channel == DAC_CHANNEL_1) 8003634: 683b ldr r3, [r7, #0] 8003636: 2b00 cmp r3, #0 8003638: d10f bne.n 800365a { /* Check if software trigger enabled */ if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE) 800363a: 687b ldr r3, [r7, #4] 800363c: 681b ldr r3, [r3, #0] 800363e: 681b ldr r3, [r3, #0] 8003640: f003 033e and.w r3, r3, #62 @ 0x3e 8003644: 2b02 cmp r3, #2 8003646: d11d bne.n 8003684 { /* Enable the selected DAC software conversion */ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1); 8003648: 687b ldr r3, [r7, #4] 800364a: 681b ldr r3, [r3, #0] 800364c: 685a ldr r2, [r3, #4] 800364e: 687b ldr r3, [r7, #4] 8003650: 681b ldr r3, [r3, #0] 8003652: f042 0201 orr.w r2, r2, #1 8003656: 605a str r2, [r3, #4] 8003658: e014 b.n 8003684 } else { /* Check if software trigger enabled */ if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (Channel & 0x10UL))) 800365a: 687b ldr r3, [r7, #4] 800365c: 681b ldr r3, [r3, #0] 800365e: 681b ldr r3, [r3, #0] 8003660: f403 1278 and.w r2, r3, #4063232 @ 0x3e0000 8003664: 683b ldr r3, [r7, #0] 8003666: f003 0310 and.w r3, r3, #16 800366a: 2102 movs r1, #2 800366c: fa01 f303 lsl.w r3, r1, r3 8003670: 429a cmp r2, r3 8003672: d107 bne.n 8003684 { /* Enable the selected DAC software conversion*/ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2); 8003674: 687b ldr r3, [r7, #4] 8003676: 681b ldr r3, [r3, #0] 8003678: 685a ldr r2, [r3, #4] 800367a: 687b ldr r3, [r7, #4] 800367c: 681b ldr r3, [r3, #0] 800367e: f042 0202 orr.w r2, r2, #2 8003682: 605a str r2, [r3, #4] } } /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; 8003684: 687b ldr r3, [r7, #4] 8003686: 2201 movs r2, #1 8003688: 711a strb r2, [r3, #4] /* Process unlocked */ __HAL_UNLOCK(hdac); 800368a: 687b ldr r3, [r7, #4] 800368c: 2200 movs r2, #0 800368e: 715a strb r2, [r3, #5] /* Return function status */ return HAL_OK; 8003690: 2300 movs r3, #0 } 8003692: 4618 mov r0, r3 8003694: 3714 adds r7, #20 8003696: 46bd mov sp, r7 8003698: f85d 7b04 ldr.w r7, [sp], #4 800369c: 4770 bx lr 800369e: bf00 nop 80036a0: 20000000 .word 0x20000000 80036a4: 053e2d63 .word 0x053e2d63 080036a8 : * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected * @param Data Data to be loaded in the selected data holding register. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) { 80036a8: b480 push {r7} 80036aa: b087 sub sp, #28 80036ac: af00 add r7, sp, #0 80036ae: 60f8 str r0, [r7, #12] 80036b0: 60b9 str r1, [r7, #8] 80036b2: 607a str r2, [r7, #4] 80036b4: 603b str r3, [r7, #0] __IO uint32_t tmp = 0UL; 80036b6: 2300 movs r3, #0 80036b8: 617b str r3, [r7, #20] /* Check the DAC peripheral handle */ if (hdac == NULL) 80036ba: 68fb ldr r3, [r7, #12] 80036bc: 2b00 cmp r3, #0 80036be: d101 bne.n 80036c4 { return HAL_ERROR; 80036c0: 2301 movs r3, #1 80036c2: e018 b.n 80036f6 /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); assert_param(IS_DAC_ALIGN(Alignment)); /* In case DMA Double data mode is activated, DATA range is almost full uin32_t one: no check */ if ((hdac->Instance->MCR & (DAC_MCR_DMADOUBLE1 << (Channel & 0x10UL))) == 0UL) 80036c4: 68fb ldr r3, [r7, #12] 80036c6: 681b ldr r3, [r3, #0] 80036c8: 6bdb ldr r3, [r3, #60] @ 0x3c { assert_param(IS_DAC_DATA(Data)); } tmp = (uint32_t)hdac->Instance; 80036ca: 68fb ldr r3, [r7, #12] 80036cc: 681b ldr r3, [r3, #0] 80036ce: 617b str r3, [r7, #20] if (Channel == DAC_CHANNEL_1) 80036d0: 68bb ldr r3, [r7, #8] 80036d2: 2b00 cmp r3, #0 80036d4: d105 bne.n 80036e2 { tmp += DAC_DHR12R1_ALIGNMENT(Alignment); 80036d6: 697a ldr r2, [r7, #20] 80036d8: 687b ldr r3, [r7, #4] 80036da: 4413 add r3, r2 80036dc: 3308 adds r3, #8 80036de: 617b str r3, [r7, #20] 80036e0: e004 b.n 80036ec } else { tmp += DAC_DHR12R2_ALIGNMENT(Alignment); 80036e2: 697a ldr r2, [r7, #20] 80036e4: 687b ldr r3, [r7, #4] 80036e6: 4413 add r3, r2 80036e8: 3314 adds r3, #20 80036ea: 617b str r3, [r7, #20] } /* Set the DAC channel selected data holding register */ *(__IO uint32_t *) tmp = Data; 80036ec: 697b ldr r3, [r7, #20] 80036ee: 461a mov r2, r3 80036f0: 683b ldr r3, [r7, #0] 80036f2: 6013 str r3, [r2, #0] /* Return function status */ return HAL_OK; 80036f4: 2300 movs r3, #0 } 80036f6: 4618 mov r0, r3 80036f8: 371c adds r7, #28 80036fa: 46bd mov sp, r7 80036fc: f85d 7b04 ldr.w r7, [sp], #4 8003700: 4770 bx lr ... 08003704 : * Refer to device datasheet for channels availability. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel) { 8003704: b580 push {r7, lr} 8003706: b08a sub sp, #40 @ 0x28 8003708: af00 add r7, sp, #0 800370a: 60f8 str r0, [r7, #12] 800370c: 60b9 str r1, [r7, #8] 800370e: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8003710: 2300 movs r3, #0 8003712: 77fb strb r3, [r7, #31] uint32_t tickstart; uint32_t hclkfreq; uint32_t connectOnChip; /* Check the DAC peripheral handle and channel configuration struct */ if ((hdac == NULL) || (sConfig == NULL)) 8003714: 68fb ldr r3, [r7, #12] 8003716: 2b00 cmp r3, #0 8003718: d002 beq.n 8003720 800371a: 68bb ldr r3, [r7, #8] 800371c: 2b00 cmp r3, #0 800371e: d101 bne.n 8003724 { return HAL_ERROR; 8003720: 2301 movs r3, #1 8003722: e1a1 b.n 8003a68 if ((sConfig->DAC_UserTrimming) == DAC_TRIMMING_USER) { assert_param(IS_DAC_TRIMMINGVALUE(sConfig->DAC_TrimmingValue)); } assert_param(IS_DAC_SAMPLEANDHOLD(sConfig->DAC_SampleAndHold)); if ((sConfig->DAC_SampleAndHold) == DAC_SAMPLEANDHOLD_ENABLE) 8003724: 68bb ldr r3, [r7, #8] 8003726: 689b ldr r3, [r3, #8] 8003728: 2b04 cmp r3, #4 assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); assert_param(IS_FUNCTIONAL_STATE(sConfig->DAC_DMADoubleDataMode)); assert_param(IS_FUNCTIONAL_STATE(sConfig->DAC_SignedFormat)); /* Process locked */ __HAL_LOCK(hdac); 800372a: 68fb ldr r3, [r7, #12] 800372c: 795b ldrb r3, [r3, #5] 800372e: 2b01 cmp r3, #1 8003730: d101 bne.n 8003736 8003732: 2302 movs r3, #2 8003734: e198 b.n 8003a68 8003736: 68fb ldr r3, [r7, #12] 8003738: 2201 movs r2, #1 800373a: 715a strb r2, [r3, #5] /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; 800373c: 68fb ldr r3, [r7, #12] 800373e: 2202 movs r2, #2 8003740: 711a strb r2, [r3, #4] /* Sample and hold configuration */ if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE) 8003742: 68bb ldr r3, [r7, #8] 8003744: 689b ldr r3, [r3, #8] 8003746: 2b04 cmp r3, #4 8003748: d17a bne.n 8003840 { /* Get timeout */ tickstart = HAL_GetTick(); 800374a: f7fe f8af bl 80018ac 800374e: 61b8 str r0, [r7, #24] if (Channel == DAC_CHANNEL_1) 8003750: 687b ldr r3, [r7, #4] 8003752: 2b00 cmp r3, #0 8003754: d13d bne.n 80037d2 { /* SHSR1 can be written when BWST1 is cleared */ while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) 8003756: e018 b.n 800378a { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) 8003758: f7fe f8a8 bl 80018ac 800375c: 4602 mov r2, r0 800375e: 69bb ldr r3, [r7, #24] 8003760: 1ad3 subs r3, r2, r3 8003762: 2b01 cmp r3, #1 8003764: d911 bls.n 800378a { /* New check to avoid false timeout detection in case of preemption */ if (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) 8003766: 68fb ldr r3, [r7, #12] 8003768: 681b ldr r3, [r3, #0] 800376a: 6b5b ldr r3, [r3, #52] @ 0x34 800376c: f403 4300 and.w r3, r3, #32768 @ 0x8000 8003770: 2b00 cmp r3, #0 8003772: d00a beq.n 800378a { /* Update error code */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); 8003774: 68fb ldr r3, [r7, #12] 8003776: 691b ldr r3, [r3, #16] 8003778: f043 0208 orr.w r2, r3, #8 800377c: 68fb ldr r3, [r7, #12] 800377e: 611a str r2, [r3, #16] /* Change the DMA state */ hdac->State = HAL_DAC_STATE_TIMEOUT; 8003780: 68fb ldr r3, [r7, #12] 8003782: 2203 movs r2, #3 8003784: 711a strb r2, [r3, #4] return HAL_TIMEOUT; 8003786: 2303 movs r3, #3 8003788: e16e b.n 8003a68 while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) 800378a: 68fb ldr r3, [r7, #12] 800378c: 681b ldr r3, [r3, #0] 800378e: 6b5b ldr r3, [r3, #52] @ 0x34 8003790: f403 4300 and.w r3, r3, #32768 @ 0x8000 8003794: 2b00 cmp r3, #0 8003796: d1df bne.n 8003758 } } } hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; 8003798: 68fb ldr r3, [r7, #12] 800379a: 681b ldr r3, [r3, #0] 800379c: 68ba ldr r2, [r7, #8] 800379e: 6a52 ldr r2, [r2, #36] @ 0x24 80037a0: 641a str r2, [r3, #64] @ 0x40 80037a2: e020 b.n 80037e6 { /* SHSR2 can be written when BWST2 is cleared */ while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) 80037a4: f7fe f882 bl 80018ac 80037a8: 4602 mov r2, r0 80037aa: 69bb ldr r3, [r7, #24] 80037ac: 1ad3 subs r3, r2, r3 80037ae: 2b01 cmp r3, #1 80037b0: d90f bls.n 80037d2 { /* New check to avoid false timeout detection in case of preemption */ if (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) 80037b2: 68fb ldr r3, [r7, #12] 80037b4: 681b ldr r3, [r3, #0] 80037b6: 6b5b ldr r3, [r3, #52] @ 0x34 80037b8: 2b00 cmp r3, #0 80037ba: da0a bge.n 80037d2 { /* Update error code */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); 80037bc: 68fb ldr r3, [r7, #12] 80037be: 691b ldr r3, [r3, #16] 80037c0: f043 0208 orr.w r2, r3, #8 80037c4: 68fb ldr r3, [r7, #12] 80037c6: 611a str r2, [r3, #16] /* Change the DMA state */ hdac->State = HAL_DAC_STATE_TIMEOUT; 80037c8: 68fb ldr r3, [r7, #12] 80037ca: 2203 movs r2, #3 80037cc: 711a strb r2, [r3, #4] return HAL_TIMEOUT; 80037ce: 2303 movs r3, #3 80037d0: e14a b.n 8003a68 while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) 80037d2: 68fb ldr r3, [r7, #12] 80037d4: 681b ldr r3, [r3, #0] 80037d6: 6b5b ldr r3, [r3, #52] @ 0x34 80037d8: 2b00 cmp r3, #0 80037da: dbe3 blt.n 80037a4 } } } hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; 80037dc: 68fb ldr r3, [r7, #12] 80037de: 681b ldr r3, [r3, #0] 80037e0: 68ba ldr r2, [r7, #8] 80037e2: 6a52 ldr r2, [r2, #36] @ 0x24 80037e4: 645a str r2, [r3, #68] @ 0x44 } /* HoldTime */ MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL), 80037e6: 68fb ldr r3, [r7, #12] 80037e8: 681b ldr r3, [r3, #0] 80037ea: 6c9a ldr r2, [r3, #72] @ 0x48 80037ec: 687b ldr r3, [r7, #4] 80037ee: f003 0310 and.w r3, r3, #16 80037f2: f240 31ff movw r1, #1023 @ 0x3ff 80037f6: fa01 f303 lsl.w r3, r1, r3 80037fa: 43db mvns r3, r3 80037fc: ea02 0103 and.w r1, r2, r3 8003800: 68bb ldr r3, [r7, #8] 8003802: 6a9a ldr r2, [r3, #40] @ 0x28 8003804: 687b ldr r3, [r7, #4] 8003806: f003 0310 and.w r3, r3, #16 800380a: 409a lsls r2, r3 800380c: 68fb ldr r3, [r7, #12] 800380e: 681b ldr r3, [r3, #0] 8003810: 430a orrs r2, r1 8003812: 649a str r2, [r3, #72] @ 0x48 (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL)); /* RefreshTime */ MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL), 8003814: 68fb ldr r3, [r7, #12] 8003816: 681b ldr r3, [r3, #0] 8003818: 6cda ldr r2, [r3, #76] @ 0x4c 800381a: 687b ldr r3, [r7, #4] 800381c: f003 0310 and.w r3, r3, #16 8003820: 21ff movs r1, #255 @ 0xff 8003822: fa01 f303 lsl.w r3, r1, r3 8003826: 43db mvns r3, r3 8003828: ea02 0103 and.w r1, r2, r3 800382c: 68bb ldr r3, [r7, #8] 800382e: 6ada ldr r2, [r3, #44] @ 0x2c 8003830: 687b ldr r3, [r7, #4] 8003832: f003 0310 and.w r3, r3, #16 8003836: 409a lsls r2, r3 8003838: 68fb ldr r3, [r7, #12] 800383a: 681b ldr r3, [r3, #0] 800383c: 430a orrs r2, r1 800383e: 64da str r2, [r3, #76] @ 0x4c (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL)); } if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER) 8003840: 68bb ldr r3, [r7, #8] 8003842: 69db ldr r3, [r3, #28] 8003844: 2b01 cmp r3, #1 8003846: d11d bne.n 8003884 /* USER TRIMMING */ { /* Get the DAC CCR value */ tmpreg1 = hdac->Instance->CCR; 8003848: 68fb ldr r3, [r7, #12] 800384a: 681b ldr r3, [r3, #0] 800384c: 6b9b ldr r3, [r3, #56] @ 0x38 800384e: 627b str r3, [r7, #36] @ 0x24 /* Clear trimming value */ tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << (Channel & 0x10UL)); 8003850: 687b ldr r3, [r7, #4] 8003852: f003 0310 and.w r3, r3, #16 8003856: 221f movs r2, #31 8003858: fa02 f303 lsl.w r3, r2, r3 800385c: 43db mvns r3, r3 800385e: 6a7a ldr r2, [r7, #36] @ 0x24 8003860: 4013 ands r3, r2 8003862: 627b str r3, [r7, #36] @ 0x24 /* Configure for the selected trimming offset */ tmpreg2 = sConfig->DAC_TrimmingValue; 8003864: 68bb ldr r3, [r7, #8] 8003866: 6a1b ldr r3, [r3, #32] 8003868: 617b str r3, [r7, #20] /* Calculate CCR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 800386a: 687b ldr r3, [r7, #4] 800386c: f003 0310 and.w r3, r3, #16 8003870: 697a ldr r2, [r7, #20] 8003872: fa02 f303 lsl.w r3, r2, r3 8003876: 6a7a ldr r2, [r7, #36] @ 0x24 8003878: 4313 orrs r3, r2 800387a: 627b str r3, [r7, #36] @ 0x24 /* Write to DAC CCR */ hdac->Instance->CCR = tmpreg1; 800387c: 68fb ldr r3, [r7, #12] 800387e: 681b ldr r3, [r3, #0] 8003880: 6a7a ldr r2, [r7, #36] @ 0x24 8003882: 639a str r2, [r3, #56] @ 0x38 } /* else factory trimming is used (factory setting are available at reset)*/ /* SW Nothing has nothing to do */ /* Get the DAC MCR value */ tmpreg1 = hdac->Instance->MCR; 8003884: 68fb ldr r3, [r7, #12] 8003886: 681b ldr r3, [r3, #0] 8003888: 6bdb ldr r3, [r3, #60] @ 0x3c 800388a: 627b str r3, [r7, #36] @ 0x24 /* Clear DAC_MCR_MODEx bits */ tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL)); 800388c: 687b ldr r3, [r7, #4] 800388e: f003 0310 and.w r3, r3, #16 8003892: 2207 movs r2, #7 8003894: fa02 f303 lsl.w r3, r2, r3 8003898: 43db mvns r3, r3 800389a: 6a7a ldr r2, [r7, #36] @ 0x24 800389c: 4013 ands r3, r2 800389e: 627b str r3, [r7, #36] @ 0x24 /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */ if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL) 80038a0: 68bb ldr r3, [r7, #8] 80038a2: 699b ldr r3, [r3, #24] 80038a4: 2b01 cmp r3, #1 80038a6: d102 bne.n 80038ae { connectOnChip = 0x00000000UL; 80038a8: 2300 movs r3, #0 80038aa: 623b str r3, [r7, #32] 80038ac: e00f b.n 80038ce } else if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_INTERNAL) 80038ae: 68bb ldr r3, [r7, #8] 80038b0: 699b ldr r3, [r3, #24] 80038b2: 2b02 cmp r3, #2 80038b4: d102 bne.n 80038bc { connectOnChip = DAC_MCR_MODE1_0; 80038b6: 2301 movs r3, #1 80038b8: 623b str r3, [r7, #32] 80038ba: e008 b.n 80038ce } else /* (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_BOTH) */ { if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_ENABLE) 80038bc: 68bb ldr r3, [r7, #8] 80038be: 695b ldr r3, [r3, #20] 80038c0: 2b00 cmp r3, #0 80038c2: d102 bne.n 80038ca { connectOnChip = DAC_MCR_MODE1_0; 80038c4: 2301 movs r3, #1 80038c6: 623b str r3, [r7, #32] 80038c8: e001 b.n 80038ce } else { connectOnChip = 0x00000000UL; 80038ca: 2300 movs r3, #0 80038cc: 623b str r3, [r7, #32] } } tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | connectOnChip); 80038ce: 68bb ldr r3, [r7, #8] 80038d0: 689a ldr r2, [r3, #8] 80038d2: 68bb ldr r3, [r7, #8] 80038d4: 695b ldr r3, [r3, #20] 80038d6: 4313 orrs r3, r2 80038d8: 6a3a ldr r2, [r7, #32] 80038da: 4313 orrs r3, r2 80038dc: 617b str r3, [r7, #20] /* Clear DAC_MCR_DMADOUBLEx */ tmpreg1 &= ~(((uint32_t)(DAC_MCR_DMADOUBLE1)) << (Channel & 0x10UL)); 80038de: 687b ldr r3, [r7, #4] 80038e0: f003 0310 and.w r3, r3, #16 80038e4: f44f 7280 mov.w r2, #256 @ 0x100 80038e8: fa02 f303 lsl.w r3, r2, r3 80038ec: 43db mvns r3, r3 80038ee: 6a7a ldr r2, [r7, #36] @ 0x24 80038f0: 4013 ands r3, r2 80038f2: 627b str r3, [r7, #36] @ 0x24 /* Configure for the selected DAC channel: DMA double data mode */ tmpreg2 |= (sConfig->DAC_DMADoubleDataMode == ENABLE) ? DAC_MCR_DMADOUBLE1 : 0UL; 80038f4: 68bb ldr r3, [r7, #8] 80038f6: 791b ldrb r3, [r3, #4] 80038f8: 2b01 cmp r3, #1 80038fa: d102 bne.n 8003902 80038fc: f44f 7380 mov.w r3, #256 @ 0x100 8003900: e000 b.n 8003904 8003902: 2300 movs r3, #0 8003904: 697a ldr r2, [r7, #20] 8003906: 4313 orrs r3, r2 8003908: 617b str r3, [r7, #20] /* Clear DAC_MCR_SINFORMATx */ tmpreg1 &= ~(((uint32_t)(DAC_MCR_SINFORMAT1)) << (Channel & 0x10UL)); 800390a: 687b ldr r3, [r7, #4] 800390c: f003 0310 and.w r3, r3, #16 8003910: f44f 7200 mov.w r2, #512 @ 0x200 8003914: fa02 f303 lsl.w r3, r2, r3 8003918: 43db mvns r3, r3 800391a: 6a7a ldr r2, [r7, #36] @ 0x24 800391c: 4013 ands r3, r2 800391e: 627b str r3, [r7, #36] @ 0x24 /* Configure for the selected DAC channel: Signed format */ tmpreg2 |= (sConfig->DAC_SignedFormat == ENABLE) ? DAC_MCR_SINFORMAT1 : 0UL; 8003920: 68bb ldr r3, [r7, #8] 8003922: 795b ldrb r3, [r3, #5] 8003924: 2b01 cmp r3, #1 8003926: d102 bne.n 800392e 8003928: f44f 7300 mov.w r3, #512 @ 0x200 800392c: e000 b.n 8003930 800392e: 2300 movs r3, #0 8003930: 697a ldr r2, [r7, #20] 8003932: 4313 orrs r3, r2 8003934: 617b str r3, [r7, #20] /* Clear DAC_MCR_HFSEL bits */ tmpreg1 &= ~(DAC_MCR_HFSEL); 8003936: 6a7b ldr r3, [r7, #36] @ 0x24 8003938: f423 4340 bic.w r3, r3, #49152 @ 0xc000 800393c: 627b str r3, [r7, #36] @ 0x24 /* Configure for both DAC channels: high frequency mode */ if (DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC == sConfig->DAC_HighFrequency) 800393e: 68bb ldr r3, [r7, #8] 8003940: 681b ldr r3, [r3, #0] 8003942: 2b02 cmp r3, #2 8003944: d114 bne.n 8003970 { hclkfreq = HAL_RCC_GetHCLKFreq(); 8003946: f002 fd3b bl 80063c0 800394a: 6138 str r0, [r7, #16] if (hclkfreq > HFSEL_ENABLE_THRESHOLD_160MHZ) 800394c: 693b ldr r3, [r7, #16] 800394e: 4a48 ldr r2, [pc, #288] @ (8003a70 ) 8003950: 4293 cmp r3, r2 8003952: d904 bls.n 800395e { tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ; 8003954: 6a7b ldr r3, [r7, #36] @ 0x24 8003956: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800395a: 627b str r3, [r7, #36] @ 0x24 800395c: e00f b.n 800397e } else if (hclkfreq > HFSEL_ENABLE_THRESHOLD_80MHZ) 800395e: 693b ldr r3, [r7, #16] 8003960: 4a44 ldr r2, [pc, #272] @ (8003a74 ) 8003962: 4293 cmp r3, r2 8003964: d90a bls.n 800397c { tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ; 8003966: 6a7b ldr r3, [r7, #36] @ 0x24 8003968: f443 4380 orr.w r3, r3, #16384 @ 0x4000 800396c: 627b str r3, [r7, #36] @ 0x24 800396e: e006 b.n 800397e tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE; } } else { tmpreg1 |= sConfig->DAC_HighFrequency; 8003970: 68bb ldr r3, [r7, #8] 8003972: 681b ldr r3, [r3, #0] 8003974: 6a7a ldr r2, [r7, #36] @ 0x24 8003976: 4313 orrs r3, r2 8003978: 627b str r3, [r7, #36] @ 0x24 800397a: e000 b.n 800397e tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE; 800397c: bf00 nop } /* Calculate MCR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 800397e: 687b ldr r3, [r7, #4] 8003980: f003 0310 and.w r3, r3, #16 8003984: 697a ldr r2, [r7, #20] 8003986: fa02 f303 lsl.w r3, r2, r3 800398a: 6a7a ldr r2, [r7, #36] @ 0x24 800398c: 4313 orrs r3, r2 800398e: 627b str r3, [r7, #36] @ 0x24 /* Write to DAC MCR */ hdac->Instance->MCR = tmpreg1; 8003990: 68fb ldr r3, [r7, #12] 8003992: 681b ldr r3, [r3, #0] 8003994: 6a7a ldr r2, [r7, #36] @ 0x24 8003996: 63da str r2, [r3, #60] @ 0x3c /* DAC in normal operating mode hence clear DAC_CR_CENx bit */ CLEAR_BIT(hdac->Instance->CR, DAC_CR_CEN1 << (Channel & 0x10UL)); 8003998: 68fb ldr r3, [r7, #12] 800399a: 681b ldr r3, [r3, #0] 800399c: 6819 ldr r1, [r3, #0] 800399e: 687b ldr r3, [r7, #4] 80039a0: f003 0310 and.w r3, r3, #16 80039a4: f44f 4280 mov.w r2, #16384 @ 0x4000 80039a8: fa02 f303 lsl.w r3, r2, r3 80039ac: 43da mvns r2, r3 80039ae: 68fb ldr r3, [r7, #12] 80039b0: 681b ldr r3, [r3, #0] 80039b2: 400a ands r2, r1 80039b4: 601a str r2, [r3, #0] /* Get the DAC CR value */ tmpreg1 = hdac->Instance->CR; 80039b6: 68fb ldr r3, [r7, #12] 80039b8: 681b ldr r3, [r3, #0] 80039ba: 681b ldr r3, [r3, #0] 80039bc: 627b str r3, [r7, #36] @ 0x24 /* Clear TENx, TSELx, WAVEx and MAMPx bits */ tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << (Channel & 0x10UL)); 80039be: 687b ldr r3, [r7, #4] 80039c0: f003 0310 and.w r3, r3, #16 80039c4: f640 72fe movw r2, #4094 @ 0xffe 80039c8: fa02 f303 lsl.w r3, r2, r3 80039cc: 43db mvns r3, r3 80039ce: 6a7a ldr r2, [r7, #36] @ 0x24 80039d0: 4013 ands r3, r2 80039d2: 627b str r3, [r7, #36] @ 0x24 /* Configure for the selected DAC channel: trigger */ /* Set TSELx and TENx bits according to DAC_Trigger value */ tmpreg2 = sConfig->DAC_Trigger; 80039d4: 68bb ldr r3, [r7, #8] 80039d6: 68db ldr r3, [r3, #12] 80039d8: 617b str r3, [r7, #20] /* Calculate CR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 80039da: 687b ldr r3, [r7, #4] 80039dc: f003 0310 and.w r3, r3, #16 80039e0: 697a ldr r2, [r7, #20] 80039e2: fa02 f303 lsl.w r3, r2, r3 80039e6: 6a7a ldr r2, [r7, #36] @ 0x24 80039e8: 4313 orrs r3, r2 80039ea: 627b str r3, [r7, #36] @ 0x24 /* Write to DAC CR */ hdac->Instance->CR = tmpreg1; 80039ec: 68fb ldr r3, [r7, #12] 80039ee: 681b ldr r3, [r3, #0] 80039f0: 6a7a ldr r2, [r7, #36] @ 0x24 80039f2: 601a str r2, [r3, #0] /* Disable wave generation */ CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL))); 80039f4: 68fb ldr r3, [r7, #12] 80039f6: 681b ldr r3, [r3, #0] 80039f8: 6819 ldr r1, [r3, #0] 80039fa: 687b ldr r3, [r7, #4] 80039fc: f003 0310 and.w r3, r3, #16 8003a00: 22c0 movs r2, #192 @ 0xc0 8003a02: fa02 f303 lsl.w r3, r2, r3 8003a06: 43da mvns r2, r3 8003a08: 68fb ldr r3, [r7, #12] 8003a0a: 681b ldr r3, [r3, #0] 8003a0c: 400a ands r2, r1 8003a0e: 601a str r2, [r3, #0] /* Set STRSTTRIGSELx and STINCTRIGSELx bits according to DAC_Trigger & DAC_Trigger2 values */ tmpreg2 = ((sConfig->DAC_Trigger & DAC_CR_TSEL1) >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STRSTTRIGSEL1_Pos; 8003a10: 68bb ldr r3, [r7, #8] 8003a12: 68db ldr r3, [r3, #12] 8003a14: 089b lsrs r3, r3, #2 8003a16: f003 030f and.w r3, r3, #15 8003a1a: 617b str r3, [r7, #20] tmpreg2 |= ((sConfig->DAC_Trigger2 & DAC_CR_TSEL1) >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STINCTRIGSEL1_Pos; 8003a1c: 68bb ldr r3, [r7, #8] 8003a1e: 691b ldr r3, [r3, #16] 8003a20: 089b lsrs r3, r3, #2 8003a22: 021b lsls r3, r3, #8 8003a24: f403 6370 and.w r3, r3, #3840 @ 0xf00 8003a28: 697a ldr r2, [r7, #20] 8003a2a: 4313 orrs r3, r2 8003a2c: 617b str r3, [r7, #20] /* Modify STMODR register value depending on DAC_Channel */ MODIFY_REG(hdac->Instance->STMODR, (DAC_STMODR_STINCTRIGSEL1 | DAC_STMODR_STRSTTRIGSEL1) 8003a2e: 68fb ldr r3, [r7, #12] 8003a30: 681b ldr r3, [r3, #0] 8003a32: 6e1a ldr r2, [r3, #96] @ 0x60 8003a34: 687b ldr r3, [r7, #4] 8003a36: f003 0310 and.w r3, r3, #16 8003a3a: f640 710f movw r1, #3855 @ 0xf0f 8003a3e: fa01 f303 lsl.w r3, r1, r3 8003a42: 43db mvns r3, r3 8003a44: ea02 0103 and.w r1, r2, r3 8003a48: 687b ldr r3, [r7, #4] 8003a4a: f003 0310 and.w r3, r3, #16 8003a4e: 697a ldr r2, [r7, #20] 8003a50: 409a lsls r2, r3 8003a52: 68fb ldr r3, [r7, #12] 8003a54: 681b ldr r3, [r3, #0] 8003a56: 430a orrs r2, r1 8003a58: 661a str r2, [r3, #96] @ 0x60 << (Channel & 0x10UL), tmpreg2 << (Channel & 0x10UL)); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; 8003a5a: 68fb ldr r3, [r7, #12] 8003a5c: 2201 movs r2, #1 8003a5e: 711a strb r2, [r3, #4] /* Process unlocked */ __HAL_UNLOCK(hdac); 8003a60: 68fb ldr r3, [r7, #12] 8003a62: 2200 movs r2, #0 8003a64: 715a strb r2, [r3, #5] /* Return function status */ return status; 8003a66: 7ffb ldrb r3, [r7, #31] } 8003a68: 4618 mov r0, r3 8003a6a: 3728 adds r7, #40 @ 0x28 8003a6c: 46bd mov sp, r7 8003a6e: bd80 pop {r7, pc} 8003a70: 09896800 .word 0x09896800 8003a74: 04c4b400 .word 0x04c4b400 08003a78 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 8003a78: b580 push {r7, lr} 8003a7a: b084 sub sp, #16 8003a7c: af00 add r7, sp, #0 8003a7e: 6078 str r0, [r7, #4] uint32_t tmp; /* Check the DMA handle allocation */ if (hdma == NULL) 8003a80: 687b ldr r3, [r7, #4] 8003a82: 2b00 cmp r3, #0 8003a84: d101 bne.n 8003a8a { return HAL_ERROR; 8003a86: 2301 movs r3, #1 8003a88: e08d b.n 8003ba6 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request)); /* Compute the channel index */ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) 8003a8a: 687b ldr r3, [r7, #4] 8003a8c: 681b ldr r3, [r3, #0] 8003a8e: 461a mov r2, r3 8003a90: 4b47 ldr r3, [pc, #284] @ (8003bb0 ) 8003a92: 429a cmp r2, r3 8003a94: d80f bhi.n 8003ab6 { /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; 8003a96: 687b ldr r3, [r7, #4] 8003a98: 681b ldr r3, [r3, #0] 8003a9a: 461a mov r2, r3 8003a9c: 4b45 ldr r3, [pc, #276] @ (8003bb4 ) 8003a9e: 4413 add r3, r2 8003aa0: 4a45 ldr r2, [pc, #276] @ (8003bb8 ) 8003aa2: fba2 2303 umull r2, r3, r2, r3 8003aa6: 091b lsrs r3, r3, #4 8003aa8: 009a lsls r2, r3, #2 8003aaa: 687b ldr r3, [r7, #4] 8003aac: 645a str r2, [r3, #68] @ 0x44 hdma->DmaBaseAddress = DMA1; 8003aae: 687b ldr r3, [r7, #4] 8003ab0: 4a42 ldr r2, [pc, #264] @ (8003bbc ) 8003ab2: 641a str r2, [r3, #64] @ 0x40 8003ab4: e00e b.n 8003ad4 } else { /* DMA2 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; 8003ab6: 687b ldr r3, [r7, #4] 8003ab8: 681b ldr r3, [r3, #0] 8003aba: 461a mov r2, r3 8003abc: 4b40 ldr r3, [pc, #256] @ (8003bc0 ) 8003abe: 4413 add r3, r2 8003ac0: 4a3d ldr r2, [pc, #244] @ (8003bb8 ) 8003ac2: fba2 2303 umull r2, r3, r2, r3 8003ac6: 091b lsrs r3, r3, #4 8003ac8: 009a lsls r2, r3, #2 8003aca: 687b ldr r3, [r7, #4] 8003acc: 645a str r2, [r3, #68] @ 0x44 hdma->DmaBaseAddress = DMA2; 8003ace: 687b ldr r3, [r7, #4] 8003ad0: 4a3c ldr r2, [pc, #240] @ (8003bc4 ) 8003ad2: 641a str r2, [r3, #64] @ 0x40 } /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8003ad4: 687b ldr r3, [r7, #4] 8003ad6: 2202 movs r2, #2 8003ad8: f883 2025 strb.w r2, [r3, #37] @ 0x25 /* Get the CR register value */ tmp = hdma->Instance->CCR; 8003adc: 687b ldr r3, [r7, #4] 8003ade: 681b ldr r3, [r3, #0] 8003ae0: 681b ldr r3, [r3, #0] 8003ae2: 60fb str r3, [r7, #12] /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */ tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | 8003ae4: 68fb ldr r3, [r7, #12] 8003ae6: f423 43ff bic.w r3, r3, #32640 @ 0x7f80 8003aea: f023 0370 bic.w r3, r3, #112 @ 0x70 8003aee: 60fb str r3, [r7, #12] DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR | DMA_CCR_MEM2MEM)); /* Prepare the DMA Channel configuration */ tmp |= hdma->Init.Direction | 8003af0: 687b ldr r3, [r7, #4] 8003af2: 689a ldr r2, [r3, #8] hdma->Init.PeriphInc | hdma->Init.MemInc | 8003af4: 687b ldr r3, [r7, #4] 8003af6: 68db ldr r3, [r3, #12] tmp |= hdma->Init.Direction | 8003af8: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 8003afa: 687b ldr r3, [r7, #4] 8003afc: 691b ldr r3, [r3, #16] 8003afe: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8003b00: 687b ldr r3, [r7, #4] 8003b02: 695b ldr r3, [r3, #20] hdma->Init.PeriphInc | hdma->Init.MemInc | 8003b04: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8003b06: 687b ldr r3, [r7, #4] 8003b08: 699b ldr r3, [r3, #24] 8003b0a: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 8003b0c: 687b ldr r3, [r7, #4] 8003b0e: 69db ldr r3, [r3, #28] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8003b10: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 8003b12: 687b ldr r3, [r7, #4] 8003b14: 6a1b ldr r3, [r3, #32] 8003b16: 4313 orrs r3, r2 tmp |= hdma->Init.Direction | 8003b18: 68fa ldr r2, [r7, #12] 8003b1a: 4313 orrs r3, r2 8003b1c: 60fb str r3, [r7, #12] /* Write to DMA Channel CR register */ hdma->Instance->CCR = tmp; 8003b1e: 687b ldr r3, [r7, #4] 8003b20: 681b ldr r3, [r3, #0] 8003b22: 68fa ldr r2, [r7, #12] 8003b24: 601a str r2, [r3, #0] /* Initialize parameters for DMAMUX channel : DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ DMA_CalcDMAMUXChannelBaseAndMask(hdma); 8003b26: 6878 ldr r0, [r7, #4] 8003b28: f000 f8fe bl 8003d28 if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) 8003b2c: 687b ldr r3, [r7, #4] 8003b2e: 689b ldr r3, [r3, #8] 8003b30: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 8003b34: d102 bne.n 8003b3c { /* if memory to memory force the request to 0*/ hdma->Init.Request = DMA_REQUEST_MEM2MEM; 8003b36: 687b ldr r3, [r7, #4] 8003b38: 2200 movs r2, #0 8003b3a: 605a str r2, [r3, #4] } /* Set peripheral request to DMAMUX channel */ hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); 8003b3c: 687b ldr r3, [r7, #4] 8003b3e: 685a ldr r2, [r3, #4] 8003b40: 687b ldr r3, [r7, #4] 8003b42: 6c9b ldr r3, [r3, #72] @ 0x48 8003b44: b2d2 uxtb r2, r2 8003b46: 601a str r2, [r3, #0] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8003b48: 687b ldr r3, [r7, #4] 8003b4a: 6cdb ldr r3, [r3, #76] @ 0x4c 8003b4c: 687a ldr r2, [r7, #4] 8003b4e: 6d12 ldr r2, [r2, #80] @ 0x50 8003b50: 605a str r2, [r3, #4] if (((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) 8003b52: 687b ldr r3, [r7, #4] 8003b54: 685b ldr r3, [r3, #4] 8003b56: 2b00 cmp r3, #0 8003b58: d010 beq.n 8003b7c 8003b5a: 687b ldr r3, [r7, #4] 8003b5c: 685b ldr r3, [r3, #4] 8003b5e: 2b04 cmp r3, #4 8003b60: d80c bhi.n 8003b7c { /* Initialize parameters for DMAMUX request generator : DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); 8003b62: 6878 ldr r0, [r7, #4] 8003b64: f000 f91e bl 8003da4 /* Reset the DMAMUX request generator register*/ hdma->DMAmuxRequestGen->RGCR = 0U; 8003b68: 687b ldr r3, [r7, #4] 8003b6a: 6d5b ldr r3, [r3, #84] @ 0x54 8003b6c: 2200 movs r2, #0 8003b6e: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8003b70: 687b ldr r3, [r7, #4] 8003b72: 6d9b ldr r3, [r3, #88] @ 0x58 8003b74: 687a ldr r2, [r7, #4] 8003b76: 6dd2 ldr r2, [r2, #92] @ 0x5c 8003b78: 605a str r2, [r3, #4] 8003b7a: e008 b.n 8003b8e } else { hdma->DMAmuxRequestGen = 0U; 8003b7c: 687b ldr r3, [r7, #4] 8003b7e: 2200 movs r2, #0 8003b80: 655a str r2, [r3, #84] @ 0x54 hdma->DMAmuxRequestGenStatus = 0U; 8003b82: 687b ldr r3, [r7, #4] 8003b84: 2200 movs r2, #0 8003b86: 659a str r2, [r3, #88] @ 0x58 hdma->DMAmuxRequestGenStatusMask = 0U; 8003b88: 687b ldr r3, [r7, #4] 8003b8a: 2200 movs r2, #0 8003b8c: 65da str r2, [r3, #92] @ 0x5c } /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8003b8e: 687b ldr r3, [r7, #4] 8003b90: 2200 movs r2, #0 8003b92: 63da str r2, [r3, #60] @ 0x3c /* Initialize the DMA state*/ hdma->State = HAL_DMA_STATE_READY; 8003b94: 687b ldr r3, [r7, #4] 8003b96: 2201 movs r2, #1 8003b98: f883 2025 strb.w r2, [r3, #37] @ 0x25 /* Allocate lock resource and initialize it */ hdma->Lock = HAL_UNLOCKED; 8003b9c: 687b ldr r3, [r7, #4] 8003b9e: 2200 movs r2, #0 8003ba0: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_OK; 8003ba4: 2300 movs r3, #0 } 8003ba6: 4618 mov r0, r3 8003ba8: 3710 adds r7, #16 8003baa: 46bd mov sp, r7 8003bac: bd80 pop {r7, pc} 8003bae: bf00 nop 8003bb0: 40020407 .word 0x40020407 8003bb4: bffdfff8 .word 0xbffdfff8 8003bb8: cccccccd .word 0xcccccccd 8003bbc: 40020000 .word 0x40020000 8003bc0: bffdfbf8 .word 0xbffdfbf8 8003bc4: 40020400 .word 0x40020400 08003bc8 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { 8003bc8: b580 push {r7, lr} 8003bca: b084 sub sp, #16 8003bcc: af00 add r7, sp, #0 8003bce: 6078 str r0, [r7, #4] uint32_t flag_it = hdma->DmaBaseAddress->ISR; 8003bd0: 687b ldr r3, [r7, #4] 8003bd2: 6c1b ldr r3, [r3, #64] @ 0x40 8003bd4: 681b ldr r3, [r3, #0] 8003bd6: 60fb str r3, [r7, #12] uint32_t source_it = hdma->Instance->CCR; 8003bd8: 687b ldr r3, [r7, #4] 8003bda: 681b ldr r3, [r3, #0] 8003bdc: 681b ldr r3, [r3, #0] 8003bde: 60bb str r3, [r7, #8] /* Half Transfer Complete Interrupt management ******************************/ if ((0U != (flag_it & ((uint32_t)DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1FU)))) && (0U != (source_it & DMA_IT_HT))) 8003be0: 687b ldr r3, [r7, #4] 8003be2: 6c5b ldr r3, [r3, #68] @ 0x44 8003be4: f003 031f and.w r3, r3, #31 8003be8: 2204 movs r2, #4 8003bea: 409a lsls r2, r3 8003bec: 68fb ldr r3, [r7, #12] 8003bee: 4013 ands r3, r2 8003bf0: 2b00 cmp r3, #0 8003bf2: d026 beq.n 8003c42 8003bf4: 68bb ldr r3, [r7, #8] 8003bf6: f003 0304 and.w r3, r3, #4 8003bfa: 2b00 cmp r3, #0 8003bfc: d021 beq.n 8003c42 { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 8003bfe: 687b ldr r3, [r7, #4] 8003c00: 681b ldr r3, [r3, #0] 8003c02: 681b ldr r3, [r3, #0] 8003c04: f003 0320 and.w r3, r3, #32 8003c08: 2b00 cmp r3, #0 8003c0a: d107 bne.n 8003c1c { /* Disable the half transfer interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 8003c0c: 687b ldr r3, [r7, #4] 8003c0e: 681b ldr r3, [r3, #0] 8003c10: 681a ldr r2, [r3, #0] 8003c12: 687b ldr r3, [r7, #4] 8003c14: 681b ldr r3, [r3, #0] 8003c16: f022 0204 bic.w r2, r2, #4 8003c1a: 601a str r2, [r3, #0] } /* Clear the half transfer complete flag */ hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1FU)); 8003c1c: 687b ldr r3, [r7, #4] 8003c1e: 6c5b ldr r3, [r3, #68] @ 0x44 8003c20: f003 021f and.w r2, r3, #31 8003c24: 687b ldr r3, [r7, #4] 8003c26: 6c1b ldr r3, [r3, #64] @ 0x40 8003c28: 2104 movs r1, #4 8003c2a: fa01 f202 lsl.w r2, r1, r2 8003c2e: 605a str r2, [r3, #4] /* DMA peripheral state is not updated in Half Transfer */ /* but in Transfer Complete case */ if (hdma->XferHalfCpltCallback != NULL) 8003c30: 687b ldr r3, [r7, #4] 8003c32: 6b1b ldr r3, [r3, #48] @ 0x30 8003c34: 2b00 cmp r3, #0 8003c36: d071 beq.n 8003d1c { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8003c38: 687b ldr r3, [r7, #4] 8003c3a: 6b1b ldr r3, [r3, #48] @ 0x30 8003c3c: 6878 ldr r0, [r7, #4] 8003c3e: 4798 blx r3 if (hdma->XferHalfCpltCallback != NULL) 8003c40: e06c b.n 8003d1c } } /* Transfer Complete Interrupt management ***********************************/ else if ((0U != (flag_it & ((uint32_t)DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1FU)))) 8003c42: 687b ldr r3, [r7, #4] 8003c44: 6c5b ldr r3, [r3, #68] @ 0x44 8003c46: f003 031f and.w r3, r3, #31 8003c4a: 2202 movs r2, #2 8003c4c: 409a lsls r2, r3 8003c4e: 68fb ldr r3, [r7, #12] 8003c50: 4013 ands r3, r2 8003c52: 2b00 cmp r3, #0 8003c54: d02e beq.n 8003cb4 && (0U != (source_it & DMA_IT_TC))) 8003c56: 68bb ldr r3, [r7, #8] 8003c58: f003 0302 and.w r3, r3, #2 8003c5c: 2b00 cmp r3, #0 8003c5e: d029 beq.n 8003cb4 { if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 8003c60: 687b ldr r3, [r7, #4] 8003c62: 681b ldr r3, [r3, #0] 8003c64: 681b ldr r3, [r3, #0] 8003c66: f003 0320 and.w r3, r3, #32 8003c6a: 2b00 cmp r3, #0 8003c6c: d10b bne.n 8003c86 { /* Disable the transfer complete and error interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); 8003c6e: 687b ldr r3, [r7, #4] 8003c70: 681b ldr r3, [r3, #0] 8003c72: 681a ldr r2, [r3, #0] 8003c74: 687b ldr r3, [r7, #4] 8003c76: 681b ldr r3, [r3, #0] 8003c78: f022 020a bic.w r2, r2, #10 8003c7c: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8003c7e: 687b ldr r3, [r7, #4] 8003c80: 2201 movs r2, #1 8003c82: f883 2025 strb.w r2, [r3, #37] @ 0x25 } /* Clear the transfer complete flag */ hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1FU)); 8003c86: 687b ldr r3, [r7, #4] 8003c88: 6c5b ldr r3, [r3, #68] @ 0x44 8003c8a: f003 021f and.w r2, r3, #31 8003c8e: 687b ldr r3, [r7, #4] 8003c90: 6c1b ldr r3, [r3, #64] @ 0x40 8003c92: 2102 movs r1, #2 8003c94: fa01 f202 lsl.w r2, r1, r2 8003c98: 605a str r2, [r3, #4] /* Process Unlocked */ __HAL_UNLOCK(hdma); 8003c9a: 687b ldr r3, [r7, #4] 8003c9c: 2200 movs r2, #0 8003c9e: f883 2024 strb.w r2, [r3, #36] @ 0x24 if (hdma->XferCpltCallback != NULL) 8003ca2: 687b ldr r3, [r7, #4] 8003ca4: 6adb ldr r3, [r3, #44] @ 0x2c 8003ca6: 2b00 cmp r3, #0 8003ca8: d038 beq.n 8003d1c { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 8003caa: 687b ldr r3, [r7, #4] 8003cac: 6adb ldr r3, [r3, #44] @ 0x2c 8003cae: 6878 ldr r0, [r7, #4] 8003cb0: 4798 blx r3 if (hdma->XferCpltCallback != NULL) 8003cb2: e033 b.n 8003d1c } } /* Transfer Error Interrupt management **************************************/ else if ((0U != (flag_it & ((uint32_t)DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1FU)))) 8003cb4: 687b ldr r3, [r7, #4] 8003cb6: 6c5b ldr r3, [r3, #68] @ 0x44 8003cb8: f003 031f and.w r3, r3, #31 8003cbc: 2208 movs r2, #8 8003cbe: 409a lsls r2, r3 8003cc0: 68fb ldr r3, [r7, #12] 8003cc2: 4013 ands r3, r2 8003cc4: 2b00 cmp r3, #0 8003cc6: d02a beq.n 8003d1e && (0U != (source_it & DMA_IT_TE))) 8003cc8: 68bb ldr r3, [r7, #8] 8003cca: f003 0308 and.w r3, r3, #8 8003cce: 2b00 cmp r3, #0 8003cd0: d025 beq.n 8003d1e { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Disable ALL DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8003cd2: 687b ldr r3, [r7, #4] 8003cd4: 681b ldr r3, [r3, #0] 8003cd6: 681a ldr r2, [r3, #0] 8003cd8: 687b ldr r3, [r7, #4] 8003cda: 681b ldr r3, [r3, #0] 8003cdc: f022 020e bic.w r2, r2, #14 8003ce0: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU)); 8003ce2: 687b ldr r3, [r7, #4] 8003ce4: 6c5b ldr r3, [r3, #68] @ 0x44 8003ce6: f003 021f and.w r2, r3, #31 8003cea: 687b ldr r3, [r7, #4] 8003cec: 6c1b ldr r3, [r3, #64] @ 0x40 8003cee: 2101 movs r1, #1 8003cf0: fa01 f202 lsl.w r2, r1, r2 8003cf4: 605a str r2, [r3, #4] /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; 8003cf6: 687b ldr r3, [r7, #4] 8003cf8: 2201 movs r2, #1 8003cfa: 63da str r2, [r3, #60] @ 0x3c /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8003cfc: 687b ldr r3, [r7, #4] 8003cfe: 2201 movs r2, #1 8003d00: f883 2025 strb.w r2, [r3, #37] @ 0x25 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8003d04: 687b ldr r3, [r7, #4] 8003d06: 2200 movs r2, #0 8003d08: f883 2024 strb.w r2, [r3, #36] @ 0x24 if (hdma->XferErrorCallback != NULL) 8003d0c: 687b ldr r3, [r7, #4] 8003d0e: 6b5b ldr r3, [r3, #52] @ 0x34 8003d10: 2b00 cmp r3, #0 8003d12: d004 beq.n 8003d1e { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 8003d14: 687b ldr r3, [r7, #4] 8003d16: 6b5b ldr r3, [r3, #52] @ 0x34 8003d18: 6878 ldr r0, [r7, #4] 8003d1a: 4798 blx r3 } else { /* Nothing To Do */ } return; 8003d1c: bf00 nop 8003d1e: bf00 nop } 8003d20: 3710 adds r7, #16 8003d22: 46bd mov sp, r7 8003d24: bd80 pop {r7, pc} ... 08003d28 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) { 8003d28: b480 push {r7} 8003d2a: b087 sub sp, #28 8003d2c: af00 add r7, sp, #0 8003d2e: 6078 str r0, [r7, #4] uint32_t dmamux_base_addr; uint32_t channel_number; DMAMUX_Channel_TypeDef *DMAMUX1_ChannelBase; /* check if instance is not outside the DMA channel range */ if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1) 8003d30: 687b ldr r3, [r7, #4] 8003d32: 681b ldr r3, [r3, #0] 8003d34: 461a mov r2, r3 8003d36: 4b16 ldr r3, [pc, #88] @ (8003d90 ) 8003d38: 429a cmp r2, r3 8003d3a: d802 bhi.n 8003d42 { /* DMA1 */ DMAMUX1_ChannelBase = DMAMUX1_Channel0; 8003d3c: 4b15 ldr r3, [pc, #84] @ (8003d94 ) 8003d3e: 617b str r3, [r7, #20] 8003d40: e001 b.n 8003d46 } else { /* DMA2 */ #if defined (STM32G471xx) || defined (STM32G473xx) || defined (STM32G474xx) || defined (STM32G414xx) || defined (STM32G483xx) || defined (STM32G484xx) || defined (STM32G491xx) || defined (STM32G4A1xx) || defined (STM32G411xC) DMAMUX1_ChannelBase = DMAMUX1_Channel8; 8003d42: 4b15 ldr r3, [pc, #84] @ (8003d98 ) 8003d44: 617b str r3, [r7, #20] DMAMUX1_ChannelBase = DMAMUX1_Channel6; #else DMAMUX1_ChannelBase = DMAMUX1_Channel7; #endif /* STM32G4x1xx) */ } dmamux_base_addr = (uint32_t)DMAMUX1_ChannelBase; 8003d46: 697b ldr r3, [r7, #20] 8003d48: 613b str r3, [r7, #16] channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U; 8003d4a: 687b ldr r3, [r7, #4] 8003d4c: 681b ldr r3, [r3, #0] 8003d4e: b2db uxtb r3, r3 8003d50: 3b08 subs r3, #8 8003d52: 4a12 ldr r2, [pc, #72] @ (8003d9c ) 8003d54: fba2 2303 umull r2, r3, r2, r3 8003d58: 091b lsrs r3, r3, #4 8003d5a: 60fb str r3, [r7, #12] hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)(dmamux_base_addr + ((hdma->ChannelIndex >> 2U) * ((uint32_t)DMAMUX1_Channel1 - (uint32_t)DMAMUX1_Channel0))); 8003d5c: 687b ldr r3, [r7, #4] 8003d5e: 6c5b ldr r3, [r3, #68] @ 0x44 8003d60: 089b lsrs r3, r3, #2 8003d62: 009a lsls r2, r3, #2 8003d64: 693b ldr r3, [r7, #16] 8003d66: 4413 add r3, r2 8003d68: 461a mov r2, r3 8003d6a: 687b ldr r3, [r7, #4] 8003d6c: 649a str r2, [r3, #72] @ 0x48 hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; 8003d6e: 687b ldr r3, [r7, #4] 8003d70: 4a0b ldr r2, [pc, #44] @ (8003da0 ) 8003d72: 64da str r2, [r3, #76] @ 0x4c hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU); 8003d74: 68fb ldr r3, [r7, #12] 8003d76: f003 031f and.w r3, r3, #31 8003d7a: 2201 movs r2, #1 8003d7c: 409a lsls r2, r3 8003d7e: 687b ldr r3, [r7, #4] 8003d80: 651a str r2, [r3, #80] @ 0x50 } 8003d82: bf00 nop 8003d84: 371c adds r7, #28 8003d86: 46bd mov sp, r7 8003d88: f85d 7b04 ldr.w r7, [sp], #4 8003d8c: 4770 bx lr 8003d8e: bf00 nop 8003d90: 40020407 .word 0x40020407 8003d94: 40020800 .word 0x40020800 8003d98: 40020820 .word 0x40020820 8003d9c: cccccccd .word 0xcccccccd 8003da0: 40020880 .word 0x40020880 08003da4 : * the configuration information for the specified DMA Channel. * @retval None */ static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) { 8003da4: b480 push {r7} 8003da6: b085 sub sp, #20 8003da8: af00 add r7, sp, #0 8003daa: 6078 str r0, [r7, #4] uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; 8003dac: 687b ldr r3, [r7, #4] 8003dae: 685b ldr r3, [r3, #4] 8003db0: b2db uxtb r3, r3 8003db2: 60fb str r3, [r7, #12] /* DMA Channels are connected to DMAMUX1 request generator blocks*/ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); 8003db4: 68fa ldr r2, [r7, #12] 8003db6: 4b0b ldr r3, [pc, #44] @ (8003de4 ) 8003db8: 4413 add r3, r2 8003dba: 009b lsls r3, r3, #2 8003dbc: 461a mov r2, r3 8003dbe: 687b ldr r3, [r7, #4] 8003dc0: 655a str r2, [r3, #84] @ 0x54 hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; 8003dc2: 687b ldr r3, [r7, #4] 8003dc4: 4a08 ldr r2, [pc, #32] @ (8003de8 ) 8003dc6: 659a str r2, [r3, #88] @ 0x58 hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x1FU); 8003dc8: 68fb ldr r3, [r7, #12] 8003dca: 3b01 subs r3, #1 8003dcc: f003 031f and.w r3, r3, #31 8003dd0: 2201 movs r2, #1 8003dd2: 409a lsls r2, r3 8003dd4: 687b ldr r3, [r7, #4] 8003dd6: 65da str r2, [r3, #92] @ 0x5c } 8003dd8: bf00 nop 8003dda: 3714 adds r7, #20 8003ddc: 46bd mov sp, r7 8003dde: f85d 7b04 ldr.w r7, [sp], #4 8003de2: 4770 bx lr 8003de4: 1000823f .word 0x1000823f 8003de8: 40020940 .word 0x40020940 08003dec : * @brief Initialize the FMAC peripheral and the associated handle. * @param hfmac pointer to a FMAC_HandleTypeDef structure. * @retval HAL_StatusTypeDef HAL status */ HAL_StatusTypeDef HAL_FMAC_Init(FMAC_HandleTypeDef *hfmac) { 8003dec: b580 push {r7, lr} 8003dee: b084 sub sp, #16 8003df0: af00 add r7, sp, #0 8003df2: 6078 str r0, [r7, #4] HAL_StatusTypeDef status; /* Check the FMAC handle allocation */ if (hfmac == NULL) 8003df4: 687b ldr r3, [r7, #4] 8003df6: 2b00 cmp r3, #0 8003df8: d101 bne.n 8003dfe { return HAL_ERROR; 8003dfa: 2301 movs r3, #1 8003dfc: e033 b.n 8003e66 } /* Check the instance */ assert_param(IS_FMAC_ALL_INSTANCE(hfmac->Instance)); if (hfmac->State == HAL_FMAC_STATE_RESET) 8003dfe: 687b ldr r3, [r7, #4] 8003e00: f893 3031 ldrb.w r3, [r3, #49] @ 0x31 8003e04: b2db uxtb r3, r3 8003e06: 2b00 cmp r3, #0 8003e08: d106 bne.n 8003e18 { /* Initialize lock resource */ hfmac->Lock = HAL_UNLOCKED; 8003e0a: 687b ldr r3, [r7, #4] 8003e0c: 2200 movs r2, #0 8003e0e: f883 2030 strb.w r2, [r3, #48] @ 0x30 /* Init the low level hardware */ hfmac->MspInitCallback(hfmac); #else /* Init the low level hardware */ HAL_FMAC_MspInit(hfmac); 8003e12: 6878 ldr r0, [r7, #4] 8003e14: f7fd fb30 bl 8001478 #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */ } /* Reset pInput and pOutput */ hfmac->FilterParam = 0U; 8003e18: 687b ldr r3, [r7, #4] 8003e1a: 2200 movs r2, #0 8003e1c: 605a str r2, [r3, #4] FMAC_ResetDataPointers(hfmac); 8003e1e: 6878 ldr r0, [r7, #4] 8003e20: f000 f854 bl 8003ecc /* Reset FMAC unit (internal pointers) */ if (FMAC_Reset(hfmac) == HAL_ERROR) 8003e24: 6878 ldr r0, [r7, #4] 8003e26: f000 f822 bl 8003e6e 8003e2a: 4603 mov r3, r0 8003e2c: 2b01 cmp r3, #1 8003e2e: d10c bne.n 8003e4a { /* Update FMAC error code and FMAC peripheral state */ hfmac->ErrorCode |= HAL_FMAC_ERROR_RESET; 8003e30: 687b ldr r3, [r7, #4] 8003e32: 6b5b ldr r3, [r3, #52] @ 0x34 8003e34: f043 0210 orr.w r2, r3, #16 8003e38: 687b ldr r3, [r7, #4] 8003e3a: 635a str r2, [r3, #52] @ 0x34 hfmac->State = HAL_FMAC_STATE_TIMEOUT; 8003e3c: 687b ldr r3, [r7, #4] 8003e3e: 22a0 movs r2, #160 @ 0xa0 8003e40: f883 2031 strb.w r2, [r3, #49] @ 0x31 status = HAL_ERROR; 8003e44: 2301 movs r3, #1 8003e46: 73fb strb r3, [r7, #15] 8003e48: e008 b.n 8003e5c } else { /* Update FMAC error code and FMAC peripheral state */ hfmac->ErrorCode = HAL_FMAC_ERROR_NONE; 8003e4a: 687b ldr r3, [r7, #4] 8003e4c: 2200 movs r2, #0 8003e4e: 635a str r2, [r3, #52] @ 0x34 hfmac->State = HAL_FMAC_STATE_READY; 8003e50: 687b ldr r3, [r7, #4] 8003e52: 2220 movs r2, #32 8003e54: f883 2031 strb.w r2, [r3, #49] @ 0x31 status = HAL_OK; 8003e58: 2300 movs r3, #0 8003e5a: 73fb strb r3, [r7, #15] } __HAL_UNLOCK(hfmac); 8003e5c: 687b ldr r3, [r7, #4] 8003e5e: 2200 movs r2, #0 8003e60: f883 2030 strb.w r2, [r3, #48] @ 0x30 return status; 8003e64: 7bfb ldrb r3, [r7, #15] } 8003e66: 4618 mov r0, r3 8003e68: 3710 adds r7, #16 8003e6a: 46bd mov sp, r7 8003e6c: bd80 pop {r7, pc} 08003e6e : * @brief Perform a reset of the FMAC unit. * @param hfmac FMAC handle. * @retval HAL_StatusTypeDef HAL status */ static HAL_StatusTypeDef FMAC_Reset(FMAC_HandleTypeDef *hfmac) { 8003e6e: b580 push {r7, lr} 8003e70: b084 sub sp, #16 8003e72: af00 add r7, sp, #0 8003e74: 6078 str r0, [r7, #4] uint32_t tickstart; /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); 8003e76: f7fd fd19 bl 80018ac 8003e7a: 60f8 str r0, [r7, #12] /* Perform the reset */ SET_BIT(hfmac->Instance->CR, FMAC_CR_RESET); 8003e7c: 687b ldr r3, [r7, #4] 8003e7e: 681b ldr r3, [r3, #0] 8003e80: 691a ldr r2, [r3, #16] 8003e82: 687b ldr r3, [r7, #4] 8003e84: 681b ldr r3, [r3, #0] 8003e86: f442 3280 orr.w r2, r2, #65536 @ 0x10000 8003e8a: 611a str r2, [r3, #16] /* Wait until flag is reset */ while (READ_BIT(hfmac->Instance->CR, FMAC_CR_RESET) != 0U) 8003e8c: e00f b.n 8003eae { if ((HAL_GetTick() - tickstart) > HAL_FMAC_RESET_TIMEOUT_VALUE) 8003e8e: f7fd fd0d bl 80018ac 8003e92: 4602 mov r2, r0 8003e94: 68fb ldr r3, [r7, #12] 8003e96: 1ad3 subs r3, r2, r3 8003e98: f5b3 7ffa cmp.w r3, #500 @ 0x1f4 8003e9c: d907 bls.n 8003eae { hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT; 8003e9e: 687b ldr r3, [r7, #4] 8003ea0: 6b5b ldr r3, [r3, #52] @ 0x34 8003ea2: f043 0280 orr.w r2, r3, #128 @ 0x80 8003ea6: 687b ldr r3, [r7, #4] 8003ea8: 635a str r2, [r3, #52] @ 0x34 return HAL_ERROR; 8003eaa: 2301 movs r3, #1 8003eac: e00a b.n 8003ec4 while (READ_BIT(hfmac->Instance->CR, FMAC_CR_RESET) != 0U) 8003eae: 687b ldr r3, [r7, #4] 8003eb0: 681b ldr r3, [r3, #0] 8003eb2: 691b ldr r3, [r3, #16] 8003eb4: f403 3380 and.w r3, r3, #65536 @ 0x10000 8003eb8: 2b00 cmp r3, #0 8003eba: d1e8 bne.n 8003e8e } } hfmac->ErrorCode = HAL_FMAC_ERROR_NONE; 8003ebc: 687b ldr r3, [r7, #4] 8003ebe: 2200 movs r2, #0 8003ec0: 635a str r2, [r3, #52] @ 0x34 return HAL_OK; 8003ec2: 2300 movs r3, #0 } 8003ec4: 4618 mov r0, r3 8003ec6: 3710 adds r7, #16 8003ec8: 46bd mov sp, r7 8003eca: bd80 pop {r7, pc} 08003ecc : * @brief Reset the data pointers of the FMAC unit. * @param hfmac FMAC handle. * @retval None */ static void FMAC_ResetDataPointers(FMAC_HandleTypeDef *hfmac) { 8003ecc: b580 push {r7, lr} 8003ece: b082 sub sp, #8 8003ed0: af00 add r7, sp, #0 8003ed2: 6078 str r0, [r7, #4] FMAC_ResetInputStateAndDataPointers(hfmac); 8003ed4: 6878 ldr r0, [r7, #4] 8003ed6: f000 f807 bl 8003ee8 FMAC_ResetOutputStateAndDataPointers(hfmac); 8003eda: 6878 ldr r0, [r7, #4] 8003edc: f000 f81b bl 8003f16 } 8003ee0: bf00 nop 8003ee2: 3708 adds r7, #8 8003ee4: 46bd mov sp, r7 8003ee6: bd80 pop {r7, pc} 08003ee8 : * @brief Reset the input data pointers of the FMAC unit. * @param hfmac FMAC handle. * @retval None */ static void FMAC_ResetInputStateAndDataPointers(FMAC_HandleTypeDef *hfmac) { 8003ee8: b480 push {r7} 8003eea: b083 sub sp, #12 8003eec: af00 add r7, sp, #0 8003eee: 6078 str r0, [r7, #4] hfmac->pInput = NULL; 8003ef0: 687b ldr r3, [r7, #4] 8003ef2: 2200 movs r2, #0 8003ef4: 60da str r2, [r3, #12] hfmac->pInputSize = NULL; 8003ef6: 687b ldr r3, [r7, #4] 8003ef8: 2200 movs r2, #0 8003efa: 615a str r2, [r3, #20] hfmac->InputCurrentSize = 0U; 8003efc: 687b ldr r3, [r7, #4] 8003efe: 2200 movs r2, #0 8003f00: 821a strh r2, [r3, #16] hfmac->WrState = HAL_FMAC_STATE_READY; 8003f02: 687b ldr r3, [r7, #4] 8003f04: 2220 movs r2, #32 8003f06: f883 2033 strb.w r2, [r3, #51] @ 0x33 } 8003f0a: bf00 nop 8003f0c: 370c adds r7, #12 8003f0e: 46bd mov sp, r7 8003f10: f85d 7b04 ldr.w r7, [sp], #4 8003f14: 4770 bx lr 08003f16 : * @brief Reset the output data pointers of the FMAC unit. * @param hfmac FMAC handle. * @retval None */ static void FMAC_ResetOutputStateAndDataPointers(FMAC_HandleTypeDef *hfmac) { 8003f16: b480 push {r7} 8003f18: b083 sub sp, #12 8003f1a: af00 add r7, sp, #0 8003f1c: 6078 str r0, [r7, #4] hfmac->pOutput = NULL; 8003f1e: 687b ldr r3, [r7, #4] 8003f20: 2200 movs r2, #0 8003f22: 619a str r2, [r3, #24] hfmac->pOutputSize = NULL; 8003f24: 687b ldr r3, [r7, #4] 8003f26: 2200 movs r2, #0 8003f28: 621a str r2, [r3, #32] hfmac->OutputCurrentSize = 0U; 8003f2a: 687b ldr r3, [r7, #4] 8003f2c: 2200 movs r2, #0 8003f2e: 839a strh r2, [r3, #28] hfmac->RdState = HAL_FMAC_STATE_READY; 8003f30: 687b ldr r3, [r7, #4] 8003f32: 2220 movs r2, #32 8003f34: f883 2032 strb.w r2, [r3, #50] @ 0x32 } 8003f38: bf00 nop 8003f3a: 370c adds r7, #12 8003f3c: 46bd mov sp, r7 8003f3e: f85d 7b04 ldr.w r7, [sp], #4 8003f42: 4770 bx lr 08003f44 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8003f44: b480 push {r7} 8003f46: b087 sub sp, #28 8003f48: af00 add r7, sp, #0 8003f4a: 6078 str r0, [r7, #4] 8003f4c: 6039 str r1, [r7, #0] uint32_t position = 0x00U; 8003f4e: 2300 movs r3, #0 8003f50: 617b str r3, [r7, #20] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0U) 8003f52: e15a b.n 800420a { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1UL << position); 8003f54: 683b ldr r3, [r7, #0] 8003f56: 681a ldr r2, [r3, #0] 8003f58: 2101 movs r1, #1 8003f5a: 697b ldr r3, [r7, #20] 8003f5c: fa01 f303 lsl.w r3, r1, r3 8003f60: 4013 ands r3, r2 8003f62: 60fb str r3, [r7, #12] if (iocurrent != 0x00u) 8003f64: 68fb ldr r3, [r7, #12] 8003f66: 2b00 cmp r3, #0 8003f68: f000 814c beq.w 8004204 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || 8003f6c: 683b ldr r3, [r7, #0] 8003f6e: 685b ldr r3, [r3, #4] 8003f70: f003 0303 and.w r3, r3, #3 8003f74: 2b01 cmp r3, #1 8003f76: d005 beq.n 8003f84 ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 8003f78: 683b ldr r3, [r7, #0] 8003f7a: 685b ldr r3, [r3, #4] 8003f7c: f003 0303 and.w r3, r3, #3 if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || 8003f80: 2b02 cmp r3, #2 8003f82: d130 bne.n 8003fe6 { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 8003f84: 687b ldr r3, [r7, #4] 8003f86: 689b ldr r3, [r3, #8] 8003f88: 613b str r3, [r7, #16] temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); 8003f8a: 697b ldr r3, [r7, #20] 8003f8c: 005b lsls r3, r3, #1 8003f8e: 2203 movs r2, #3 8003f90: fa02 f303 lsl.w r3, r2, r3 8003f94: 43db mvns r3, r3 8003f96: 693a ldr r2, [r7, #16] 8003f98: 4013 ands r3, r2 8003f9a: 613b str r3, [r7, #16] temp |= (GPIO_Init->Speed << (position * 2U)); 8003f9c: 683b ldr r3, [r7, #0] 8003f9e: 68da ldr r2, [r3, #12] 8003fa0: 697b ldr r3, [r7, #20] 8003fa2: 005b lsls r3, r3, #1 8003fa4: fa02 f303 lsl.w r3, r2, r3 8003fa8: 693a ldr r2, [r7, #16] 8003faa: 4313 orrs r3, r2 8003fac: 613b str r3, [r7, #16] GPIOx->OSPEEDR = temp; 8003fae: 687b ldr r3, [r7, #4] 8003fb0: 693a ldr r2, [r7, #16] 8003fb2: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 8003fb4: 687b ldr r3, [r7, #4] 8003fb6: 685b ldr r3, [r3, #4] 8003fb8: 613b str r3, [r7, #16] temp &= ~(GPIO_OTYPER_OT0 << position) ; 8003fba: 2201 movs r2, #1 8003fbc: 697b ldr r3, [r7, #20] 8003fbe: fa02 f303 lsl.w r3, r2, r3 8003fc2: 43db mvns r3, r3 8003fc4: 693a ldr r2, [r7, #16] 8003fc6: 4013 ands r3, r2 8003fc8: 613b str r3, [r7, #16] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 8003fca: 683b ldr r3, [r7, #0] 8003fcc: 685b ldr r3, [r3, #4] 8003fce: 091b lsrs r3, r3, #4 8003fd0: f003 0201 and.w r2, r3, #1 8003fd4: 697b ldr r3, [r7, #20] 8003fd6: fa02 f303 lsl.w r3, r2, r3 8003fda: 693a ldr r2, [r7, #16] 8003fdc: 4313 orrs r3, r2 8003fde: 613b str r3, [r7, #16] GPIOx->OTYPER = temp; 8003fe0: 687b ldr r3, [r7, #4] 8003fe2: 693a ldr r2, [r7, #16] 8003fe4: 605a str r2, [r3, #4] } if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 8003fe6: 683b ldr r3, [r7, #0] 8003fe8: 685b ldr r3, [r3, #4] 8003fea: f003 0303 and.w r3, r3, #3 8003fee: 2b03 cmp r3, #3 8003ff0: d017 beq.n 8004022 { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 8003ff2: 687b ldr r3, [r7, #4] 8003ff4: 68db ldr r3, [r3, #12] 8003ff6: 613b str r3, [r7, #16] temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); 8003ff8: 697b ldr r3, [r7, #20] 8003ffa: 005b lsls r3, r3, #1 8003ffc: 2203 movs r2, #3 8003ffe: fa02 f303 lsl.w r3, r2, r3 8004002: 43db mvns r3, r3 8004004: 693a ldr r2, [r7, #16] 8004006: 4013 ands r3, r2 8004008: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Pull) << (position * 2U)); 800400a: 683b ldr r3, [r7, #0] 800400c: 689a ldr r2, [r3, #8] 800400e: 697b ldr r3, [r7, #20] 8004010: 005b lsls r3, r3, #1 8004012: fa02 f303 lsl.w r3, r2, r3 8004016: 693a ldr r2, [r7, #16] 8004018: 4313 orrs r3, r2 800401a: 613b str r3, [r7, #16] GPIOx->PUPDR = temp; 800401c: 687b ldr r3, [r7, #4] 800401e: 693a ldr r2, [r7, #16] 8004020: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8004022: 683b ldr r3, [r7, #0] 8004024: 685b ldr r3, [r3, #4] 8004026: f003 0303 and.w r3, r3, #3 800402a: 2b02 cmp r3, #2 800402c: d123 bne.n 8004076 /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; 800402e: 697b ldr r3, [r7, #20] 8004030: 08da lsrs r2, r3, #3 8004032: 687b ldr r3, [r7, #4] 8004034: 3208 adds r2, #8 8004036: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800403a: 613b str r3, [r7, #16] temp &= ~(0xFU << ((position & 0x07U) * 4U)); 800403c: 697b ldr r3, [r7, #20] 800403e: f003 0307 and.w r3, r3, #7 8004042: 009b lsls r3, r3, #2 8004044: 220f movs r2, #15 8004046: fa02 f303 lsl.w r3, r2, r3 800404a: 43db mvns r3, r3 800404c: 693a ldr r2, [r7, #16] 800404e: 4013 ands r3, r2 8004050: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); 8004052: 683b ldr r3, [r7, #0] 8004054: 691a ldr r2, [r3, #16] 8004056: 697b ldr r3, [r7, #20] 8004058: f003 0307 and.w r3, r3, #7 800405c: 009b lsls r3, r3, #2 800405e: fa02 f303 lsl.w r3, r2, r3 8004062: 693a ldr r2, [r7, #16] 8004064: 4313 orrs r3, r2 8004066: 613b str r3, [r7, #16] GPIOx->AFR[position >> 3U] = temp; 8004068: 697b ldr r3, [r7, #20] 800406a: 08da lsrs r2, r3, #3 800406c: 687b ldr r3, [r7, #4] 800406e: 3208 adds r2, #8 8004070: 6939 ldr r1, [r7, #16] 8004072: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 8004076: 687b ldr r3, [r7, #4] 8004078: 681b ldr r3, [r3, #0] 800407a: 613b str r3, [r7, #16] temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); 800407c: 697b ldr r3, [r7, #20] 800407e: 005b lsls r3, r3, #1 8004080: 2203 movs r2, #3 8004082: fa02 f303 lsl.w r3, r2, r3 8004086: 43db mvns r3, r3 8004088: 693a ldr r2, [r7, #16] 800408a: 4013 ands r3, r2 800408c: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 800408e: 683b ldr r3, [r7, #0] 8004090: 685b ldr r3, [r3, #4] 8004092: f003 0203 and.w r2, r3, #3 8004096: 697b ldr r3, [r7, #20] 8004098: 005b lsls r3, r3, #1 800409a: fa02 f303 lsl.w r3, r2, r3 800409e: 693a ldr r2, [r7, #16] 80040a0: 4313 orrs r3, r2 80040a2: 613b str r3, [r7, #16] GPIOx->MODER = temp; 80040a4: 687b ldr r3, [r7, #4] 80040a6: 693a ldr r2, [r7, #16] 80040a8: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) 80040aa: 683b ldr r3, [r7, #0] 80040ac: 685b ldr r3, [r3, #4] 80040ae: f403 3340 and.w r3, r3, #196608 @ 0x30000 80040b2: 2b00 cmp r3, #0 80040b4: f000 80a6 beq.w 8004204 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 80040b8: 4b5b ldr r3, [pc, #364] @ (8004228 ) 80040ba: 6e1b ldr r3, [r3, #96] @ 0x60 80040bc: 4a5a ldr r2, [pc, #360] @ (8004228 ) 80040be: f043 0301 orr.w r3, r3, #1 80040c2: 6613 str r3, [r2, #96] @ 0x60 80040c4: 4b58 ldr r3, [pc, #352] @ (8004228 ) 80040c6: 6e1b ldr r3, [r3, #96] @ 0x60 80040c8: f003 0301 and.w r3, r3, #1 80040cc: 60bb str r3, [r7, #8] 80040ce: 68bb ldr r3, [r7, #8] temp = SYSCFG->EXTICR[position >> 2U]; 80040d0: 4a56 ldr r2, [pc, #344] @ (800422c ) 80040d2: 697b ldr r3, [r7, #20] 80040d4: 089b lsrs r3, r3, #2 80040d6: 3302 adds r3, #2 80040d8: f852 3023 ldr.w r3, [r2, r3, lsl #2] 80040dc: 613b str r3, [r7, #16] temp &= ~(0x0FUL << (4U * (position & 0x03U))); 80040de: 697b ldr r3, [r7, #20] 80040e0: f003 0303 and.w r3, r3, #3 80040e4: 009b lsls r3, r3, #2 80040e6: 220f movs r2, #15 80040e8: fa02 f303 lsl.w r3, r2, r3 80040ec: 43db mvns r3, r3 80040ee: 693a ldr r2, [r7, #16] 80040f0: 4013 ands r3, r2 80040f2: 613b str r3, [r7, #16] temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); 80040f4: 687b ldr r3, [r7, #4] 80040f6: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000 80040fa: d01f beq.n 800413c 80040fc: 687b ldr r3, [r7, #4] 80040fe: 4a4c ldr r2, [pc, #304] @ (8004230 ) 8004100: 4293 cmp r3, r2 8004102: d019 beq.n 8004138 8004104: 687b ldr r3, [r7, #4] 8004106: 4a4b ldr r2, [pc, #300] @ (8004234 ) 8004108: 4293 cmp r3, r2 800410a: d013 beq.n 8004134 800410c: 687b ldr r3, [r7, #4] 800410e: 4a4a ldr r2, [pc, #296] @ (8004238 ) 8004110: 4293 cmp r3, r2 8004112: d00d beq.n 8004130 8004114: 687b ldr r3, [r7, #4] 8004116: 4a49 ldr r2, [pc, #292] @ (800423c ) 8004118: 4293 cmp r3, r2 800411a: d007 beq.n 800412c 800411c: 687b ldr r3, [r7, #4] 800411e: 4a48 ldr r2, [pc, #288] @ (8004240 ) 8004120: 4293 cmp r3, r2 8004122: d101 bne.n 8004128 8004124: 2305 movs r3, #5 8004126: e00a b.n 800413e 8004128: 2306 movs r3, #6 800412a: e008 b.n 800413e 800412c: 2304 movs r3, #4 800412e: e006 b.n 800413e 8004130: 2303 movs r3, #3 8004132: e004 b.n 800413e 8004134: 2302 movs r3, #2 8004136: e002 b.n 800413e 8004138: 2301 movs r3, #1 800413a: e000 b.n 800413e 800413c: 2300 movs r3, #0 800413e: 697a ldr r2, [r7, #20] 8004140: f002 0203 and.w r2, r2, #3 8004144: 0092 lsls r2, r2, #2 8004146: 4093 lsls r3, r2 8004148: 693a ldr r2, [r7, #16] 800414a: 4313 orrs r3, r2 800414c: 613b str r3, [r7, #16] SYSCFG->EXTICR[position >> 2U] = temp; 800414e: 4937 ldr r1, [pc, #220] @ (800422c ) 8004150: 697b ldr r3, [r7, #20] 8004152: 089b lsrs r3, r3, #2 8004154: 3302 adds r3, #2 8004156: 693a ldr r2, [r7, #16] 8004158: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; 800415c: 4b39 ldr r3, [pc, #228] @ (8004244 ) 800415e: 689b ldr r3, [r3, #8] 8004160: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8004162: 68fb ldr r3, [r7, #12] 8004164: 43db mvns r3, r3 8004166: 693a ldr r2, [r7, #16] 8004168: 4013 ands r3, r2 800416a: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) 800416c: 683b ldr r3, [r7, #0] 800416e: 685b ldr r3, [r3, #4] 8004170: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8004174: 2b00 cmp r3, #0 8004176: d003 beq.n 8004180 { temp |= iocurrent; 8004178: 693a ldr r2, [r7, #16] 800417a: 68fb ldr r3, [r7, #12] 800417c: 4313 orrs r3, r2 800417e: 613b str r3, [r7, #16] } EXTI->RTSR1 = temp; 8004180: 4a30 ldr r2, [pc, #192] @ (8004244 ) 8004182: 693b ldr r3, [r7, #16] 8004184: 6093 str r3, [r2, #8] temp = EXTI->FTSR1; 8004186: 4b2f ldr r3, [pc, #188] @ (8004244 ) 8004188: 68db ldr r3, [r3, #12] 800418a: 613b str r3, [r7, #16] temp &= ~(iocurrent); 800418c: 68fb ldr r3, [r7, #12] 800418e: 43db mvns r3, r3 8004190: 693a ldr r2, [r7, #16] 8004192: 4013 ands r3, r2 8004194: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) 8004196: 683b ldr r3, [r7, #0] 8004198: 685b ldr r3, [r3, #4] 800419a: f403 1300 and.w r3, r3, #2097152 @ 0x200000 800419e: 2b00 cmp r3, #0 80041a0: d003 beq.n 80041aa { temp |= iocurrent; 80041a2: 693a ldr r2, [r7, #16] 80041a4: 68fb ldr r3, [r7, #12] 80041a6: 4313 orrs r3, r2 80041a8: 613b str r3, [r7, #16] } EXTI->FTSR1 = temp; 80041aa: 4a26 ldr r2, [pc, #152] @ (8004244 ) 80041ac: 693b ldr r3, [r7, #16] 80041ae: 60d3 str r3, [r2, #12] temp = EXTI->EMR1; 80041b0: 4b24 ldr r3, [pc, #144] @ (8004244 ) 80041b2: 685b ldr r3, [r3, #4] 80041b4: 613b str r3, [r7, #16] temp &= ~(iocurrent); 80041b6: 68fb ldr r3, [r7, #12] 80041b8: 43db mvns r3, r3 80041ba: 693a ldr r2, [r7, #16] 80041bc: 4013 ands r3, r2 80041be: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) 80041c0: 683b ldr r3, [r7, #0] 80041c2: 685b ldr r3, [r3, #4] 80041c4: f403 3300 and.w r3, r3, #131072 @ 0x20000 80041c8: 2b00 cmp r3, #0 80041ca: d003 beq.n 80041d4 { temp |= iocurrent; 80041cc: 693a ldr r2, [r7, #16] 80041ce: 68fb ldr r3, [r7, #12] 80041d0: 4313 orrs r3, r2 80041d2: 613b str r3, [r7, #16] } EXTI->EMR1 = temp; 80041d4: 4a1b ldr r2, [pc, #108] @ (8004244 ) 80041d6: 693b ldr r3, [r7, #16] 80041d8: 6053 str r3, [r2, #4] /* Clear EXTI line configuration */ temp = EXTI->IMR1; 80041da: 4b1a ldr r3, [pc, #104] @ (8004244 ) 80041dc: 681b ldr r3, [r3, #0] 80041de: 613b str r3, [r7, #16] temp &= ~(iocurrent); 80041e0: 68fb ldr r3, [r7, #12] 80041e2: 43db mvns r3, r3 80041e4: 693a ldr r2, [r7, #16] 80041e6: 4013 ands r3, r2 80041e8: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) 80041ea: 683b ldr r3, [r7, #0] 80041ec: 685b ldr r3, [r3, #4] 80041ee: f403 3380 and.w r3, r3, #65536 @ 0x10000 80041f2: 2b00 cmp r3, #0 80041f4: d003 beq.n 80041fe { temp |= iocurrent; 80041f6: 693a ldr r2, [r7, #16] 80041f8: 68fb ldr r3, [r7, #12] 80041fa: 4313 orrs r3, r2 80041fc: 613b str r3, [r7, #16] } EXTI->IMR1 = temp; 80041fe: 4a11 ldr r2, [pc, #68] @ (8004244 ) 8004200: 693b ldr r3, [r7, #16] 8004202: 6013 str r3, [r2, #0] } } position++; 8004204: 697b ldr r3, [r7, #20] 8004206: 3301 adds r3, #1 8004208: 617b str r3, [r7, #20] while (((GPIO_Init->Pin) >> position) != 0U) 800420a: 683b ldr r3, [r7, #0] 800420c: 681a ldr r2, [r3, #0] 800420e: 697b ldr r3, [r7, #20] 8004210: fa22 f303 lsr.w r3, r2, r3 8004214: 2b00 cmp r3, #0 8004216: f47f ae9d bne.w 8003f54 } } 800421a: bf00 nop 800421c: bf00 nop 800421e: 371c adds r7, #28 8004220: 46bd mov sp, r7 8004222: f85d 7b04 ldr.w r7, [sp], #4 8004226: 4770 bx lr 8004228: 40021000 .word 0x40021000 800422c: 40010000 .word 0x40010000 8004230: 48000400 .word 0x48000400 8004234: 48000800 .word 0x48000800 8004238: 48000c00 .word 0x48000c00 800423c: 48001000 .word 0x48001000 8004240: 48001400 .word 0x48001400 8004244: 40010400 .word 0x40010400 08004248 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8004248: b480 push {r7} 800424a: b083 sub sp, #12 800424c: af00 add r7, sp, #0 800424e: 6078 str r0, [r7, #4] 8004250: 460b mov r3, r1 8004252: 807b strh r3, [r7, #2] 8004254: 4613 mov r3, r2 8004256: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 8004258: 787b ldrb r3, [r7, #1] 800425a: 2b00 cmp r3, #0 800425c: d003 beq.n 8004266 { GPIOx->BSRR = (uint32_t)GPIO_Pin; 800425e: 887a ldrh r2, [r7, #2] 8004260: 687b ldr r3, [r7, #4] 8004262: 619a str r2, [r3, #24] } else { GPIOx->BRR = (uint32_t)GPIO_Pin; } } 8004264: e002 b.n 800426c GPIOx->BRR = (uint32_t)GPIO_Pin; 8004266: 887a ldrh r2, [r7, #2] 8004268: 687b ldr r3, [r7, #4] 800426a: 629a str r2, [r3, #40] @ 0x28 } 800426c: bf00 nop 800426e: 370c adds r7, #12 8004270: 46bd mov sp, r7 8004272: f85d 7b04 ldr.w r7, [sp], #4 8004276: 4770 bx lr 08004278 : * @brief Initialize a HRTIM instance * @param hhrtim pointer to HAL HRTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef *hhrtim) { 8004278: b580 push {r7, lr} 800427a: b086 sub sp, #24 800427c: af00 add r7, sp, #0 800427e: 6078 str r0, [r7, #4] uint8_t timer_idx; uint32_t hrtim_mcr; /* Check the HRTIM handle allocation */ if (hhrtim == NULL) 8004280: 687b ldr r3, [r7, #4] 8004282: 2b00 cmp r3, #0 8004284: d101 bne.n 800428a { return HAL_ERROR; 8004286: 2301 movs r3, #1 8004288: e0be b.n 8004408 } } #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ /* Set the HRTIM state */ hhrtim->State = HAL_HRTIM_STATE_BUSY; 800428a: 687b ldr r3, [r7, #4] 800428c: 2202 movs r2, #2 800428e: f883 20dd strb.w r2, [r3, #221] @ 0xdd /* Initialize the DMA handles */ hhrtim->hdmaMaster = (DMA_HandleTypeDef *)NULL; 8004292: 687b ldr r3, [r7, #4] 8004294: 2200 movs r2, #0 8004296: f8c3 20e0 str.w r2, [r3, #224] @ 0xe0 hhrtim->hdmaTimerA = (DMA_HandleTypeDef *)NULL; 800429a: 687b ldr r3, [r7, #4] 800429c: 2200 movs r2, #0 800429e: f8c3 20e4 str.w r2, [r3, #228] @ 0xe4 hhrtim->hdmaTimerB = (DMA_HandleTypeDef *)NULL; 80042a2: 687b ldr r3, [r7, #4] 80042a4: 2200 movs r2, #0 80042a6: f8c3 20e8 str.w r2, [r3, #232] @ 0xe8 hhrtim->hdmaTimerC = (DMA_HandleTypeDef *)NULL; 80042aa: 687b ldr r3, [r7, #4] 80042ac: 2200 movs r2, #0 80042ae: f8c3 20ec str.w r2, [r3, #236] @ 0xec hhrtim->hdmaTimerD = (DMA_HandleTypeDef *)NULL; 80042b2: 687b ldr r3, [r7, #4] 80042b4: 2200 movs r2, #0 80042b6: f8c3 20f0 str.w r2, [r3, #240] @ 0xf0 hhrtim->hdmaTimerE = (DMA_HandleTypeDef *)NULL; 80042ba: 687b ldr r3, [r7, #4] 80042bc: 2200 movs r2, #0 80042be: f8c3 20f4 str.w r2, [r3, #244] @ 0xf4 hhrtim->hdmaTimerF = (DMA_HandleTypeDef *)NULL; 80042c2: 687b ldr r3, [r7, #4] 80042c4: 2200 movs r2, #0 80042c6: f8c3 20f8 str.w r2, [r3, #248] @ 0xf8 /* HRTIM output synchronization configuration (if required) */ if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_MASTER) != (uint32_t)RESET) 80042ca: 687b ldr r3, [r7, #4] 80042cc: 689b ldr r3, [r3, #8] 80042ce: f003 0301 and.w r3, r3, #1 80042d2: 2b00 cmp r3, #0 80042d4: d02e beq.n 8004334 assert_param(IS_HRTIM_SYNCOUTPUTPOLARITY(hhrtim->Init.SyncOutputPolarity)); /* The synchronization output initialization procedure must be done prior to the configuration of the MCU outputs (done within HAL_HRTIM_MspInit) */ if (hhrtim->Instance == HRTIM1) 80042d6: 687b ldr r3, [r7, #4] 80042d8: 681b ldr r3, [r3, #0] 80042da: 4a4d ldr r2, [pc, #308] @ (8004410 ) 80042dc: 4293 cmp r3, r2 80042de: d10b bne.n 80042f8 { /* Enable the HRTIM peripheral clock */ __HAL_RCC_HRTIM1_CLK_ENABLE(); 80042e0: 4b4c ldr r3, [pc, #304] @ (8004414 ) 80042e2: 6e1b ldr r3, [r3, #96] @ 0x60 80042e4: 4a4b ldr r2, [pc, #300] @ (8004414 ) 80042e6: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 80042ea: 6613 str r3, [r2, #96] @ 0x60 80042ec: 4b49 ldr r3, [pc, #292] @ (8004414 ) 80042ee: 6e1b ldr r3, [r3, #96] @ 0x60 80042f0: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 80042f4: 60fb str r3, [r7, #12] 80042f6: 68fb ldr r3, [r7, #12] } hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR; 80042f8: 687b ldr r3, [r7, #4] 80042fa: 681b ldr r3, [r3, #0] 80042fc: 681b ldr r3, [r3, #0] 80042fe: 613b str r3, [r7, #16] /* Set the event to be sent on the synchronization output */ hrtim_mcr &= ~(HRTIM_MCR_SYNC_SRC); 8004300: 693b ldr r3, [r7, #16] 8004302: f423 4340 bic.w r3, r3, #49152 @ 0xc000 8004306: 613b str r3, [r7, #16] hrtim_mcr |= (hhrtim->Init.SyncOutputSource & HRTIM_MCR_SYNC_SRC); 8004308: 687b ldr r3, [r7, #4] 800430a: 691b ldr r3, [r3, #16] 800430c: f403 4340 and.w r3, r3, #49152 @ 0xc000 8004310: 693a ldr r2, [r7, #16] 8004312: 4313 orrs r3, r2 8004314: 613b str r3, [r7, #16] /* Set the polarity of the synchronization output */ hrtim_mcr &= ~(HRTIM_MCR_SYNC_OUT); 8004316: 693b ldr r3, [r7, #16] 8004318: f423 5340 bic.w r3, r3, #12288 @ 0x3000 800431c: 613b str r3, [r7, #16] hrtim_mcr |= (hhrtim->Init.SyncOutputPolarity & HRTIM_MCR_SYNC_OUT); 800431e: 687b ldr r3, [r7, #4] 8004320: 695b ldr r3, [r3, #20] 8004322: f403 5340 and.w r3, r3, #12288 @ 0x3000 8004326: 693a ldr r2, [r7, #16] 8004328: 4313 orrs r3, r2 800432a: 613b str r3, [r7, #16] /* Update the HRTIM registers */ hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr; 800432c: 687b ldr r3, [r7, #4] 800432e: 681b ldr r3, [r3, #0] 8004330: 693a ldr r2, [r7, #16] 8004332: 601a str r2, [r3, #0] /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) hhrtim->MspInitCallback(hhrtim); #else HAL_HRTIM_MspInit(hhrtim); 8004334: 6878 ldr r0, [r7, #4] 8004336: f7fd f8bf bl 80014b8 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ /* HRTIM input synchronization configuration (if required) */ if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_SLAVE) != (uint32_t)RESET) 800433a: 687b ldr r3, [r7, #4] 800433c: 689b ldr r3, [r3, #8] 800433e: f003 0302 and.w r3, r3, #2 8004342: 2b00 cmp r3, #0 8004344: d012 beq.n 800436c { /* Check parameters */ assert_param(IS_HRTIM_SYNCINPUTSOURCE(hhrtim->Init.SyncInputSource)); hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR; 8004346: 687b ldr r3, [r7, #4] 8004348: 681b ldr r3, [r3, #0] 800434a: 681b ldr r3, [r3, #0] 800434c: 613b str r3, [r7, #16] /* Set the synchronization input source */ hrtim_mcr &= ~(HRTIM_MCR_SYNC_IN); 800434e: 693b ldr r3, [r7, #16] 8004350: f423 7340 bic.w r3, r3, #768 @ 0x300 8004354: 613b str r3, [r7, #16] hrtim_mcr |= (hhrtim->Init.SyncInputSource & HRTIM_MCR_SYNC_IN); 8004356: 687b ldr r3, [r7, #4] 8004358: 68db ldr r3, [r3, #12] 800435a: f403 7340 and.w r3, r3, #768 @ 0x300 800435e: 693a ldr r2, [r7, #16] 8004360: 4313 orrs r3, r2 8004362: 613b str r3, [r7, #16] /* Update the HRTIM registers */ hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr; 8004364: 687b ldr r3, [r7, #4] 8004366: 681b ldr r3, [r3, #0] 8004368: 693a ldr r2, [r7, #16] 800436a: 601a str r2, [r3, #0] } /* Initialize the HRTIM state*/ hhrtim->State = HAL_HRTIM_STATE_READY; 800436c: 687b ldr r3, [r7, #4] 800436e: 2201 movs r2, #1 8004370: f883 20dd strb.w r2, [r3, #221] @ 0xdd /* Initialize the lock status of the HRTIM HAL API */ __HAL_UNLOCK(hhrtim); 8004374: 687b ldr r3, [r7, #4] 8004376: 2200 movs r2, #0 8004378: f883 20dc strb.w r2, [r3, #220] @ 0xdc /* Initialize timer related parameters */ for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ; 800437c: 2300 movs r3, #0 800437e: 75fb strb r3, [r7, #23] 8004380: e03e b.n 8004400 timer_idx <= HRTIM_TIMERINDEX_MASTER ; timer_idx++) { hhrtim->TimerParam[timer_idx].CaptureTrigger1 = HRTIM_CAPTURETRIGGER_NONE; 8004382: 7dfa ldrb r2, [r7, #23] 8004384: 6879 ldr r1, [r7, #4] 8004386: 4613 mov r3, r2 8004388: 00db lsls r3, r3, #3 800438a: 1a9b subs r3, r3, r2 800438c: 009b lsls r3, r3, #2 800438e: 440b add r3, r1 8004390: 3318 adds r3, #24 8004392: 2200 movs r2, #0 8004394: 601a str r2, [r3, #0] hhrtim->TimerParam[timer_idx].CaptureTrigger2 = HRTIM_CAPTURETRIGGER_NONE; 8004396: 7dfa ldrb r2, [r7, #23] 8004398: 6879 ldr r1, [r7, #4] 800439a: 4613 mov r3, r2 800439c: 00db lsls r3, r3, #3 800439e: 1a9b subs r3, r3, r2 80043a0: 009b lsls r3, r3, #2 80043a2: 440b add r3, r1 80043a4: 331c adds r3, #28 80043a6: 2200 movs r2, #0 80043a8: 601a str r2, [r3, #0] hhrtim->TimerParam[timer_idx].InterruptRequests = HRTIM_IT_NONE; 80043aa: 7dfa ldrb r2, [r7, #23] 80043ac: 6879 ldr r1, [r7, #4] 80043ae: 4613 mov r3, r2 80043b0: 00db lsls r3, r3, #3 80043b2: 1a9b subs r3, r3, r2 80043b4: 009b lsls r3, r3, #2 80043b6: 440b add r3, r1 80043b8: 3320 adds r3, #32 80043ba: 2200 movs r2, #0 80043bc: 601a str r2, [r3, #0] hhrtim->TimerParam[timer_idx].DMARequests = HRTIM_IT_NONE; 80043be: 7dfa ldrb r2, [r7, #23] 80043c0: 6879 ldr r1, [r7, #4] 80043c2: 4613 mov r3, r2 80043c4: 00db lsls r3, r3, #3 80043c6: 1a9b subs r3, r3, r2 80043c8: 009b lsls r3, r3, #2 80043ca: 440b add r3, r1 80043cc: 3324 adds r3, #36 @ 0x24 80043ce: 2200 movs r2, #0 80043d0: 601a str r2, [r3, #0] hhrtim->TimerParam[timer_idx].DMASrcAddress = 0U; 80043d2: 7dfa ldrb r2, [r7, #23] 80043d4: 6879 ldr r1, [r7, #4] 80043d6: 4613 mov r3, r2 80043d8: 00db lsls r3, r3, #3 80043da: 1a9b subs r3, r3, r2 80043dc: 009b lsls r3, r3, #2 80043de: 440b add r3, r1 80043e0: 3328 adds r3, #40 @ 0x28 80043e2: 2200 movs r2, #0 80043e4: 601a str r2, [r3, #0] hhrtim->TimerParam[timer_idx].DMASize = 0U; 80043e6: 7dfa ldrb r2, [r7, #23] 80043e8: 6879 ldr r1, [r7, #4] 80043ea: 4613 mov r3, r2 80043ec: 00db lsls r3, r3, #3 80043ee: 1a9b subs r3, r3, r2 80043f0: 009b lsls r3, r3, #2 80043f2: 440b add r3, r1 80043f4: 3330 adds r3, #48 @ 0x30 80043f6: 2200 movs r2, #0 80043f8: 601a str r2, [r3, #0] timer_idx++) 80043fa: 7dfb ldrb r3, [r7, #23] 80043fc: 3301 adds r3, #1 80043fe: 75fb strb r3, [r7, #23] timer_idx <= HRTIM_TIMERINDEX_MASTER ; 8004400: 7dfb ldrb r3, [r7, #23] 8004402: 2b06 cmp r3, #6 8004404: d9bd bls.n 8004382 } return HAL_OK; 8004406: 2300 movs r3, #0 } 8004408: 4618 mov r0, r3 800440a: 3718 adds r7, #24 800440c: 46bd mov sp, r7 800440e: bd80 pop {r7, pc} 8004410: 40016800 .word 0x40016800 8004414: 40021000 .word 0x40021000 08004418 : * within the HAL_HRTIM_PollForDLLCalibration function, just before * exiting the function. */ HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef *hhrtim, uint32_t CalibrationRate) { 8004418: b480 push {r7} 800441a: b083 sub sp, #12 800441c: af00 add r7, sp, #0 800441e: 6078 str r0, [r7, #4] 8004420: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_HRTIM_CALIBRATIONRATE(CalibrationRate)); /* Process Locked */ __HAL_LOCK(hhrtim); 8004422: 687b ldr r3, [r7, #4] 8004424: f893 30dc ldrb.w r3, [r3, #220] @ 0xdc 8004428: 2b01 cmp r3, #1 800442a: d101 bne.n 8004430 800442c: 2302 movs r3, #2 800442e: e045 b.n 80044bc 8004430: 687b ldr r3, [r7, #4] 8004432: 2201 movs r2, #1 8004434: f883 20dc strb.w r2, [r3, #220] @ 0xdc hhrtim->State = HAL_HRTIM_STATE_BUSY; 8004438: 687b ldr r3, [r7, #4] 800443a: 2202 movs r2, #2 800443c: f883 20dd strb.w r2, [r3, #221] @ 0xdd if (CalibrationRate == HRTIM_SINGLE_CALIBRATION) 8004440: 683b ldr r3, [r7, #0] 8004442: f1b3 3fff cmp.w r3, #4294967295 8004446: d114 bne.n 8004472 { /* One shot DLL calibration */ CLEAR_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALEN); 8004448: 687b ldr r3, [r7, #4] 800444a: 681b ldr r3, [r3, #0] 800444c: f8d3 23cc ldr.w r2, [r3, #972] @ 0x3cc 8004450: 687b ldr r3, [r7, #4] 8004452: 681b ldr r3, [r3, #0] 8004454: f022 0202 bic.w r2, r2, #2 8004458: f8c3 23cc str.w r2, [r3, #972] @ 0x3cc SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL); 800445c: 687b ldr r3, [r7, #4] 800445e: 681b ldr r3, [r3, #0] 8004460: f8d3 23cc ldr.w r2, [r3, #972] @ 0x3cc 8004464: 687b ldr r3, [r7, #4] 8004466: 681b ldr r3, [r3, #0] 8004468: f042 0201 orr.w r2, r2, #1 800446c: f8c3 23cc str.w r2, [r3, #972] @ 0x3cc 8004470: e01f b.n 80044b2 } else { /* Periodic DLL calibration */ SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALEN); 8004472: 687b ldr r3, [r7, #4] 8004474: 681b ldr r3, [r3, #0] 8004476: f8d3 23cc ldr.w r2, [r3, #972] @ 0x3cc 800447a: 687b ldr r3, [r7, #4] 800447c: 681b ldr r3, [r3, #0] 800447e: f042 0202 orr.w r2, r2, #2 8004482: f8c3 23cc str.w r2, [r3, #972] @ 0x3cc MODIFY_REG(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALRTE, CalibrationRate); 8004486: 687b ldr r3, [r7, #4] 8004488: 681b ldr r3, [r3, #0] 800448a: f8d3 33cc ldr.w r3, [r3, #972] @ 0x3cc 800448e: f023 010c bic.w r1, r3, #12 8004492: 687b ldr r3, [r7, #4] 8004494: 681b ldr r3, [r3, #0] 8004496: 683a ldr r2, [r7, #0] 8004498: 430a orrs r2, r1 800449a: f8c3 23cc str.w r2, [r3, #972] @ 0x3cc SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL); 800449e: 687b ldr r3, [r7, #4] 80044a0: 681b ldr r3, [r3, #0] 80044a2: f8d3 23cc ldr.w r2, [r3, #972] @ 0x3cc 80044a6: 687b ldr r3, [r7, #4] 80044a8: 681b ldr r3, [r3, #0] 80044aa: f042 0201 orr.w r2, r2, #1 80044ae: f8c3 23cc str.w r2, [r3, #972] @ 0x3cc } /* Set HRTIM state */ hhrtim->State = HAL_HRTIM_STATE_READY; 80044b2: 687b ldr r3, [r7, #4] 80044b4: 2201 movs r2, #1 80044b6: f883 20dd strb.w r2, [r3, #221] @ 0xdd return HAL_OK; 80044ba: 2300 movs r3, #0 } 80044bc: 4618 mov r0, r3 80044be: 370c adds r7, #12 80044c0: 46bd mov sp, r7 80044c2: f85d 7b04 ldr.w r7, [sp], #4 80044c6: 4770 bx lr 080044c8 : * @param Timeout Timeout duration in millisecond * @retval HAL status */ HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef *hhrtim, uint32_t Timeout) { 80044c8: b580 push {r7, lr} 80044ca: b084 sub sp, #16 80044cc: af00 add r7, sp, #0 80044ce: 6078 str r0, [r7, #4] 80044d0: 6039 str r1, [r7, #0] uint32_t tickstart; tickstart = HAL_GetTick(); 80044d2: f7fd f9eb bl 80018ac 80044d6: 60f8 str r0, [r7, #12] /* Check End of conversion flag */ while (__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_IT_DLLRDY) == (uint32_t)RESET) 80044d8: e014 b.n 8004504 { if (Timeout != HAL_MAX_DELAY) 80044da: 683b ldr r3, [r7, #0] 80044dc: f1b3 3fff cmp.w r3, #4294967295 80044e0: d010 beq.n 8004504 { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) 80044e2: f7fd f9e3 bl 80018ac 80044e6: 4602 mov r2, r0 80044e8: 68fb ldr r3, [r7, #12] 80044ea: 1ad3 subs r3, r2, r3 80044ec: 683a ldr r2, [r7, #0] 80044ee: 429a cmp r2, r3 80044f0: d302 bcc.n 80044f8 80044f2: 683b ldr r3, [r7, #0] 80044f4: 2b00 cmp r3, #0 80044f6: d105 bne.n 8004504 { hhrtim->State = HAL_HRTIM_STATE_ERROR; 80044f8: 687b ldr r3, [r7, #4] 80044fa: 2207 movs r2, #7 80044fc: f883 20dd strb.w r2, [r3, #221] @ 0xdd return HAL_TIMEOUT; 8004500: 2303 movs r3, #3 8004502: e011 b.n 8004528 while (__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_IT_DLLRDY) == (uint32_t)RESET) 8004504: 687b ldr r3, [r7, #4] 8004506: 681b ldr r3, [r3, #0] 8004508: f8d3 3388 ldr.w r3, [r3, #904] @ 0x388 800450c: f403 3380 and.w r3, r3, #65536 @ 0x10000 8004510: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8004514: d1e1 bne.n 80044da } } } /* Set HRTIM State */ hhrtim->State = HAL_HRTIM_STATE_READY; 8004516: 687b ldr r3, [r7, #4] 8004518: 2201 movs r2, #1 800451a: f883 20dd strb.w r2, [r3, #221] @ 0xdd /* Process unlocked */ __HAL_UNLOCK(hhrtim); 800451e: 687b ldr r3, [r7, #4] 8004520: 2200 movs r2, #0 8004522: f883 20dc strb.w r2, [r3, #220] @ 0xdc return HAL_OK; 8004526: 2300 movs r3, #0 } 8004528: 4618 mov r0, r3 800452a: 3710 adds r7, #16 800452c: 46bd mov sp, r7 800452e: bd80 pop {r7, pc} 08004530 : * @retval HAL status */ HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg) { 8004530: b580 push {r7, lr} 8004532: b084 sub sp, #16 8004534: af00 add r7, sp, #0 8004536: 60f8 str r0, [r7, #12] 8004538: 60b9 str r1, [r7, #8] 800453a: 607a str r2, [r7, #4] /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); assert_param(IS_HRTIM_PRESCALERRATIO(pTimeBaseCfg->PrescalerRatio)); assert_param(IS_HRTIM_MODE(pTimeBaseCfg->Mode)); if (hhrtim->State == HAL_HRTIM_STATE_BUSY) 800453c: 68fb ldr r3, [r7, #12] 800453e: f893 30dd ldrb.w r3, [r3, #221] @ 0xdd 8004542: b2db uxtb r3, r3 8004544: 2b02 cmp r3, #2 8004546: d101 bne.n 800454c { return HAL_BUSY; 8004548: 2302 movs r3, #2 800454a: e015 b.n 8004578 } /* Set the HRTIM state */ hhrtim->State = HAL_HRTIM_STATE_BUSY; 800454c: 68fb ldr r3, [r7, #12] 800454e: 2202 movs r2, #2 8004550: f883 20dd strb.w r2, [r3, #221] @ 0xdd if (TimerIdx == HRTIM_TIMERINDEX_MASTER) 8004554: 68bb ldr r3, [r7, #8] 8004556: 2b06 cmp r3, #6 8004558: d104 bne.n 8004564 { /* Configure master timer time base unit */ HRTIM_MasterBase_Config(hhrtim, pTimeBaseCfg); 800455a: 6879 ldr r1, [r7, #4] 800455c: 68f8 ldr r0, [r7, #12] 800455e: f000 fb5b bl 8004c18 8004562: e004 b.n 800456e } else { /* Configure timing unit time base unit */ HRTIM_TimingUnitBase_Config(hhrtim, TimerIdx, pTimeBaseCfg); 8004564: 687a ldr r2, [r7, #4] 8004566: 68b9 ldr r1, [r7, #8] 8004568: 68f8 ldr r0, [r7, #12] 800456a: f000 fb84 bl 8004c76 } /* Set HRTIM state */ hhrtim->State = HAL_HRTIM_STATE_READY; 800456e: 68fb ldr r3, [r7, #12] 8004570: 2201 movs r2, #1 8004572: f883 20dd strb.w r2, [r3, #221] @ 0xdd return HAL_OK; 8004576: 2300 movs r3, #0 } 8004578: 4618 mov r0, r3 800457a: 3710 adds r7, #16 800457c: 46bd mov sp, r7 800457e: bd80 pop {r7, pc} 08004580 : * @retval HAL status */ HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Event, const HRTIM_EventCfgTypeDef *pEventCfg) { 8004580: b580 push {r7, lr} 8004582: b084 sub sp, #16 8004584: af00 add r7, sp, #0 8004586: 60f8 str r0, [r7, #12] 8004588: 60b9 str r1, [r7, #8] 800458a: 607a str r2, [r7, #4] assert_param(IS_HRTIM_EVENTPOLARITY(pEventCfg->Sensitivity, pEventCfg->Polarity)); assert_param(IS_HRTIM_EVENTSENSITIVITY(pEventCfg->Sensitivity)); assert_param(IS_HRTIM_EVENTFASTMODE(Event, pEventCfg->FastMode)); assert_param(IS_HRTIM_EVENTFILTER(Event, pEventCfg->Filter)); if (hhrtim->State == HAL_HRTIM_STATE_BUSY) 800458c: 68fb ldr r3, [r7, #12] 800458e: f893 30dd ldrb.w r3, [r3, #221] @ 0xdd 8004592: b2db uxtb r3, r3 8004594: 2b02 cmp r3, #2 8004596: d101 bne.n 800459c { return HAL_BUSY; 8004598: 2302 movs r3, #2 800459a: e01c b.n 80045d6 } /* Process Locked */ __HAL_LOCK(hhrtim); 800459c: 68fb ldr r3, [r7, #12] 800459e: f893 30dc ldrb.w r3, [r3, #220] @ 0xdc 80045a2: 2b01 cmp r3, #1 80045a4: d101 bne.n 80045aa 80045a6: 2302 movs r3, #2 80045a8: e015 b.n 80045d6 80045aa: 68fb ldr r3, [r7, #12] 80045ac: 2201 movs r2, #1 80045ae: f883 20dc strb.w r2, [r3, #220] @ 0xdc hhrtim->State = HAL_HRTIM_STATE_BUSY; 80045b2: 68fb ldr r3, [r7, #12] 80045b4: 2202 movs r2, #2 80045b6: f883 20dd strb.w r2, [r3, #221] @ 0xdd /* Configure the event channel */ HRTIM_EventConfig(hhrtim, Event, pEventCfg); 80045ba: 687a ldr r2, [r7, #4] 80045bc: 68b9 ldr r1, [r7, #8] 80045be: 68f8 ldr r0, [r7, #12] 80045c0: f000 ff04 bl 80053cc hhrtim->State = HAL_HRTIM_STATE_READY; 80045c4: 68fb ldr r3, [r7, #12] 80045c6: 2201 movs r2, #1 80045c8: f883 20dd strb.w r2, [r3, #221] @ 0xdd /* Process Unlocked */ __HAL_UNLOCK(hhrtim); 80045cc: 68fb ldr r3, [r7, #12] 80045ce: 2200 movs r2, #0 80045d0: f883 20dc strb.w r2, [r3, #220] @ 0xdc return HAL_OK; 80045d4: 2300 movs r3, #0 } 80045d6: 4618 mov r0, r3 80045d8: 3710 adds r7, #16 80045da: 46bd mov sp, r7 80045dc: bd80 pop {r7, pc} 080045de : * @note This function must be called before starting the timer * @retval HAL status */ HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Prescaler) { 80045de: b480 push {r7} 80045e0: b083 sub sp, #12 80045e2: af00 add r7, sp, #0 80045e4: 6078 str r0, [r7, #4] 80045e6: 6039 str r1, [r7, #0] /* Check parameters */ assert_param(IS_HRTIM_EVENTPRESCALER(Prescaler)); if (hhrtim->State == HAL_HRTIM_STATE_BUSY) 80045e8: 687b ldr r3, [r7, #4] 80045ea: f893 30dd ldrb.w r3, [r3, #221] @ 0xdd 80045ee: b2db uxtb r3, r3 80045f0: 2b02 cmp r3, #2 80045f2: d101 bne.n 80045f8 { return HAL_BUSY; 80045f4: 2302 movs r3, #2 80045f6: e025 b.n 8004644 } /* Process Locked */ __HAL_LOCK(hhrtim); 80045f8: 687b ldr r3, [r7, #4] 80045fa: f893 30dc ldrb.w r3, [r3, #220] @ 0xdc 80045fe: 2b01 cmp r3, #1 8004600: d101 bne.n 8004606 8004602: 2302 movs r3, #2 8004604: e01e b.n 8004644 8004606: 687b ldr r3, [r7, #4] 8004608: 2201 movs r2, #1 800460a: f883 20dc strb.w r2, [r3, #220] @ 0xdc hhrtim->State = HAL_HRTIM_STATE_BUSY; 800460e: 687b ldr r3, [r7, #4] 8004610: 2202 movs r2, #2 8004612: f883 20dd strb.w r2, [r3, #221] @ 0xdd /* Set the external event prescaler */ MODIFY_REG(hhrtim->Instance->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD, (Prescaler & HRTIM_EECR3_EEVSD)); 8004616: 687b ldr r3, [r7, #4] 8004618: 681b ldr r3, [r3, #0] 800461a: f8d3 33b8 ldr.w r3, [r3, #952] @ 0x3b8 800461e: f023 4140 bic.w r1, r3, #3221225472 @ 0xc0000000 8004622: 683b ldr r3, [r7, #0] 8004624: f003 4240 and.w r2, r3, #3221225472 @ 0xc0000000 8004628: 687b ldr r3, [r7, #4] 800462a: 681b ldr r3, [r3, #0] 800462c: 430a orrs r2, r1 800462e: f8c3 23b8 str.w r2, [r3, #952] @ 0x3b8 hhrtim->State = HAL_HRTIM_STATE_READY; 8004632: 687b ldr r3, [r7, #4] 8004634: 2201 movs r2, #1 8004636: f883 20dd strb.w r2, [r3, #221] @ 0xdd /* Process Unlocked */ __HAL_UNLOCK(hhrtim); 800463a: 687b ldr r3, [r7, #4] 800463c: 2200 movs r2, #0 800463e: f883 20dc strb.w r2, [r3, #220] @ 0xdc return HAL_OK; 8004642: 2300 movs r3, #0 } 8004644: 4618 mov r0, r3 8004646: 370c adds r7, #12 8004648: 46bd mov sp, r7 800464a: f85d 7b04 ldr.w r7, [sp], #4 800464e: 4770 bx lr 08004650 : * @note This function must be called before starting the timer */ HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, const HRTIM_TimerCfgTypeDef *pTimerCfg) { 8004650: b580 push {r7, lr} 8004652: b084 sub sp, #16 8004654: af00 add r7, sp, #0 8004656: 60f8 str r0, [r7, #12] 8004658: 60b9 str r1, [r7, #8] 800465a: 607a str r2, [r7, #4] assert_param(IS_HRTIM_DACSYNC(pTimerCfg->DACSynchro)); assert_param(IS_HRTIM_PRELOAD(pTimerCfg->PreloadEnable)); assert_param(IS_HRTIM_TIMERBURSTMODE(pTimerCfg->BurstMode)); assert_param(IS_HRTIM_UPDATEONREPETITION(pTimerCfg->RepetitionUpdate)); if (hhrtim->State == HAL_HRTIM_STATE_BUSY) 800465c: 68fb ldr r3, [r7, #12] 800465e: f893 30dd ldrb.w r3, [r3, #221] @ 0xdd 8004662: b2db uxtb r3, r3 8004664: 2b02 cmp r3, #2 8004666: d101 bne.n 800466c { return HAL_BUSY; 8004668: 2302 movs r3, #2 800466a: e07a b.n 8004762 } /* Process Locked */ __HAL_LOCK(hhrtim); 800466c: 68fb ldr r3, [r7, #12] 800466e: f893 30dc ldrb.w r3, [r3, #220] @ 0xdc 8004672: 2b01 cmp r3, #1 8004674: d101 bne.n 800467a 8004676: 2302 movs r3, #2 8004678: e073 b.n 8004762 800467a: 68fb ldr r3, [r7, #12] 800467c: 2201 movs r2, #1 800467e: f883 20dc strb.w r2, [r3, #220] @ 0xdc hhrtim->State = HAL_HRTIM_STATE_BUSY; 8004682: 68fb ldr r3, [r7, #12] 8004684: 2202 movs r2, #2 8004686: f883 20dd strb.w r2, [r3, #221] @ 0xdd if (TimerIdx == HRTIM_TIMERINDEX_MASTER) 800468a: 68bb ldr r3, [r7, #8] 800468c: 2b06 cmp r3, #6 800468e: d104 bne.n 800469a assert_param(IS_HRTIM_UPDATEGATING_MASTER(pTimerCfg->UpdateGating)); assert_param(IS_HRTIM_MASTER_IT(pTimerCfg->InterruptRequests)); assert_param(IS_HRTIM_MASTER_DMA(pTimerCfg->DMARequests)); /* Configure master timer */ HRTIM_MasterWaveform_Config(hhrtim, pTimerCfg); 8004690: 6879 ldr r1, [r7, #4] 8004692: 68f8 ldr r0, [r7, #12] 8004694: f000 fb2f bl 8004cf6 8004698: e004 b.n 80046a4 assert_param(IS_HRTIM_TIMRESETTRIGGER(pTimerCfg->ResetTrigger)); assert_param(IS_HRTIM_TIMUPDATEONRESET(pTimerCfg->ResetUpdate)); assert_param(IS_HRTIM_TIMSYNCUPDATE(pTimerCfg->ReSyncUpdate)); /* Configure timing unit */ HRTIM_TimingUnitWaveform_Config(hhrtim, TimerIdx, pTimerCfg); 800469a: 687a ldr r2, [r7, #4] 800469c: 68b9 ldr r1, [r7, #8] 800469e: 68f8 ldr r0, [r7, #12] 80046a0: f000 fbc6 bl 8004e30 } /* Update timer parameters */ hhrtim->TimerParam[TimerIdx].InterruptRequests = pTimerCfg->InterruptRequests; 80046a4: 687b ldr r3, [r7, #4] 80046a6: 6819 ldr r1, [r3, #0] 80046a8: 68f8 ldr r0, [r7, #12] 80046aa: 68ba ldr r2, [r7, #8] 80046ac: 4613 mov r3, r2 80046ae: 00db lsls r3, r3, #3 80046b0: 1a9b subs r3, r3, r2 80046b2: 009b lsls r3, r3, #2 80046b4: 4403 add r3, r0 80046b6: 3320 adds r3, #32 80046b8: 6019 str r1, [r3, #0] hhrtim->TimerParam[TimerIdx].DMARequests = pTimerCfg->DMARequests; 80046ba: 687b ldr r3, [r7, #4] 80046bc: 6859 ldr r1, [r3, #4] 80046be: 68f8 ldr r0, [r7, #12] 80046c0: 68ba ldr r2, [r7, #8] 80046c2: 4613 mov r3, r2 80046c4: 00db lsls r3, r3, #3 80046c6: 1a9b subs r3, r3, r2 80046c8: 009b lsls r3, r3, #2 80046ca: 4403 add r3, r0 80046cc: 3324 adds r3, #36 @ 0x24 80046ce: 6019 str r1, [r3, #0] hhrtim->TimerParam[TimerIdx].DMASrcAddress = pTimerCfg->DMASrcAddress; 80046d0: 687b ldr r3, [r7, #4] 80046d2: 6899 ldr r1, [r3, #8] 80046d4: 68f8 ldr r0, [r7, #12] 80046d6: 68ba ldr r2, [r7, #8] 80046d8: 4613 mov r3, r2 80046da: 00db lsls r3, r3, #3 80046dc: 1a9b subs r3, r3, r2 80046de: 009b lsls r3, r3, #2 80046e0: 4403 add r3, r0 80046e2: 3328 adds r3, #40 @ 0x28 80046e4: 6019 str r1, [r3, #0] hhrtim->TimerParam[TimerIdx].DMADstAddress = pTimerCfg->DMADstAddress; 80046e6: 687b ldr r3, [r7, #4] 80046e8: 68d9 ldr r1, [r3, #12] 80046ea: 68f8 ldr r0, [r7, #12] 80046ec: 68ba ldr r2, [r7, #8] 80046ee: 4613 mov r3, r2 80046f0: 00db lsls r3, r3, #3 80046f2: 1a9b subs r3, r3, r2 80046f4: 009b lsls r3, r3, #2 80046f6: 4403 add r3, r0 80046f8: 332c adds r3, #44 @ 0x2c 80046fa: 6019 str r1, [r3, #0] hhrtim->TimerParam[TimerIdx].DMASize = pTimerCfg->DMASize; 80046fc: 687b ldr r3, [r7, #4] 80046fe: 6919 ldr r1, [r3, #16] 8004700: 68f8 ldr r0, [r7, #12] 8004702: 68ba ldr r2, [r7, #8] 8004704: 4613 mov r3, r2 8004706: 00db lsls r3, r3, #3 8004708: 1a9b subs r3, r3, r2 800470a: 009b lsls r3, r3, #2 800470c: 4403 add r3, r0 800470e: 3330 adds r3, #48 @ 0x30 8004710: 6019 str r1, [r3, #0] /* Force a software update */ HRTIM_ForceRegistersUpdate(hhrtim, TimerIdx); 8004712: 68b9 ldr r1, [r7, #8] 8004714: 68f8 ldr r0, [r7, #12] 8004716: f001 f881 bl 800581c /* Configure slave timer update re-synchronization */ if ((TimerIdx != HRTIM_TIMERINDEX_MASTER) 800471a: 68bb ldr r3, [r7, #8] 800471c: 2b06 cmp r3, #6 800471e: d017 beq.n 8004750 && (pTimerCfg->UpdateGating == HRTIM_UPDATEGATING_INDEPENDENT)) 8004720: 687b ldr r3, [r7, #4] 8004722: 6adb ldr r3, [r3, #44] @ 0x2c 8004724: 2b00 cmp r3, #0 8004726: d113 bne.n 8004750 { MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, 8004728: 68fb ldr r3, [r7, #12] 800472a: 681a ldr r2, [r3, #0] 800472c: 68bb ldr r3, [r7, #8] 800472e: 3301 adds r3, #1 8004730: 01db lsls r3, r3, #7 8004732: 4413 add r3, r2 8004734: 681b ldr r3, [r3, #0] 8004736: f423 7200 bic.w r2, r3, #512 @ 0x200 800473a: 687b ldr r3, [r7, #4] 800473c: 6ddb ldr r3, [r3, #92] @ 0x5c 800473e: 025b lsls r3, r3, #9 8004740: 68f9 ldr r1, [r7, #12] 8004742: 6809 ldr r1, [r1, #0] 8004744: 431a orrs r2, r3 8004746: 68bb ldr r3, [r7, #8] 8004748: 3301 adds r3, #1 800474a: 01db lsls r3, r3, #7 800474c: 440b add r3, r1 800474e: 601a str r2, [r3, #0] HRTIM_TIMCR_RSYNCU_Msk, pTimerCfg->ReSyncUpdate << HRTIM_TIMCR_RSYNCU_Pos); } hhrtim->State = HAL_HRTIM_STATE_READY; 8004750: 68fb ldr r3, [r7, #12] 8004752: 2201 movs r2, #1 8004754: f883 20dd strb.w r2, [r3, #221] @ 0xdd /* Process Unlocked */ __HAL_UNLOCK(hhrtim); 8004758: 68fb ldr r3, [r7, #12] 800475a: 2200 movs r2, #0 800475c: f883 20dc strb.w r2, [r3, #220] @ 0xdc return HAL_OK; 8004760: 2300 movs r3, #0 } 8004762: 4618 mov r0, r3 8004764: 3710 adds r7, #16 8004766: 46bd mov sp, r7 8004768: bd80 pop {r7, pc} 0800476a : * @note This function must be called before starting the timer */ HAL_StatusTypeDef HAL_HRTIM_WaveformTimerControl(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, const HRTIM_TimerCtlTypeDef *pTimerCtl) { 800476a: b580 push {r7, lr} 800476c: b084 sub sp, #16 800476e: af00 add r7, sp, #0 8004770: 60f8 str r0, [r7, #12] 8004772: 60b9 str r1, [r7, #8] 8004774: 607a str r2, [r7, #4] assert_param(IS_HRTIM_TIMERGTCMP1(pTimerCtl->GreaterCMP1)); assert_param(IS_HRTIM_DUALDAC_RESET(pTimerCtl->DualChannelDacReset)); assert_param(IS_HRTIM_DUALDAC_STEP(pTimerCtl->DualChannelDacStep)); assert_param(IS_HRTIM_DUALDAC_ENABLE(pTimerCtl->DualChannelDacEnable)); if (hhrtim->State == HAL_HRTIM_STATE_BUSY) 8004776: 68fb ldr r3, [r7, #12] 8004778: f893 30dd ldrb.w r3, [r3, #221] @ 0xdd 800477c: b2db uxtb r3, r3 800477e: 2b02 cmp r3, #2 8004780: d101 bne.n 8004786 { return HAL_BUSY; 8004782: 2302 movs r3, #2 8004784: e020 b.n 80047c8 } /* Process Locked */ __HAL_LOCK(hhrtim); 8004786: 68fb ldr r3, [r7, #12] 8004788: f893 30dc ldrb.w r3, [r3, #220] @ 0xdc 800478c: 2b01 cmp r3, #1 800478e: d101 bne.n 8004794 8004790: 2302 movs r3, #2 8004792: e019 b.n 80047c8 8004794: 68fb ldr r3, [r7, #12] 8004796: 2201 movs r2, #1 8004798: f883 20dc strb.w r2, [r3, #220] @ 0xdc hhrtim->State = HAL_HRTIM_STATE_BUSY; 800479c: 68fb ldr r3, [r7, #12] 800479e: 2202 movs r2, #2 80047a0: f883 20dd strb.w r2, [r3, #221] @ 0xdd /* Configure timing unit */ HRTIM_TimingUnitWaveform_Control(hhrtim, TimerIdx, pTimerCtl); 80047a4: 687a ldr r2, [r7, #4] 80047a6: 68b9 ldr r1, [r7, #8] 80047a8: 68f8 ldr r0, [r7, #12] 80047aa: f000 fcc7 bl 800513c /* Force a software update */ HRTIM_ForceRegistersUpdate(hhrtim, TimerIdx); 80047ae: 68b9 ldr r1, [r7, #8] 80047b0: 68f8 ldr r0, [r7, #12] 80047b2: f001 f833 bl 800581c hhrtim->State = HAL_HRTIM_STATE_READY; 80047b6: 68fb ldr r3, [r7, #12] 80047b8: 2201 movs r2, #1 80047ba: f883 20dd strb.w r2, [r3, #221] @ 0xdd /* Process Unlocked */ __HAL_UNLOCK(hhrtim); 80047be: 68fb ldr r3, [r7, #12] 80047c0: 2200 movs r2, #0 80047c2: f883 20dc strb.w r2, [r3, #220] @ 0xdc return HAL_OK; 80047c6: 2300 movs r3, #0 } 80047c8: 4618 mov r0, r3 80047ca: 3710 adds r7, #16 80047cc: 46bd mov sp, r7 80047ce: bd80 pop {r7, pc} 080047d0 : */ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CompareUnit, const HRTIM_CompareCfgTypeDef *pCompareCfg) { 80047d0: b480 push {r7} 80047d2: b085 sub sp, #20 80047d4: af00 add r7, sp, #0 80047d6: 60f8 str r0, [r7, #12] 80047d8: 60b9 str r1, [r7, #8] 80047da: 607a str r2, [r7, #4] 80047dc: 603b str r3, [r7, #0] /* Check parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); if (hhrtim->State == HAL_HRTIM_STATE_BUSY) 80047de: 68fb ldr r3, [r7, #12] 80047e0: f893 30dd ldrb.w r3, [r3, #221] @ 0xdd 80047e4: b2db uxtb r3, r3 80047e6: 2b02 cmp r3, #2 80047e8: d101 bne.n 80047ee { return HAL_BUSY; 80047ea: 2302 movs r3, #2 80047ec: e157 b.n 8004a9e } /* Process Locked */ __HAL_LOCK(hhrtim); 80047ee: 68fb ldr r3, [r7, #12] 80047f0: f893 30dc ldrb.w r3, [r3, #220] @ 0xdc 80047f4: 2b01 cmp r3, #1 80047f6: d101 bne.n 80047fc 80047f8: 2302 movs r3, #2 80047fa: e150 b.n 8004a9e 80047fc: 68fb ldr r3, [r7, #12] 80047fe: 2201 movs r2, #1 8004800: f883 20dc strb.w r2, [r3, #220] @ 0xdc hhrtim->State = HAL_HRTIM_STATE_BUSY; 8004804: 68fb ldr r3, [r7, #12] 8004806: 2202 movs r2, #2 8004808: f883 20dd strb.w r2, [r3, #221] @ 0xdd /* Configure the compare unit */ if (TimerIdx == HRTIM_TIMERINDEX_MASTER) 800480c: 68bb ldr r3, [r7, #8] 800480e: 2b06 cmp r3, #6 8004810: d140 bne.n 8004894 { switch (CompareUnit) 8004812: 687b ldr r3, [r7, #4] 8004814: 3b01 subs r3, #1 8004816: 2b07 cmp r3, #7 8004818: d82a bhi.n 8004870 800481a: a201 add r2, pc, #4 @ (adr r2, 8004820 ) 800481c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8004820: 08004841 .word 0x08004841 8004824: 0800484d .word 0x0800484d 8004828: 08004871 .word 0x08004871 800482c: 08004859 .word 0x08004859 8004830: 08004871 .word 0x08004871 8004834: 08004871 .word 0x08004871 8004838: 08004871 .word 0x08004871 800483c: 08004865 .word 0x08004865 { case HRTIM_COMPAREUNIT_1: { hhrtim->Instance->sMasterRegs.MCMP1R = pCompareCfg->CompareValue; 8004840: 68fb ldr r3, [r7, #12] 8004842: 681b ldr r3, [r3, #0] 8004844: 683a ldr r2, [r7, #0] 8004846: 6812 ldr r2, [r2, #0] 8004848: 61da str r2, [r3, #28] break; 800484a: e01a b.n 8004882 } case HRTIM_COMPAREUNIT_2: { hhrtim->Instance->sMasterRegs.MCMP2R = pCompareCfg->CompareValue; 800484c: 68fb ldr r3, [r7, #12] 800484e: 681b ldr r3, [r3, #0] 8004850: 683a ldr r2, [r7, #0] 8004852: 6812 ldr r2, [r2, #0] 8004854: 625a str r2, [r3, #36] @ 0x24 break; 8004856: e014 b.n 8004882 } case HRTIM_COMPAREUNIT_3: { hhrtim->Instance->sMasterRegs.MCMP3R = pCompareCfg->CompareValue; 8004858: 68fb ldr r3, [r7, #12] 800485a: 681b ldr r3, [r3, #0] 800485c: 683a ldr r2, [r7, #0] 800485e: 6812 ldr r2, [r2, #0] 8004860: 629a str r2, [r3, #40] @ 0x28 break; 8004862: e00e b.n 8004882 } case HRTIM_COMPAREUNIT_4: { hhrtim->Instance->sMasterRegs.MCMP4R = pCompareCfg->CompareValue; 8004864: 68fb ldr r3, [r7, #12] 8004866: 681b ldr r3, [r3, #0] 8004868: 683a ldr r2, [r7, #0] 800486a: 6812 ldr r2, [r2, #0] 800486c: 62da str r2, [r3, #44] @ 0x2c break; 800486e: e008 b.n 8004882 } default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; 8004870: 68fb ldr r3, [r7, #12] 8004872: 2207 movs r2, #7 8004874: f883 20dd strb.w r2, [r3, #221] @ 0xdd /* Process Unlocked */ __HAL_UNLOCK(hhrtim); 8004878: 68fb ldr r3, [r7, #12] 800487a: 2200 movs r2, #0 800487c: f883 20dc strb.w r2, [r3, #220] @ 0xdc break; 8004880: bf00 nop } } if (hhrtim->State == HAL_HRTIM_STATE_ERROR) 8004882: 68fb ldr r3, [r7, #12] 8004884: f893 30dd ldrb.w r3, [r3, #221] @ 0xdd 8004888: b2db uxtb r3, r3 800488a: 2b07 cmp r3, #7 800488c: f040 80fe bne.w 8004a8c { return HAL_ERROR; 8004890: 2301 movs r3, #1 8004892: e104 b.n 8004a9e } } else { switch (CompareUnit) 8004894: 687b ldr r3, [r7, #4] 8004896: 3b01 subs r3, #1 8004898: 2b07 cmp r3, #7 800489a: f200 80e3 bhi.w 8004a64 800489e: a201 add r2, pc, #4 @ (adr r2, 80048a4 ) 80048a0: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80048a4: 080048c5 .word 0x080048c5 80048a8: 080048d9 .word 0x080048d9 80048ac: 08004a65 .word 0x08004a65 80048b0: 08004995 .word 0x08004995 80048b4: 08004a65 .word 0x08004a65 80048b8: 08004a65 .word 0x08004a65 80048bc: 08004a65 .word 0x08004a65 80048c0: 080049a9 .word 0x080049a9 { case HRTIM_COMPAREUNIT_1: { /* Set the compare value */ hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->CompareValue; 80048c4: 68fb ldr r3, [r7, #12] 80048c6: 6819 ldr r1, [r3, #0] 80048c8: 683b ldr r3, [r7, #0] 80048ca: 681a ldr r2, [r3, #0] 80048cc: 68bb ldr r3, [r7, #8] 80048ce: 01db lsls r3, r3, #7 80048d0: 440b add r3, r1 80048d2: 339c adds r3, #156 @ 0x9c 80048d4: 601a str r2, [r3, #0] break; 80048d6: e0d1 b.n 8004a7c { /* Check parameters */ assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode)); /* Set the compare value */ hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pCompareCfg->CompareValue; 80048d8: 68fb ldr r3, [r7, #12] 80048da: 6819 ldr r1, [r3, #0] 80048dc: 683b ldr r3, [r7, #0] 80048de: 681a ldr r2, [r3, #0] 80048e0: 68bb ldr r3, [r7, #8] 80048e2: 01db lsls r3, r3, #7 80048e4: 440b add r3, r1 80048e6: 33a4 adds r3, #164 @ 0xa4 80048e8: 601a str r2, [r3, #0] if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR) 80048ea: 683b ldr r3, [r7, #0] 80048ec: 685b ldr r3, [r3, #4] 80048ee: 2b00 cmp r3, #0 80048f0: d03f beq.n 8004972 { /* Configure auto-delayed mode */ /* DELCMP2 bitfield must be reset when reprogrammed from one value */ /* to the other to reinitialize properly the auto-delayed mechanism */ hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP2; 80048f2: 68fb ldr r3, [r7, #12] 80048f4: 681a ldr r2, [r3, #0] 80048f6: 68bb ldr r3, [r7, #8] 80048f8: 3301 adds r3, #1 80048fa: 01db lsls r3, r3, #7 80048fc: 4413 add r3, r2 80048fe: 681b ldr r3, [r3, #0] 8004900: 68fa ldr r2, [r7, #12] 8004902: 6811 ldr r1, [r2, #0] 8004904: f423 5240 bic.w r2, r3, #12288 @ 0x3000 8004908: 68bb ldr r3, [r7, #8] 800490a: 3301 adds r3, #1 800490c: 01db lsls r3, r3, #7 800490e: 440b add r3, r1 8004910: 601a str r2, [r3, #0] hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= pCompareCfg->AutoDelayedMode; 8004912: 68fb ldr r3, [r7, #12] 8004914: 681a ldr r2, [r3, #0] 8004916: 68bb ldr r3, [r7, #8] 8004918: 3301 adds r3, #1 800491a: 01db lsls r3, r3, #7 800491c: 4413 add r3, r2 800491e: 681a ldr r2, [r3, #0] 8004920: 683b ldr r3, [r7, #0] 8004922: 685b ldr r3, [r3, #4] 8004924: 68f9 ldr r1, [r7, #12] 8004926: 6809 ldr r1, [r1, #0] 8004928: 431a orrs r2, r3 800492a: 68bb ldr r3, [r7, #8] 800492c: 3301 adds r3, #1 800492e: 01db lsls r3, r3, #7 8004930: 440b add r3, r1 8004932: 601a str r2, [r3, #0] /* Set the compare value for timeout compare unit (if any) */ if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) 8004934: 683b ldr r3, [r7, #0] 8004936: 685b ldr r3, [r3, #4] 8004938: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800493c: d109 bne.n 8004952 { hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout; 800493e: 68fb ldr r3, [r7, #12] 8004940: 6819 ldr r1, [r3, #0] 8004942: 683b ldr r3, [r7, #0] 8004944: 689a ldr r2, [r3, #8] 8004946: 68bb ldr r3, [r7, #8] 8004948: 01db lsls r3, r3, #7 800494a: 440b add r3, r1 800494c: 339c adds r3, #156 @ 0x9c 800494e: 601a str r2, [r3, #0] else { /* Clear HRTIM_TIMxCR.DELCMP2 bitfield */ MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP2, 0U); } break; 8004950: e091 b.n 8004a76 else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3) 8004952: 683b ldr r3, [r7, #0] 8004954: 685b ldr r3, [r3, #4] 8004956: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 800495a: f040 808c bne.w 8004a76 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout; 800495e: 68fb ldr r3, [r7, #12] 8004960: 6819 ldr r1, [r3, #0] 8004962: 683b ldr r3, [r7, #0] 8004964: 689a ldr r2, [r3, #8] 8004966: 68bb ldr r3, [r7, #8] 8004968: 01db lsls r3, r3, #7 800496a: 440b add r3, r1 800496c: 33a8 adds r3, #168 @ 0xa8 800496e: 601a str r2, [r3, #0] break; 8004970: e081 b.n 8004a76 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP2, 0U); 8004972: 68fb ldr r3, [r7, #12] 8004974: 681a ldr r2, [r3, #0] 8004976: 68bb ldr r3, [r7, #8] 8004978: 3301 adds r3, #1 800497a: 01db lsls r3, r3, #7 800497c: 4413 add r3, r2 800497e: 681b ldr r3, [r3, #0] 8004980: 68fa ldr r2, [r7, #12] 8004982: 6811 ldr r1, [r2, #0] 8004984: f423 5240 bic.w r2, r3, #12288 @ 0x3000 8004988: 68bb ldr r3, [r7, #8] 800498a: 3301 adds r3, #1 800498c: 01db lsls r3, r3, #7 800498e: 440b add r3, r1 8004990: 601a str r2, [r3, #0] break; 8004992: e070 b.n 8004a76 } case HRTIM_COMPAREUNIT_3: { /* Set the compare value */ hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->CompareValue; 8004994: 68fb ldr r3, [r7, #12] 8004996: 6819 ldr r1, [r3, #0] 8004998: 683b ldr r3, [r7, #0] 800499a: 681a ldr r2, [r3, #0] 800499c: 68bb ldr r3, [r7, #8] 800499e: 01db lsls r3, r3, #7 80049a0: 440b add r3, r1 80049a2: 33a8 adds r3, #168 @ 0xa8 80049a4: 601a str r2, [r3, #0] break; 80049a6: e069 b.n 8004a7c { /* Check parameters */ assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode)); /* Set the compare value */ hhrtim->Instance->sTimerxRegs[TimerIdx].CMP4xR = pCompareCfg->CompareValue; 80049a8: 68fb ldr r3, [r7, #12] 80049aa: 6819 ldr r1, [r3, #0] 80049ac: 683b ldr r3, [r7, #0] 80049ae: 681a ldr r2, [r3, #0] 80049b0: 68bb ldr r3, [r7, #8] 80049b2: 01db lsls r3, r3, #7 80049b4: 440b add r3, r1 80049b6: 33ac adds r3, #172 @ 0xac 80049b8: 601a str r2, [r3, #0] if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR) 80049ba: 683b ldr r3, [r7, #0] 80049bc: 685b ldr r3, [r3, #4] 80049be: 2b00 cmp r3, #0 80049c0: d03f beq.n 8004a42 { /* Configure auto-delayed mode */ /* DELCMP4 bitfield must be reset when reprogrammed from one value */ /* to the other to reinitialize properly the auto-delayed mechanism */ hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP4; 80049c2: 68fb ldr r3, [r7, #12] 80049c4: 681a ldr r2, [r3, #0] 80049c6: 68bb ldr r3, [r7, #8] 80049c8: 3301 adds r3, #1 80049ca: 01db lsls r3, r3, #7 80049cc: 4413 add r3, r2 80049ce: 681b ldr r3, [r3, #0] 80049d0: 68fa ldr r2, [r7, #12] 80049d2: 6811 ldr r1, [r2, #0] 80049d4: f423 4240 bic.w r2, r3, #49152 @ 0xc000 80049d8: 68bb ldr r3, [r7, #8] 80049da: 3301 adds r3, #1 80049dc: 01db lsls r3, r3, #7 80049de: 440b add r3, r1 80049e0: 601a str r2, [r3, #0] hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= (pCompareCfg->AutoDelayedMode << 2U); 80049e2: 68fb ldr r3, [r7, #12] 80049e4: 681a ldr r2, [r3, #0] 80049e6: 68bb ldr r3, [r7, #8] 80049e8: 3301 adds r3, #1 80049ea: 01db lsls r3, r3, #7 80049ec: 4413 add r3, r2 80049ee: 681a ldr r2, [r3, #0] 80049f0: 683b ldr r3, [r7, #0] 80049f2: 685b ldr r3, [r3, #4] 80049f4: 009b lsls r3, r3, #2 80049f6: 68f9 ldr r1, [r7, #12] 80049f8: 6809 ldr r1, [r1, #0] 80049fa: 431a orrs r2, r3 80049fc: 68bb ldr r3, [r7, #8] 80049fe: 3301 adds r3, #1 8004a00: 01db lsls r3, r3, #7 8004a02: 440b add r3, r1 8004a04: 601a str r2, [r3, #0] /* Set the compare value for timeout compare unit (if any) */ if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) 8004a06: 683b ldr r3, [r7, #0] 8004a08: 685b ldr r3, [r3, #4] 8004a0a: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8004a0e: d109 bne.n 8004a24 { hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout; 8004a10: 68fb ldr r3, [r7, #12] 8004a12: 6819 ldr r1, [r3, #0] 8004a14: 683b ldr r3, [r7, #0] 8004a16: 689a ldr r2, [r3, #8] 8004a18: 68bb ldr r3, [r7, #8] 8004a1a: 01db lsls r3, r3, #7 8004a1c: 440b add r3, r1 8004a1e: 339c adds r3, #156 @ 0x9c 8004a20: 601a str r2, [r3, #0] else { /* Clear HRTIM_TIMxCR.DELCMP4 bitfield */ MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP4, 0U); } break; 8004a22: e02a b.n 8004a7a else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3) 8004a24: 683b ldr r3, [r7, #0] 8004a26: 685b ldr r3, [r3, #4] 8004a28: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 8004a2c: d125 bne.n 8004a7a hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout; 8004a2e: 68fb ldr r3, [r7, #12] 8004a30: 6819 ldr r1, [r3, #0] 8004a32: 683b ldr r3, [r7, #0] 8004a34: 689a ldr r2, [r3, #8] 8004a36: 68bb ldr r3, [r7, #8] 8004a38: 01db lsls r3, r3, #7 8004a3a: 440b add r3, r1 8004a3c: 33a8 adds r3, #168 @ 0xa8 8004a3e: 601a str r2, [r3, #0] break; 8004a40: e01b b.n 8004a7a MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP4, 0U); 8004a42: 68fb ldr r3, [r7, #12] 8004a44: 681a ldr r2, [r3, #0] 8004a46: 68bb ldr r3, [r7, #8] 8004a48: 3301 adds r3, #1 8004a4a: 01db lsls r3, r3, #7 8004a4c: 4413 add r3, r2 8004a4e: 681b ldr r3, [r3, #0] 8004a50: 68fa ldr r2, [r7, #12] 8004a52: 6811 ldr r1, [r2, #0] 8004a54: f423 4240 bic.w r2, r3, #49152 @ 0xc000 8004a58: 68bb ldr r3, [r7, #8] 8004a5a: 3301 adds r3, #1 8004a5c: 01db lsls r3, r3, #7 8004a5e: 440b add r3, r1 8004a60: 601a str r2, [r3, #0] break; 8004a62: e00a b.n 8004a7a } default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; 8004a64: 68fb ldr r3, [r7, #12] 8004a66: 2207 movs r2, #7 8004a68: f883 20dd strb.w r2, [r3, #221] @ 0xdd /* Process Unlocked */ __HAL_UNLOCK(hhrtim); 8004a6c: 68fb ldr r3, [r7, #12] 8004a6e: 2200 movs r2, #0 8004a70: f883 20dc strb.w r2, [r3, #220] @ 0xdc break; 8004a74: e002 b.n 8004a7c break; 8004a76: bf00 nop 8004a78: e000 b.n 8004a7c break; 8004a7a: bf00 nop } } if (hhrtim->State == HAL_HRTIM_STATE_ERROR) 8004a7c: 68fb ldr r3, [r7, #12] 8004a7e: f893 30dd ldrb.w r3, [r3, #221] @ 0xdd 8004a82: b2db uxtb r3, r3 8004a84: 2b07 cmp r3, #7 8004a86: d101 bne.n 8004a8c { return HAL_ERROR; 8004a88: 2301 movs r3, #1 8004a8a: e008 b.n 8004a9e } } hhrtim->State = HAL_HRTIM_STATE_READY; 8004a8c: 68fb ldr r3, [r7, #12] 8004a8e: 2201 movs r2, #1 8004a90: f883 20dd strb.w r2, [r3, #221] @ 0xdd /* Process Unlocked */ __HAL_UNLOCK(hhrtim); 8004a94: 68fb ldr r3, [r7, #12] 8004a96: 2200 movs r2, #0 8004a98: f883 20dc strb.w r2, [r3, #220] @ 0xdc return HAL_OK; 8004a9c: 2300 movs r3, #0 } 8004a9e: 4618 mov r0, r3 8004aa0: 3714 adds r7, #20 8004aa2: 46bd mov sp, r7 8004aa4: f85d 7b04 ldr.w r7, [sp], #4 8004aa8: 4770 bx lr 8004aaa: bf00 nop 08004aac : */ HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output, const HRTIM_OutputCfgTypeDef *pOutputCfg) { 8004aac: b580 push {r7, lr} 8004aae: b084 sub sp, #16 8004ab0: af00 add r7, sp, #0 8004ab2: 60f8 str r0, [r7, #12] 8004ab4: 60b9 str r1, [r7, #8] 8004ab6: 607a str r2, [r7, #4] 8004ab8: 603b str r3, [r7, #0] assert_param(IS_HRTIM_OUTPUTIDLEMODE(pOutputCfg->IdleMode)); assert_param(IS_HRTIM_OUTPUTFAULTLEVEL(pOutputCfg->FaultLevel)); assert_param(IS_HRTIM_OUTPUTCHOPPERMODE(pOutputCfg->ChopperModeEnable)); assert_param(IS_HRTIM_OUTPUTBURSTMODEENTRY(pOutputCfg->BurstModeEntryDelayed)); if (hhrtim->State == HAL_HRTIM_STATE_BUSY) 8004aba: 68fb ldr r3, [r7, #12] 8004abc: f893 30dd ldrb.w r3, [r3, #221] @ 0xdd 8004ac0: b2db uxtb r3, r3 8004ac2: 2b02 cmp r3, #2 8004ac4: d101 bne.n 8004aca { return HAL_BUSY; 8004ac6: 2302 movs r3, #2 8004ac8: e01d b.n 8004b06 } /* Process Locked */ __HAL_LOCK(hhrtim); 8004aca: 68fb ldr r3, [r7, #12] 8004acc: f893 30dc ldrb.w r3, [r3, #220] @ 0xdc 8004ad0: 2b01 cmp r3, #1 8004ad2: d101 bne.n 8004ad8 8004ad4: 2302 movs r3, #2 8004ad6: e016 b.n 8004b06 8004ad8: 68fb ldr r3, [r7, #12] 8004ada: 2201 movs r2, #1 8004adc: f883 20dc strb.w r2, [r3, #220] @ 0xdc hhrtim->State = HAL_HRTIM_STATE_BUSY; 8004ae0: 68fb ldr r3, [r7, #12] 8004ae2: 2202 movs r2, #2 8004ae4: f883 20dd strb.w r2, [r3, #221] @ 0xdd /* Configure the timer output */ HRTIM_OutputConfig(hhrtim, 8004ae8: 683b ldr r3, [r7, #0] 8004aea: 687a ldr r2, [r7, #4] 8004aec: 68b9 ldr r1, [r7, #8] 8004aee: 68f8 ldr r0, [r7, #12] 8004af0: f000 fb84 bl 80051fc TimerIdx, Output, pOutputCfg); hhrtim->State = HAL_HRTIM_STATE_READY; 8004af4: 68fb ldr r3, [r7, #12] 8004af6: 2201 movs r2, #1 8004af8: f883 20dd strb.w r2, [r3, #221] @ 0xdd /* Process Unlocked */ __HAL_UNLOCK(hhrtim); 8004afc: 68fb ldr r3, [r7, #12] 8004afe: 2200 movs r2, #0 8004b00: f883 20dc strb.w r2, [r3, #220] @ 0xdc return HAL_OK; 8004b04: 2300 movs r3, #0 } 8004b06: 4618 mov r0, r3 8004b08: 3710 adds r7, #16 8004b0a: 46bd mov sp, r7 8004b0c: bd80 pop {r7, pc} 08004b0e : * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2 * @retval HAL status */ HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef *hhrtim, uint32_t OutputsToStart) { 8004b0e: b480 push {r7} 8004b10: b083 sub sp, #12 8004b12: af00 add r7, sp, #0 8004b14: 6078 str r0, [r7, #4] 8004b16: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_HRTIM_OUTPUT(OutputsToStart)); /* Process Locked */ __HAL_LOCK(hhrtim); 8004b18: 687b ldr r3, [r7, #4] 8004b1a: f893 30dc ldrb.w r3, [r3, #220] @ 0xdc 8004b1e: 2b01 cmp r3, #1 8004b20: d101 bne.n 8004b26 8004b22: 2302 movs r3, #2 8004b24: e01a b.n 8004b5c 8004b26: 687b ldr r3, [r7, #4] 8004b28: 2201 movs r2, #1 8004b2a: f883 20dc strb.w r2, [r3, #220] @ 0xdc hhrtim->State = HAL_HRTIM_STATE_BUSY; 8004b2e: 687b ldr r3, [r7, #4] 8004b30: 2202 movs r2, #2 8004b32: f883 20dd strb.w r2, [r3, #221] @ 0xdd /* Enable the HRTIM outputs */ hhrtim->Instance->sCommonRegs.OENR |= (OutputsToStart); 8004b36: 687b ldr r3, [r7, #4] 8004b38: 681b ldr r3, [r3, #0] 8004b3a: f8d3 1394 ldr.w r1, [r3, #916] @ 0x394 8004b3e: 687b ldr r3, [r7, #4] 8004b40: 681b ldr r3, [r3, #0] 8004b42: 683a ldr r2, [r7, #0] 8004b44: 430a orrs r2, r1 8004b46: f8c3 2394 str.w r2, [r3, #916] @ 0x394 hhrtim->State = HAL_HRTIM_STATE_READY; 8004b4a: 687b ldr r3, [r7, #4] 8004b4c: 2201 movs r2, #1 8004b4e: f883 20dd strb.w r2, [r3, #221] @ 0xdd /* Process Unlocked */ __HAL_UNLOCK(hhrtim); 8004b52: 687b ldr r3, [r7, #4] 8004b54: 2200 movs r2, #0 8004b56: f883 20dc strb.w r2, [r3, #220] @ 0xdc return HAL_OK; 8004b5a: 2300 movs r3, #0 } 8004b5c: 4618 mov r0, r3 8004b5e: 370c adds r7, #12 8004b60: 46bd mov sp, r7 8004b62: f85d 7b04 ldr.w r7, [sp], #4 8004b66: 4770 bx lr 08004b68 : * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2 * @retval HAL status */ HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef *hhrtim, uint32_t OutputsToStop) { 8004b68: b480 push {r7} 8004b6a: b083 sub sp, #12 8004b6c: af00 add r7, sp, #0 8004b6e: 6078 str r0, [r7, #4] 8004b70: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_HRTIM_OUTPUT(OutputsToStop)); /* Process Locked */ __HAL_LOCK(hhrtim); 8004b72: 687b ldr r3, [r7, #4] 8004b74: f893 30dc ldrb.w r3, [r3, #220] @ 0xdc 8004b78: 2b01 cmp r3, #1 8004b7a: d101 bne.n 8004b80 8004b7c: 2302 movs r3, #2 8004b7e: e01a b.n 8004bb6 8004b80: 687b ldr r3, [r7, #4] 8004b82: 2201 movs r2, #1 8004b84: f883 20dc strb.w r2, [r3, #220] @ 0xdc hhrtim->State = HAL_HRTIM_STATE_BUSY; 8004b88: 687b ldr r3, [r7, #4] 8004b8a: 2202 movs r2, #2 8004b8c: f883 20dd strb.w r2, [r3, #221] @ 0xdd /* Enable the HRTIM outputs */ hhrtim->Instance->sCommonRegs.ODISR |= (OutputsToStop); 8004b90: 687b ldr r3, [r7, #4] 8004b92: 681b ldr r3, [r3, #0] 8004b94: f8d3 1398 ldr.w r1, [r3, #920] @ 0x398 8004b98: 687b ldr r3, [r7, #4] 8004b9a: 681b ldr r3, [r3, #0] 8004b9c: 683a ldr r2, [r7, #0] 8004b9e: 430a orrs r2, r1 8004ba0: f8c3 2398 str.w r2, [r3, #920] @ 0x398 hhrtim->State = HAL_HRTIM_STATE_READY; 8004ba4: 687b ldr r3, [r7, #4] 8004ba6: 2201 movs r2, #1 8004ba8: f883 20dd strb.w r2, [r3, #221] @ 0xdd /* Process Unlocked */ __HAL_UNLOCK(hhrtim); 8004bac: 687b ldr r3, [r7, #4] 8004bae: 2200 movs r2, #0 8004bb0: f883 20dc strb.w r2, [r3, #220] @ 0xdc return HAL_OK; 8004bb4: 2300 movs r3, #0 } 8004bb6: 4618 mov r0, r3 8004bb8: 370c adds r7, #12 8004bba: 46bd mov sp, r7 8004bbc: f85d 7b04 ldr.w r7, [sp], #4 8004bc0: 4770 bx lr 08004bc2 : * @arg HRTIM_TIMERID_TIMER_F * @retval HAL status */ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef *hhrtim, uint32_t Timers) { 8004bc2: b480 push {r7} 8004bc4: b083 sub sp, #12 8004bc6: af00 add r7, sp, #0 8004bc8: 6078 str r0, [r7, #4] 8004bca: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_HRTIM_TIMERID(Timers)); /* Process Locked */ __HAL_LOCK(hhrtim); 8004bcc: 687b ldr r3, [r7, #4] 8004bce: f893 30dc ldrb.w r3, [r3, #220] @ 0xdc 8004bd2: 2b01 cmp r3, #1 8004bd4: d101 bne.n 8004bda 8004bd6: 2302 movs r3, #2 8004bd8: e018 b.n 8004c0c 8004bda: 687b ldr r3, [r7, #4] 8004bdc: 2201 movs r2, #1 8004bde: f883 20dc strb.w r2, [r3, #220] @ 0xdc hhrtim->State = HAL_HRTIM_STATE_BUSY; 8004be2: 687b ldr r3, [r7, #4] 8004be4: 2202 movs r2, #2 8004be6: f883 20dd strb.w r2, [r3, #221] @ 0xdd /* Enable timer(s) counter */ hhrtim->Instance->sMasterRegs.MCR |= (Timers); 8004bea: 687b ldr r3, [r7, #4] 8004bec: 681b ldr r3, [r3, #0] 8004bee: 6819 ldr r1, [r3, #0] 8004bf0: 687b ldr r3, [r7, #4] 8004bf2: 681b ldr r3, [r3, #0] 8004bf4: 683a ldr r2, [r7, #0] 8004bf6: 430a orrs r2, r1 8004bf8: 601a str r2, [r3, #0] hhrtim->State = HAL_HRTIM_STATE_READY; 8004bfa: 687b ldr r3, [r7, #4] 8004bfc: 2201 movs r2, #1 8004bfe: f883 20dd strb.w r2, [r3, #221] @ 0xdd /* Process Unlocked */ __HAL_UNLOCK(hhrtim); 8004c02: 687b ldr r3, [r7, #4] 8004c04: 2200 movs r2, #0 8004c06: f883 20dc strb.w r2, [r3, #220] @ 0xdc return HAL_OK; 8004c0a: 2300 movs r3, #0 } 8004c0c: 4618 mov r0, r3 8004c0e: 370c adds r7, #12 8004c10: 46bd mov sp, r7 8004c12: f85d 7b04 ldr.w r7, [sp], #4 8004c16: 4770 bx lr 08004c18 : * @param pTimeBaseCfg pointer to the time base configuration structure * @retval None */ static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef *hhrtim, const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg) { 8004c18: b480 push {r7} 8004c1a: b085 sub sp, #20 8004c1c: af00 add r7, sp, #0 8004c1e: 6078 str r0, [r7, #4] 8004c20: 6039 str r1, [r7, #0] uint32_t hrtim_mcr; /* Configure master timer */ hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR; 8004c22: 687b ldr r3, [r7, #4] 8004c24: 681b ldr r3, [r3, #0] 8004c26: 681b ldr r3, [r3, #0] 8004c28: 60fb str r3, [r7, #12] /* Set the prescaler ratio */ hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CK_PSC); 8004c2a: 68fb ldr r3, [r7, #12] 8004c2c: f023 0307 bic.w r3, r3, #7 8004c30: 60fb str r3, [r7, #12] hrtim_mcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio; 8004c32: 683b ldr r3, [r7, #0] 8004c34: 689b ldr r3, [r3, #8] 8004c36: 68fa ldr r2, [r7, #12] 8004c38: 4313 orrs r3, r2 8004c3a: 60fb str r3, [r7, #12] /* Set the operating mode */ hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CONT | HRTIM_MCR_RETRIG); 8004c3c: 68fb ldr r3, [r7, #12] 8004c3e: f023 0318 bic.w r3, r3, #24 8004c42: 60fb str r3, [r7, #12] hrtim_mcr |= (uint32_t)pTimeBaseCfg->Mode; 8004c44: 683b ldr r3, [r7, #0] 8004c46: 68db ldr r3, [r3, #12] 8004c48: 68fa ldr r2, [r7, #12] 8004c4a: 4313 orrs r3, r2 8004c4c: 60fb str r3, [r7, #12] /* Update the HRTIM registers */ hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr; 8004c4e: 687b ldr r3, [r7, #4] 8004c50: 681b ldr r3, [r3, #0] 8004c52: 68fa ldr r2, [r7, #12] 8004c54: 601a str r2, [r3, #0] hhrtim->Instance->sMasterRegs.MPER = pTimeBaseCfg->Period; 8004c56: 687b ldr r3, [r7, #4] 8004c58: 681b ldr r3, [r3, #0] 8004c5a: 683a ldr r2, [r7, #0] 8004c5c: 6812 ldr r2, [r2, #0] 8004c5e: 615a str r2, [r3, #20] hhrtim->Instance->sMasterRegs.MREP = pTimeBaseCfg->RepetitionCounter; 8004c60: 687b ldr r3, [r7, #4] 8004c62: 681b ldr r3, [r3, #0] 8004c64: 683a ldr r2, [r7, #0] 8004c66: 6852 ldr r2, [r2, #4] 8004c68: 619a str r2, [r3, #24] } 8004c6a: bf00 nop 8004c6c: 3714 adds r7, #20 8004c6e: 46bd mov sp, r7 8004c70: f85d 7b04 ldr.w r7, [sp], #4 8004c74: 4770 bx lr 08004c76 : * @retval None */ static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg) { 8004c76: b480 push {r7} 8004c78: b087 sub sp, #28 8004c7a: af00 add r7, sp, #0 8004c7c: 60f8 str r0, [r7, #12] 8004c7e: 60b9 str r1, [r7, #8] 8004c80: 607a str r2, [r7, #4] uint32_t hrtim_timcr; /* Configure master timing unit */ hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR; 8004c82: 68fb ldr r3, [r7, #12] 8004c84: 681a ldr r2, [r3, #0] 8004c86: 68bb ldr r3, [r7, #8] 8004c88: 3301 adds r3, #1 8004c8a: 01db lsls r3, r3, #7 8004c8c: 4413 add r3, r2 8004c8e: 681b ldr r3, [r3, #0] 8004c90: 617b str r3, [r7, #20] /* Set the prescaler ratio */ hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CK_PSC); 8004c92: 697b ldr r3, [r7, #20] 8004c94: f023 0307 bic.w r3, r3, #7 8004c98: 617b str r3, [r7, #20] hrtim_timcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio; 8004c9a: 687b ldr r3, [r7, #4] 8004c9c: 689b ldr r3, [r3, #8] 8004c9e: 697a ldr r2, [r7, #20] 8004ca0: 4313 orrs r3, r2 8004ca2: 617b str r3, [r7, #20] /* Set the operating mode */ hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CONT | HRTIM_TIMCR_RETRIG); 8004ca4: 697b ldr r3, [r7, #20] 8004ca6: f023 0318 bic.w r3, r3, #24 8004caa: 617b str r3, [r7, #20] hrtim_timcr |= (uint32_t)pTimeBaseCfg->Mode; 8004cac: 687b ldr r3, [r7, #4] 8004cae: 68db ldr r3, [r3, #12] 8004cb0: 697a ldr r2, [r7, #20] 8004cb2: 4313 orrs r3, r2 8004cb4: 617b str r3, [r7, #20] /* Update the HRTIM registers */ hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr; 8004cb6: 68fb ldr r3, [r7, #12] 8004cb8: 681a ldr r2, [r3, #0] 8004cba: 68bb ldr r3, [r7, #8] 8004cbc: 3301 adds r3, #1 8004cbe: 01db lsls r3, r3, #7 8004cc0: 4413 add r3, r2 8004cc2: 697a ldr r2, [r7, #20] 8004cc4: 601a str r2, [r3, #0] hhrtim->Instance->sTimerxRegs[TimerIdx].PERxR = pTimeBaseCfg->Period; 8004cc6: 68fb ldr r3, [r7, #12] 8004cc8: 6819 ldr r1, [r3, #0] 8004cca: 687b ldr r3, [r7, #4] 8004ccc: 681a ldr r2, [r3, #0] 8004cce: 68bb ldr r3, [r7, #8] 8004cd0: 01db lsls r3, r3, #7 8004cd2: 440b add r3, r1 8004cd4: 3394 adds r3, #148 @ 0x94 8004cd6: 601a str r2, [r3, #0] hhrtim->Instance->sTimerxRegs[TimerIdx].REPxR = pTimeBaseCfg->RepetitionCounter; 8004cd8: 68fb ldr r3, [r7, #12] 8004cda: 6819 ldr r1, [r3, #0] 8004cdc: 687b ldr r3, [r7, #4] 8004cde: 685a ldr r2, [r3, #4] 8004ce0: 68bb ldr r3, [r7, #8] 8004ce2: 01db lsls r3, r3, #7 8004ce4: 440b add r3, r1 8004ce6: 3398 adds r3, #152 @ 0x98 8004ce8: 601a str r2, [r3, #0] } 8004cea: bf00 nop 8004cec: 371c adds r7, #28 8004cee: 46bd mov sp, r7 8004cf0: f85d 7b04 ldr.w r7, [sp], #4 8004cf4: 4770 bx lr 08004cf6 : * @param pTimerCfg pointer to the timer configuration data structure * @retval None */ static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef *hhrtim, const HRTIM_TimerCfgTypeDef *pTimerCfg) { 8004cf6: b480 push {r7} 8004cf8: b085 sub sp, #20 8004cfa: af00 add r7, sp, #0 8004cfc: 6078 str r0, [r7, #4] 8004cfe: 6039 str r1, [r7, #0] uint32_t hrtim_mcr; uint32_t hrtim_bmcr; /* Configure master timer */ hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR; 8004d00: 687b ldr r3, [r7, #4] 8004d02: 681b ldr r3, [r3, #0] 8004d04: 681b ldr r3, [r3, #0] 8004d06: 60fb str r3, [r7, #12] hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR; 8004d08: 687b ldr r3, [r7, #4] 8004d0a: 681b ldr r3, [r3, #0] 8004d0c: f8d3 33a0 ldr.w r3, [r3, #928] @ 0x3a0 8004d10: 60bb str r3, [r7, #8] /* Enable/Disable the half mode */ hrtim_mcr &= ~(HRTIM_MCR_HALF); 8004d12: 68fb ldr r3, [r7, #12] 8004d14: f023 0320 bic.w r3, r3, #32 8004d18: 60fb str r3, [r7, #12] hrtim_mcr |= pTimerCfg->HalfModeEnable; 8004d1a: 683b ldr r3, [r7, #0] 8004d1c: 695b ldr r3, [r3, #20] 8004d1e: 68fa ldr r2, [r7, #12] 8004d20: 4313 orrs r3, r2 8004d22: 60fb str r3, [r7, #12] /* INTLVD bits are set to 00 */ hrtim_mcr &= ~(HRTIM_MCR_INTLVD); 8004d24: 68fb ldr r3, [r7, #12] 8004d26: f023 03c0 bic.w r3, r3, #192 @ 0xc0 8004d2a: 60fb str r3, [r7, #12] if ((pTimerCfg->HalfModeEnable == HRTIM_HALFMODE_ENABLED) 8004d2c: 683b ldr r3, [r7, #0] 8004d2e: 695b ldr r3, [r3, #20] 8004d30: 2b20 cmp r3, #32 8004d32: d003 beq.n 8004d3c || (pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_DUAL)) 8004d34: 683b ldr r3, [r7, #0] 8004d36: 699b ldr r3, [r3, #24] 8004d38: 2b02 cmp r3, #2 8004d3a: d108 bne.n 8004d4e { /* INTLVD bits set to 00 */ hrtim_mcr &= ~(HRTIM_MCR_INTLVD); 8004d3c: 68fb ldr r3, [r7, #12] 8004d3e: f023 03c0 bic.w r3, r3, #192 @ 0xc0 8004d42: 60fb str r3, [r7, #12] hrtim_mcr |= (HRTIM_MCR_HALF); 8004d44: 68fb ldr r3, [r7, #12] 8004d46: f043 0320 orr.w r3, r3, #32 8004d4a: 60fb str r3, [r7, #12] 8004d4c: e021 b.n 8004d92 } else if (pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_TRIPLE) 8004d4e: 683b ldr r3, [r7, #0] 8004d50: 699b ldr r3, [r3, #24] 8004d52: 2b03 cmp r3, #3 8004d54: d108 bne.n 8004d68 { hrtim_mcr |= (HRTIM_MCR_INTLVD_0); 8004d56: 68fb ldr r3, [r7, #12] 8004d58: f043 0340 orr.w r3, r3, #64 @ 0x40 8004d5c: 60fb str r3, [r7, #12] hrtim_mcr &= ~(HRTIM_MCR_INTLVD_1); 8004d5e: 68fb ldr r3, [r7, #12] 8004d60: f023 0380 bic.w r3, r3, #128 @ 0x80 8004d64: 60fb str r3, [r7, #12] 8004d66: e014 b.n 8004d92 } else if (pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_QUAD) 8004d68: 683b ldr r3, [r7, #0] 8004d6a: 699b ldr r3, [r3, #24] 8004d6c: 2b04 cmp r3, #4 8004d6e: d108 bne.n 8004d82 { hrtim_mcr |= (HRTIM_MCR_INTLVD_1); 8004d70: 68fb ldr r3, [r7, #12] 8004d72: f043 0380 orr.w r3, r3, #128 @ 0x80 8004d76: 60fb str r3, [r7, #12] hrtim_mcr &= ~(HRTIM_MCR_INTLVD_0); 8004d78: 68fb ldr r3, [r7, #12] 8004d7a: f023 0340 bic.w r3, r3, #64 @ 0x40 8004d7e: 60fb str r3, [r7, #12] 8004d80: e007 b.n 8004d92 } else { hrtim_mcr &= ~(HRTIM_MCR_HALF); 8004d82: 68fb ldr r3, [r7, #12] 8004d84: f023 0320 bic.w r3, r3, #32 8004d88: 60fb str r3, [r7, #12] hrtim_mcr &= ~(HRTIM_MCR_INTLVD); 8004d8a: 68fb ldr r3, [r7, #12] 8004d8c: f023 03c0 bic.w r3, r3, #192 @ 0xc0 8004d90: 60fb str r3, [r7, #12] } /* Enable/Disable the timer start upon synchronization event reception */ hrtim_mcr &= ~(HRTIM_MCR_SYNCSTRTM); 8004d92: 68fb ldr r3, [r7, #12] 8004d94: f423 6300 bic.w r3, r3, #2048 @ 0x800 8004d98: 60fb str r3, [r7, #12] hrtim_mcr |= pTimerCfg->StartOnSync; 8004d9a: 683b ldr r3, [r7, #0] 8004d9c: 69db ldr r3, [r3, #28] 8004d9e: 68fa ldr r2, [r7, #12] 8004da0: 4313 orrs r3, r2 8004da2: 60fb str r3, [r7, #12] /* Enable/Disable the timer reset upon synchronization event reception */ hrtim_mcr &= ~(HRTIM_MCR_SYNCRSTM); 8004da4: 68fb ldr r3, [r7, #12] 8004da6: f423 6380 bic.w r3, r3, #1024 @ 0x400 8004daa: 60fb str r3, [r7, #12] hrtim_mcr |= pTimerCfg->ResetOnSync; 8004dac: 683b ldr r3, [r7, #0] 8004dae: 6a1b ldr r3, [r3, #32] 8004db0: 68fa ldr r2, [r7, #12] 8004db2: 4313 orrs r3, r2 8004db4: 60fb str r3, [r7, #12] /* Enable/Disable the DAC synchronization event generation */ hrtim_mcr &= ~(HRTIM_MCR_DACSYNC); 8004db6: 68fb ldr r3, [r7, #12] 8004db8: f023 63c0 bic.w r3, r3, #100663296 @ 0x6000000 8004dbc: 60fb str r3, [r7, #12] hrtim_mcr |= pTimerCfg->DACSynchro; 8004dbe: 683b ldr r3, [r7, #0] 8004dc0: 6a5b ldr r3, [r3, #36] @ 0x24 8004dc2: 68fa ldr r2, [r7, #12] 8004dc4: 4313 orrs r3, r2 8004dc6: 60fb str r3, [r7, #12] /* Enable/Disable preload mechanism for timer registers */ hrtim_mcr &= ~(HRTIM_MCR_PREEN); 8004dc8: 68fb ldr r3, [r7, #12] 8004dca: f023 6300 bic.w r3, r3, #134217728 @ 0x8000000 8004dce: 60fb str r3, [r7, #12] hrtim_mcr |= pTimerCfg->PreloadEnable; 8004dd0: 683b ldr r3, [r7, #0] 8004dd2: 6a9b ldr r3, [r3, #40] @ 0x28 8004dd4: 68fa ldr r2, [r7, #12] 8004dd6: 4313 orrs r3, r2 8004dd8: 60fb str r3, [r7, #12] /* Master timer registers update handling */ hrtim_mcr &= ~(HRTIM_MCR_BRSTDMA); 8004dda: 68fb ldr r3, [r7, #12] 8004ddc: f023 4340 bic.w r3, r3, #3221225472 @ 0xc0000000 8004de0: 60fb str r3, [r7, #12] hrtim_mcr |= (pTimerCfg->UpdateGating << 2U); 8004de2: 683b ldr r3, [r7, #0] 8004de4: 6adb ldr r3, [r3, #44] @ 0x2c 8004de6: 009b lsls r3, r3, #2 8004de8: 68fa ldr r2, [r7, #12] 8004dea: 4313 orrs r3, r2 8004dec: 60fb str r3, [r7, #12] /* Enable/Disable registers update on repetition */ hrtim_mcr &= ~(HRTIM_MCR_MREPU); 8004dee: 68fb ldr r3, [r7, #12] 8004df0: f023 5300 bic.w r3, r3, #536870912 @ 0x20000000 8004df4: 60fb str r3, [r7, #12] hrtim_mcr |= pTimerCfg->RepetitionUpdate; 8004df6: 683b ldr r3, [r7, #0] 8004df8: 6b5b ldr r3, [r3, #52] @ 0x34 8004dfa: 68fa ldr r2, [r7, #12] 8004dfc: 4313 orrs r3, r2 8004dfe: 60fb str r3, [r7, #12] /* Set the timer burst mode */ hrtim_bmcr &= ~(HRTIM_BMCR_MTBM); 8004e00: 68bb ldr r3, [r7, #8] 8004e02: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8004e06: 60bb str r3, [r7, #8] hrtim_bmcr |= pTimerCfg->BurstMode; 8004e08: 683b ldr r3, [r7, #0] 8004e0a: 6b1b ldr r3, [r3, #48] @ 0x30 8004e0c: 68ba ldr r2, [r7, #8] 8004e0e: 4313 orrs r3, r2 8004e10: 60bb str r3, [r7, #8] /* Update the HRTIM registers */ hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr; 8004e12: 687b ldr r3, [r7, #4] 8004e14: 681b ldr r3, [r3, #0] 8004e16: 68fa ldr r2, [r7, #12] 8004e18: 601a str r2, [r3, #0] hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr; 8004e1a: 687b ldr r3, [r7, #4] 8004e1c: 681b ldr r3, [r3, #0] 8004e1e: 68ba ldr r2, [r7, #8] 8004e20: f8c3 23a0 str.w r2, [r3, #928] @ 0x3a0 } 8004e24: bf00 nop 8004e26: 3714 adds r7, #20 8004e28: 46bd mov sp, r7 8004e2a: f85d 7b04 ldr.w r7, [sp], #4 8004e2e: 4770 bx lr 08004e30 : * @retval None */ static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, const HRTIM_TimerCfgTypeDef *pTimerCfg) { 8004e30: b480 push {r7} 8004e32: b08b sub sp, #44 @ 0x2c 8004e34: af00 add r7, sp, #0 8004e36: 60f8 str r0, [r7, #12] 8004e38: 60b9 str r1, [r7, #8] 8004e3a: 607a str r2, [r7, #4] uint32_t hrtim_timoutr; uint32_t hrtim_timrstr; uint32_t hrtim_bmcr; /* UPDGAT bitfield must be reset before programming a new value */ hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~(HRTIM_TIMCR_UPDGAT); 8004e3c: 68fb ldr r3, [r7, #12] 8004e3e: 681a ldr r2, [r3, #0] 8004e40: 68bb ldr r3, [r7, #8] 8004e42: 3301 adds r3, #1 8004e44: 01db lsls r3, r3, #7 8004e46: 4413 add r3, r2 8004e48: 681b ldr r3, [r3, #0] 8004e4a: 68fa ldr r2, [r7, #12] 8004e4c: 6811 ldr r1, [r2, #0] 8004e4e: f023 4270 bic.w r2, r3, #4026531840 @ 0xf0000000 8004e52: 68bb ldr r3, [r7, #8] 8004e54: 3301 adds r3, #1 8004e56: 01db lsls r3, r3, #7 8004e58: 440b add r3, r1 8004e5a: 601a str r2, [r3, #0] /* Configure timing unit (Timer A to Timer F) */ hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR; 8004e5c: 68fb ldr r3, [r7, #12] 8004e5e: 681a ldr r2, [r3, #0] 8004e60: 68bb ldr r3, [r7, #8] 8004e62: 3301 adds r3, #1 8004e64: 01db lsls r3, r3, #7 8004e66: 4413 add r3, r2 8004e68: 681b ldr r3, [r3, #0] 8004e6a: 627b str r3, [r7, #36] @ 0x24 hrtim_timfltr = hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR; 8004e6c: 68fb ldr r3, [r7, #12] 8004e6e: 681a ldr r2, [r3, #0] 8004e70: 68bb ldr r3, [r7, #8] 8004e72: 01db lsls r3, r3, #7 8004e74: 4413 add r3, r2 8004e76: 33e8 adds r3, #232 @ 0xe8 8004e78: 681b ldr r3, [r3, #0] 8004e7a: 61bb str r3, [r7, #24] hrtim_timoutr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR; 8004e7c: 68fb ldr r3, [r7, #12] 8004e7e: 681a ldr r2, [r3, #0] 8004e80: 68bb ldr r3, [r7, #8] 8004e82: 01db lsls r3, r3, #7 8004e84: 4413 add r3, r2 8004e86: 33e4 adds r3, #228 @ 0xe4 8004e88: 681b ldr r3, [r3, #0] 8004e8a: 623b str r3, [r7, #32] hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR; 8004e8c: 68fb ldr r3, [r7, #12] 8004e8e: 681b ldr r3, [r3, #0] 8004e90: f8d3 33a0 ldr.w r3, [r3, #928] @ 0x3a0 8004e94: 61fb str r3, [r7, #28] /* Enable/Disable the half mode */ hrtim_timcr &= ~(HRTIM_TIMCR_HALF); 8004e96: 6a7b ldr r3, [r7, #36] @ 0x24 8004e98: f023 0320 bic.w r3, r3, #32 8004e9c: 627b str r3, [r7, #36] @ 0x24 hrtim_timcr |= pTimerCfg->HalfModeEnable; 8004e9e: 687b ldr r3, [r7, #4] 8004ea0: 695b ldr r3, [r3, #20] 8004ea2: 6a7a ldr r2, [r7, #36] @ 0x24 8004ea4: 4313 orrs r3, r2 8004ea6: 627b str r3, [r7, #36] @ 0x24 if ((pTimerCfg->HalfModeEnable == HRTIM_HALFMODE_ENABLED) 8004ea8: 687b ldr r3, [r7, #4] 8004eaa: 695b ldr r3, [r3, #20] 8004eac: 2b20 cmp r3, #32 8004eae: d003 beq.n 8004eb8 || (pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_DUAL)) 8004eb0: 687b ldr r3, [r7, #4] 8004eb2: 699b ldr r3, [r3, #24] 8004eb4: 2b02 cmp r3, #2 8004eb6: d108 bne.n 8004eca { /* INTLVD bits set to 00 */ hrtim_timcr &= ~(HRTIM_TIMCR_INTLVD); 8004eb8: 6a7b ldr r3, [r7, #36] @ 0x24 8004eba: f423 73c0 bic.w r3, r3, #384 @ 0x180 8004ebe: 627b str r3, [r7, #36] @ 0x24 hrtim_timcr |= (HRTIM_TIMCR_HALF); 8004ec0: 6a7b ldr r3, [r7, #36] @ 0x24 8004ec2: f043 0320 orr.w r3, r3, #32 8004ec6: 627b str r3, [r7, #36] @ 0x24 8004ec8: e021 b.n 8004f0e } else if (pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_TRIPLE) 8004eca: 687b ldr r3, [r7, #4] 8004ecc: 699b ldr r3, [r3, #24] 8004ece: 2b03 cmp r3, #3 8004ed0: d108 bne.n 8004ee4 { hrtim_timcr |= (HRTIM_TIMCR_INTLVD_0); 8004ed2: 6a7b ldr r3, [r7, #36] @ 0x24 8004ed4: f043 0380 orr.w r3, r3, #128 @ 0x80 8004ed8: 627b str r3, [r7, #36] @ 0x24 hrtim_timcr &= ~(HRTIM_TIMCR_INTLVD_1); 8004eda: 6a7b ldr r3, [r7, #36] @ 0x24 8004edc: f423 7380 bic.w r3, r3, #256 @ 0x100 8004ee0: 627b str r3, [r7, #36] @ 0x24 8004ee2: e014 b.n 8004f0e } else if (pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_QUAD) 8004ee4: 687b ldr r3, [r7, #4] 8004ee6: 699b ldr r3, [r3, #24] 8004ee8: 2b04 cmp r3, #4 8004eea: d108 bne.n 8004efe { hrtim_timcr |= (HRTIM_TIMCR_INTLVD_1); 8004eec: 6a7b ldr r3, [r7, #36] @ 0x24 8004eee: f443 7380 orr.w r3, r3, #256 @ 0x100 8004ef2: 627b str r3, [r7, #36] @ 0x24 hrtim_timcr &= ~(HRTIM_TIMCR_INTLVD_0); 8004ef4: 6a7b ldr r3, [r7, #36] @ 0x24 8004ef6: f023 0380 bic.w r3, r3, #128 @ 0x80 8004efa: 627b str r3, [r7, #36] @ 0x24 8004efc: e007 b.n 8004f0e } else { hrtim_timcr &= ~(HRTIM_TIMCR_HALF); 8004efe: 6a7b ldr r3, [r7, #36] @ 0x24 8004f00: f023 0320 bic.w r3, r3, #32 8004f04: 627b str r3, [r7, #36] @ 0x24 hrtim_timcr &= ~(HRTIM_TIMCR_INTLVD); 8004f06: 6a7b ldr r3, [r7, #36] @ 0x24 8004f08: f423 73c0 bic.w r3, r3, #384 @ 0x180 8004f0c: 627b str r3, [r7, #36] @ 0x24 } /* Enable/Disable the timer start upon synchronization event reception */ hrtim_timcr &= ~(HRTIM_TIMCR_SYNCSTRT); 8004f0e: 6a7b ldr r3, [r7, #36] @ 0x24 8004f10: f423 6300 bic.w r3, r3, #2048 @ 0x800 8004f14: 627b str r3, [r7, #36] @ 0x24 hrtim_timcr |= pTimerCfg->StartOnSync; 8004f16: 687b ldr r3, [r7, #4] 8004f18: 69db ldr r3, [r3, #28] 8004f1a: 6a7a ldr r2, [r7, #36] @ 0x24 8004f1c: 4313 orrs r3, r2 8004f1e: 627b str r3, [r7, #36] @ 0x24 /* Enable/Disable the timer reset upon synchronization event reception */ hrtim_timcr &= ~(HRTIM_TIMCR_SYNCRST); 8004f20: 6a7b ldr r3, [r7, #36] @ 0x24 8004f22: f423 6380 bic.w r3, r3, #1024 @ 0x400 8004f26: 627b str r3, [r7, #36] @ 0x24 hrtim_timcr |= pTimerCfg->ResetOnSync; 8004f28: 687b ldr r3, [r7, #4] 8004f2a: 6a1b ldr r3, [r3, #32] 8004f2c: 6a7a ldr r2, [r7, #36] @ 0x24 8004f2e: 4313 orrs r3, r2 8004f30: 627b str r3, [r7, #36] @ 0x24 /* Enable/Disable the DAC synchronization event generation */ hrtim_timcr &= ~(HRTIM_TIMCR_DACSYNC); 8004f32: 6a7b ldr r3, [r7, #36] @ 0x24 8004f34: f023 63c0 bic.w r3, r3, #100663296 @ 0x6000000 8004f38: 627b str r3, [r7, #36] @ 0x24 hrtim_timcr |= pTimerCfg->DACSynchro; 8004f3a: 687b ldr r3, [r7, #4] 8004f3c: 6a5b ldr r3, [r3, #36] @ 0x24 8004f3e: 6a7a ldr r2, [r7, #36] @ 0x24 8004f40: 4313 orrs r3, r2 8004f42: 627b str r3, [r7, #36] @ 0x24 /* Enable/Disable preload mechanism for timer registers */ hrtim_timcr &= ~(HRTIM_TIMCR_PREEN); 8004f44: 6a7b ldr r3, [r7, #36] @ 0x24 8004f46: f023 6300 bic.w r3, r3, #134217728 @ 0x8000000 8004f4a: 627b str r3, [r7, #36] @ 0x24 hrtim_timcr |= pTimerCfg->PreloadEnable; 8004f4c: 687b ldr r3, [r7, #4] 8004f4e: 6a9b ldr r3, [r3, #40] @ 0x28 8004f50: 6a7a ldr r2, [r7, #36] @ 0x24 8004f52: 4313 orrs r3, r2 8004f54: 627b str r3, [r7, #36] @ 0x24 /* Timing unit registers update handling */ hrtim_timcr &= ~(HRTIM_TIMCR_UPDGAT); 8004f56: 6a7b ldr r3, [r7, #36] @ 0x24 8004f58: f023 4370 bic.w r3, r3, #4026531840 @ 0xf0000000 8004f5c: 627b str r3, [r7, #36] @ 0x24 hrtim_timcr |= pTimerCfg->UpdateGating; 8004f5e: 687b ldr r3, [r7, #4] 8004f60: 6adb ldr r3, [r3, #44] @ 0x2c 8004f62: 6a7a ldr r2, [r7, #36] @ 0x24 8004f64: 4313 orrs r3, r2 8004f66: 627b str r3, [r7, #36] @ 0x24 /* Enable/Disable registers update on repetition */ hrtim_timcr &= ~(HRTIM_TIMCR_TREPU); 8004f68: 6a7b ldr r3, [r7, #36] @ 0x24 8004f6a: f423 3300 bic.w r3, r3, #131072 @ 0x20000 8004f6e: 627b str r3, [r7, #36] @ 0x24 if (pTimerCfg->RepetitionUpdate == HRTIM_UPDATEONREPETITION_ENABLED) 8004f70: 687b ldr r3, [r7, #4] 8004f72: 6b5b ldr r3, [r3, #52] @ 0x34 8004f74: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8004f78: d103 bne.n 8004f82 { hrtim_timcr |= HRTIM_TIMCR_TREPU; 8004f7a: 6a7b ldr r3, [r7, #36] @ 0x24 8004f7c: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8004f80: 627b str r3, [r7, #36] @ 0x24 } /* Set the push-pull mode */ hrtim_timcr &= ~(HRTIM_TIMCR_PSHPLL); 8004f82: 6a7b ldr r3, [r7, #36] @ 0x24 8004f84: f023 0340 bic.w r3, r3, #64 @ 0x40 8004f88: 627b str r3, [r7, #36] @ 0x24 hrtim_timcr |= pTimerCfg->PushPull; 8004f8a: 687b ldr r3, [r7, #4] 8004f8c: 6b9b ldr r3, [r3, #56] @ 0x38 8004f8e: 6a7a ldr r2, [r7, #36] @ 0x24 8004f90: 4313 orrs r3, r2 8004f92: 627b str r3, [r7, #36] @ 0x24 /* Enable/Disable registers update on timer counter reset */ hrtim_timcr &= ~(HRTIM_TIMCR_TRSTU); 8004f94: 6a7b ldr r3, [r7, #36] @ 0x24 8004f96: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8004f9a: 627b str r3, [r7, #36] @ 0x24 hrtim_timcr |= pTimerCfg->ResetUpdate; 8004f9c: 687b ldr r3, [r7, #4] 8004f9e: 6d9b ldr r3, [r3, #88] @ 0x58 8004fa0: 6a7a ldr r2, [r7, #36] @ 0x24 8004fa2: 4313 orrs r3, r2 8004fa4: 627b str r3, [r7, #36] @ 0x24 /* Set the timer update trigger */ hrtim_timcr &= ~(HRTIM_TIMCR_TIMUPDATETRIGGER); 8004fa6: 6a7b ldr r3, [r7, #36] @ 0x24 8004fa8: f023 73fc bic.w r3, r3, #33030144 @ 0x1f80000 8004fac: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8004fb0: 627b str r3, [r7, #36] @ 0x24 hrtim_timcr |= pTimerCfg->UpdateTrigger; 8004fb2: 687b ldr r3, [r7, #4] 8004fb4: 6d1b ldr r3, [r3, #80] @ 0x50 8004fb6: 6a7a ldr r2, [r7, #36] @ 0x24 8004fb8: 4313 orrs r3, r2 8004fba: 627b str r3, [r7, #36] @ 0x24 /* Enable/Disable the fault channel at timer level */ hrtim_timfltr &= ~(HRTIM_FLTR_FLTxEN); 8004fbc: 69bb ldr r3, [r7, #24] 8004fbe: f023 033f bic.w r3, r3, #63 @ 0x3f 8004fc2: 61bb str r3, [r7, #24] hrtim_timfltr |= (pTimerCfg->FaultEnable & HRTIM_FLTR_FLTxEN); 8004fc4: 687b ldr r3, [r7, #4] 8004fc6: 6bdb ldr r3, [r3, #60] @ 0x3c 8004fc8: f003 033f and.w r3, r3, #63 @ 0x3f 8004fcc: 69ba ldr r2, [r7, #24] 8004fce: 4313 orrs r3, r2 8004fd0: 61bb str r3, [r7, #24] /* Lock/Unlock fault sources at timer level */ hrtim_timfltr &= ~(HRTIM_FLTR_FLTLCK); 8004fd2: 69bb ldr r3, [r7, #24] 8004fd4: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 8004fd8: 61bb str r3, [r7, #24] hrtim_timfltr |= pTimerCfg->FaultLock; 8004fda: 687b ldr r3, [r7, #4] 8004fdc: 6c1b ldr r3, [r3, #64] @ 0x40 8004fde: 69ba ldr r2, [r7, #24] 8004fe0: 4313 orrs r3, r2 8004fe2: 61bb str r3, [r7, #24] /* Enable/Disable dead time insertion at timer level */ hrtim_timoutr &= ~(HRTIM_OUTR_DTEN); 8004fe4: 6a3b ldr r3, [r7, #32] 8004fe6: f423 7380 bic.w r3, r3, #256 @ 0x100 8004fea: 623b str r3, [r7, #32] hrtim_timoutr |= pTimerCfg->DeadTimeInsertion; 8004fec: 687b ldr r3, [r7, #4] 8004fee: 6c5b ldr r3, [r3, #68] @ 0x44 8004ff0: 6a3a ldr r2, [r7, #32] 8004ff2: 4313 orrs r3, r2 8004ff4: 623b str r3, [r7, #32] /* Enable/Disable delayed protection at timer level Delayed Idle is available whatever the timer operating mode (regular, push-pull) Balanced Idle is only available in push-pull mode */ if (((pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) 8004ff6: 687b ldr r3, [r7, #4] 8004ff8: 6c9b ldr r3, [r3, #72] @ 0x48 8004ffa: f5b3 6f60 cmp.w r3, #3584 @ 0xe00 8004ffe: d004 beq.n 800500a && (pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7)) 8005000: 687b ldr r3, [r7, #4] 8005002: 6c9b ldr r3, [r3, #72] @ 0x48 8005004: f5b3 5ff0 cmp.w r3, #7680 @ 0x1e00 8005008: d103 bne.n 8005012 || (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_ENABLED)) 800500a: 687b ldr r3, [r7, #4] 800500c: 6b9b ldr r3, [r3, #56] @ 0x38 800500e: 2b40 cmp r3, #64 @ 0x40 8005010: d108 bne.n 8005024 { hrtim_timoutr &= ~(HRTIM_OUTR_DLYPRT | HRTIM_OUTR_DLYPRTEN); 8005012: 6a3b ldr r3, [r7, #32] 8005014: f423 53f0 bic.w r3, r3, #7680 @ 0x1e00 8005018: 623b str r3, [r7, #32] hrtim_timoutr |= pTimerCfg->DelayedProtectionMode; 800501a: 687b ldr r3, [r7, #4] 800501c: 6c9b ldr r3, [r3, #72] @ 0x48 800501e: 6a3a ldr r2, [r7, #32] 8005020: 4313 orrs r3, r2 8005022: 623b str r3, [r7, #32] } /* Set the BIAR mode : one bit for both outputs */ hrtim_timoutr &= ~(HRTIM_OUTR_BIAR); 8005024: 6a3b ldr r3, [r7, #32] 8005026: f423 4380 bic.w r3, r3, #16384 @ 0x4000 800502a: 623b str r3, [r7, #32] hrtim_timoutr |= (pTimerCfg->BalancedIdleAutomaticResume); 800502c: 687b ldr r3, [r7, #4] 800502e: 6cdb ldr r3, [r3, #76] @ 0x4c 8005030: 6a3a ldr r2, [r7, #32] 8005032: 4313 orrs r3, r2 8005034: 623b str r3, [r7, #32] /* Set the timer counter reset trigger */ hrtim_timrstr = pTimerCfg->ResetTrigger; 8005036: 687b ldr r3, [r7, #4] 8005038: 6d5b ldr r3, [r3, #84] @ 0x54 800503a: 617b str r3, [r7, #20] /* Set the timer burst mode */ switch (TimerIdx) 800503c: 68bb ldr r3, [r7, #8] 800503e: 2b05 cmp r3, #5 8005040: d850 bhi.n 80050e4 8005042: a201 add r2, pc, #4 @ (adr r2, 8005048 ) 8005044: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8005048: 08005061 .word 0x08005061 800504c: 08005077 .word 0x08005077 8005050: 0800508d .word 0x0800508d 8005054: 080050a3 .word 0x080050a3 8005058: 080050b9 .word 0x080050b9 800505c: 080050cf .word 0x080050cf { case HRTIM_TIMERINDEX_TIMER_A: { hrtim_bmcr &= ~(HRTIM_BMCR_TABM); 8005060: 69fb ldr r3, [r7, #28] 8005062: f423 3300 bic.w r3, r3, #131072 @ 0x20000 8005066: 61fb str r3, [r7, #28] hrtim_bmcr |= (pTimerCfg->BurstMode << 1U); 8005068: 687b ldr r3, [r7, #4] 800506a: 6b1b ldr r3, [r3, #48] @ 0x30 800506c: 005b lsls r3, r3, #1 800506e: 69fa ldr r2, [r7, #28] 8005070: 4313 orrs r3, r2 8005072: 61fb str r3, [r7, #28] break; 8005074: e037 b.n 80050e6 } case HRTIM_TIMERINDEX_TIMER_B: { hrtim_bmcr &= ~(HRTIM_BMCR_TBBM); 8005076: 69fb ldr r3, [r7, #28] 8005078: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800507c: 61fb str r3, [r7, #28] hrtim_bmcr |= (pTimerCfg->BurstMode << 2U); 800507e: 687b ldr r3, [r7, #4] 8005080: 6b1b ldr r3, [r3, #48] @ 0x30 8005082: 009b lsls r3, r3, #2 8005084: 69fa ldr r2, [r7, #28] 8005086: 4313 orrs r3, r2 8005088: 61fb str r3, [r7, #28] break; 800508a: e02c b.n 80050e6 } case HRTIM_TIMERINDEX_TIMER_C: { hrtim_bmcr &= ~(HRTIM_BMCR_TCBM); 800508c: 69fb ldr r3, [r7, #28] 800508e: f423 2300 bic.w r3, r3, #524288 @ 0x80000 8005092: 61fb str r3, [r7, #28] hrtim_bmcr |= (pTimerCfg->BurstMode << 3U); 8005094: 687b ldr r3, [r7, #4] 8005096: 6b1b ldr r3, [r3, #48] @ 0x30 8005098: 00db lsls r3, r3, #3 800509a: 69fa ldr r2, [r7, #28] 800509c: 4313 orrs r3, r2 800509e: 61fb str r3, [r7, #28] break; 80050a0: e021 b.n 80050e6 } case HRTIM_TIMERINDEX_TIMER_D: { hrtim_bmcr &= ~(HRTIM_BMCR_TDBM); 80050a2: 69fb ldr r3, [r7, #28] 80050a4: f423 1380 bic.w r3, r3, #1048576 @ 0x100000 80050a8: 61fb str r3, [r7, #28] hrtim_bmcr |= (pTimerCfg->BurstMode << 4U); 80050aa: 687b ldr r3, [r7, #4] 80050ac: 6b1b ldr r3, [r3, #48] @ 0x30 80050ae: 011b lsls r3, r3, #4 80050b0: 69fa ldr r2, [r7, #28] 80050b2: 4313 orrs r3, r2 80050b4: 61fb str r3, [r7, #28] break; 80050b6: e016 b.n 80050e6 } case HRTIM_TIMERINDEX_TIMER_E: { hrtim_bmcr &= ~(HRTIM_BMCR_TEBM); 80050b8: 69fb ldr r3, [r7, #28] 80050ba: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 80050be: 61fb str r3, [r7, #28] hrtim_bmcr |= (pTimerCfg->BurstMode << 5U); 80050c0: 687b ldr r3, [r7, #4] 80050c2: 6b1b ldr r3, [r3, #48] @ 0x30 80050c4: 015b lsls r3, r3, #5 80050c6: 69fa ldr r2, [r7, #28] 80050c8: 4313 orrs r3, r2 80050ca: 61fb str r3, [r7, #28] break; 80050cc: e00b b.n 80050e6 } case HRTIM_TIMERINDEX_TIMER_F: { hrtim_bmcr &= ~(HRTIM_BMCR_TFBM); 80050ce: 69fb ldr r3, [r7, #28] 80050d0: f423 0380 bic.w r3, r3, #4194304 @ 0x400000 80050d4: 61fb str r3, [r7, #28] hrtim_bmcr |= (pTimerCfg->BurstMode << 6U); 80050d6: 687b ldr r3, [r7, #4] 80050d8: 6b1b ldr r3, [r3, #48] @ 0x30 80050da: 019b lsls r3, r3, #6 80050dc: 69fa ldr r2, [r7, #28] 80050de: 4313 orrs r3, r2 80050e0: 61fb str r3, [r7, #28] break; 80050e2: e000 b.n 80050e6 } default: break; 80050e4: bf00 nop } /* Update the HRTIM registers */ hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr; 80050e6: 68fb ldr r3, [r7, #12] 80050e8: 681a ldr r2, [r3, #0] 80050ea: 68bb ldr r3, [r7, #8] 80050ec: 3301 adds r3, #1 80050ee: 01db lsls r3, r3, #7 80050f0: 4413 add r3, r2 80050f2: 6a7a ldr r2, [r7, #36] @ 0x24 80050f4: 601a str r2, [r3, #0] hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR = hrtim_timfltr; 80050f6: 68fb ldr r3, [r7, #12] 80050f8: 681a ldr r2, [r3, #0] 80050fa: 68bb ldr r3, [r7, #8] 80050fc: 01db lsls r3, r3, #7 80050fe: 4413 add r3, r2 8005100: 33e8 adds r3, #232 @ 0xe8 8005102: 69ba ldr r2, [r7, #24] 8005104: 601a str r2, [r3, #0] hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_timoutr; 8005106: 68fb ldr r3, [r7, #12] 8005108: 681a ldr r2, [r3, #0] 800510a: 68bb ldr r3, [r7, #8] 800510c: 01db lsls r3, r3, #7 800510e: 4413 add r3, r2 8005110: 33e4 adds r3, #228 @ 0xe4 8005112: 6a3a ldr r2, [r7, #32] 8005114: 601a str r2, [r3, #0] hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = hrtim_timrstr; 8005116: 68fb ldr r3, [r7, #12] 8005118: 681a ldr r2, [r3, #0] 800511a: 68bb ldr r3, [r7, #8] 800511c: 01db lsls r3, r3, #7 800511e: 4413 add r3, r2 8005120: 33d4 adds r3, #212 @ 0xd4 8005122: 697a ldr r2, [r7, #20] 8005124: 601a str r2, [r3, #0] hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr; 8005126: 68fb ldr r3, [r7, #12] 8005128: 681b ldr r3, [r3, #0] 800512a: 69fa ldr r2, [r7, #28] 800512c: f8c3 23a0 str.w r2, [r3, #928] @ 0x3a0 } 8005130: bf00 nop 8005132: 372c adds r7, #44 @ 0x2c 8005134: 46bd mov sp, r7 8005136: f85d 7b04 ldr.w r7, [sp], #4 800513a: 4770 bx lr 0800513c : * @retval None */ static void HRTIM_TimingUnitWaveform_Control(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, const HRTIM_TimerCtlTypeDef *pTimerCtl) { 800513c: b480 push {r7} 800513e: b087 sub sp, #28 8005140: af00 add r7, sp, #0 8005142: 60f8 str r0, [r7, #12] 8005144: 60b9 str r1, [r7, #8] 8005146: 607a str r2, [r7, #4] uint32_t hrtim_timcr2; /* Configure timing unit (Timer A to Timer F) */ hrtim_timcr2 = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2; 8005148: 68fb ldr r3, [r7, #12] 800514a: 681a ldr r2, [r3, #0] 800514c: 68bb ldr r3, [r7, #8] 800514e: 01db lsls r3, r3, #7 8005150: 4413 add r3, r2 8005152: 33ec adds r3, #236 @ 0xec 8005154: 681b ldr r3, [r3, #0] 8005156: 617b str r3, [r7, #20] /* Set the UpDown counting Mode */ hrtim_timcr2 &= ~(HRTIM_TIMCR2_UDM); 8005158: 697b ldr r3, [r7, #20] 800515a: f023 0310 bic.w r3, r3, #16 800515e: 617b str r3, [r7, #20] hrtim_timcr2 |= (pTimerCtl->UpDownMode << HRTIM_TIMCR2_UDM_Pos) ; 8005160: 687b ldr r3, [r7, #4] 8005162: 681b ldr r3, [r3, #0] 8005164: 011b lsls r3, r3, #4 8005166: 697a ldr r2, [r7, #20] 8005168: 4313 orrs r3, r2 800516a: 617b str r3, [r7, #20] /* Set the TrigHalf Mode : requires the counter to be disabled */ hrtim_timcr2 &= ~(HRTIM_TIMCR2_TRGHLF); 800516c: 697b ldr r3, [r7, #20] 800516e: f423 1380 bic.w r3, r3, #1048576 @ 0x100000 8005172: 617b str r3, [r7, #20] hrtim_timcr2 |= pTimerCtl->TrigHalf; 8005174: 687b ldr r3, [r7, #4] 8005176: 685b ldr r3, [r3, #4] 8005178: 697a ldr r2, [r7, #20] 800517a: 4313 orrs r3, r2 800517c: 617b str r3, [r7, #20] /* define the compare event operating mode */ hrtim_timcr2 &= ~(HRTIM_TIMCR2_GTCMP1); 800517e: 697b ldr r3, [r7, #20] 8005180: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8005184: 617b str r3, [r7, #20] hrtim_timcr2 |= pTimerCtl->GreaterCMP1; 8005186: 687b ldr r3, [r7, #4] 8005188: 68db ldr r3, [r3, #12] 800518a: 697a ldr r2, [r7, #20] 800518c: 4313 orrs r3, r2 800518e: 617b str r3, [r7, #20] /* define the compare event operating mode */ hrtim_timcr2 &= ~(HRTIM_TIMCR2_GTCMP3); 8005190: 697b ldr r3, [r7, #20] 8005192: f423 3300 bic.w r3, r3, #131072 @ 0x20000 8005196: 617b str r3, [r7, #20] hrtim_timcr2 |= pTimerCtl->GreaterCMP3; 8005198: 687b ldr r3, [r7, #4] 800519a: 689b ldr r3, [r3, #8] 800519c: 697a ldr r2, [r7, #20] 800519e: 4313 orrs r3, r2 80051a0: 617b str r3, [r7, #20] if (pTimerCtl->DualChannelDacEnable == HRTIM_TIMER_DCDE_ENABLED) 80051a2: 687b ldr r3, [r7, #4] 80051a4: 699b ldr r3, [r3, #24] 80051a6: 2b01 cmp r3, #1 80051a8: d11a bne.n 80051e0 { /* Set the DualChannel DAC Reset trigger : requires DCDE enabled */ hrtim_timcr2 &= ~(HRTIM_TIMCR2_DCDR); 80051aa: 697b ldr r3, [r7, #20] 80051ac: f023 0304 bic.w r3, r3, #4 80051b0: 617b str r3, [r7, #20] hrtim_timcr2 |= pTimerCtl->DualChannelDacReset; 80051b2: 687b ldr r3, [r7, #4] 80051b4: 691b ldr r3, [r3, #16] 80051b6: 697a ldr r2, [r7, #20] 80051b8: 4313 orrs r3, r2 80051ba: 617b str r3, [r7, #20] /* Set the DualChannel DAC Step trigger : requires DCDE enabled */ hrtim_timcr2 &= ~(HRTIM_TIMCR2_DCDS); 80051bc: 697b ldr r3, [r7, #20] 80051be: f023 0302 bic.w r3, r3, #2 80051c2: 617b str r3, [r7, #20] hrtim_timcr2 |= pTimerCtl->DualChannelDacStep; 80051c4: 687b ldr r3, [r7, #4] 80051c6: 695b ldr r3, [r3, #20] 80051c8: 697a ldr r2, [r7, #20] 80051ca: 4313 orrs r3, r2 80051cc: 617b str r3, [r7, #20] /* Enable the DualChannel DAC trigger */ hrtim_timcr2 &= ~(HRTIM_TIMCR2_DCDE); 80051ce: 697b ldr r3, [r7, #20] 80051d0: f023 0301 bic.w r3, r3, #1 80051d4: 617b str r3, [r7, #20] hrtim_timcr2 |= pTimerCtl->DualChannelDacEnable; 80051d6: 687b ldr r3, [r7, #4] 80051d8: 699b ldr r3, [r3, #24] 80051da: 697a ldr r2, [r7, #20] 80051dc: 4313 orrs r3, r2 80051de: 617b str r3, [r7, #20] } /* Update the HRTIM registers */ hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2 = hrtim_timcr2; 80051e0: 68fb ldr r3, [r7, #12] 80051e2: 681a ldr r2, [r3, #0] 80051e4: 68bb ldr r3, [r7, #8] 80051e6: 01db lsls r3, r3, #7 80051e8: 4413 add r3, r2 80051ea: 33ec adds r3, #236 @ 0xec 80051ec: 697a ldr r2, [r7, #20] 80051ee: 601a str r2, [r3, #0] } 80051f0: bf00 nop 80051f2: 371c adds r7, #28 80051f4: 46bd mov sp, r7 80051f6: f85d 7b04 ldr.w r7, [sp], #4 80051fa: 4770 bx lr 080051fc : */ static void HRTIM_OutputConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output, const HRTIM_OutputCfgTypeDef *pOutputCfg) { 80051fc: b480 push {r7} 80051fe: b089 sub sp, #36 @ 0x24 8005200: af00 add r7, sp, #0 8005202: 60f8 str r0, [r7, #12] 8005204: 60b9 str r1, [r7, #8] 8005206: 607a str r2, [r7, #4] 8005208: 603b str r3, [r7, #0] uint32_t hrtim_outr; uint32_t hrtim_dtr; uint32_t shift = 0U; 800520a: 2300 movs r3, #0 800520c: 61bb str r3, [r7, #24] hrtim_outr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR; 800520e: 68fb ldr r3, [r7, #12] 8005210: 681a ldr r2, [r3, #0] 8005212: 68bb ldr r3, [r7, #8] 8005214: 01db lsls r3, r3, #7 8005216: 4413 add r3, r2 8005218: 33e4 adds r3, #228 @ 0xe4 800521a: 681b ldr r3, [r3, #0] 800521c: 61fb str r3, [r7, #28] hrtim_dtr = hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR; 800521e: 68fb ldr r3, [r7, #12] 8005220: 681a ldr r2, [r3, #0] 8005222: 68bb ldr r3, [r7, #8] 8005224: 01db lsls r3, r3, #7 8005226: 4413 add r3, r2 8005228: 33b8 adds r3, #184 @ 0xb8 800522a: 681b ldr r3, [r3, #0] 800522c: 617b str r3, [r7, #20] switch (Output) 800522e: 687b ldr r3, [r7, #4] 8005230: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8005234: d05d beq.n 80052f2 8005236: 687b ldr r3, [r7, #4] 8005238: f5b3 6f00 cmp.w r3, #2048 @ 0x800 800523c: d86e bhi.n 800531c 800523e: 687b ldr r3, [r7, #4] 8005240: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8005244: d042 beq.n 80052cc 8005246: 687b ldr r3, [r7, #4] 8005248: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800524c: d866 bhi.n 800531c 800524e: 687b ldr r3, [r7, #4] 8005250: f5b3 7f00 cmp.w r3, #512 @ 0x200 8005254: d04d beq.n 80052f2 8005256: 687b ldr r3, [r7, #4] 8005258: f5b3 7f00 cmp.w r3, #512 @ 0x200 800525c: d85e bhi.n 800531c 800525e: 687b ldr r3, [r7, #4] 8005260: f5b3 7f80 cmp.w r3, #256 @ 0x100 8005264: d032 beq.n 80052cc 8005266: 687b ldr r3, [r7, #4] 8005268: f5b3 7f80 cmp.w r3, #256 @ 0x100 800526c: d856 bhi.n 800531c 800526e: 687b ldr r3, [r7, #4] 8005270: 2b80 cmp r3, #128 @ 0x80 8005272: d03e beq.n 80052f2 8005274: 687b ldr r3, [r7, #4] 8005276: 2b80 cmp r3, #128 @ 0x80 8005278: d850 bhi.n 800531c 800527a: 687b ldr r3, [r7, #4] 800527c: 2b40 cmp r3, #64 @ 0x40 800527e: d025 beq.n 80052cc 8005280: 687b ldr r3, [r7, #4] 8005282: 2b40 cmp r3, #64 @ 0x40 8005284: d84a bhi.n 800531c 8005286: 687b ldr r3, [r7, #4] 8005288: 2b01 cmp r3, #1 800528a: d01f beq.n 80052cc 800528c: 687b ldr r3, [r7, #4] 800528e: 2b00 cmp r3, #0 8005290: d044 beq.n 800531c 8005292: 687b ldr r3, [r7, #4] 8005294: 2b20 cmp r3, #32 8005296: d841 bhi.n 800531c 8005298: 687b ldr r3, [r7, #4] 800529a: 2b02 cmp r3, #2 800529c: d33e bcc.n 800531c 800529e: 687b ldr r3, [r7, #4] 80052a0: 3b02 subs r3, #2 80052a2: 2201 movs r2, #1 80052a4: 409a lsls r2, r3 80052a6: 4b48 ldr r3, [pc, #288] @ (80053c8 ) 80052a8: 4013 ands r3, r2 80052aa: 2b00 cmp r3, #0 80052ac: bf14 ite ne 80052ae: 2301 movne r3, #1 80052b0: 2300 moveq r3, #0 80052b2: b2db uxtb r3, r3 80052b4: 2b00 cmp r3, #0 80052b6: d11c bne.n 80052f2 80052b8: f244 0304 movw r3, #16388 @ 0x4004 80052bc: 4013 ands r3, r2 80052be: 2b00 cmp r3, #0 80052c0: bf14 ite ne 80052c2: 2301 movne r3, #1 80052c4: 2300 moveq r3, #0 80052c6: b2db uxtb r3, r3 80052c8: 2b00 cmp r3, #0 80052ca: d027 beq.n 800531c case HRTIM_OUTPUT_TD1: case HRTIM_OUTPUT_TE1: case HRTIM_OUTPUT_TF1: { /* Set the output set/reset crossbar */ hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R = pOutputCfg->SetSource; 80052cc: 68fb ldr r3, [r7, #12] 80052ce: 6819 ldr r1, [r3, #0] 80052d0: 683b ldr r3, [r7, #0] 80052d2: 685a ldr r2, [r3, #4] 80052d4: 68bb ldr r3, [r7, #8] 80052d6: 01db lsls r3, r3, #7 80052d8: 440b add r3, r1 80052da: 33bc adds r3, #188 @ 0xbc 80052dc: 601a str r2, [r3, #0] hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R = pOutputCfg->ResetSource; 80052de: 68fb ldr r3, [r7, #12] 80052e0: 6819 ldr r1, [r3, #0] 80052e2: 683b ldr r3, [r7, #0] 80052e4: 689a ldr r2, [r3, #8] 80052e6: 68bb ldr r3, [r7, #8] 80052e8: 01db lsls r3, r3, #7 80052ea: 440b add r3, r1 80052ec: 33c0 adds r3, #192 @ 0xc0 80052ee: 601a str r2, [r3, #0] break; 80052f0: e015 b.n 800531e case HRTIM_OUTPUT_TD2: case HRTIM_OUTPUT_TE2: case HRTIM_OUTPUT_TF2: { /* Set the output set/reset crossbar */ hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R = pOutputCfg->SetSource; 80052f2: 68fb ldr r3, [r7, #12] 80052f4: 6819 ldr r1, [r3, #0] 80052f6: 683b ldr r3, [r7, #0] 80052f8: 685a ldr r2, [r3, #4] 80052fa: 68bb ldr r3, [r7, #8] 80052fc: 01db lsls r3, r3, #7 80052fe: 440b add r3, r1 8005300: 33c4 adds r3, #196 @ 0xc4 8005302: 601a str r2, [r3, #0] hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R = pOutputCfg->ResetSource; 8005304: 68fb ldr r3, [r7, #12] 8005306: 6819 ldr r1, [r3, #0] 8005308: 683b ldr r3, [r7, #0] 800530a: 689a ldr r2, [r3, #8] 800530c: 68bb ldr r3, [r7, #8] 800530e: 01db lsls r3, r3, #7 8005310: 440b add r3, r1 8005312: 33c8 adds r3, #200 @ 0xc8 8005314: 601a str r2, [r3, #0] shift = 16U; 8005316: 2310 movs r3, #16 8005318: 61bb str r3, [r7, #24] break; 800531a: e000 b.n 800531e } default: break; 800531c: bf00 nop hrtim_outr &= ~((HRTIM_OUTR_POL1 | HRTIM_OUTR_IDLM1 | HRTIM_OUTR_IDLES1 | HRTIM_OUTR_FAULT1 | HRTIM_OUTR_CHP1 | HRTIM_OUTR_DIDL1) << shift); 800531e: 22fe movs r2, #254 @ 0xfe 8005320: 69bb ldr r3, [r7, #24] 8005322: fa02 f303 lsl.w r3, r2, r3 hrtim_outr &= ~((HRTIM_OUTR_POL1 | 8005326: 43db mvns r3, r3 8005328: 69fa ldr r2, [r7, #28] 800532a: 4013 ands r3, r2 800532c: 61fb str r3, [r7, #28] /* Set the polarity */ hrtim_outr |= (pOutputCfg->Polarity << shift); 800532e: 683b ldr r3, [r7, #0] 8005330: 681a ldr r2, [r3, #0] 8005332: 69bb ldr r3, [r7, #24] 8005334: fa02 f303 lsl.w r3, r2, r3 8005338: 69fa ldr r2, [r7, #28] 800533a: 4313 orrs r3, r2 800533c: 61fb str r3, [r7, #28] /* Set the IDLE mode */ hrtim_outr |= (pOutputCfg->IdleMode << shift); 800533e: 683b ldr r3, [r7, #0] 8005340: 68da ldr r2, [r3, #12] 8005342: 69bb ldr r3, [r7, #24] 8005344: fa02 f303 lsl.w r3, r2, r3 8005348: 69fa ldr r2, [r7, #28] 800534a: 4313 orrs r3, r2 800534c: 61fb str r3, [r7, #28] /* Set the IDLE state */ hrtim_outr |= (pOutputCfg->IdleLevel << shift); 800534e: 683b ldr r3, [r7, #0] 8005350: 691a ldr r2, [r3, #16] 8005352: 69bb ldr r3, [r7, #24] 8005354: fa02 f303 lsl.w r3, r2, r3 8005358: 69fa ldr r2, [r7, #28] 800535a: 4313 orrs r3, r2 800535c: 61fb str r3, [r7, #28] /* Set the FAULT state */ hrtim_outr |= (pOutputCfg->FaultLevel << shift); 800535e: 683b ldr r3, [r7, #0] 8005360: 695a ldr r2, [r3, #20] 8005362: 69bb ldr r3, [r7, #24] 8005364: fa02 f303 lsl.w r3, r2, r3 8005368: 69fa ldr r2, [r7, #28] 800536a: 4313 orrs r3, r2 800536c: 61fb str r3, [r7, #28] /* Set the chopper mode */ hrtim_outr |= (pOutputCfg->ChopperModeEnable << shift); 800536e: 683b ldr r3, [r7, #0] 8005370: 699a ldr r2, [r3, #24] 8005372: 69bb ldr r3, [r7, #24] 8005374: fa02 f303 lsl.w r3, r2, r3 8005378: 69fa ldr r2, [r7, #28] 800537a: 4313 orrs r3, r2 800537c: 61fb str r3, [r7, #28] state during a burst mode operation is allowed only under the following conditions: - the outputs is active during the burst mode (IDLES=1U) - positive deadtimes (SDTR/SDTF set to 0U) */ if ((pOutputCfg->IdleLevel == HRTIM_OUTPUTIDLELEVEL_ACTIVE) && 800537e: 683b ldr r3, [r7, #0] 8005380: 691b ldr r3, [r3, #16] 8005382: 2b08 cmp r3, #8 8005384: d111 bne.n 80053aa ((hrtim_dtr & HRTIM_DTR_SDTR) == (uint32_t)RESET) && 8005386: 697b ldr r3, [r7, #20] 8005388: f403 7300 and.w r3, r3, #512 @ 0x200 if ((pOutputCfg->IdleLevel == HRTIM_OUTPUTIDLELEVEL_ACTIVE) && 800538c: 2b00 cmp r3, #0 800538e: d10c bne.n 80053aa ((hrtim_dtr & HRTIM_DTR_SDTF) == (uint32_t)RESET)) 8005390: 697b ldr r3, [r7, #20] 8005392: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 ((hrtim_dtr & HRTIM_DTR_SDTR) == (uint32_t)RESET) && 8005396: 2b00 cmp r3, #0 8005398: d107 bne.n 80053aa { hrtim_outr |= (pOutputCfg->BurstModeEntryDelayed << shift); 800539a: 683b ldr r3, [r7, #0] 800539c: 69da ldr r2, [r3, #28] 800539e: 69bb ldr r3, [r7, #24] 80053a0: fa02 f303 lsl.w r3, r2, r3 80053a4: 69fa ldr r2, [r7, #28] 80053a6: 4313 orrs r3, r2 80053a8: 61fb str r3, [r7, #28] } /* Update HRTIM register */ hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_outr; 80053aa: 68fb ldr r3, [r7, #12] 80053ac: 681a ldr r2, [r3, #0] 80053ae: 68bb ldr r3, [r7, #8] 80053b0: 01db lsls r3, r3, #7 80053b2: 4413 add r3, r2 80053b4: 33e4 adds r3, #228 @ 0xe4 80053b6: 69fa ldr r2, [r7, #28] 80053b8: 601a str r2, [r3, #0] } 80053ba: bf00 nop 80053bc: 3724 adds r7, #36 @ 0x24 80053be: 46bd mov sp, r7 80053c0: f85d 7b04 ldr.w r7, [sp], #4 80053c4: 4770 bx lr 80053c6: bf00 nop 80053c8: 40000041 .word 0x40000041 080053cc : * @retval None */ static void HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Event, const HRTIM_EventCfgTypeDef *pEventCfg) { 80053cc: b480 push {r7} 80053ce: b089 sub sp, #36 @ 0x24 80053d0: af00 add r7, sp, #0 80053d2: 60f8 str r0, [r7, #12] 80053d4: 60b9 str r1, [r7, #8] 80053d6: 607a str r2, [r7, #4] uint32_t hrtim_eecr1; uint32_t hrtim_eecr2; uint32_t hrtim_eecr3; /* Configure external event channel */ hrtim_eecr1 = hhrtim->Instance->sCommonRegs.EECR1; 80053d8: 68fb ldr r3, [r7, #12] 80053da: 681b ldr r3, [r3, #0] 80053dc: f8d3 33b0 ldr.w r3, [r3, #944] @ 0x3b0 80053e0: 61fb str r3, [r7, #28] hrtim_eecr2 = hhrtim->Instance->sCommonRegs.EECR2; 80053e2: 68fb ldr r3, [r7, #12] 80053e4: 681b ldr r3, [r3, #0] 80053e6: f8d3 33b4 ldr.w r3, [r3, #948] @ 0x3b4 80053ea: 61bb str r3, [r7, #24] hrtim_eecr3 = hhrtim->Instance->sCommonRegs.EECR3; 80053ec: 68fb ldr r3, [r7, #12] 80053ee: 681b ldr r3, [r3, #0] 80053f0: f8d3 33b8 ldr.w r3, [r3, #952] @ 0x3b8 80053f4: 617b str r3, [r7, #20] switch (Event) 80053f6: 68bb ldr r3, [r7, #8] 80053f8: 2b0a cmp r3, #10 80053fa: f200 8208 bhi.w 800580e 80053fe: a201 add r2, pc, #4 @ (adr r2, 8005404 ) 8005400: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8005404: 08005431 .word 0x08005431 8005408: 08005451 .word 0x08005451 800540c: 080054a7 .word 0x080054a7 8005410: 08005503 .word 0x08005503 8005414: 08005561 .word 0x08005561 8005418: 080055bf .word 0x080055bf 800541c: 0800561d .word 0x0800561d 8005420: 0800567b .word 0x0800567b 8005424: 080056df .word 0x080056df 8005428: 08005743 .word 0x08005743 800542c: 080057a9 .word 0x080057a9 { case HRTIM_EVENT_NONE: { /* Update the HRTIM registers */ hhrtim->Instance->sCommonRegs.EECR1 = 0U; 8005430: 68fb ldr r3, [r7, #12] 8005432: 681b ldr r3, [r3, #0] 8005434: 2200 movs r2, #0 8005436: f8c3 23b0 str.w r2, [r3, #944] @ 0x3b0 hhrtim->Instance->sCommonRegs.EECR2 = 0U; 800543a: 68fb ldr r3, [r7, #12] 800543c: 681b ldr r3, [r3, #0] 800543e: 2200 movs r2, #0 8005440: f8c3 23b4 str.w r2, [r3, #948] @ 0x3b4 hhrtim->Instance->sCommonRegs.EECR3 = 0U; 8005444: 68fb ldr r3, [r7, #12] 8005446: 681b ldr r3, [r3, #0] 8005448: 2200 movs r2, #0 800544a: f8c3 23b8 str.w r2, [r3, #952] @ 0x3b8 break; 800544e: e1df b.n 8005810 } case HRTIM_EVENT_1: { hrtim_eecr1 &= ~(HRTIM_EECR1_EE1SRC | HRTIM_EECR1_EE1POL | HRTIM_EECR1_EE1SNS | HRTIM_EECR1_EE1FAST); 8005450: 69fb ldr r3, [r7, #28] 8005452: f023 033f bic.w r3, r3, #63 @ 0x3f 8005456: 61fb str r3, [r7, #28] hrtim_eecr1 |= (pEventCfg->Source & HRTIM_EECR1_EE1SRC); 8005458: 687b ldr r3, [r7, #4] 800545a: 681b ldr r3, [r3, #0] 800545c: f003 0303 and.w r3, r3, #3 8005460: 69fa ldr r2, [r7, #28] 8005462: 4313 orrs r3, r2 8005464: 61fb str r3, [r7, #28] hrtim_eecr1 |= (pEventCfg->Polarity & HRTIM_EECR1_EE1POL); 8005466: 687b ldr r3, [r7, #4] 8005468: 685b ldr r3, [r3, #4] 800546a: f003 0304 and.w r3, r3, #4 800546e: 69fa ldr r2, [r7, #28] 8005470: 4313 orrs r3, r2 8005472: 61fb str r3, [r7, #28] hrtim_eecr1 |= (pEventCfg->Sensitivity & HRTIM_EECR1_EE1SNS); 8005474: 687b ldr r3, [r7, #4] 8005476: 689b ldr r3, [r3, #8] 8005478: f003 0318 and.w r3, r3, #24 800547c: 69fa ldr r2, [r7, #28] 800547e: 4313 orrs r3, r2 8005480: 61fb str r3, [r7, #28] /* Update the HRTIM registers (all bitfields but EE1FAST bit) */ hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1; 8005482: 68fb ldr r3, [r7, #12] 8005484: 681b ldr r3, [r3, #0] 8005486: 69fa ldr r2, [r7, #28] 8005488: f8c3 23b0 str.w r2, [r3, #944] @ 0x3b0 /* Update the HRTIM registers (EE1FAST bit) */ hrtim_eecr1 |= (pEventCfg->FastMode & HRTIM_EECR1_EE1FAST); 800548c: 687b ldr r3, [r7, #4] 800548e: 691b ldr r3, [r3, #16] 8005490: f003 0320 and.w r3, r3, #32 8005494: 69fa ldr r2, [r7, #28] 8005496: 4313 orrs r3, r2 8005498: 61fb str r3, [r7, #28] hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1; 800549a: 68fb ldr r3, [r7, #12] 800549c: 681b ldr r3, [r3, #0] 800549e: 69fa ldr r2, [r7, #28] 80054a0: f8c3 23b0 str.w r2, [r3, #944] @ 0x3b0 break; 80054a4: e1b4 b.n 8005810 } case HRTIM_EVENT_2: { hrtim_eecr1 &= ~(HRTIM_EECR1_EE2SRC | HRTIM_EECR1_EE2POL | HRTIM_EECR1_EE2SNS | HRTIM_EECR1_EE2FAST); 80054a6: 69fb ldr r3, [r7, #28] 80054a8: f423 637c bic.w r3, r3, #4032 @ 0xfc0 80054ac: 61fb str r3, [r7, #28] hrtim_eecr1 |= ((pEventCfg->Source << 6U) & HRTIM_EECR1_EE2SRC); 80054ae: 687b ldr r3, [r7, #4] 80054b0: 681b ldr r3, [r3, #0] 80054b2: 019b lsls r3, r3, #6 80054b4: b2db uxtb r3, r3 80054b6: 69fa ldr r2, [r7, #28] 80054b8: 4313 orrs r3, r2 80054ba: 61fb str r3, [r7, #28] hrtim_eecr1 |= ((pEventCfg->Polarity << 6U) & HRTIM_EECR1_EE2POL); 80054bc: 687b ldr r3, [r7, #4] 80054be: 685b ldr r3, [r3, #4] 80054c0: 019b lsls r3, r3, #6 80054c2: f403 7380 and.w r3, r3, #256 @ 0x100 80054c6: 69fa ldr r2, [r7, #28] 80054c8: 4313 orrs r3, r2 80054ca: 61fb str r3, [r7, #28] hrtim_eecr1 |= ((pEventCfg->Sensitivity << 6U) & HRTIM_EECR1_EE2SNS); 80054cc: 687b ldr r3, [r7, #4] 80054ce: 689b ldr r3, [r3, #8] 80054d0: 019b lsls r3, r3, #6 80054d2: f403 63c0 and.w r3, r3, #1536 @ 0x600 80054d6: 69fa ldr r2, [r7, #28] 80054d8: 4313 orrs r3, r2 80054da: 61fb str r3, [r7, #28] /* Update the HRTIM registers (all bitfields but EE2FAST bit) */ hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1; 80054dc: 68fb ldr r3, [r7, #12] 80054de: 681b ldr r3, [r3, #0] 80054e0: 69fa ldr r2, [r7, #28] 80054e2: f8c3 23b0 str.w r2, [r3, #944] @ 0x3b0 /* Update the HRTIM registers (EE2FAST bit) */ hrtim_eecr1 |= ((pEventCfg->FastMode << 6U) & HRTIM_EECR1_EE2FAST); 80054e6: 687b ldr r3, [r7, #4] 80054e8: 691b ldr r3, [r3, #16] 80054ea: 019b lsls r3, r3, #6 80054ec: f403 6300 and.w r3, r3, #2048 @ 0x800 80054f0: 69fa ldr r2, [r7, #28] 80054f2: 4313 orrs r3, r2 80054f4: 61fb str r3, [r7, #28] hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1; 80054f6: 68fb ldr r3, [r7, #12] 80054f8: 681b ldr r3, [r3, #0] 80054fa: 69fa ldr r2, [r7, #28] 80054fc: f8c3 23b0 str.w r2, [r3, #944] @ 0x3b0 break; 8005500: e186 b.n 8005810 } case HRTIM_EVENT_3: { hrtim_eecr1 &= ~(HRTIM_EECR1_EE3SRC | HRTIM_EECR1_EE3POL | HRTIM_EECR1_EE3SNS | HRTIM_EECR1_EE3FAST); 8005502: 69fb ldr r3, [r7, #28] 8005504: f423 337c bic.w r3, r3, #258048 @ 0x3f000 8005508: 61fb str r3, [r7, #28] hrtim_eecr1 |= ((pEventCfg->Source << 12U) & HRTIM_EECR1_EE3SRC); 800550a: 687b ldr r3, [r7, #4] 800550c: 681b ldr r3, [r3, #0] 800550e: 031b lsls r3, r3, #12 8005510: f403 5340 and.w r3, r3, #12288 @ 0x3000 8005514: 69fa ldr r2, [r7, #28] 8005516: 4313 orrs r3, r2 8005518: 61fb str r3, [r7, #28] hrtim_eecr1 |= ((pEventCfg->Polarity << 12U) & HRTIM_EECR1_EE3POL); 800551a: 687b ldr r3, [r7, #4] 800551c: 685b ldr r3, [r3, #4] 800551e: 031b lsls r3, r3, #12 8005520: f403 4380 and.w r3, r3, #16384 @ 0x4000 8005524: 69fa ldr r2, [r7, #28] 8005526: 4313 orrs r3, r2 8005528: 61fb str r3, [r7, #28] hrtim_eecr1 |= ((pEventCfg->Sensitivity << 12U) & HRTIM_EECR1_EE3SNS); 800552a: 687b ldr r3, [r7, #4] 800552c: 689b ldr r3, [r3, #8] 800552e: 031b lsls r3, r3, #12 8005530: f403 33c0 and.w r3, r3, #98304 @ 0x18000 8005534: 69fa ldr r2, [r7, #28] 8005536: 4313 orrs r3, r2 8005538: 61fb str r3, [r7, #28] /* Update the HRTIM registers (all bitfields but EE3FAST bit) */ hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1; 800553a: 68fb ldr r3, [r7, #12] 800553c: 681b ldr r3, [r3, #0] 800553e: 69fa ldr r2, [r7, #28] 8005540: f8c3 23b0 str.w r2, [r3, #944] @ 0x3b0 /* Update the HRTIM registers (EE3FAST bit) */ hrtim_eecr1 |= ((pEventCfg->FastMode << 12U) & HRTIM_EECR1_EE3FAST); 8005544: 687b ldr r3, [r7, #4] 8005546: 691b ldr r3, [r3, #16] 8005548: 031b lsls r3, r3, #12 800554a: f403 3300 and.w r3, r3, #131072 @ 0x20000 800554e: 69fa ldr r2, [r7, #28] 8005550: 4313 orrs r3, r2 8005552: 61fb str r3, [r7, #28] hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1; 8005554: 68fb ldr r3, [r7, #12] 8005556: 681b ldr r3, [r3, #0] 8005558: 69fa ldr r2, [r7, #28] 800555a: f8c3 23b0 str.w r2, [r3, #944] @ 0x3b0 break; 800555e: e157 b.n 8005810 } case HRTIM_EVENT_4: { hrtim_eecr1 &= ~(HRTIM_EECR1_EE4SRC | HRTIM_EECR1_EE4POL | HRTIM_EECR1_EE4SNS | HRTIM_EECR1_EE4FAST); 8005560: 69fb ldr r3, [r7, #28] 8005562: f423 037c bic.w r3, r3, #16515072 @ 0xfc0000 8005566: 61fb str r3, [r7, #28] hrtim_eecr1 |= ((pEventCfg->Source << 18U) & HRTIM_EECR1_EE4SRC); 8005568: 687b ldr r3, [r7, #4] 800556a: 681b ldr r3, [r3, #0] 800556c: 049b lsls r3, r3, #18 800556e: f403 2340 and.w r3, r3, #786432 @ 0xc0000 8005572: 69fa ldr r2, [r7, #28] 8005574: 4313 orrs r3, r2 8005576: 61fb str r3, [r7, #28] hrtim_eecr1 |= ((pEventCfg->Polarity << 18U) & HRTIM_EECR1_EE4POL); 8005578: 687b ldr r3, [r7, #4] 800557a: 685b ldr r3, [r3, #4] 800557c: 049b lsls r3, r3, #18 800557e: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8005582: 69fa ldr r2, [r7, #28] 8005584: 4313 orrs r3, r2 8005586: 61fb str r3, [r7, #28] hrtim_eecr1 |= ((pEventCfg->Sensitivity << 18U) & HRTIM_EECR1_EE4SNS); 8005588: 687b ldr r3, [r7, #4] 800558a: 689b ldr r3, [r3, #8] 800558c: 049b lsls r3, r3, #18 800558e: f403 03c0 and.w r3, r3, #6291456 @ 0x600000 8005592: 69fa ldr r2, [r7, #28] 8005594: 4313 orrs r3, r2 8005596: 61fb str r3, [r7, #28] /* Update the HRTIM registers (all bitfields but EE4FAST bit) */ hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1; 8005598: 68fb ldr r3, [r7, #12] 800559a: 681b ldr r3, [r3, #0] 800559c: 69fa ldr r2, [r7, #28] 800559e: f8c3 23b0 str.w r2, [r3, #944] @ 0x3b0 /* Update the HRTIM registers (EE4FAST bit) */ hrtim_eecr1 |= ((pEventCfg->FastMode << 18U) & HRTIM_EECR1_EE4FAST); 80055a2: 687b ldr r3, [r7, #4] 80055a4: 691b ldr r3, [r3, #16] 80055a6: 049b lsls r3, r3, #18 80055a8: f403 0300 and.w r3, r3, #8388608 @ 0x800000 80055ac: 69fa ldr r2, [r7, #28] 80055ae: 4313 orrs r3, r2 80055b0: 61fb str r3, [r7, #28] hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1; 80055b2: 68fb ldr r3, [r7, #12] 80055b4: 681b ldr r3, [r3, #0] 80055b6: 69fa ldr r2, [r7, #28] 80055b8: f8c3 23b0 str.w r2, [r3, #944] @ 0x3b0 break; 80055bc: e128 b.n 8005810 } case HRTIM_EVENT_5: { hrtim_eecr1 &= ~(HRTIM_EECR1_EE5SRC | HRTIM_EECR1_EE5POL | HRTIM_EECR1_EE5SNS | HRTIM_EECR1_EE5FAST); 80055be: 69fb ldr r3, [r7, #28] 80055c0: f023 537c bic.w r3, r3, #1056964608 @ 0x3f000000 80055c4: 61fb str r3, [r7, #28] hrtim_eecr1 |= ((pEventCfg->Source << 24U) & HRTIM_EECR1_EE5SRC); 80055c6: 687b ldr r3, [r7, #4] 80055c8: 681b ldr r3, [r3, #0] 80055ca: 061b lsls r3, r3, #24 80055cc: f003 7340 and.w r3, r3, #50331648 @ 0x3000000 80055d0: 69fa ldr r2, [r7, #28] 80055d2: 4313 orrs r3, r2 80055d4: 61fb str r3, [r7, #28] hrtim_eecr1 |= ((pEventCfg->Polarity << 24U) & HRTIM_EECR1_EE5POL); 80055d6: 687b ldr r3, [r7, #4] 80055d8: 685b ldr r3, [r3, #4] 80055da: 061b lsls r3, r3, #24 80055dc: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 80055e0: 69fa ldr r2, [r7, #28] 80055e2: 4313 orrs r3, r2 80055e4: 61fb str r3, [r7, #28] hrtim_eecr1 |= ((pEventCfg->Sensitivity << 24U) & HRTIM_EECR1_EE5SNS); 80055e6: 687b ldr r3, [r7, #4] 80055e8: 689b ldr r3, [r3, #8] 80055ea: 061b lsls r3, r3, #24 80055ec: f003 53c0 and.w r3, r3, #402653184 @ 0x18000000 80055f0: 69fa ldr r2, [r7, #28] 80055f2: 4313 orrs r3, r2 80055f4: 61fb str r3, [r7, #28] /* Update the HRTIM registers (all bitfields but EE5FAST bit) */ hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1; 80055f6: 68fb ldr r3, [r7, #12] 80055f8: 681b ldr r3, [r3, #0] 80055fa: 69fa ldr r2, [r7, #28] 80055fc: f8c3 23b0 str.w r2, [r3, #944] @ 0x3b0 /* Update the HRTIM registers (EE5FAST bit) */ hrtim_eecr1 |= ((pEventCfg->FastMode << 24U) & HRTIM_EECR1_EE5FAST); 8005600: 687b ldr r3, [r7, #4] 8005602: 691b ldr r3, [r3, #16] 8005604: 061b lsls r3, r3, #24 8005606: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800560a: 69fa ldr r2, [r7, #28] 800560c: 4313 orrs r3, r2 800560e: 61fb str r3, [r7, #28] hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1; 8005610: 68fb ldr r3, [r7, #12] 8005612: 681b ldr r3, [r3, #0] 8005614: 69fa ldr r2, [r7, #28] 8005616: f8c3 23b0 str.w r2, [r3, #944] @ 0x3b0 break; 800561a: e0f9 b.n 8005810 } case HRTIM_EVENT_6: { hrtim_eecr2 &= ~(HRTIM_EECR2_EE6SRC | HRTIM_EECR2_EE6POL | HRTIM_EECR2_EE6SNS); 800561c: 69bb ldr r3, [r7, #24] 800561e: f023 031f bic.w r3, r3, #31 8005622: 61bb str r3, [r7, #24] hrtim_eecr2 |= (pEventCfg->Source & HRTIM_EECR2_EE6SRC); 8005624: 687b ldr r3, [r7, #4] 8005626: 681b ldr r3, [r3, #0] 8005628: f003 0303 and.w r3, r3, #3 800562c: 69ba ldr r2, [r7, #24] 800562e: 4313 orrs r3, r2 8005630: 61bb str r3, [r7, #24] hrtim_eecr2 |= (pEventCfg->Polarity & HRTIM_EECR2_EE6POL); 8005632: 687b ldr r3, [r7, #4] 8005634: 685b ldr r3, [r3, #4] 8005636: f003 0304 and.w r3, r3, #4 800563a: 69ba ldr r2, [r7, #24] 800563c: 4313 orrs r3, r2 800563e: 61bb str r3, [r7, #24] hrtim_eecr2 |= (pEventCfg->Sensitivity & HRTIM_EECR2_EE6SNS); 8005640: 687b ldr r3, [r7, #4] 8005642: 689b ldr r3, [r3, #8] 8005644: f003 0318 and.w r3, r3, #24 8005648: 69ba ldr r2, [r7, #24] 800564a: 4313 orrs r3, r2 800564c: 61bb str r3, [r7, #24] hrtim_eecr3 &= ~(HRTIM_EECR3_EE6F); 800564e: 697b ldr r3, [r7, #20] 8005650: f023 030f bic.w r3, r3, #15 8005654: 617b str r3, [r7, #20] hrtim_eecr3 |= (pEventCfg->Filter & HRTIM_EECR3_EE6F); 8005656: 687b ldr r3, [r7, #4] 8005658: 68db ldr r3, [r3, #12] 800565a: f003 030f and.w r3, r3, #15 800565e: 697a ldr r2, [r7, #20] 8005660: 4313 orrs r3, r2 8005662: 617b str r3, [r7, #20] /* Update the HRTIM registers */ hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2; 8005664: 68fb ldr r3, [r7, #12] 8005666: 681b ldr r3, [r3, #0] 8005668: 69ba ldr r2, [r7, #24] 800566a: f8c3 23b4 str.w r2, [r3, #948] @ 0x3b4 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3; 800566e: 68fb ldr r3, [r7, #12] 8005670: 681b ldr r3, [r3, #0] 8005672: 697a ldr r2, [r7, #20] 8005674: f8c3 23b8 str.w r2, [r3, #952] @ 0x3b8 break; 8005678: e0ca b.n 8005810 } case HRTIM_EVENT_7: { hrtim_eecr2 &= ~(HRTIM_EECR2_EE7SRC | HRTIM_EECR2_EE7POL | HRTIM_EECR2_EE7SNS); 800567a: 69bb ldr r3, [r7, #24] 800567c: f423 63f8 bic.w r3, r3, #1984 @ 0x7c0 8005680: 61bb str r3, [r7, #24] hrtim_eecr2 |= ((pEventCfg->Source << 6U) & HRTIM_EECR2_EE7SRC); 8005682: 687b ldr r3, [r7, #4] 8005684: 681b ldr r3, [r3, #0] 8005686: 019b lsls r3, r3, #6 8005688: b2db uxtb r3, r3 800568a: 69ba ldr r2, [r7, #24] 800568c: 4313 orrs r3, r2 800568e: 61bb str r3, [r7, #24] hrtim_eecr2 |= ((pEventCfg->Polarity << 6U) & HRTIM_EECR2_EE7POL); 8005690: 687b ldr r3, [r7, #4] 8005692: 685b ldr r3, [r3, #4] 8005694: 019b lsls r3, r3, #6 8005696: f403 7380 and.w r3, r3, #256 @ 0x100 800569a: 69ba ldr r2, [r7, #24] 800569c: 4313 orrs r3, r2 800569e: 61bb str r3, [r7, #24] hrtim_eecr2 |= ((pEventCfg->Sensitivity << 6U) & HRTIM_EECR2_EE7SNS); 80056a0: 687b ldr r3, [r7, #4] 80056a2: 689b ldr r3, [r3, #8] 80056a4: 019b lsls r3, r3, #6 80056a6: f403 63c0 and.w r3, r3, #1536 @ 0x600 80056aa: 69ba ldr r2, [r7, #24] 80056ac: 4313 orrs r3, r2 80056ae: 61bb str r3, [r7, #24] hrtim_eecr3 &= ~(HRTIM_EECR3_EE7F); 80056b0: 697b ldr r3, [r7, #20] 80056b2: f423 7370 bic.w r3, r3, #960 @ 0x3c0 80056b6: 617b str r3, [r7, #20] hrtim_eecr3 |= ((pEventCfg->Filter << 6U) & HRTIM_EECR3_EE7F); 80056b8: 687b ldr r3, [r7, #4] 80056ba: 68db ldr r3, [r3, #12] 80056bc: 019b lsls r3, r3, #6 80056be: f403 7370 and.w r3, r3, #960 @ 0x3c0 80056c2: 697a ldr r2, [r7, #20] 80056c4: 4313 orrs r3, r2 80056c6: 617b str r3, [r7, #20] /* Update the HRTIM registers */ hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2; 80056c8: 68fb ldr r3, [r7, #12] 80056ca: 681b ldr r3, [r3, #0] 80056cc: 69ba ldr r2, [r7, #24] 80056ce: f8c3 23b4 str.w r2, [r3, #948] @ 0x3b4 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3; 80056d2: 68fb ldr r3, [r7, #12] 80056d4: 681b ldr r3, [r3, #0] 80056d6: 697a ldr r2, [r7, #20] 80056d8: f8c3 23b8 str.w r2, [r3, #952] @ 0x3b8 break; 80056dc: e098 b.n 8005810 } case HRTIM_EVENT_8: { hrtim_eecr2 &= ~(HRTIM_EECR2_EE8SRC | HRTIM_EECR2_EE8POL | HRTIM_EECR2_EE8SNS); 80056de: 69bb ldr r3, [r7, #24] 80056e0: f423 33f8 bic.w r3, r3, #126976 @ 0x1f000 80056e4: 61bb str r3, [r7, #24] hrtim_eecr2 |= ((pEventCfg->Source << 12U) & HRTIM_EECR2_EE8SRC); 80056e6: 687b ldr r3, [r7, #4] 80056e8: 681b ldr r3, [r3, #0] 80056ea: 031b lsls r3, r3, #12 80056ec: f403 5340 and.w r3, r3, #12288 @ 0x3000 80056f0: 69ba ldr r2, [r7, #24] 80056f2: 4313 orrs r3, r2 80056f4: 61bb str r3, [r7, #24] hrtim_eecr2 |= ((pEventCfg->Polarity << 12U) & HRTIM_EECR2_EE8POL); 80056f6: 687b ldr r3, [r7, #4] 80056f8: 685b ldr r3, [r3, #4] 80056fa: 031b lsls r3, r3, #12 80056fc: f403 4380 and.w r3, r3, #16384 @ 0x4000 8005700: 69ba ldr r2, [r7, #24] 8005702: 4313 orrs r3, r2 8005704: 61bb str r3, [r7, #24] hrtim_eecr2 |= ((pEventCfg->Sensitivity << 12U) & HRTIM_EECR2_EE8SNS); 8005706: 687b ldr r3, [r7, #4] 8005708: 689b ldr r3, [r3, #8] 800570a: 031b lsls r3, r3, #12 800570c: f403 33c0 and.w r3, r3, #98304 @ 0x18000 8005710: 69ba ldr r2, [r7, #24] 8005712: 4313 orrs r3, r2 8005714: 61bb str r3, [r7, #24] hrtim_eecr3 &= ~(HRTIM_EECR3_EE8F); 8005716: 697b ldr r3, [r7, #20] 8005718: f423 4370 bic.w r3, r3, #61440 @ 0xf000 800571c: 617b str r3, [r7, #20] hrtim_eecr3 |= ((pEventCfg->Filter << 12U) & HRTIM_EECR3_EE8F); 800571e: 687b ldr r3, [r7, #4] 8005720: 68db ldr r3, [r3, #12] 8005722: 031b lsls r3, r3, #12 8005724: b29b uxth r3, r3 8005726: 697a ldr r2, [r7, #20] 8005728: 4313 orrs r3, r2 800572a: 617b str r3, [r7, #20] /* Update the HRTIM registers */ hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2; 800572c: 68fb ldr r3, [r7, #12] 800572e: 681b ldr r3, [r3, #0] 8005730: 69ba ldr r2, [r7, #24] 8005732: f8c3 23b4 str.w r2, [r3, #948] @ 0x3b4 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3; 8005736: 68fb ldr r3, [r7, #12] 8005738: 681b ldr r3, [r3, #0] 800573a: 697a ldr r2, [r7, #20] 800573c: f8c3 23b8 str.w r2, [r3, #952] @ 0x3b8 break; 8005740: e066 b.n 8005810 } case HRTIM_EVENT_9: { hrtim_eecr2 &= ~(HRTIM_EECR2_EE9SRC | HRTIM_EECR2_EE9POL | HRTIM_EECR2_EE9SNS); 8005742: 69bb ldr r3, [r7, #24] 8005744: f423 03f8 bic.w r3, r3, #8126464 @ 0x7c0000 8005748: 61bb str r3, [r7, #24] hrtim_eecr2 |= ((pEventCfg->Source << 18U) & HRTIM_EECR2_EE9SRC); 800574a: 687b ldr r3, [r7, #4] 800574c: 681b ldr r3, [r3, #0] 800574e: 049b lsls r3, r3, #18 8005750: f403 2340 and.w r3, r3, #786432 @ 0xc0000 8005754: 69ba ldr r2, [r7, #24] 8005756: 4313 orrs r3, r2 8005758: 61bb str r3, [r7, #24] hrtim_eecr2 |= ((pEventCfg->Polarity << 18U) & HRTIM_EECR2_EE9POL); 800575a: 687b ldr r3, [r7, #4] 800575c: 685b ldr r3, [r3, #4] 800575e: 049b lsls r3, r3, #18 8005760: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8005764: 69ba ldr r2, [r7, #24] 8005766: 4313 orrs r3, r2 8005768: 61bb str r3, [r7, #24] hrtim_eecr2 |= ((pEventCfg->Sensitivity << 18U) & HRTIM_EECR2_EE9SNS); 800576a: 687b ldr r3, [r7, #4] 800576c: 689b ldr r3, [r3, #8] 800576e: 049b lsls r3, r3, #18 8005770: f403 03c0 and.w r3, r3, #6291456 @ 0x600000 8005774: 69ba ldr r2, [r7, #24] 8005776: 4313 orrs r3, r2 8005778: 61bb str r3, [r7, #24] hrtim_eecr3 &= ~(HRTIM_EECR3_EE9F); 800577a: 697b ldr r3, [r7, #20] 800577c: f423 1370 bic.w r3, r3, #3932160 @ 0x3c0000 8005780: 617b str r3, [r7, #20] hrtim_eecr3 |= ((pEventCfg->Filter << 18U) & HRTIM_EECR3_EE9F); 8005782: 687b ldr r3, [r7, #4] 8005784: 68db ldr r3, [r3, #12] 8005786: 049b lsls r3, r3, #18 8005788: f403 1370 and.w r3, r3, #3932160 @ 0x3c0000 800578c: 697a ldr r2, [r7, #20] 800578e: 4313 orrs r3, r2 8005790: 617b str r3, [r7, #20] /* Update the HRTIM registers */ hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2; 8005792: 68fb ldr r3, [r7, #12] 8005794: 681b ldr r3, [r3, #0] 8005796: 69ba ldr r2, [r7, #24] 8005798: f8c3 23b4 str.w r2, [r3, #948] @ 0x3b4 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3; 800579c: 68fb ldr r3, [r7, #12] 800579e: 681b ldr r3, [r3, #0] 80057a0: 697a ldr r2, [r7, #20] 80057a2: f8c3 23b8 str.w r2, [r3, #952] @ 0x3b8 break; 80057a6: e033 b.n 8005810 } case HRTIM_EVENT_10: { hrtim_eecr2 &= ~(HRTIM_EECR2_EE10SRC | HRTIM_EECR2_EE10POL | HRTIM_EECR2_EE10SNS); 80057a8: 69bb ldr r3, [r7, #24] 80057aa: f023 53f8 bic.w r3, r3, #520093696 @ 0x1f000000 80057ae: 61bb str r3, [r7, #24] hrtim_eecr2 |= ((pEventCfg->Source << 24U) & HRTIM_EECR2_EE10SRC); 80057b0: 687b ldr r3, [r7, #4] 80057b2: 681b ldr r3, [r3, #0] 80057b4: 061b lsls r3, r3, #24 80057b6: f003 7340 and.w r3, r3, #50331648 @ 0x3000000 80057ba: 69ba ldr r2, [r7, #24] 80057bc: 4313 orrs r3, r2 80057be: 61bb str r3, [r7, #24] hrtim_eecr2 |= ((pEventCfg->Polarity << 24U) & HRTIM_EECR2_EE10POL); 80057c0: 687b ldr r3, [r7, #4] 80057c2: 685b ldr r3, [r3, #4] 80057c4: 061b lsls r3, r3, #24 80057c6: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 80057ca: 69ba ldr r2, [r7, #24] 80057cc: 4313 orrs r3, r2 80057ce: 61bb str r3, [r7, #24] hrtim_eecr2 |= ((pEventCfg->Sensitivity << 24U) & HRTIM_EECR2_EE10SNS); 80057d0: 687b ldr r3, [r7, #4] 80057d2: 689b ldr r3, [r3, #8] 80057d4: 061b lsls r3, r3, #24 80057d6: f003 53c0 and.w r3, r3, #402653184 @ 0x18000000 80057da: 69ba ldr r2, [r7, #24] 80057dc: 4313 orrs r3, r2 80057de: 61bb str r3, [r7, #24] hrtim_eecr3 &= ~(HRTIM_EECR3_EE10F); 80057e0: 697b ldr r3, [r7, #20] 80057e2: f023 6370 bic.w r3, r3, #251658240 @ 0xf000000 80057e6: 617b str r3, [r7, #20] hrtim_eecr3 |= ((pEventCfg->Filter << 24U) & HRTIM_EECR3_EE10F); 80057e8: 687b ldr r3, [r7, #4] 80057ea: 68db ldr r3, [r3, #12] 80057ec: 061b lsls r3, r3, #24 80057ee: f003 6370 and.w r3, r3, #251658240 @ 0xf000000 80057f2: 697a ldr r2, [r7, #20] 80057f4: 4313 orrs r3, r2 80057f6: 617b str r3, [r7, #20] /* Update the HRTIM registers */ hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2; 80057f8: 68fb ldr r3, [r7, #12] 80057fa: 681b ldr r3, [r3, #0] 80057fc: 69ba ldr r2, [r7, #24] 80057fe: f8c3 23b4 str.w r2, [r3, #948] @ 0x3b4 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3; 8005802: 68fb ldr r3, [r7, #12] 8005804: 681b ldr r3, [r3, #0] 8005806: 697a ldr r2, [r7, #20] 8005808: f8c3 23b8 str.w r2, [r3, #952] @ 0x3b8 break; 800580c: e000 b.n 8005810 } default: break; 800580e: bf00 nop } } 8005810: bf00 nop 8005812: 3724 adds r7, #36 @ 0x24 8005814: 46bd mov sp, r7 8005816: f85d 7b04 ldr.w r7, [sp], #4 800581a: 4770 bx lr 0800581c : * @param TimerIdx Timer index * @retval None */ static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx) { 800581c: b480 push {r7} 800581e: b083 sub sp, #12 8005820: af00 add r7, sp, #0 8005822: 6078 str r0, [r7, #4] 8005824: 6039 str r1, [r7, #0] switch (TimerIdx) 8005826: 683b ldr r3, [r7, #0] 8005828: 2b06 cmp r3, #6 800582a: d85e bhi.n 80058ea 800582c: a201 add r2, pc, #4 @ (adr r2, 8005834 ) 800582e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8005832: bf00 nop 8005834: 08005867 .word 0x08005867 8005838: 0800587d .word 0x0800587d 800583c: 08005893 .word 0x08005893 8005840: 080058a9 .word 0x080058a9 8005844: 080058bf .word 0x080058bf 8005848: 080058d5 .word 0x080058d5 800584c: 08005851 .word 0x08005851 { case HRTIM_TIMERINDEX_MASTER: { hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_MSWU; 8005850: 687b ldr r3, [r7, #4] 8005852: 681b ldr r3, [r3, #0] 8005854: f8d3 2384 ldr.w r2, [r3, #900] @ 0x384 8005858: 687b ldr r3, [r7, #4] 800585a: 681b ldr r3, [r3, #0] 800585c: f042 0201 orr.w r2, r2, #1 8005860: f8c3 2384 str.w r2, [r3, #900] @ 0x384 break; 8005864: e042 b.n 80058ec } case HRTIM_TIMERINDEX_TIMER_A: { hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TASWU; 8005866: 687b ldr r3, [r7, #4] 8005868: 681b ldr r3, [r3, #0] 800586a: f8d3 2384 ldr.w r2, [r3, #900] @ 0x384 800586e: 687b ldr r3, [r7, #4] 8005870: 681b ldr r3, [r3, #0] 8005872: f042 0202 orr.w r2, r2, #2 8005876: f8c3 2384 str.w r2, [r3, #900] @ 0x384 break; 800587a: e037 b.n 80058ec } case HRTIM_TIMERINDEX_TIMER_B: { hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TBSWU; 800587c: 687b ldr r3, [r7, #4] 800587e: 681b ldr r3, [r3, #0] 8005880: f8d3 2384 ldr.w r2, [r3, #900] @ 0x384 8005884: 687b ldr r3, [r7, #4] 8005886: 681b ldr r3, [r3, #0] 8005888: f042 0204 orr.w r2, r2, #4 800588c: f8c3 2384 str.w r2, [r3, #900] @ 0x384 break; 8005890: e02c b.n 80058ec } case HRTIM_TIMERINDEX_TIMER_C: { hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TCSWU; 8005892: 687b ldr r3, [r7, #4] 8005894: 681b ldr r3, [r3, #0] 8005896: f8d3 2384 ldr.w r2, [r3, #900] @ 0x384 800589a: 687b ldr r3, [r7, #4] 800589c: 681b ldr r3, [r3, #0] 800589e: f042 0208 orr.w r2, r2, #8 80058a2: f8c3 2384 str.w r2, [r3, #900] @ 0x384 break; 80058a6: e021 b.n 80058ec } case HRTIM_TIMERINDEX_TIMER_D: { hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TDSWU; 80058a8: 687b ldr r3, [r7, #4] 80058aa: 681b ldr r3, [r3, #0] 80058ac: f8d3 2384 ldr.w r2, [r3, #900] @ 0x384 80058b0: 687b ldr r3, [r7, #4] 80058b2: 681b ldr r3, [r3, #0] 80058b4: f042 0210 orr.w r2, r2, #16 80058b8: f8c3 2384 str.w r2, [r3, #900] @ 0x384 break; 80058bc: e016 b.n 80058ec } case HRTIM_TIMERINDEX_TIMER_E: { hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TESWU; 80058be: 687b ldr r3, [r7, #4] 80058c0: 681b ldr r3, [r3, #0] 80058c2: f8d3 2384 ldr.w r2, [r3, #900] @ 0x384 80058c6: 687b ldr r3, [r7, #4] 80058c8: 681b ldr r3, [r3, #0] 80058ca: f042 0220 orr.w r2, r2, #32 80058ce: f8c3 2384 str.w r2, [r3, #900] @ 0x384 break; 80058d2: e00b b.n 80058ec } case HRTIM_TIMERINDEX_TIMER_F: { hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TFSWU; 80058d4: 687b ldr r3, [r7, #4] 80058d6: 681b ldr r3, [r3, #0] 80058d8: f8d3 2384 ldr.w r2, [r3, #900] @ 0x384 80058dc: 687b ldr r3, [r7, #4] 80058de: 681b ldr r3, [r3, #0] 80058e0: f042 0240 orr.w r2, r2, #64 @ 0x40 80058e4: f8c3 2384 str.w r2, [r3, #900] @ 0x384 break; 80058e8: e000 b.n 80058ec } default: break; 80058ea: bf00 nop } } 80058ec: bf00 nop 80058ee: 370c adds r7, #12 80058f0: 46bd mov sp, r7 80058f2: f85d 7b04 ldr.w r7, [sp], #4 80058f6: 4770 bx lr 080058f8 : * cleared before returning the status. If the flag is not cleared within * 50 microseconds, HAL_TIMEOUT status is reported. * @retval HAL Status */ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) { 80058f8: b480 push {r7} 80058fa: b085 sub sp, #20 80058fc: af00 add r7, sp, #0 80058fe: 6078 str r0, [r7, #4] uint32_t wait_loop_index; assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) 8005900: 687b ldr r3, [r7, #4] 8005902: 2b00 cmp r3, #0 8005904: d141 bne.n 800598a { /* If current range is range 2 */ if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) 8005906: 4b4b ldr r3, [pc, #300] @ (8005a34 ) 8005908: 681b ldr r3, [r3, #0] 800590a: f403 63c0 and.w r3, r3, #1536 @ 0x600 800590e: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8005912: d131 bne.n 8005978 { /* Make sure Range 1 Boost is enabled */ CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); 8005914: 4b47 ldr r3, [pc, #284] @ (8005a34 ) 8005916: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800591a: 4a46 ldr r2, [pc, #280] @ (8005a34 ) 800591c: f423 7380 bic.w r3, r3, #256 @ 0x100 8005920: f8c2 3080 str.w r3, [r2, #128] @ 0x80 /* Set Range 1 */ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); 8005924: 4b43 ldr r3, [pc, #268] @ (8005a34 ) 8005926: 681b ldr r3, [r3, #0] 8005928: f423 63c0 bic.w r3, r3, #1536 @ 0x600 800592c: 4a41 ldr r2, [pc, #260] @ (8005a34 ) 800592e: f443 7300 orr.w r3, r3, #512 @ 0x200 8005932: 6013 str r3, [r2, #0] /* Wait until VOSF is cleared */ wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U; 8005934: 4b40 ldr r3, [pc, #256] @ (8005a38 ) 8005936: 681b ldr r3, [r3, #0] 8005938: 2232 movs r2, #50 @ 0x32 800593a: fb02 f303 mul.w r3, r2, r3 800593e: 4a3f ldr r2, [pc, #252] @ (8005a3c ) 8005940: fba2 2303 umull r2, r3, r2, r3 8005944: 0c9b lsrs r3, r3, #18 8005946: 3301 adds r3, #1 8005948: 60fb str r3, [r7, #12] while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) 800594a: e002 b.n 8005952 { wait_loop_index--; 800594c: 68fb ldr r3, [r7, #12] 800594e: 3b01 subs r3, #1 8005950: 60fb str r3, [r7, #12] while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) 8005952: 4b38 ldr r3, [pc, #224] @ (8005a34 ) 8005954: 695b ldr r3, [r3, #20] 8005956: f403 6380 and.w r3, r3, #1024 @ 0x400 800595a: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800595e: d102 bne.n 8005966 8005960: 68fb ldr r3, [r7, #12] 8005962: 2b00 cmp r3, #0 8005964: d1f2 bne.n 800594c } if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) 8005966: 4b33 ldr r3, [pc, #204] @ (8005a34 ) 8005968: 695b ldr r3, [r3, #20] 800596a: f403 6380 and.w r3, r3, #1024 @ 0x400 800596e: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8005972: d158 bne.n 8005a26 { return HAL_TIMEOUT; 8005974: 2303 movs r3, #3 8005976: e057 b.n 8005a28 } /* If current range is range 1 normal or boost mode */ else { /* Enable Range 1 Boost (no issue if bit already reset) */ CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); 8005978: 4b2e ldr r3, [pc, #184] @ (8005a34 ) 800597a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800597e: 4a2d ldr r2, [pc, #180] @ (8005a34 ) 8005980: f423 7380 bic.w r3, r3, #256 @ 0x100 8005984: f8c2 3080 str.w r3, [r2, #128] @ 0x80 8005988: e04d b.n 8005a26 } } else if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) 800598a: 687b ldr r3, [r7, #4] 800598c: f5b3 7f00 cmp.w r3, #512 @ 0x200 8005990: d141 bne.n 8005a16 { /* If current range is range 2 */ if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) 8005992: 4b28 ldr r3, [pc, #160] @ (8005a34 ) 8005994: 681b ldr r3, [r3, #0] 8005996: f403 63c0 and.w r3, r3, #1536 @ 0x600 800599a: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800599e: d131 bne.n 8005a04 { /* Make sure Range 1 Boost is disabled */ SET_BIT(PWR->CR5, PWR_CR5_R1MODE); 80059a0: 4b24 ldr r3, [pc, #144] @ (8005a34 ) 80059a2: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80059a6: 4a23 ldr r2, [pc, #140] @ (8005a34 ) 80059a8: f443 7380 orr.w r3, r3, #256 @ 0x100 80059ac: f8c2 3080 str.w r3, [r2, #128] @ 0x80 /* Set Range 1 */ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); 80059b0: 4b20 ldr r3, [pc, #128] @ (8005a34 ) 80059b2: 681b ldr r3, [r3, #0] 80059b4: f423 63c0 bic.w r3, r3, #1536 @ 0x600 80059b8: 4a1e ldr r2, [pc, #120] @ (8005a34 ) 80059ba: f443 7300 orr.w r3, r3, #512 @ 0x200 80059be: 6013 str r3, [r2, #0] /* Wait until VOSF is cleared */ wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U; 80059c0: 4b1d ldr r3, [pc, #116] @ (8005a38 ) 80059c2: 681b ldr r3, [r3, #0] 80059c4: 2232 movs r2, #50 @ 0x32 80059c6: fb02 f303 mul.w r3, r2, r3 80059ca: 4a1c ldr r2, [pc, #112] @ (8005a3c ) 80059cc: fba2 2303 umull r2, r3, r2, r3 80059d0: 0c9b lsrs r3, r3, #18 80059d2: 3301 adds r3, #1 80059d4: 60fb str r3, [r7, #12] while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) 80059d6: e002 b.n 80059de { wait_loop_index--; 80059d8: 68fb ldr r3, [r7, #12] 80059da: 3b01 subs r3, #1 80059dc: 60fb str r3, [r7, #12] while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) 80059de: 4b15 ldr r3, [pc, #84] @ (8005a34 ) 80059e0: 695b ldr r3, [r3, #20] 80059e2: f403 6380 and.w r3, r3, #1024 @ 0x400 80059e6: f5b3 6f80 cmp.w r3, #1024 @ 0x400 80059ea: d102 bne.n 80059f2 80059ec: 68fb ldr r3, [r7, #12] 80059ee: 2b00 cmp r3, #0 80059f0: d1f2 bne.n 80059d8 } if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) 80059f2: 4b10 ldr r3, [pc, #64] @ (8005a34 ) 80059f4: 695b ldr r3, [r3, #20] 80059f6: f403 6380 and.w r3, r3, #1024 @ 0x400 80059fa: f5b3 6f80 cmp.w r3, #1024 @ 0x400 80059fe: d112 bne.n 8005a26 { return HAL_TIMEOUT; 8005a00: 2303 movs r3, #3 8005a02: e011 b.n 8005a28 } /* If current range is range 1 normal or boost mode */ else { /* Disable Range 1 Boost (no issue if bit already set) */ SET_BIT(PWR->CR5, PWR_CR5_R1MODE); 8005a04: 4b0b ldr r3, [pc, #44] @ (8005a34 ) 8005a06: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8005a0a: 4a0a ldr r2, [pc, #40] @ (8005a34 ) 8005a0c: f443 7380 orr.w r3, r3, #256 @ 0x100 8005a10: f8c2 3080 str.w r3, [r2, #128] @ 0x80 8005a14: e007 b.n 8005a26 } } else { /* Set Range 2 */ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2); 8005a16: 4b07 ldr r3, [pc, #28] @ (8005a34 ) 8005a18: 681b ldr r3, [r3, #0] 8005a1a: f423 63c0 bic.w r3, r3, #1536 @ 0x600 8005a1e: 4a05 ldr r2, [pc, #20] @ (8005a34 ) 8005a20: f443 6380 orr.w r3, r3, #1024 @ 0x400 8005a24: 6013 str r3, [r2, #0] /* No need to wait for VOSF to be cleared for this transition */ /* PWR_CR5_R1MODE bit setting has no effect in Range 2 */ } return HAL_OK; 8005a26: 2300 movs r3, #0 } 8005a28: 4618 mov r0, r3 8005a2a: 3714 adds r7, #20 8005a2c: 46bd mov sp, r7 8005a2e: f85d 7b04 ldr.w r7, [sp], #4 8005a32: 4770 bx lr 8005a34: 40007000 .word 0x40007000 8005a38: 20000000 .word 0x20000000 8005a3c: 431bde83 .word 0x431bde83 08005a40 : * or to hand over control to the UCPD (which should therefore be * initialized before doing the disable). * @retval None */ void HAL_PWREx_DisableUCPDDeadBattery(void) { 8005a40: b480 push {r7} 8005a42: af00 add r7, sp, #0 /* Write 1 to disable the USB Type-C dead battery pull-down behavior */ SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS); 8005a44: 4b05 ldr r3, [pc, #20] @ (8005a5c ) 8005a46: 689b ldr r3, [r3, #8] 8005a48: 4a04 ldr r2, [pc, #16] @ (8005a5c ) 8005a4a: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8005a4e: 6093 str r3, [r2, #8] } 8005a50: bf00 nop 8005a52: 46bd mov sp, r7 8005a54: f85d 7b04 ldr.w r7, [sp], #4 8005a58: 4770 bx lr 8005a5a: bf00 nop 8005a5c: 40007000 .word 0x40007000 08005a60 : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8005a60: b580 push {r7, lr} 8005a62: b088 sub sp, #32 8005a64: af00 add r7, sp, #0 8005a66: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t temp_sysclksrc; uint32_t temp_pllckcfg; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8005a68: 687b ldr r3, [r7, #4] 8005a6a: 2b00 cmp r3, #0 8005a6c: d101 bne.n 8005a72 { return HAL_ERROR; 8005a6e: 2301 movs r3, #1 8005a70: e2fe b.n 8006070 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8005a72: 687b ldr r3, [r7, #4] 8005a74: 681b ldr r3, [r3, #0] 8005a76: f003 0301 and.w r3, r3, #1 8005a7a: 2b00 cmp r3, #0 8005a7c: d075 beq.n 8005b6a { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 8005a7e: 4b97 ldr r3, [pc, #604] @ (8005cdc ) 8005a80: 689b ldr r3, [r3, #8] 8005a82: f003 030c and.w r3, r3, #12 8005a86: 61bb str r3, [r7, #24] temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); 8005a88: 4b94 ldr r3, [pc, #592] @ (8005cdc ) 8005a8a: 68db ldr r3, [r3, #12] 8005a8c: f003 0303 and.w r3, r3, #3 8005a90: 617b str r3, [r7, #20] /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSE)) || (temp_sysclksrc == RCC_CFGR_SWS_HSE)) 8005a92: 69bb ldr r3, [r7, #24] 8005a94: 2b0c cmp r3, #12 8005a96: d102 bne.n 8005a9e 8005a98: 697b ldr r3, [r7, #20] 8005a9a: 2b03 cmp r3, #3 8005a9c: d002 beq.n 8005aa4 8005a9e: 69bb ldr r3, [r7, #24] 8005aa0: 2b08 cmp r3, #8 8005aa2: d10b bne.n 8005abc { if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8005aa4: 4b8d ldr r3, [pc, #564] @ (8005cdc ) 8005aa6: 681b ldr r3, [r3, #0] 8005aa8: f403 3300 and.w r3, r3, #131072 @ 0x20000 8005aac: 2b00 cmp r3, #0 8005aae: d05b beq.n 8005b68 8005ab0: 687b ldr r3, [r7, #4] 8005ab2: 685b ldr r3, [r3, #4] 8005ab4: 2b00 cmp r3, #0 8005ab6: d157 bne.n 8005b68 { return HAL_ERROR; 8005ab8: 2301 movs r3, #1 8005aba: e2d9 b.n 8006070 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8005abc: 687b ldr r3, [r7, #4] 8005abe: 685b ldr r3, [r3, #4] 8005ac0: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8005ac4: d106 bne.n 8005ad4 8005ac6: 4b85 ldr r3, [pc, #532] @ (8005cdc ) 8005ac8: 681b ldr r3, [r3, #0] 8005aca: 4a84 ldr r2, [pc, #528] @ (8005cdc ) 8005acc: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8005ad0: 6013 str r3, [r2, #0] 8005ad2: e01d b.n 8005b10 8005ad4: 687b ldr r3, [r7, #4] 8005ad6: 685b ldr r3, [r3, #4] 8005ad8: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 8005adc: d10c bne.n 8005af8 8005ade: 4b7f ldr r3, [pc, #508] @ (8005cdc ) 8005ae0: 681b ldr r3, [r3, #0] 8005ae2: 4a7e ldr r2, [pc, #504] @ (8005cdc ) 8005ae4: f443 2380 orr.w r3, r3, #262144 @ 0x40000 8005ae8: 6013 str r3, [r2, #0] 8005aea: 4b7c ldr r3, [pc, #496] @ (8005cdc ) 8005aec: 681b ldr r3, [r3, #0] 8005aee: 4a7b ldr r2, [pc, #492] @ (8005cdc ) 8005af0: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8005af4: 6013 str r3, [r2, #0] 8005af6: e00b b.n 8005b10 8005af8: 4b78 ldr r3, [pc, #480] @ (8005cdc ) 8005afa: 681b ldr r3, [r3, #0] 8005afc: 4a77 ldr r2, [pc, #476] @ (8005cdc ) 8005afe: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8005b02: 6013 str r3, [r2, #0] 8005b04: 4b75 ldr r3, [pc, #468] @ (8005cdc ) 8005b06: 681b ldr r3, [r3, #0] 8005b08: 4a74 ldr r2, [pc, #464] @ (8005cdc ) 8005b0a: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8005b0e: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8005b10: 687b ldr r3, [r7, #4] 8005b12: 685b ldr r3, [r3, #4] 8005b14: 2b00 cmp r3, #0 8005b16: d013 beq.n 8005b40 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005b18: f7fb fec8 bl 80018ac 8005b1c: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 8005b1e: e008 b.n 8005b32 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8005b20: f7fb fec4 bl 80018ac 8005b24: 4602 mov r2, r0 8005b26: 693b ldr r3, [r7, #16] 8005b28: 1ad3 subs r3, r2, r3 8005b2a: 2b64 cmp r3, #100 @ 0x64 8005b2c: d901 bls.n 8005b32 { return HAL_TIMEOUT; 8005b2e: 2303 movs r3, #3 8005b30: e29e b.n 8006070 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 8005b32: 4b6a ldr r3, [pc, #424] @ (8005cdc ) 8005b34: 681b ldr r3, [r3, #0] 8005b36: f403 3300 and.w r3, r3, #131072 @ 0x20000 8005b3a: 2b00 cmp r3, #0 8005b3c: d0f0 beq.n 8005b20 8005b3e: e014 b.n 8005b6a } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005b40: f7fb feb4 bl 80018ac 8005b44: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) 8005b46: e008 b.n 8005b5a { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8005b48: f7fb feb0 bl 80018ac 8005b4c: 4602 mov r2, r0 8005b4e: 693b ldr r3, [r7, #16] 8005b50: 1ad3 subs r3, r2, r3 8005b52: 2b64 cmp r3, #100 @ 0x64 8005b54: d901 bls.n 8005b5a { return HAL_TIMEOUT; 8005b56: 2303 movs r3, #3 8005b58: e28a b.n 8006070 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) 8005b5a: 4b60 ldr r3, [pc, #384] @ (8005cdc ) 8005b5c: 681b ldr r3, [r3, #0] 8005b5e: f403 3300 and.w r3, r3, #131072 @ 0x20000 8005b62: 2b00 cmp r3, #0 8005b64: d1f0 bne.n 8005b48 8005b66: e000 b.n 8005b6a if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8005b68: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8005b6a: 687b ldr r3, [r7, #4] 8005b6c: 681b ldr r3, [r3, #0] 8005b6e: f003 0302 and.w r3, r3, #2 8005b72: 2b00 cmp r3, #0 8005b74: d075 beq.n 8005c62 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 8005b76: 4b59 ldr r3, [pc, #356] @ (8005cdc ) 8005b78: 689b ldr r3, [r3, #8] 8005b7a: f003 030c and.w r3, r3, #12 8005b7e: 61bb str r3, [r7, #24] temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); 8005b80: 4b56 ldr r3, [pc, #344] @ (8005cdc ) 8005b82: 68db ldr r3, [r3, #12] 8005b84: f003 0303 and.w r3, r3, #3 8005b88: 617b str r3, [r7, #20] if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSI)) || (temp_sysclksrc == RCC_CFGR_SWS_HSI)) 8005b8a: 69bb ldr r3, [r7, #24] 8005b8c: 2b0c cmp r3, #12 8005b8e: d102 bne.n 8005b96 8005b90: 697b ldr r3, [r7, #20] 8005b92: 2b02 cmp r3, #2 8005b94: d002 beq.n 8005b9c 8005b96: 69bb ldr r3, [r7, #24] 8005b98: 2b04 cmp r3, #4 8005b9a: d11f bne.n 8005bdc { /* When HSI is used as system clock it will not be disabled */ if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 8005b9c: 4b4f ldr r3, [pc, #316] @ (8005cdc ) 8005b9e: 681b ldr r3, [r3, #0] 8005ba0: f403 6380 and.w r3, r3, #1024 @ 0x400 8005ba4: 2b00 cmp r3, #0 8005ba6: d005 beq.n 8005bb4 8005ba8: 687b ldr r3, [r7, #4] 8005baa: 68db ldr r3, [r3, #12] 8005bac: 2b00 cmp r3, #0 8005bae: d101 bne.n 8005bb4 { return HAL_ERROR; 8005bb0: 2301 movs r3, #1 8005bb2: e25d b.n 8006070 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8005bb4: 4b49 ldr r3, [pc, #292] @ (8005cdc ) 8005bb6: 685b ldr r3, [r3, #4] 8005bb8: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000 8005bbc: 687b ldr r3, [r7, #4] 8005bbe: 691b ldr r3, [r3, #16] 8005bc0: 061b lsls r3, r3, #24 8005bc2: 4946 ldr r1, [pc, #280] @ (8005cdc ) 8005bc4: 4313 orrs r3, r2 8005bc6: 604b str r3, [r1, #4] /* Adapt Systick interrupt period */ if (HAL_InitTick(uwTickPrio) != HAL_OK) 8005bc8: 4b45 ldr r3, [pc, #276] @ (8005ce0 ) 8005bca: 681b ldr r3, [r3, #0] 8005bcc: 4618 mov r0, r3 8005bce: f7fb fe21 bl 8001814 8005bd2: 4603 mov r3, r0 8005bd4: 2b00 cmp r3, #0 8005bd6: d043 beq.n 8005c60 { return HAL_ERROR; 8005bd8: 2301 movs r3, #1 8005bda: e249 b.n 8006070 } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8005bdc: 687b ldr r3, [r7, #4] 8005bde: 68db ldr r3, [r3, #12] 8005be0: 2b00 cmp r3, #0 8005be2: d023 beq.n 8005c2c { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8005be4: 4b3d ldr r3, [pc, #244] @ (8005cdc ) 8005be6: 681b ldr r3, [r3, #0] 8005be8: 4a3c ldr r2, [pc, #240] @ (8005cdc ) 8005bea: f443 7380 orr.w r3, r3, #256 @ 0x100 8005bee: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005bf0: f7fb fe5c bl 80018ac 8005bf4: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 8005bf6: e008 b.n 8005c0a { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8005bf8: f7fb fe58 bl 80018ac 8005bfc: 4602 mov r2, r0 8005bfe: 693b ldr r3, [r7, #16] 8005c00: 1ad3 subs r3, r2, r3 8005c02: 2b02 cmp r3, #2 8005c04: d901 bls.n 8005c0a { return HAL_TIMEOUT; 8005c06: 2303 movs r3, #3 8005c08: e232 b.n 8006070 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 8005c0a: 4b34 ldr r3, [pc, #208] @ (8005cdc ) 8005c0c: 681b ldr r3, [r3, #0] 8005c0e: f403 6380 and.w r3, r3, #1024 @ 0x400 8005c12: 2b00 cmp r3, #0 8005c14: d0f0 beq.n 8005bf8 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8005c16: 4b31 ldr r3, [pc, #196] @ (8005cdc ) 8005c18: 685b ldr r3, [r3, #4] 8005c1a: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000 8005c1e: 687b ldr r3, [r7, #4] 8005c20: 691b ldr r3, [r3, #16] 8005c22: 061b lsls r3, r3, #24 8005c24: 492d ldr r1, [pc, #180] @ (8005cdc ) 8005c26: 4313 orrs r3, r2 8005c28: 604b str r3, [r1, #4] 8005c2a: e01a b.n 8005c62 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8005c2c: 4b2b ldr r3, [pc, #172] @ (8005cdc ) 8005c2e: 681b ldr r3, [r3, #0] 8005c30: 4a2a ldr r2, [pc, #168] @ (8005cdc ) 8005c32: f423 7380 bic.w r3, r3, #256 @ 0x100 8005c36: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005c38: f7fb fe38 bl 80018ac 8005c3c: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) 8005c3e: e008 b.n 8005c52 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8005c40: f7fb fe34 bl 80018ac 8005c44: 4602 mov r2, r0 8005c46: 693b ldr r3, [r7, #16] 8005c48: 1ad3 subs r3, r2, r3 8005c4a: 2b02 cmp r3, #2 8005c4c: d901 bls.n 8005c52 { return HAL_TIMEOUT; 8005c4e: 2303 movs r3, #3 8005c50: e20e b.n 8006070 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) 8005c52: 4b22 ldr r3, [pc, #136] @ (8005cdc ) 8005c54: 681b ldr r3, [r3, #0] 8005c56: f403 6380 and.w r3, r3, #1024 @ 0x400 8005c5a: 2b00 cmp r3, #0 8005c5c: d1f0 bne.n 8005c40 8005c5e: e000 b.n 8005c62 if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 8005c60: bf00 nop } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8005c62: 687b ldr r3, [r7, #4] 8005c64: 681b ldr r3, [r3, #0] 8005c66: f003 0308 and.w r3, r3, #8 8005c6a: 2b00 cmp r3, #0 8005c6c: d041 beq.n 8005cf2 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 8005c6e: 687b ldr r3, [r7, #4] 8005c70: 695b ldr r3, [r3, #20] 8005c72: 2b00 cmp r3, #0 8005c74: d01c beq.n 8005cb0 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8005c76: 4b19 ldr r3, [pc, #100] @ (8005cdc ) 8005c78: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8005c7c: 4a17 ldr r2, [pc, #92] @ (8005cdc ) 8005c7e: f043 0301 orr.w r3, r3, #1 8005c82: f8c2 3094 str.w r3, [r2, #148] @ 0x94 /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005c86: f7fb fe11 bl 80018ac 8005c8a: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) 8005c8c: e008 b.n 8005ca0 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8005c8e: f7fb fe0d bl 80018ac 8005c92: 4602 mov r2, r0 8005c94: 693b ldr r3, [r7, #16] 8005c96: 1ad3 subs r3, r2, r3 8005c98: 2b02 cmp r3, #2 8005c9a: d901 bls.n 8005ca0 { return HAL_TIMEOUT; 8005c9c: 2303 movs r3, #3 8005c9e: e1e7 b.n 8006070 while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) 8005ca0: 4b0e ldr r3, [pc, #56] @ (8005cdc ) 8005ca2: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8005ca6: f003 0302 and.w r3, r3, #2 8005caa: 2b00 cmp r3, #0 8005cac: d0ef beq.n 8005c8e 8005cae: e020 b.n 8005cf2 } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8005cb0: 4b0a ldr r3, [pc, #40] @ (8005cdc ) 8005cb2: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8005cb6: 4a09 ldr r2, [pc, #36] @ (8005cdc ) 8005cb8: f023 0301 bic.w r3, r3, #1 8005cbc: f8c2 3094 str.w r3, [r2, #148] @ 0x94 /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005cc0: f7fb fdf4 bl 80018ac 8005cc4: 6138 str r0, [r7, #16] /* Wait till LSI is disabled */ while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) 8005cc6: e00d b.n 8005ce4 { if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8005cc8: f7fb fdf0 bl 80018ac 8005ccc: 4602 mov r2, r0 8005cce: 693b ldr r3, [r7, #16] 8005cd0: 1ad3 subs r3, r2, r3 8005cd2: 2b02 cmp r3, #2 8005cd4: d906 bls.n 8005ce4 { return HAL_TIMEOUT; 8005cd6: 2303 movs r3, #3 8005cd8: e1ca b.n 8006070 8005cda: bf00 nop 8005cdc: 40021000 .word 0x40021000 8005ce0: 20000004 .word 0x20000004 while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) 8005ce4: 4b8c ldr r3, [pc, #560] @ (8005f18 ) 8005ce6: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8005cea: f003 0302 and.w r3, r3, #2 8005cee: 2b00 cmp r3, #0 8005cf0: d1ea bne.n 8005cc8 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8005cf2: 687b ldr r3, [r7, #4] 8005cf4: 681b ldr r3, [r3, #0] 8005cf6: f003 0304 and.w r3, r3, #4 8005cfa: 2b00 cmp r3, #0 8005cfc: f000 80a6 beq.w 8005e4c { FlagStatus pwrclkchanged = RESET; 8005d00: 2300 movs r3, #0 8005d02: 77fb strb r3, [r7, #31] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain if necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U) 8005d04: 4b84 ldr r3, [pc, #528] @ (8005f18 ) 8005d06: 6d9b ldr r3, [r3, #88] @ 0x58 8005d08: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8005d0c: 2b00 cmp r3, #0 8005d0e: d101 bne.n 8005d14 8005d10: 2301 movs r3, #1 8005d12: e000 b.n 8005d16 8005d14: 2300 movs r3, #0 8005d16: 2b00 cmp r3, #0 8005d18: d00d beq.n 8005d36 { __HAL_RCC_PWR_CLK_ENABLE(); 8005d1a: 4b7f ldr r3, [pc, #508] @ (8005f18 ) 8005d1c: 6d9b ldr r3, [r3, #88] @ 0x58 8005d1e: 4a7e ldr r2, [pc, #504] @ (8005f18 ) 8005d20: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8005d24: 6593 str r3, [r2, #88] @ 0x58 8005d26: 4b7c ldr r3, [pc, #496] @ (8005f18 ) 8005d28: 6d9b ldr r3, [r3, #88] @ 0x58 8005d2a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8005d2e: 60fb str r3, [r7, #12] 8005d30: 68fb ldr r3, [r7, #12] pwrclkchanged = SET; 8005d32: 2301 movs r3, #1 8005d34: 77fb strb r3, [r7, #31] } if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 8005d36: 4b79 ldr r3, [pc, #484] @ (8005f1c ) 8005d38: 681b ldr r3, [r3, #0] 8005d3a: f403 7380 and.w r3, r3, #256 @ 0x100 8005d3e: 2b00 cmp r3, #0 8005d40: d118 bne.n 8005d74 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); 8005d42: 4b76 ldr r3, [pc, #472] @ (8005f1c ) 8005d44: 681b ldr r3, [r3, #0] 8005d46: 4a75 ldr r2, [pc, #468] @ (8005f1c ) 8005d48: f443 7380 orr.w r3, r3, #256 @ 0x100 8005d4c: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8005d4e: f7fb fdad bl 80018ac 8005d52: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 8005d54: e008 b.n 8005d68 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8005d56: f7fb fda9 bl 80018ac 8005d5a: 4602 mov r2, r0 8005d5c: 693b ldr r3, [r7, #16] 8005d5e: 1ad3 subs r3, r2, r3 8005d60: 2b02 cmp r3, #2 8005d62: d901 bls.n 8005d68 { return HAL_TIMEOUT; 8005d64: 2303 movs r3, #3 8005d66: e183 b.n 8006070 while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 8005d68: 4b6c ldr r3, [pc, #432] @ (8005f1c ) 8005d6a: 681b ldr r3, [r3, #0] 8005d6c: f403 7380 and.w r3, r3, #256 @ 0x100 8005d70: 2b00 cmp r3, #0 8005d72: d0f0 beq.n 8005d56 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8005d74: 687b ldr r3, [r7, #4] 8005d76: 689b ldr r3, [r3, #8] 8005d78: 2b01 cmp r3, #1 8005d7a: d108 bne.n 8005d8e 8005d7c: 4b66 ldr r3, [pc, #408] @ (8005f18 ) 8005d7e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8005d82: 4a65 ldr r2, [pc, #404] @ (8005f18 ) 8005d84: f043 0301 orr.w r3, r3, #1 8005d88: f8c2 3090 str.w r3, [r2, #144] @ 0x90 8005d8c: e024 b.n 8005dd8 8005d8e: 687b ldr r3, [r7, #4] 8005d90: 689b ldr r3, [r3, #8] 8005d92: 2b05 cmp r3, #5 8005d94: d110 bne.n 8005db8 8005d96: 4b60 ldr r3, [pc, #384] @ (8005f18 ) 8005d98: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8005d9c: 4a5e ldr r2, [pc, #376] @ (8005f18 ) 8005d9e: f043 0304 orr.w r3, r3, #4 8005da2: f8c2 3090 str.w r3, [r2, #144] @ 0x90 8005da6: 4b5c ldr r3, [pc, #368] @ (8005f18 ) 8005da8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8005dac: 4a5a ldr r2, [pc, #360] @ (8005f18 ) 8005dae: f043 0301 orr.w r3, r3, #1 8005db2: f8c2 3090 str.w r3, [r2, #144] @ 0x90 8005db6: e00f b.n 8005dd8 8005db8: 4b57 ldr r3, [pc, #348] @ (8005f18 ) 8005dba: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8005dbe: 4a56 ldr r2, [pc, #344] @ (8005f18 ) 8005dc0: f023 0301 bic.w r3, r3, #1 8005dc4: f8c2 3090 str.w r3, [r2, #144] @ 0x90 8005dc8: 4b53 ldr r3, [pc, #332] @ (8005f18 ) 8005dca: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8005dce: 4a52 ldr r2, [pc, #328] @ (8005f18 ) 8005dd0: f023 0304 bic.w r3, r3, #4 8005dd4: f8c2 3090 str.w r3, [r2, #144] @ 0x90 /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 8005dd8: 687b ldr r3, [r7, #4] 8005dda: 689b ldr r3, [r3, #8] 8005ddc: 2b00 cmp r3, #0 8005dde: d016 beq.n 8005e0e { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005de0: f7fb fd64 bl 80018ac 8005de4: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 8005de6: e00a b.n 8005dfe { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8005de8: f7fb fd60 bl 80018ac 8005dec: 4602 mov r2, r0 8005dee: 693b ldr r3, [r7, #16] 8005df0: 1ad3 subs r3, r2, r3 8005df2: f241 3288 movw r2, #5000 @ 0x1388 8005df6: 4293 cmp r3, r2 8005df8: d901 bls.n 8005dfe { return HAL_TIMEOUT; 8005dfa: 2303 movs r3, #3 8005dfc: e138 b.n 8006070 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 8005dfe: 4b46 ldr r3, [pc, #280] @ (8005f18 ) 8005e00: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8005e04: f003 0302 and.w r3, r3, #2 8005e08: 2b00 cmp r3, #0 8005e0a: d0ed beq.n 8005de8 8005e0c: e015 b.n 8005e3a } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005e0e: f7fb fd4d bl 80018ac 8005e12: 6138 str r0, [r7, #16] /* Wait till LSE is disabled */ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) 8005e14: e00a b.n 8005e2c { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8005e16: f7fb fd49 bl 80018ac 8005e1a: 4602 mov r2, r0 8005e1c: 693b ldr r3, [r7, #16] 8005e1e: 1ad3 subs r3, r2, r3 8005e20: f241 3288 movw r2, #5000 @ 0x1388 8005e24: 4293 cmp r3, r2 8005e26: d901 bls.n 8005e2c { return HAL_TIMEOUT; 8005e28: 2303 movs r3, #3 8005e2a: e121 b.n 8006070 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) 8005e2c: 4b3a ldr r3, [pc, #232] @ (8005f18 ) 8005e2e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8005e32: f003 0302 and.w r3, r3, #2 8005e36: 2b00 cmp r3, #0 8005e38: d1ed bne.n 8005e16 } } } /* Restore clock configuration if changed */ if (pwrclkchanged == SET) 8005e3a: 7ffb ldrb r3, [r7, #31] 8005e3c: 2b01 cmp r3, #1 8005e3e: d105 bne.n 8005e4c { __HAL_RCC_PWR_CLK_DISABLE(); 8005e40: 4b35 ldr r3, [pc, #212] @ (8005f18 ) 8005e42: 6d9b ldr r3, [r3, #88] @ 0x58 8005e44: 4a34 ldr r2, [pc, #208] @ (8005f18 ) 8005e46: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8005e4a: 6593 str r3, [r2, #88] @ 0x58 } } /*------------------------------ HSI48 Configuration -----------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) 8005e4c: 687b ldr r3, [r7, #4] 8005e4e: 681b ldr r3, [r3, #0] 8005e50: f003 0320 and.w r3, r3, #32 8005e54: 2b00 cmp r3, #0 8005e56: d03c beq.n 8005ed2 { /* Check the parameters */ assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); /* Check the HSI48 State */ if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) 8005e58: 687b ldr r3, [r7, #4] 8005e5a: 699b ldr r3, [r3, #24] 8005e5c: 2b00 cmp r3, #0 8005e5e: d01c beq.n 8005e9a { /* Enable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_ENABLE(); 8005e60: 4b2d ldr r3, [pc, #180] @ (8005f18 ) 8005e62: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 8005e66: 4a2c ldr r2, [pc, #176] @ (8005f18 ) 8005e68: f043 0301 orr.w r3, r3, #1 8005e6c: f8c2 3098 str.w r3, [r2, #152] @ 0x98 /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005e70: f7fb fd1c bl 80018ac 8005e74: 6138 str r0, [r7, #16] /* Wait till HSI48 is ready */ while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U) 8005e76: e008 b.n 8005e8a { if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 8005e78: f7fb fd18 bl 80018ac 8005e7c: 4602 mov r2, r0 8005e7e: 693b ldr r3, [r7, #16] 8005e80: 1ad3 subs r3, r2, r3 8005e82: 2b02 cmp r3, #2 8005e84: d901 bls.n 8005e8a { return HAL_TIMEOUT; 8005e86: 2303 movs r3, #3 8005e88: e0f2 b.n 8006070 while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U) 8005e8a: 4b23 ldr r3, [pc, #140] @ (8005f18 ) 8005e8c: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 8005e90: f003 0302 and.w r3, r3, #2 8005e94: 2b00 cmp r3, #0 8005e96: d0ef beq.n 8005e78 8005e98: e01b b.n 8005ed2 } } else { /* Disable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_DISABLE(); 8005e9a: 4b1f ldr r3, [pc, #124] @ (8005f18 ) 8005e9c: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 8005ea0: 4a1d ldr r2, [pc, #116] @ (8005f18 ) 8005ea2: f023 0301 bic.w r3, r3, #1 8005ea6: f8c2 3098 str.w r3, [r2, #152] @ 0x98 /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005eaa: f7fb fcff bl 80018ac 8005eae: 6138 str r0, [r7, #16] /* Wait till HSI48 is disabled */ while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U) 8005eb0: e008 b.n 8005ec4 { if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 8005eb2: f7fb fcfb bl 80018ac 8005eb6: 4602 mov r2, r0 8005eb8: 693b ldr r3, [r7, #16] 8005eba: 1ad3 subs r3, r2, r3 8005ebc: 2b02 cmp r3, #2 8005ebe: d901 bls.n 8005ec4 { return HAL_TIMEOUT; 8005ec0: 2303 movs r3, #3 8005ec2: e0d5 b.n 8006070 while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U) 8005ec4: 4b14 ldr r3, [pc, #80] @ (8005f18 ) 8005ec6: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 8005eca: f003 0302 and.w r3, r3, #2 8005ece: 2b00 cmp r3, #0 8005ed0: d1ef bne.n 8005eb2 /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) 8005ed2: 687b ldr r3, [r7, #4] 8005ed4: 69db ldr r3, [r3, #28] 8005ed6: 2b00 cmp r3, #0 8005ed8: f000 80c9 beq.w 800606e { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) 8005edc: 4b0e ldr r3, [pc, #56] @ (8005f18 ) 8005ede: 689b ldr r3, [r3, #8] 8005ee0: f003 030c and.w r3, r3, #12 8005ee4: 2b0c cmp r3, #12 8005ee6: f000 8083 beq.w 8005ff0 { if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) 8005eea: 687b ldr r3, [r7, #4] 8005eec: 69db ldr r3, [r3, #28] 8005eee: 2b02 cmp r3, #2 8005ef0: d15e bne.n 8005fb0 assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8005ef2: 4b09 ldr r3, [pc, #36] @ (8005f18 ) 8005ef4: 681b ldr r3, [r3, #0] 8005ef6: 4a08 ldr r2, [pc, #32] @ (8005f18 ) 8005ef8: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 8005efc: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005efe: f7fb fcd5 bl 80018ac 8005f02: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 8005f04: e00c b.n 8005f20 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8005f06: f7fb fcd1 bl 80018ac 8005f0a: 4602 mov r2, r0 8005f0c: 693b ldr r3, [r7, #16] 8005f0e: 1ad3 subs r3, r2, r3 8005f10: 2b02 cmp r3, #2 8005f12: d905 bls.n 8005f20 { return HAL_TIMEOUT; 8005f14: 2303 movs r3, #3 8005f16: e0ab b.n 8006070 8005f18: 40021000 .word 0x40021000 8005f1c: 40007000 .word 0x40007000 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 8005f20: 4b55 ldr r3, [pc, #340] @ (8006078 ) 8005f22: 681b ldr r3, [r3, #0] 8005f24: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8005f28: 2b00 cmp r3, #0 8005f2a: d1ec bne.n 8005f06 } } /* Configure the main PLL clock source, multiplication and division factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8005f2c: 4b52 ldr r3, [pc, #328] @ (8006078 ) 8005f2e: 68da ldr r2, [r3, #12] 8005f30: 4b52 ldr r3, [pc, #328] @ (800607c ) 8005f32: 4013 ands r3, r2 8005f34: 687a ldr r2, [r7, #4] 8005f36: 6a11 ldr r1, [r2, #32] 8005f38: 687a ldr r2, [r7, #4] 8005f3a: 6a52 ldr r2, [r2, #36] @ 0x24 8005f3c: 3a01 subs r2, #1 8005f3e: 0112 lsls r2, r2, #4 8005f40: 4311 orrs r1, r2 8005f42: 687a ldr r2, [r7, #4] 8005f44: 6a92 ldr r2, [r2, #40] @ 0x28 8005f46: 0212 lsls r2, r2, #8 8005f48: 4311 orrs r1, r2 8005f4a: 687a ldr r2, [r7, #4] 8005f4c: 6b12 ldr r2, [r2, #48] @ 0x30 8005f4e: 0852 lsrs r2, r2, #1 8005f50: 3a01 subs r2, #1 8005f52: 0552 lsls r2, r2, #21 8005f54: 4311 orrs r1, r2 8005f56: 687a ldr r2, [r7, #4] 8005f58: 6b52 ldr r2, [r2, #52] @ 0x34 8005f5a: 0852 lsrs r2, r2, #1 8005f5c: 3a01 subs r2, #1 8005f5e: 0652 lsls r2, r2, #25 8005f60: 4311 orrs r1, r2 8005f62: 687a ldr r2, [r7, #4] 8005f64: 6ad2 ldr r2, [r2, #44] @ 0x2c 8005f66: 06d2 lsls r2, r2, #27 8005f68: 430a orrs r2, r1 8005f6a: 4943 ldr r1, [pc, #268] @ (8006078 ) 8005f6c: 4313 orrs r3, r2 8005f6e: 60cb str r3, [r1, #12] RCC_OscInitStruct->PLL.PLLP, RCC_OscInitStruct->PLL.PLLQ, RCC_OscInitStruct->PLL.PLLR); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8005f70: 4b41 ldr r3, [pc, #260] @ (8006078 ) 8005f72: 681b ldr r3, [r3, #0] 8005f74: 4a40 ldr r2, [pc, #256] @ (8006078 ) 8005f76: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 8005f7a: 6013 str r3, [r2, #0] /* Enable PLL System Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); 8005f7c: 4b3e ldr r3, [pc, #248] @ (8006078 ) 8005f7e: 68db ldr r3, [r3, #12] 8005f80: 4a3d ldr r2, [pc, #244] @ (8006078 ) 8005f82: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 8005f86: 60d3 str r3, [r2, #12] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005f88: f7fb fc90 bl 80018ac 8005f8c: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 8005f8e: e008 b.n 8005fa2 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8005f90: f7fb fc8c bl 80018ac 8005f94: 4602 mov r2, r0 8005f96: 693b ldr r3, [r7, #16] 8005f98: 1ad3 subs r3, r2, r3 8005f9a: 2b02 cmp r3, #2 8005f9c: d901 bls.n 8005fa2 { return HAL_TIMEOUT; 8005f9e: 2303 movs r3, #3 8005fa0: e066 b.n 8006070 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 8005fa2: 4b35 ldr r3, [pc, #212] @ (8006078 ) 8005fa4: 681b ldr r3, [r3, #0] 8005fa6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8005faa: 2b00 cmp r3, #0 8005fac: d0f0 beq.n 8005f90 8005fae: e05e b.n 800606e } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8005fb0: 4b31 ldr r3, [pc, #196] @ (8006078 ) 8005fb2: 681b ldr r3, [r3, #0] 8005fb4: 4a30 ldr r2, [pc, #192] @ (8006078 ) 8005fb6: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 8005fba: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005fbc: f7fb fc76 bl 80018ac 8005fc0: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 8005fc2: e008 b.n 8005fd6 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8005fc4: f7fb fc72 bl 80018ac 8005fc8: 4602 mov r2, r0 8005fca: 693b ldr r3, [r7, #16] 8005fcc: 1ad3 subs r3, r2, r3 8005fce: 2b02 cmp r3, #2 8005fd0: d901 bls.n 8005fd6 { return HAL_TIMEOUT; 8005fd2: 2303 movs r3, #3 8005fd4: e04c b.n 8006070 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 8005fd6: 4b28 ldr r3, [pc, #160] @ (8006078 ) 8005fd8: 681b ldr r3, [r3, #0] 8005fda: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8005fde: 2b00 cmp r3, #0 8005fe0: d1f0 bne.n 8005fc4 } } /* Unselect PLL clock source and disable outputs to save power */ RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_ADCCLK); 8005fe2: 4b25 ldr r3, [pc, #148] @ (8006078 ) 8005fe4: 68da ldr r2, [r3, #12] 8005fe6: 4924 ldr r1, [pc, #144] @ (8006078 ) 8005fe8: 4b25 ldr r3, [pc, #148] @ (8006080 ) 8005fea: 4013 ands r3, r2 8005fec: 60cb str r3, [r1, #12] 8005fee: e03e b.n 800606e } } else { /* Check if there is a request to disable the PLL used as System clock source */ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8005ff0: 687b ldr r3, [r7, #4] 8005ff2: 69db ldr r3, [r3, #28] 8005ff4: 2b01 cmp r3, #1 8005ff6: d101 bne.n 8005ffc { return HAL_ERROR; 8005ff8: 2301 movs r3, #1 8005ffa: e039 b.n 8006070 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ temp_pllckcfg = RCC->PLLCFGR; 8005ffc: 4b1e ldr r3, [pc, #120] @ (8006078 ) 8005ffe: 68db ldr r3, [r3, #12] 8006000: 617b str r3, [r7, #20] if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8006002: 697b ldr r3, [r7, #20] 8006004: f003 0203 and.w r2, r3, #3 8006008: 687b ldr r3, [r7, #4] 800600a: 6a1b ldr r3, [r3, #32] 800600c: 429a cmp r2, r3 800600e: d12c bne.n 800606a (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC_PLLCFGR_PLLM_Pos)) || 8006010: 697b ldr r3, [r7, #20] 8006012: f003 02f0 and.w r2, r3, #240 @ 0xf0 8006016: 687b ldr r3, [r7, #4] 8006018: 6a5b ldr r3, [r3, #36] @ 0x24 800601a: 3b01 subs r3, #1 800601c: 011b lsls r3, r3, #4 if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800601e: 429a cmp r2, r3 8006020: d123 bne.n 800606a (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos)) || 8006022: 697b ldr r3, [r7, #20] 8006024: f403 42fe and.w r2, r3, #32512 @ 0x7f00 8006028: 687b ldr r3, [r7, #4] 800602a: 6a9b ldr r3, [r3, #40] @ 0x28 800602c: 021b lsls r3, r3, #8 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC_PLLCFGR_PLLM_Pos)) || 800602e: 429a cmp r2, r3 8006030: d11b bne.n 800606a (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLLCFGR_PLLPDIV_Pos)) || 8006032: 697b ldr r3, [r7, #20] 8006034: f003 4278 and.w r2, r3, #4160749568 @ 0xf8000000 8006038: 687b ldr r3, [r7, #4] 800603a: 6adb ldr r3, [r3, #44] @ 0x2c 800603c: 06db lsls r3, r3, #27 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos)) || 800603e: 429a cmp r2, r3 8006040: d113 bne.n 800606a (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) || 8006042: 697b ldr r3, [r7, #20] 8006044: f403 02c0 and.w r2, r3, #6291456 @ 0x600000 8006048: 687b ldr r3, [r7, #4] 800604a: 6b1b ldr r3, [r3, #48] @ 0x30 800604c: 085b lsrs r3, r3, #1 800604e: 3b01 subs r3, #1 8006050: 055b lsls r3, r3, #21 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLLCFGR_PLLPDIV_Pos)) || 8006052: 429a cmp r2, r3 8006054: d109 bne.n 800606a (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos))) 8006056: 697b ldr r3, [r7, #20] 8006058: f003 62c0 and.w r2, r3, #100663296 @ 0x6000000 800605c: 687b ldr r3, [r7, #4] 800605e: 6b5b ldr r3, [r3, #52] @ 0x34 8006060: 085b lsrs r3, r3, #1 8006062: 3b01 subs r3, #1 8006064: 065b lsls r3, r3, #25 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) || 8006066: 429a cmp r2, r3 8006068: d001 beq.n 800606e { return HAL_ERROR; 800606a: 2301 movs r3, #1 800606c: e000 b.n 8006070 } } } } return HAL_OK; 800606e: 2300 movs r3, #0 } 8006070: 4618 mov r0, r3 8006072: 3720 adds r7, #32 8006074: 46bd mov sp, r7 8006076: bd80 pop {r7, pc} 8006078: 40021000 .word 0x40021000 800607c: 019f800c .word 0x019f800c 8006080: feeefffc .word 0xfeeefffc 08006084 : * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8006084: b580 push {r7, lr} 8006086: b086 sub sp, #24 8006088: af00 add r7, sp, #0 800608a: 6078 str r0, [r7, #4] 800608c: 6039 str r1, [r7, #0] uint32_t tickstart; uint32_t pllfreq; uint32_t hpre = RCC_SYSCLK_DIV1; 800608e: 2300 movs r3, #0 8006090: 617b str r3, [r7, #20] /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 8006092: 687b ldr r3, [r7, #4] 8006094: 2b00 cmp r3, #0 8006096: d101 bne.n 800609c { return HAL_ERROR; 8006098: 2301 movs r3, #1 800609a: e11e b.n 80062da /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 800609c: 4b91 ldr r3, [pc, #580] @ (80062e4 ) 800609e: 681b ldr r3, [r3, #0] 80060a0: f003 030f and.w r3, r3, #15 80060a4: 683a ldr r2, [r7, #0] 80060a6: 429a cmp r2, r3 80060a8: d910 bls.n 80060cc { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 80060aa: 4b8e ldr r3, [pc, #568] @ (80062e4 ) 80060ac: 681b ldr r3, [r3, #0] 80060ae: f023 020f bic.w r2, r3, #15 80060b2: 498c ldr r1, [pc, #560] @ (80062e4 ) 80060b4: 683b ldr r3, [r7, #0] 80060b6: 4313 orrs r3, r2 80060b8: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 80060ba: 4b8a ldr r3, [pc, #552] @ (80062e4 ) 80060bc: 681b ldr r3, [r3, #0] 80060be: f003 030f and.w r3, r3, #15 80060c2: 683a ldr r2, [r7, #0] 80060c4: 429a cmp r2, r3 80060c6: d001 beq.n 80060cc { return HAL_ERROR; 80060c8: 2301 movs r3, #1 80060ca: e106 b.n 80062da } } /*------------------------- SYSCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 80060cc: 687b ldr r3, [r7, #4] 80060ce: 681b ldr r3, [r3, #0] 80060d0: f003 0301 and.w r3, r3, #1 80060d4: 2b00 cmp r3, #0 80060d6: d073 beq.n 80061c0 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* PLL is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 80060d8: 687b ldr r3, [r7, #4] 80060da: 685b ldr r3, [r3, #4] 80060dc: 2b03 cmp r3, #3 80060de: d129 bne.n 8006134 { /* Check the PLL ready flag */ if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 80060e0: 4b81 ldr r3, [pc, #516] @ (80062e8 ) 80060e2: 681b ldr r3, [r3, #0] 80060e4: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80060e8: 2b00 cmp r3, #0 80060ea: d101 bne.n 80060f0 { return HAL_ERROR; 80060ec: 2301 movs r3, #1 80060ee: e0f4 b.n 80062da } /* Undershoot management when selection PLL as SYSCLK source and frequency above 80Mhz */ /* Compute target PLL output frequency */ pllfreq = RCC_GetSysClockFreqFromPLLSource(); 80060f0: f000 f99e bl 8006430 80060f4: 6138 str r0, [r7, #16] /* Intermediate step with HCLK prescaler 2 necessary before to go over 80Mhz */ if(pllfreq > 80000000U) 80060f6: 693b ldr r3, [r7, #16] 80060f8: 4a7c ldr r2, [pc, #496] @ (80062ec ) 80060fa: 4293 cmp r3, r2 80060fc: d93f bls.n 800617e { if (((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)) || 80060fe: 4b7a ldr r3, [pc, #488] @ (80062e8 ) 8006100: 689b ldr r3, [r3, #8] 8006102: f003 03f0 and.w r3, r3, #240 @ 0xf0 8006106: 2b00 cmp r3, #0 8006108: d009 beq.n 800611e (((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) && 800610a: 687b ldr r3, [r7, #4] 800610c: 681b ldr r3, [r3, #0] 800610e: f003 0302 and.w r3, r3, #2 if (((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)) || 8006112: 2b00 cmp r3, #0 8006114: d033 beq.n 800617e (RCC_ClkInitStruct->AHBCLKDivider == RCC_SYSCLK_DIV1)))) 8006116: 687b ldr r3, [r7, #4] 8006118: 689b ldr r3, [r3, #8] (((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) && 800611a: 2b00 cmp r3, #0 800611c: d12f bne.n 800617e { MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); 800611e: 4b72 ldr r3, [pc, #456] @ (80062e8 ) 8006120: 689b ldr r3, [r3, #8] 8006122: f023 03f0 bic.w r3, r3, #240 @ 0xf0 8006126: 4a70 ldr r2, [pc, #448] @ (80062e8 ) 8006128: f043 0380 orr.w r3, r3, #128 @ 0x80 800612c: 6093 str r3, [r2, #8] hpre = RCC_SYSCLK_DIV2; 800612e: 2380 movs r3, #128 @ 0x80 8006130: 617b str r3, [r7, #20] 8006132: e024 b.n 800617e } } else { /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8006134: 687b ldr r3, [r7, #4] 8006136: 685b ldr r3, [r3, #4] 8006138: 2b02 cmp r3, #2 800613a: d107 bne.n 800614c { /* Check the HSE ready flag */ if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 800613c: 4b6a ldr r3, [pc, #424] @ (80062e8 ) 800613e: 681b ldr r3, [r3, #0] 8006140: f403 3300 and.w r3, r3, #131072 @ 0x20000 8006144: 2b00 cmp r3, #0 8006146: d109 bne.n 800615c { return HAL_ERROR; 8006148: 2301 movs r3, #1 800614a: e0c6 b.n 80062da } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 800614c: 4b66 ldr r3, [pc, #408] @ (80062e8 ) 800614e: 681b ldr r3, [r3, #0] 8006150: f403 6380 and.w r3, r3, #1024 @ 0x400 8006154: 2b00 cmp r3, #0 8006156: d101 bne.n 800615c { return HAL_ERROR; 8006158: 2301 movs r3, #1 800615a: e0be b.n 80062da } } /* Overshoot management when going down from PLL as SYSCLK source and frequency above 80Mhz */ pllfreq = HAL_RCC_GetSysClockFreq(); 800615c: f000 f8ce bl 80062fc 8006160: 6138 str r0, [r7, #16] /* Intermediate step with HCLK prescaler 2 necessary before to go under 80Mhz */ if(pllfreq > 80000000U) 8006162: 693b ldr r3, [r7, #16] 8006164: 4a61 ldr r2, [pc, #388] @ (80062ec ) 8006166: 4293 cmp r3, r2 8006168: d909 bls.n 800617e { MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); 800616a: 4b5f ldr r3, [pc, #380] @ (80062e8 ) 800616c: 689b ldr r3, [r3, #8] 800616e: f023 03f0 bic.w r3, r3, #240 @ 0xf0 8006172: 4a5d ldr r2, [pc, #372] @ (80062e8 ) 8006174: f043 0380 orr.w r3, r3, #128 @ 0x80 8006178: 6093 str r3, [r2, #8] hpre = RCC_SYSCLK_DIV2; 800617a: 2380 movs r3, #128 @ 0x80 800617c: 617b str r3, [r7, #20] } } MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); 800617e: 4b5a ldr r3, [pc, #360] @ (80062e8 ) 8006180: 689b ldr r3, [r3, #8] 8006182: f023 0203 bic.w r2, r3, #3 8006186: 687b ldr r3, [r7, #4] 8006188: 685b ldr r3, [r3, #4] 800618a: 4957 ldr r1, [pc, #348] @ (80062e8 ) 800618c: 4313 orrs r3, r2 800618e: 608b str r3, [r1, #8] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8006190: f7fb fb8c bl 80018ac 8006194: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8006196: e00a b.n 80061ae { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8006198: f7fb fb88 bl 80018ac 800619c: 4602 mov r2, r0 800619e: 68fb ldr r3, [r7, #12] 80061a0: 1ad3 subs r3, r2, r3 80061a2: f241 3288 movw r2, #5000 @ 0x1388 80061a6: 4293 cmp r3, r2 80061a8: d901 bls.n 80061ae { return HAL_TIMEOUT; 80061aa: 2303 movs r3, #3 80061ac: e095 b.n 80062da while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 80061ae: 4b4e ldr r3, [pc, #312] @ (80062e8 ) 80061b0: 689b ldr r3, [r3, #8] 80061b2: f003 020c and.w r2, r3, #12 80061b6: 687b ldr r3, [r7, #4] 80061b8: 685b ldr r3, [r3, #4] 80061ba: 009b lsls r3, r3, #2 80061bc: 429a cmp r2, r3 80061be: d1eb bne.n 8006198 } } } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 80061c0: 687b ldr r3, [r7, #4] 80061c2: 681b ldr r3, [r3, #0] 80061c4: f003 0302 and.w r3, r3, #2 80061c8: 2b00 cmp r3, #0 80061ca: d023 beq.n 8006214 { /* Set the highest APB divider in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 80061cc: 687b ldr r3, [r7, #4] 80061ce: 681b ldr r3, [r3, #0] 80061d0: f003 0304 and.w r3, r3, #4 80061d4: 2b00 cmp r3, #0 80061d6: d005 beq.n 80061e4 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 80061d8: 4b43 ldr r3, [pc, #268] @ (80062e8 ) 80061da: 689b ldr r3, [r3, #8] 80061dc: 4a42 ldr r2, [pc, #264] @ (80062e8 ) 80061de: f443 63e0 orr.w r3, r3, #1792 @ 0x700 80061e2: 6093 str r3, [r2, #8] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 80061e4: 687b ldr r3, [r7, #4] 80061e6: 681b ldr r3, [r3, #0] 80061e8: f003 0308 and.w r3, r3, #8 80061ec: 2b00 cmp r3, #0 80061ee: d007 beq.n 8006200 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, RCC_HCLK_DIV16); 80061f0: 4b3d ldr r3, [pc, #244] @ (80062e8 ) 80061f2: 689b ldr r3, [r3, #8] 80061f4: f423 537c bic.w r3, r3, #16128 @ 0x3f00 80061f8: 4a3b ldr r2, [pc, #236] @ (80062e8 ) 80061fa: f443 63e0 orr.w r3, r3, #1792 @ 0x700 80061fe: 6093 str r3, [r2, #8] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8006200: 4b39 ldr r3, [pc, #228] @ (80062e8 ) 8006202: 689b ldr r3, [r3, #8] 8006204: f023 02f0 bic.w r2, r3, #240 @ 0xf0 8006208: 687b ldr r3, [r7, #4] 800620a: 689b ldr r3, [r3, #8] 800620c: 4936 ldr r1, [pc, #216] @ (80062e8 ) 800620e: 4313 orrs r3, r2 8006210: 608b str r3, [r1, #8] 8006212: e008 b.n 8006226 } else { /* Is intermediate HCLK prescaler 2 applied internally, complete with HCLK prescaler 1 */ if(hpre == RCC_SYSCLK_DIV2) 8006214: 697b ldr r3, [r7, #20] 8006216: 2b80 cmp r3, #128 @ 0x80 8006218: d105 bne.n 8006226 { MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1); 800621a: 4b33 ldr r3, [pc, #204] @ (80062e8 ) 800621c: 689b ldr r3, [r3, #8] 800621e: 4a32 ldr r2, [pc, #200] @ (80062e8 ) 8006220: f023 03f0 bic.w r3, r3, #240 @ 0xf0 8006224: 6093 str r3, [r2, #8] } } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 8006226: 4b2f ldr r3, [pc, #188] @ (80062e4 ) 8006228: 681b ldr r3, [r3, #0] 800622a: f003 030f and.w r3, r3, #15 800622e: 683a ldr r2, [r7, #0] 8006230: 429a cmp r2, r3 8006232: d21d bcs.n 8006270 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8006234: 4b2b ldr r3, [pc, #172] @ (80062e4 ) 8006236: 681b ldr r3, [r3, #0] 8006238: f023 020f bic.w r2, r3, #15 800623c: 4929 ldr r1, [pc, #164] @ (80062e4 ) 800623e: 683b ldr r3, [r7, #0] 8006240: 4313 orrs r3, r2 8006242: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by polling the FLASH_ACR register */ tickstart = HAL_GetTick(); 8006244: f7fb fb32 bl 80018ac 8006248: 60f8 str r0, [r7, #12] while (__HAL_FLASH_GET_LATENCY() != FLatency) 800624a: e00a b.n 8006262 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 800624c: f7fb fb2e bl 80018ac 8006250: 4602 mov r2, r0 8006252: 68fb ldr r3, [r7, #12] 8006254: 1ad3 subs r3, r2, r3 8006256: f241 3288 movw r2, #5000 @ 0x1388 800625a: 4293 cmp r3, r2 800625c: d901 bls.n 8006262 { return HAL_TIMEOUT; 800625e: 2303 movs r3, #3 8006260: e03b b.n 80062da while (__HAL_FLASH_GET_LATENCY() != FLatency) 8006262: 4b20 ldr r3, [pc, #128] @ (80062e4 ) 8006264: 681b ldr r3, [r3, #0] 8006266: f003 030f and.w r3, r3, #15 800626a: 683a ldr r2, [r7, #0] 800626c: 429a cmp r2, r3 800626e: d1ed bne.n 800624c } } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8006270: 687b ldr r3, [r7, #4] 8006272: 681b ldr r3, [r3, #0] 8006274: f003 0304 and.w r3, r3, #4 8006278: 2b00 cmp r3, #0 800627a: d008 beq.n 800628e { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 800627c: 4b1a ldr r3, [pc, #104] @ (80062e8 ) 800627e: 689b ldr r3, [r3, #8] 8006280: f423 62e0 bic.w r2, r3, #1792 @ 0x700 8006284: 687b ldr r3, [r7, #4] 8006286: 68db ldr r3, [r3, #12] 8006288: 4917 ldr r1, [pc, #92] @ (80062e8 ) 800628a: 4313 orrs r3, r2 800628c: 608b str r3, [r1, #8] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 800628e: 687b ldr r3, [r7, #4] 8006290: 681b ldr r3, [r3, #0] 8006292: f003 0308 and.w r3, r3, #8 8006296: 2b00 cmp r3, #0 8006298: d009 beq.n 80062ae { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); 800629a: 4b13 ldr r3, [pc, #76] @ (80062e8 ) 800629c: 689b ldr r3, [r3, #8] 800629e: f423 5260 bic.w r2, r3, #14336 @ 0x3800 80062a2: 687b ldr r3, [r7, #4] 80062a4: 691b ldr r3, [r3, #16] 80062a6: 00db lsls r3, r3, #3 80062a8: 490f ldr r1, [pc, #60] @ (80062e8 ) 80062aa: 4313 orrs r3, r2 80062ac: 608b str r3, [r1, #8] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU); 80062ae: f000 f825 bl 80062fc 80062b2: 4602 mov r2, r0 80062b4: 4b0c ldr r3, [pc, #48] @ (80062e8 ) 80062b6: 689b ldr r3, [r3, #8] 80062b8: 091b lsrs r3, r3, #4 80062ba: f003 030f and.w r3, r3, #15 80062be: 490c ldr r1, [pc, #48] @ (80062f0 ) 80062c0: 5ccb ldrb r3, [r1, r3] 80062c2: f003 031f and.w r3, r3, #31 80062c6: fa22 f303 lsr.w r3, r2, r3 80062ca: 4a0a ldr r2, [pc, #40] @ (80062f4 ) 80062cc: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ return HAL_InitTick(uwTickPrio); 80062ce: 4b0a ldr r3, [pc, #40] @ (80062f8 ) 80062d0: 681b ldr r3, [r3, #0] 80062d2: 4618 mov r0, r3 80062d4: f7fb fa9e bl 8001814 80062d8: 4603 mov r3, r0 } 80062da: 4618 mov r0, r3 80062dc: 3718 adds r7, #24 80062de: 46bd mov sp, r7 80062e0: bd80 pop {r7, pc} 80062e2: bf00 nop 80062e4: 40022000 .word 0x40022000 80062e8: 40021000 .word 0x40021000 80062ec: 04c4b400 .word 0x04c4b400 80062f0: 080086e4 .word 0x080086e4 80062f4: 20000000 .word 0x20000000 80062f8: 20000004 .word 0x20000004 080062fc : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 80062fc: b480 push {r7} 80062fe: b087 sub sp, #28 8006300: af00 add r7, sp, #0 uint32_t pllvco, pllsource, pllr, pllm; uint32_t sysclockfreq; if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) 8006302: 4b2c ldr r3, [pc, #176] @ (80063b4 ) 8006304: 689b ldr r3, [r3, #8] 8006306: f003 030c and.w r3, r3, #12 800630a: 2b04 cmp r3, #4 800630c: d102 bne.n 8006314 { /* HSI used as system clock source */ sysclockfreq = HSI_VALUE; 800630e: 4b2a ldr r3, [pc, #168] @ (80063b8 ) 8006310: 613b str r3, [r7, #16] 8006312: e047 b.n 80063a4 } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) 8006314: 4b27 ldr r3, [pc, #156] @ (80063b4 ) 8006316: 689b ldr r3, [r3, #8] 8006318: f003 030c and.w r3, r3, #12 800631c: 2b08 cmp r3, #8 800631e: d102 bne.n 8006326 { /* HSE used as system clock source */ sysclockfreq = HSE_VALUE; 8006320: 4b26 ldr r3, [pc, #152] @ (80063bc ) 8006322: 613b str r3, [r7, #16] 8006324: e03e b.n 80063a4 } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) 8006326: 4b23 ldr r3, [pc, #140] @ (80063b4 ) 8006328: 689b ldr r3, [r3, #8] 800632a: f003 030c and.w r3, r3, #12 800632e: 2b0c cmp r3, #12 8006330: d136 bne.n 80063a0 /* PLL used as system clock source */ /* PLL_VCO = ((HSE_VALUE or HSI_VALUE)/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); 8006332: 4b20 ldr r3, [pc, #128] @ (80063b4 ) 8006334: 68db ldr r3, [r3, #12] 8006336: f003 0303 and.w r3, r3, #3 800633a: 60fb str r3, [r7, #12] pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; 800633c: 4b1d ldr r3, [pc, #116] @ (80063b4 ) 800633e: 68db ldr r3, [r3, #12] 8006340: 091b lsrs r3, r3, #4 8006342: f003 030f and.w r3, r3, #15 8006346: 3301 adds r3, #1 8006348: 60bb str r3, [r7, #8] switch (pllsource) 800634a: 68fb ldr r3, [r7, #12] 800634c: 2b03 cmp r3, #3 800634e: d10c bne.n 800636a { case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 8006350: 4a1a ldr r2, [pc, #104] @ (80063bc ) 8006352: 68bb ldr r3, [r7, #8] 8006354: fbb2 f3f3 udiv r3, r2, r3 8006358: 4a16 ldr r2, [pc, #88] @ (80063b4 ) 800635a: 68d2 ldr r2, [r2, #12] 800635c: 0a12 lsrs r2, r2, #8 800635e: f002 027f and.w r2, r2, #127 @ 0x7f 8006362: fb02 f303 mul.w r3, r2, r3 8006366: 617b str r3, [r7, #20] break; 8006368: e00c b.n 8006384 case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ default: pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 800636a: 4a13 ldr r2, [pc, #76] @ (80063b8 ) 800636c: 68bb ldr r3, [r7, #8] 800636e: fbb2 f3f3 udiv r3, r2, r3 8006372: 4a10 ldr r2, [pc, #64] @ (80063b4 ) 8006374: 68d2 ldr r2, [r2, #12] 8006376: 0a12 lsrs r2, r2, #8 8006378: f002 027f and.w r2, r2, #127 @ 0x7f 800637c: fb02 f303 mul.w r3, r2, r3 8006380: 617b str r3, [r7, #20] break; 8006382: bf00 nop } pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; 8006384: 4b0b ldr r3, [pc, #44] @ (80063b4 ) 8006386: 68db ldr r3, [r3, #12] 8006388: 0e5b lsrs r3, r3, #25 800638a: f003 0303 and.w r3, r3, #3 800638e: 3301 adds r3, #1 8006390: 005b lsls r3, r3, #1 8006392: 607b str r3, [r7, #4] sysclockfreq = pllvco/pllr; 8006394: 697a ldr r2, [r7, #20] 8006396: 687b ldr r3, [r7, #4] 8006398: fbb2 f3f3 udiv r3, r2, r3 800639c: 613b str r3, [r7, #16] 800639e: e001 b.n 80063a4 } else { sysclockfreq = 0U; 80063a0: 2300 movs r3, #0 80063a2: 613b str r3, [r7, #16] } return sysclockfreq; 80063a4: 693b ldr r3, [r7, #16] } 80063a6: 4618 mov r0, r3 80063a8: 371c adds r7, #28 80063aa: 46bd mov sp, r7 80063ac: f85d 7b04 ldr.w r7, [sp], #4 80063b0: 4770 bx lr 80063b2: bf00 nop 80063b4: 40021000 .word 0x40021000 80063b8: 00f42400 .word 0x00f42400 80063bc: 02625a00 .word 0x02625a00 080063c0 : * * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. * @retval HCLK frequency in Hz */ uint32_t HAL_RCC_GetHCLKFreq(void) { 80063c0: b480 push {r7} 80063c2: af00 add r7, sp, #0 return SystemCoreClock; 80063c4: 4b03 ldr r3, [pc, #12] @ (80063d4 ) 80063c6: 681b ldr r3, [r3, #0] } 80063c8: 4618 mov r0, r3 80063ca: 46bd mov sp, r7 80063cc: f85d 7b04 ldr.w r7, [sp], #4 80063d0: 4770 bx lr 80063d2: bf00 nop 80063d4: 20000000 .word 0x20000000 080063d8 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency in Hz */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 80063d8: b580 push {r7, lr} 80063da: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU)); 80063dc: f7ff fff0 bl 80063c0 80063e0: 4602 mov r2, r0 80063e2: 4b06 ldr r3, [pc, #24] @ (80063fc ) 80063e4: 689b ldr r3, [r3, #8] 80063e6: 0a1b lsrs r3, r3, #8 80063e8: f003 0307 and.w r3, r3, #7 80063ec: 4904 ldr r1, [pc, #16] @ (8006400 ) 80063ee: 5ccb ldrb r3, [r1, r3] 80063f0: f003 031f and.w r3, r3, #31 80063f4: fa22 f303 lsr.w r3, r2, r3 } 80063f8: 4618 mov r0, r3 80063fa: bd80 pop {r7, pc} 80063fc: 40021000 .word 0x40021000 8006400: 080086f4 .word 0x080086f4 08006404 : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency in Hz */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 8006404: b580 push {r7, lr} 8006406: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU)); 8006408: f7ff ffda bl 80063c0 800640c: 4602 mov r2, r0 800640e: 4b06 ldr r3, [pc, #24] @ (8006428 ) 8006410: 689b ldr r3, [r3, #8] 8006412: 0adb lsrs r3, r3, #11 8006414: f003 0307 and.w r3, r3, #7 8006418: 4904 ldr r1, [pc, #16] @ (800642c ) 800641a: 5ccb ldrb r3, [r1, r3] 800641c: f003 031f and.w r3, r3, #31 8006420: fa22 f303 lsr.w r3, r2, r3 } 8006424: 4618 mov r0, r3 8006426: bd80 pop {r7, pc} 8006428: 40021000 .word 0x40021000 800642c: 080086f4 .word 0x080086f4 08006430 : /** * @brief Compute SYSCLK frequency based on PLL SYSCLK source. * @retval SYSCLK frequency */ static uint32_t RCC_GetSysClockFreqFromPLLSource(void) { 8006430: b480 push {r7} 8006432: b087 sub sp, #28 8006434: af00 add r7, sp, #0 uint32_t sysclockfreq; /* PLL_VCO = (HSE_VALUE or HSI_VALUE/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); 8006436: 4b1e ldr r3, [pc, #120] @ (80064b0 ) 8006438: 68db ldr r3, [r3, #12] 800643a: f003 0303 and.w r3, r3, #3 800643e: 613b str r3, [r7, #16] pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; 8006440: 4b1b ldr r3, [pc, #108] @ (80064b0 ) 8006442: 68db ldr r3, [r3, #12] 8006444: 091b lsrs r3, r3, #4 8006446: f003 030f and.w r3, r3, #15 800644a: 3301 adds r3, #1 800644c: 60fb str r3, [r7, #12] switch (pllsource) 800644e: 693b ldr r3, [r7, #16] 8006450: 2b03 cmp r3, #3 8006452: d10c bne.n 800646e { case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 8006454: 4a17 ldr r2, [pc, #92] @ (80064b4 ) 8006456: 68fb ldr r3, [r7, #12] 8006458: fbb2 f3f3 udiv r3, r2, r3 800645c: 4a14 ldr r2, [pc, #80] @ (80064b0 ) 800645e: 68d2 ldr r2, [r2, #12] 8006460: 0a12 lsrs r2, r2, #8 8006462: f002 027f and.w r2, r2, #127 @ 0x7f 8006466: fb02 f303 mul.w r3, r2, r3 800646a: 617b str r3, [r7, #20] break; 800646c: e00c b.n 8006488 case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ default: pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 800646e: 4a12 ldr r2, [pc, #72] @ (80064b8 ) 8006470: 68fb ldr r3, [r7, #12] 8006472: fbb2 f3f3 udiv r3, r2, r3 8006476: 4a0e ldr r2, [pc, #56] @ (80064b0 ) 8006478: 68d2 ldr r2, [r2, #12] 800647a: 0a12 lsrs r2, r2, #8 800647c: f002 027f and.w r2, r2, #127 @ 0x7f 8006480: fb02 f303 mul.w r3, r2, r3 8006484: 617b str r3, [r7, #20] break; 8006486: bf00 nop } pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; 8006488: 4b09 ldr r3, [pc, #36] @ (80064b0 ) 800648a: 68db ldr r3, [r3, #12] 800648c: 0e5b lsrs r3, r3, #25 800648e: f003 0303 and.w r3, r3, #3 8006492: 3301 adds r3, #1 8006494: 005b lsls r3, r3, #1 8006496: 60bb str r3, [r7, #8] sysclockfreq = pllvco/pllr; 8006498: 697a ldr r2, [r7, #20] 800649a: 68bb ldr r3, [r7, #8] 800649c: fbb2 f3f3 udiv r3, r2, r3 80064a0: 607b str r3, [r7, #4] return sysclockfreq; 80064a2: 687b ldr r3, [r7, #4] } 80064a4: 4618 mov r0, r3 80064a6: 371c adds r7, #28 80064a8: 46bd mov sp, r7 80064aa: f85d 7b04 ldr.w r7, [sp], #4 80064ae: 4770 bx lr 80064b0: 40021000 .word 0x40021000 80064b4: 02625a00 .word 0x02625a00 80064b8: 00f42400 .word 0x00f42400 080064bc : * the RTC clock source: in this case the access to Backup domain is enabled. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 80064bc: b580 push {r7, lr} 80064be: b086 sub sp, #24 80064c0: af00 add r7, sp, #0 80064c2: 6078 str r0, [r7, #4] uint32_t tmpregister; uint32_t tickstart; HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ 80064c4: 2300 movs r3, #0 80064c6: 74fb strb r3, [r7, #19] HAL_StatusTypeDef status = HAL_OK; /* Final status */ 80064c8: 2300 movs r3, #0 80064ca: 74bb strb r3, [r7, #18] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*-------------------------- RTC clock source configuration ----------------------*/ if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 80064cc: 687b ldr r3, [r7, #4] 80064ce: 681b ldr r3, [r3, #0] 80064d0: f403 2300 and.w r3, r3, #524288 @ 0x80000 80064d4: 2b00 cmp r3, #0 80064d6: f000 8098 beq.w 800660a { FlagStatus pwrclkchanged = RESET; 80064da: 2300 movs r3, #0 80064dc: 747b strb r3, [r7, #17] /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable Power Clock */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) 80064de: 4b43 ldr r3, [pc, #268] @ (80065ec ) 80064e0: 6d9b ldr r3, [r3, #88] @ 0x58 80064e2: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80064e6: 2b00 cmp r3, #0 80064e8: d10d bne.n 8006506 { __HAL_RCC_PWR_CLK_ENABLE(); 80064ea: 4b40 ldr r3, [pc, #256] @ (80065ec ) 80064ec: 6d9b ldr r3, [r3, #88] @ 0x58 80064ee: 4a3f ldr r2, [pc, #252] @ (80065ec ) 80064f0: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80064f4: 6593 str r3, [r2, #88] @ 0x58 80064f6: 4b3d ldr r3, [pc, #244] @ (80065ec ) 80064f8: 6d9b ldr r3, [r3, #88] @ 0x58 80064fa: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80064fe: 60bb str r3, [r7, #8] 8006500: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8006502: 2301 movs r3, #1 8006504: 747b strb r3, [r7, #17] } /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); 8006506: 4b3a ldr r3, [pc, #232] @ (80065f0 ) 8006508: 681b ldr r3, [r3, #0] 800650a: 4a39 ldr r2, [pc, #228] @ (80065f0 ) 800650c: f443 7380 orr.w r3, r3, #256 @ 0x100 8006510: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8006512: f7fb f9cb bl 80018ac 8006516: 60f8 str r0, [r7, #12] while((PWR->CR1 & PWR_CR1_DBP) == 0U) 8006518: e009 b.n 800652e { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800651a: f7fb f9c7 bl 80018ac 800651e: 4602 mov r2, r0 8006520: 68fb ldr r3, [r7, #12] 8006522: 1ad3 subs r3, r2, r3 8006524: 2b02 cmp r3, #2 8006526: d902 bls.n 800652e { ret = HAL_TIMEOUT; 8006528: 2303 movs r3, #3 800652a: 74fb strb r3, [r7, #19] break; 800652c: e005 b.n 800653a while((PWR->CR1 & PWR_CR1_DBP) == 0U) 800652e: 4b30 ldr r3, [pc, #192] @ (80065f0 ) 8006530: 681b ldr r3, [r3, #0] 8006532: f403 7380 and.w r3, r3, #256 @ 0x100 8006536: 2b00 cmp r3, #0 8006538: d0ef beq.n 800651a } } if(ret == HAL_OK) 800653a: 7cfb ldrb r3, [r7, #19] 800653c: 2b00 cmp r3, #0 800653e: d159 bne.n 80065f4 { /* Reset the Backup domain only if the RTC Clock source selection is modified from default */ tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL); 8006540: 4b2a ldr r3, [pc, #168] @ (80065ec ) 8006542: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8006546: f403 7340 and.w r3, r3, #768 @ 0x300 800654a: 617b str r3, [r7, #20] if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection)) 800654c: 697b ldr r3, [r7, #20] 800654e: 2b00 cmp r3, #0 8006550: d01e beq.n 8006590 8006552: 687b ldr r3, [r7, #4] 8006554: 6d1b ldr r3, [r3, #80] @ 0x50 8006556: 697a ldr r2, [r7, #20] 8006558: 429a cmp r2, r3 800655a: d019 beq.n 8006590 { /* Store the content of BDCR register before the reset of Backup Domain */ tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); 800655c: 4b23 ldr r3, [pc, #140] @ (80065ec ) 800655e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8006562: f423 7340 bic.w r3, r3, #768 @ 0x300 8006566: 617b str r3, [r7, #20] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 8006568: 4b20 ldr r3, [pc, #128] @ (80065ec ) 800656a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800656e: 4a1f ldr r2, [pc, #124] @ (80065ec ) 8006570: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8006574: f8c2 3090 str.w r3, [r2, #144] @ 0x90 __HAL_RCC_BACKUPRESET_RELEASE(); 8006578: 4b1c ldr r3, [pc, #112] @ (80065ec ) 800657a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800657e: 4a1b ldr r2, [pc, #108] @ (80065ec ) 8006580: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8006584: f8c2 3090 str.w r3, [r2, #144] @ 0x90 /* Restore the Content of BDCR register */ RCC->BDCR = tmpregister; 8006588: 4a18 ldr r2, [pc, #96] @ (80065ec ) 800658a: 697b ldr r3, [r7, #20] 800658c: f8c2 3090 str.w r3, [r2, #144] @ 0x90 } /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON)) 8006590: 697b ldr r3, [r7, #20] 8006592: f003 0301 and.w r3, r3, #1 8006596: 2b00 cmp r3, #0 8006598: d016 beq.n 80065c8 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800659a: f7fb f987 bl 80018ac 800659e: 60f8 str r0, [r7, #12] /* Wait till LSE is ready */ while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 80065a0: e00b b.n 80065ba { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80065a2: f7fb f983 bl 80018ac 80065a6: 4602 mov r2, r0 80065a8: 68fb ldr r3, [r7, #12] 80065aa: 1ad3 subs r3, r2, r3 80065ac: f241 3288 movw r2, #5000 @ 0x1388 80065b0: 4293 cmp r3, r2 80065b2: d902 bls.n 80065ba { ret = HAL_TIMEOUT; 80065b4: 2303 movs r3, #3 80065b6: 74fb strb r3, [r7, #19] break; 80065b8: e006 b.n 80065c8 while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 80065ba: 4b0c ldr r3, [pc, #48] @ (80065ec ) 80065bc: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80065c0: f003 0302 and.w r3, r3, #2 80065c4: 2b00 cmp r3, #0 80065c6: d0ec beq.n 80065a2 } } } if(ret == HAL_OK) 80065c8: 7cfb ldrb r3, [r7, #19] 80065ca: 2b00 cmp r3, #0 80065cc: d10b bne.n 80065e6 { /* Apply new RTC clock source selection */ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 80065ce: 4b07 ldr r3, [pc, #28] @ (80065ec ) 80065d0: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80065d4: f423 7240 bic.w r2, r3, #768 @ 0x300 80065d8: 687b ldr r3, [r7, #4] 80065da: 6d1b ldr r3, [r3, #80] @ 0x50 80065dc: 4903 ldr r1, [pc, #12] @ (80065ec ) 80065de: 4313 orrs r3, r2 80065e0: f8c1 3090 str.w r3, [r1, #144] @ 0x90 80065e4: e008 b.n 80065f8 } else { /* set overall return value */ status = ret; 80065e6: 7cfb ldrb r3, [r7, #19] 80065e8: 74bb strb r3, [r7, #18] 80065ea: e005 b.n 80065f8 80065ec: 40021000 .word 0x40021000 80065f0: 40007000 .word 0x40007000 } } else { /* set overall return value */ status = ret; 80065f4: 7cfb ldrb r3, [r7, #19] 80065f6: 74bb strb r3, [r7, #18] } /* Restore clock configuration if changed */ if(pwrclkchanged == SET) 80065f8: 7c7b ldrb r3, [r7, #17] 80065fa: 2b01 cmp r3, #1 80065fc: d105 bne.n 800660a { __HAL_RCC_PWR_CLK_DISABLE(); 80065fe: 4ba7 ldr r3, [pc, #668] @ (800689c ) 8006600: 6d9b ldr r3, [r3, #88] @ 0x58 8006602: 4aa6 ldr r2, [pc, #664] @ (800689c ) 8006604: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8006608: 6593 str r3, [r2, #88] @ 0x58 } } /*-------------------------- USART1 clock source configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) 800660a: 687b ldr r3, [r7, #4] 800660c: 681b ldr r3, [r3, #0] 800660e: f003 0301 and.w r3, r3, #1 8006612: 2b00 cmp r3, #0 8006614: d00a beq.n 800662c { /* Check the parameters */ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); /* Configure the USART1 clock source */ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); 8006616: 4ba1 ldr r3, [pc, #644] @ (800689c ) 8006618: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800661c: f023 0203 bic.w r2, r3, #3 8006620: 687b ldr r3, [r7, #4] 8006622: 685b ldr r3, [r3, #4] 8006624: 499d ldr r1, [pc, #628] @ (800689c ) 8006626: 4313 orrs r3, r2 8006628: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } /*-------------------------- USART2 clock source configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) 800662c: 687b ldr r3, [r7, #4] 800662e: 681b ldr r3, [r3, #0] 8006630: f003 0302 and.w r3, r3, #2 8006634: 2b00 cmp r3, #0 8006636: d00a beq.n 800664e { /* Check the parameters */ assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); /* Configure the USART2 clock source */ __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); 8006638: 4b98 ldr r3, [pc, #608] @ (800689c ) 800663a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800663e: f023 020c bic.w r2, r3, #12 8006642: 687b ldr r3, [r7, #4] 8006644: 689b ldr r3, [r3, #8] 8006646: 4995 ldr r1, [pc, #596] @ (800689c ) 8006648: 4313 orrs r3, r2 800664a: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } #if defined(USART3) /*-------------------------- USART3 clock source configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) 800664e: 687b ldr r3, [r7, #4] 8006650: 681b ldr r3, [r3, #0] 8006652: f003 0304 and.w r3, r3, #4 8006656: 2b00 cmp r3, #0 8006658: d00a beq.n 8006670 { /* Check the parameters */ assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); /* Configure the USART3 clock source */ __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); 800665a: 4b90 ldr r3, [pc, #576] @ (800689c ) 800665c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8006660: f023 0230 bic.w r2, r3, #48 @ 0x30 8006664: 687b ldr r3, [r7, #4] 8006666: 68db ldr r3, [r3, #12] 8006668: 498c ldr r1, [pc, #560] @ (800689c ) 800666a: 4313 orrs r3, r2 800666c: f8c1 3088 str.w r3, [r1, #136] @ 0x88 #endif /* USART3 */ #if defined(UART4) /*-------------------------- UART4 clock source configuration --------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) 8006670: 687b ldr r3, [r7, #4] 8006672: 681b ldr r3, [r3, #0] 8006674: f003 0308 and.w r3, r3, #8 8006678: 2b00 cmp r3, #0 800667a: d00a beq.n 8006692 { /* Check the parameters */ assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); /* Configure the UART4 clock source */ __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); 800667c: 4b87 ldr r3, [pc, #540] @ (800689c ) 800667e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8006682: f023 02c0 bic.w r2, r3, #192 @ 0xc0 8006686: 687b ldr r3, [r7, #4] 8006688: 691b ldr r3, [r3, #16] 800668a: 4984 ldr r1, [pc, #528] @ (800689c ) 800668c: 4313 orrs r3, r2 800668e: f8c1 3088 str.w r3, [r1, #136] @ 0x88 #endif /* UART4 */ #if defined(UART5) /*-------------------------- UART5 clock source configuration --------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) 8006692: 687b ldr r3, [r7, #4] 8006694: 681b ldr r3, [r3, #0] 8006696: f003 0310 and.w r3, r3, #16 800669a: 2b00 cmp r3, #0 800669c: d00a beq.n 80066b4 { /* Check the parameters */ assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); /* Configure the UART5 clock source */ __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); 800669e: 4b7f ldr r3, [pc, #508] @ (800689c ) 80066a0: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80066a4: f423 7240 bic.w r2, r3, #768 @ 0x300 80066a8: 687b ldr r3, [r7, #4] 80066aa: 695b ldr r3, [r3, #20] 80066ac: 497b ldr r1, [pc, #492] @ (800689c ) 80066ae: 4313 orrs r3, r2 80066b0: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } #endif /* UART5 */ /*-------------------------- LPUART1 clock source configuration ------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) 80066b4: 687b ldr r3, [r7, #4] 80066b6: 681b ldr r3, [r3, #0] 80066b8: f003 0320 and.w r3, r3, #32 80066bc: 2b00 cmp r3, #0 80066be: d00a beq.n 80066d6 { /* Check the parameters */ assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection)); /* Configure the LPUAR1 clock source */ __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); 80066c0: 4b76 ldr r3, [pc, #472] @ (800689c ) 80066c2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80066c6: f423 6240 bic.w r2, r3, #3072 @ 0xc00 80066ca: 687b ldr r3, [r7, #4] 80066cc: 699b ldr r3, [r3, #24] 80066ce: 4973 ldr r1, [pc, #460] @ (800689c ) 80066d0: 4313 orrs r3, r2 80066d2: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } /*-------------------------- I2C1 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) 80066d6: 687b ldr r3, [r7, #4] 80066d8: 681b ldr r3, [r3, #0] 80066da: f003 0340 and.w r3, r3, #64 @ 0x40 80066de: 2b00 cmp r3, #0 80066e0: d00a beq.n 80066f8 { /* Check the parameters */ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); /* Configure the I2C1 clock source */ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); 80066e2: 4b6e ldr r3, [pc, #440] @ (800689c ) 80066e4: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80066e8: f423 5240 bic.w r2, r3, #12288 @ 0x3000 80066ec: 687b ldr r3, [r7, #4] 80066ee: 69db ldr r3, [r3, #28] 80066f0: 496a ldr r1, [pc, #424] @ (800689c ) 80066f2: 4313 orrs r3, r2 80066f4: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } /*-------------------------- I2C2 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) 80066f8: 687b ldr r3, [r7, #4] 80066fa: 681b ldr r3, [r3, #0] 80066fc: f003 0380 and.w r3, r3, #128 @ 0x80 8006700: 2b00 cmp r3, #0 8006702: d00a beq.n 800671a { /* Check the parameters */ assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); /* Configure the I2C2 clock source */ __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); 8006704: 4b65 ldr r3, [pc, #404] @ (800689c ) 8006706: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800670a: f423 4240 bic.w r2, r3, #49152 @ 0xc000 800670e: 687b ldr r3, [r7, #4] 8006710: 6a1b ldr r3, [r3, #32] 8006712: 4962 ldr r1, [pc, #392] @ (800689c ) 8006714: 4313 orrs r3, r2 8006716: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } #if defined(I2C3) /*-------------------------- I2C3 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) 800671a: 687b ldr r3, [r7, #4] 800671c: 681b ldr r3, [r3, #0] 800671e: f403 7380 and.w r3, r3, #256 @ 0x100 8006722: 2b00 cmp r3, #0 8006724: d00a beq.n 800673c { /* Check the parameters */ assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); /* Configure the I2C3 clock source */ __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); 8006726: 4b5d ldr r3, [pc, #372] @ (800689c ) 8006728: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800672c: f423 3240 bic.w r2, r3, #196608 @ 0x30000 8006730: 687b ldr r3, [r7, #4] 8006732: 6a5b ldr r3, [r3, #36] @ 0x24 8006734: 4959 ldr r1, [pc, #356] @ (800689c ) 8006736: 4313 orrs r3, r2 8006738: f8c1 3088 str.w r3, [r1, #136] @ 0x88 #endif /* I2C3 */ #if defined(I2C4) /*-------------------------- I2C4 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) 800673c: 687b ldr r3, [r7, #4] 800673e: 681b ldr r3, [r3, #0] 8006740: f403 3300 and.w r3, r3, #131072 @ 0x20000 8006744: 2b00 cmp r3, #0 8006746: d00a beq.n 800675e { /* Check the parameters */ assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); /* Configure the I2C4 clock source */ __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); 8006748: 4b54 ldr r3, [pc, #336] @ (800689c ) 800674a: f8d3 309c ldr.w r3, [r3, #156] @ 0x9c 800674e: f023 0203 bic.w r2, r3, #3 8006752: 687b ldr r3, [r7, #4] 8006754: 6a9b ldr r3, [r3, #40] @ 0x28 8006756: 4951 ldr r1, [pc, #324] @ (800689c ) 8006758: 4313 orrs r3, r2 800675a: f8c1 309c str.w r3, [r1, #156] @ 0x9c } #endif /* I2C4 */ /*-------------------------- LPTIM1 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) 800675e: 687b ldr r3, [r7, #4] 8006760: 681b ldr r3, [r3, #0] 8006762: f403 7300 and.w r3, r3, #512 @ 0x200 8006766: 2b00 cmp r3, #0 8006768: d00a beq.n 8006780 { /* Check the parameters */ assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection)); /* Configure the LPTIM1 clock source */ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); 800676a: 4b4c ldr r3, [pc, #304] @ (800689c ) 800676c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8006770: f423 2240 bic.w r2, r3, #786432 @ 0xc0000 8006774: 687b ldr r3, [r7, #4] 8006776: 6adb ldr r3, [r3, #44] @ 0x2c 8006778: 4948 ldr r1, [pc, #288] @ (800689c ) 800677a: 4313 orrs r3, r2 800677c: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } #if defined(SAI1) /*-------------------------- SAI1 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 8006780: 687b ldr r3, [r7, #4] 8006782: 681b ldr r3, [r3, #0] 8006784: f403 6380 and.w r3, r3, #1024 @ 0x400 8006788: 2b00 cmp r3, #0 800678a: d015 beq.n 80067b8 { /* Check the parameters */ assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); /* Configure the SAI1 interface clock source */ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 800678c: 4b43 ldr r3, [pc, #268] @ (800689c ) 800678e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8006792: f423 1240 bic.w r2, r3, #3145728 @ 0x300000 8006796: 687b ldr r3, [r7, #4] 8006798: 6b1b ldr r3, [r3, #48] @ 0x30 800679a: 4940 ldr r1, [pc, #256] @ (800689c ) 800679c: 4313 orrs r3, r2 800679e: f8c1 3088 str.w r3, [r1, #136] @ 0x88 if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLL) 80067a2: 687b ldr r3, [r7, #4] 80067a4: 6b1b ldr r3, [r3, #48] @ 0x30 80067a6: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 80067aa: d105 bne.n 80067b8 { /* Enable PLL48M1CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); 80067ac: 4b3b ldr r3, [pc, #236] @ (800689c ) 80067ae: 68db ldr r3, [r3, #12] 80067b0: 4a3a ldr r2, [pc, #232] @ (800689c ) 80067b2: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 80067b6: 60d3 str r3, [r2, #12] #endif /* SAI1 */ #if defined(SPI_I2S_SUPPORT) /*-------------------------- I2S clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) 80067b8: 687b ldr r3, [r7, #4] 80067ba: 681b ldr r3, [r3, #0] 80067bc: f403 6300 and.w r3, r3, #2048 @ 0x800 80067c0: 2b00 cmp r3, #0 80067c2: d015 beq.n 80067f0 { /* Check the parameters */ assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); /* Configure the I2S interface clock source */ __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); 80067c4: 4b35 ldr r3, [pc, #212] @ (800689c ) 80067c6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80067ca: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000 80067ce: 687b ldr r3, [r7, #4] 80067d0: 6b5b ldr r3, [r3, #52] @ 0x34 80067d2: 4932 ldr r1, [pc, #200] @ (800689c ) 80067d4: 4313 orrs r3, r2 80067d6: f8c1 3088 str.w r3, [r1, #136] @ 0x88 if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLL) 80067da: 687b ldr r3, [r7, #4] 80067dc: 6b5b ldr r3, [r3, #52] @ 0x34 80067de: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 80067e2: d105 bne.n 80067f0 { /* Enable PLL48M1CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); 80067e4: 4b2d ldr r3, [pc, #180] @ (800689c ) 80067e6: 68db ldr r3, [r3, #12] 80067e8: 4a2c ldr r2, [pc, #176] @ (800689c ) 80067ea: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 80067ee: 60d3 str r3, [r2, #12] #endif /* SPI_I2S_SUPPORT */ #if defined(FDCAN1) /*-------------------------- FDCAN clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) 80067f0: 687b ldr r3, [r7, #4] 80067f2: 681b ldr r3, [r3, #0] 80067f4: f403 5380 and.w r3, r3, #4096 @ 0x1000 80067f8: 2b00 cmp r3, #0 80067fa: d015 beq.n 8006828 { /* Check the parameters */ assert_param(IS_RCC_FDCANCLKSOURCE(PeriphClkInit->FdcanClockSelection)); /* Configure the FDCAN interface clock source */ __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); 80067fc: 4b27 ldr r3, [pc, #156] @ (800689c ) 80067fe: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8006802: f023 7240 bic.w r2, r3, #50331648 @ 0x3000000 8006806: 687b ldr r3, [r7, #4] 8006808: 6b9b ldr r3, [r3, #56] @ 0x38 800680a: 4924 ldr r1, [pc, #144] @ (800689c ) 800680c: 4313 orrs r3, r2 800680e: f8c1 3088 str.w r3, [r1, #136] @ 0x88 if(PeriphClkInit->FdcanClockSelection == RCC_FDCANCLKSOURCE_PLL) 8006812: 687b ldr r3, [r7, #4] 8006814: 6b9b ldr r3, [r3, #56] @ 0x38 8006816: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 800681a: d105 bne.n 8006828 { /* Enable PLL48M1CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); 800681c: 4b1f ldr r3, [pc, #124] @ (800689c ) 800681e: 68db ldr r3, [r3, #12] 8006820: 4a1e ldr r2, [pc, #120] @ (800689c ) 8006822: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 8006826: 60d3 str r3, [r2, #12] #endif /* FDCAN1 */ #if defined(USB) /*-------------------------- USB clock source configuration ----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB)) 8006828: 687b ldr r3, [r7, #4] 800682a: 681b ldr r3, [r3, #0] 800682c: f403 5300 and.w r3, r3, #8192 @ 0x2000 8006830: 2b00 cmp r3, #0 8006832: d015 beq.n 8006860 { assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 8006834: 4b19 ldr r3, [pc, #100] @ (800689c ) 8006836: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800683a: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000 800683e: 687b ldr r3, [r7, #4] 8006840: 6bdb ldr r3, [r3, #60] @ 0x3c 8006842: 4916 ldr r1, [pc, #88] @ (800689c ) 8006844: 4313 orrs r3, r2 8006846: f8c1 3088 str.w r3, [r1, #136] @ 0x88 if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL) 800684a: 687b ldr r3, [r7, #4] 800684c: 6bdb ldr r3, [r3, #60] @ 0x3c 800684e: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 8006852: d105 bne.n 8006860 { /* Enable PLL48M1CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); 8006854: 4b11 ldr r3, [pc, #68] @ (800689c ) 8006856: 68db ldr r3, [r3, #12] 8006858: 4a10 ldr r2, [pc, #64] @ (800689c ) 800685a: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 800685e: 60d3 str r3, [r2, #12] } #endif /* USB */ /*-------------------------- RNG clock source configuration ----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG)) 8006860: 687b ldr r3, [r7, #4] 8006862: 681b ldr r3, [r3, #0] 8006864: f403 4380 and.w r3, r3, #16384 @ 0x4000 8006868: 2b00 cmp r3, #0 800686a: d019 beq.n 80068a0 { assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection)); __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); 800686c: 4b0b ldr r3, [pc, #44] @ (800689c ) 800686e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8006872: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000 8006876: 687b ldr r3, [r7, #4] 8006878: 6c1b ldr r3, [r3, #64] @ 0x40 800687a: 4908 ldr r1, [pc, #32] @ (800689c ) 800687c: 4313 orrs r3, r2 800687e: f8c1 3088 str.w r3, [r1, #136] @ 0x88 if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL) 8006882: 687b ldr r3, [r7, #4] 8006884: 6c1b ldr r3, [r3, #64] @ 0x40 8006886: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800688a: d109 bne.n 80068a0 { /* Enable PLL48M1CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); 800688c: 4b03 ldr r3, [pc, #12] @ (800689c ) 800688e: 68db ldr r3, [r3, #12] 8006890: 4a02 ldr r2, [pc, #8] @ (800689c ) 8006892: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 8006896: 60d3 str r3, [r2, #12] 8006898: e002 b.n 80068a0 800689a: bf00 nop 800689c: 40021000 .word 0x40021000 } } /*-------------------------- ADC12 clock source configuration ----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) 80068a0: 687b ldr r3, [r7, #4] 80068a2: 681b ldr r3, [r3, #0] 80068a4: f403 4300 and.w r3, r3, #32768 @ 0x8000 80068a8: 2b00 cmp r3, #0 80068aa: d015 beq.n 80068d8 { /* Check the parameters */ assert_param(IS_RCC_ADC12CLKSOURCE(PeriphClkInit->Adc12ClockSelection)); /* Configure the ADC12 interface clock source */ __HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection); 80068ac: 4b29 ldr r3, [pc, #164] @ (8006954 ) 80068ae: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80068b2: f023 5240 bic.w r2, r3, #805306368 @ 0x30000000 80068b6: 687b ldr r3, [r7, #4] 80068b8: 6c5b ldr r3, [r3, #68] @ 0x44 80068ba: 4926 ldr r1, [pc, #152] @ (8006954 ) 80068bc: 4313 orrs r3, r2 80068be: f8c1 3088 str.w r3, [r1, #136] @ 0x88 if(PeriphClkInit->Adc12ClockSelection == RCC_ADC12CLKSOURCE_PLL) 80068c2: 687b ldr r3, [r7, #4] 80068c4: 6c5b ldr r3, [r3, #68] @ 0x44 80068c6: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 80068ca: d105 bne.n 80068d8 { /* Enable PLLADCCLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK); 80068cc: 4b21 ldr r3, [pc, #132] @ (8006954 ) 80068ce: 68db ldr r3, [r3, #12] 80068d0: 4a20 ldr r2, [pc, #128] @ (8006954 ) 80068d2: f443 3380 orr.w r3, r3, #65536 @ 0x10000 80068d6: 60d3 str r3, [r2, #12] } } #if defined(ADC345_COMMON) /*-------------------------- ADC345 clock source configuration ----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345) 80068d8: 687b ldr r3, [r7, #4] 80068da: 681b ldr r3, [r3, #0] 80068dc: f403 3380 and.w r3, r3, #65536 @ 0x10000 80068e0: 2b00 cmp r3, #0 80068e2: d015 beq.n 8006910 { /* Check the parameters */ assert_param(IS_RCC_ADC345CLKSOURCE(PeriphClkInit->Adc345ClockSelection)); /* Configure the ADC345 interface clock source */ __HAL_RCC_ADC345_CONFIG(PeriphClkInit->Adc345ClockSelection); 80068e4: 4b1b ldr r3, [pc, #108] @ (8006954 ) 80068e6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80068ea: f023 4240 bic.w r2, r3, #3221225472 @ 0xc0000000 80068ee: 687b ldr r3, [r7, #4] 80068f0: 6c9b ldr r3, [r3, #72] @ 0x48 80068f2: 4918 ldr r1, [pc, #96] @ (8006954 ) 80068f4: 4313 orrs r3, r2 80068f6: f8c1 3088 str.w r3, [r1, #136] @ 0x88 if(PeriphClkInit->Adc345ClockSelection == RCC_ADC345CLKSOURCE_PLL) 80068fa: 687b ldr r3, [r7, #4] 80068fc: 6c9b ldr r3, [r3, #72] @ 0x48 80068fe: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8006902: d105 bne.n 8006910 { /* Enable PLLADCCLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK); 8006904: 4b13 ldr r3, [pc, #76] @ (8006954 ) 8006906: 68db ldr r3, [r3, #12] 8006908: 4a12 ldr r2, [pc, #72] @ (8006954 ) 800690a: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800690e: 60d3 str r3, [r2, #12] #endif /* ADC345_COMMON */ #if defined(QUADSPI) /*-------------------------- QuadSPIx clock source configuration ----------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) 8006910: 687b ldr r3, [r7, #4] 8006912: 681b ldr r3, [r3, #0] 8006914: f403 2380 and.w r3, r3, #262144 @ 0x40000 8006918: 2b00 cmp r3, #0 800691a: d015 beq.n 8006948 { /* Check the parameters */ assert_param(IS_RCC_QSPICLKSOURCE(PeriphClkInit->QspiClockSelection)); /* Configure the QuadSPI clock source */ __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection); 800691c: 4b0d ldr r3, [pc, #52] @ (8006954 ) 800691e: f8d3 309c ldr.w r3, [r3, #156] @ 0x9c 8006922: f423 1240 bic.w r2, r3, #3145728 @ 0x300000 8006926: 687b ldr r3, [r7, #4] 8006928: 6cdb ldr r3, [r3, #76] @ 0x4c 800692a: 490a ldr r1, [pc, #40] @ (8006954 ) 800692c: 4313 orrs r3, r2 800692e: f8c1 309c str.w r3, [r1, #156] @ 0x9c if(PeriphClkInit->QspiClockSelection == RCC_QSPICLKSOURCE_PLL) 8006932: 687b ldr r3, [r7, #4] 8006934: 6cdb ldr r3, [r3, #76] @ 0x4c 8006936: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800693a: d105 bne.n 8006948 { /* Enable PLL48M1CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); 800693c: 4b05 ldr r3, [pc, #20] @ (8006954 ) 800693e: 68db ldr r3, [r3, #12] 8006940: 4a04 ldr r2, [pc, #16] @ (8006954 ) 8006942: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 8006946: 60d3 str r3, [r2, #12] } } #endif /* QUADSPI */ return status; 8006948: 7cbb ldrb r3, [r7, #18] } 800694a: 4618 mov r0, r3 800694c: 3718 adds r7, #24 800694e: 46bd mov sp, r7 8006950: bd80 pop {r7, pc} 8006952: bf00 nop 8006954: 40021000 .word 0x40021000 08006958 : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 8006958: b580 push {r7, lr} 800695a: b082 sub sp, #8 800695c: af00 add r7, sp, #0 800695e: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8006960: 687b ldr r3, [r7, #4] 8006962: 2b00 cmp r3, #0 8006964: d101 bne.n 800696a { return HAL_ERROR; 8006966: 2301 movs r3, #1 8006968: e049 b.n 80069fe assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 800696a: 687b ldr r3, [r7, #4] 800696c: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8006970: b2db uxtb r3, r3 8006972: 2b00 cmp r3, #0 8006974: d106 bne.n 8006984 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8006976: 687b ldr r3, [r7, #4] 8006978: 2200 movs r2, #0 800697a: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 800697e: 6878 ldr r0, [r7, #4] 8006980: f7fa fdf2 bl 8001568 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8006984: 687b ldr r3, [r7, #4] 8006986: 2202 movs r2, #2 8006988: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800698c: 687b ldr r3, [r7, #4] 800698e: 681a ldr r2, [r3, #0] 8006990: 687b ldr r3, [r7, #4] 8006992: 3304 adds r3, #4 8006994: 4619 mov r1, r3 8006996: 4610 mov r0, r2 8006998: f000 fb3c bl 8007014 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 800699c: 687b ldr r3, [r7, #4] 800699e: 2201 movs r2, #1 80069a0: f883 2048 strb.w r2, [r3, #72] @ 0x48 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 80069a4: 687b ldr r3, [r7, #4] 80069a6: 2201 movs r2, #1 80069a8: f883 203e strb.w r2, [r3, #62] @ 0x3e 80069ac: 687b ldr r3, [r7, #4] 80069ae: 2201 movs r2, #1 80069b0: f883 203f strb.w r2, [r3, #63] @ 0x3f 80069b4: 687b ldr r3, [r7, #4] 80069b6: 2201 movs r2, #1 80069b8: f883 2040 strb.w r2, [r3, #64] @ 0x40 80069bc: 687b ldr r3, [r7, #4] 80069be: 2201 movs r2, #1 80069c0: f883 2041 strb.w r2, [r3, #65] @ 0x41 80069c4: 687b ldr r3, [r7, #4] 80069c6: 2201 movs r2, #1 80069c8: f883 2042 strb.w r2, [r3, #66] @ 0x42 80069cc: 687b ldr r3, [r7, #4] 80069ce: 2201 movs r2, #1 80069d0: f883 2043 strb.w r2, [r3, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 80069d4: 687b ldr r3, [r7, #4] 80069d6: 2201 movs r2, #1 80069d8: f883 2044 strb.w r2, [r3, #68] @ 0x44 80069dc: 687b ldr r3, [r7, #4] 80069de: 2201 movs r2, #1 80069e0: f883 2045 strb.w r2, [r3, #69] @ 0x45 80069e4: 687b ldr r3, [r7, #4] 80069e6: 2201 movs r2, #1 80069e8: f883 2046 strb.w r2, [r3, #70] @ 0x46 80069ec: 687b ldr r3, [r7, #4] 80069ee: 2201 movs r2, #1 80069f0: f883 2047 strb.w r2, [r3, #71] @ 0x47 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 80069f4: 687b ldr r3, [r7, #4] 80069f6: 2201 movs r2, #1 80069f8: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 80069fc: 2300 movs r3, #0 } 80069fe: 4618 mov r0, r3 8006a00: 3708 adds r7, #8 8006a02: 46bd mov sp, r7 8006a04: bd80 pop {r7, pc} ... 08006a08 : * @brief Starts the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { 8006a08: b480 push {r7} 8006a0a: b085 sub sp, #20 8006a0c: af00 add r7, sp, #0 8006a0e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) 8006a10: 687b ldr r3, [r7, #4] 8006a12: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8006a16: b2db uxtb r3, r3 8006a18: 2b01 cmp r3, #1 8006a1a: d001 beq.n 8006a20 { return HAL_ERROR; 8006a1c: 2301 movs r3, #1 8006a1e: e054 b.n 8006aca } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8006a20: 687b ldr r3, [r7, #4] 8006a22: 2202 movs r2, #2 8006a24: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 8006a28: 687b ldr r3, [r7, #4] 8006a2a: 681b ldr r3, [r3, #0] 8006a2c: 68da ldr r2, [r3, #12] 8006a2e: 687b ldr r3, [r7, #4] 8006a30: 681b ldr r3, [r3, #0] 8006a32: f042 0201 orr.w r2, r2, #1 8006a36: 60da str r2, [r3, #12] /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8006a38: 687b ldr r3, [r7, #4] 8006a3a: 681b ldr r3, [r3, #0] 8006a3c: 4a26 ldr r2, [pc, #152] @ (8006ad8 ) 8006a3e: 4293 cmp r3, r2 8006a40: d022 beq.n 8006a88 8006a42: 687b ldr r3, [r7, #4] 8006a44: 681b ldr r3, [r3, #0] 8006a46: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8006a4a: d01d beq.n 8006a88 8006a4c: 687b ldr r3, [r7, #4] 8006a4e: 681b ldr r3, [r3, #0] 8006a50: 4a22 ldr r2, [pc, #136] @ (8006adc ) 8006a52: 4293 cmp r3, r2 8006a54: d018 beq.n 8006a88 8006a56: 687b ldr r3, [r7, #4] 8006a58: 681b ldr r3, [r3, #0] 8006a5a: 4a21 ldr r2, [pc, #132] @ (8006ae0 ) 8006a5c: 4293 cmp r3, r2 8006a5e: d013 beq.n 8006a88 8006a60: 687b ldr r3, [r7, #4] 8006a62: 681b ldr r3, [r3, #0] 8006a64: 4a1f ldr r2, [pc, #124] @ (8006ae4 ) 8006a66: 4293 cmp r3, r2 8006a68: d00e beq.n 8006a88 8006a6a: 687b ldr r3, [r7, #4] 8006a6c: 681b ldr r3, [r3, #0] 8006a6e: 4a1e ldr r2, [pc, #120] @ (8006ae8 ) 8006a70: 4293 cmp r3, r2 8006a72: d009 beq.n 8006a88 8006a74: 687b ldr r3, [r7, #4] 8006a76: 681b ldr r3, [r3, #0] 8006a78: 4a1c ldr r2, [pc, #112] @ (8006aec ) 8006a7a: 4293 cmp r3, r2 8006a7c: d004 beq.n 8006a88 8006a7e: 687b ldr r3, [r7, #4] 8006a80: 681b ldr r3, [r3, #0] 8006a82: 4a1b ldr r2, [pc, #108] @ (8006af0 ) 8006a84: 4293 cmp r3, r2 8006a86: d115 bne.n 8006ab4 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 8006a88: 687b ldr r3, [r7, #4] 8006a8a: 681b ldr r3, [r3, #0] 8006a8c: 689a ldr r2, [r3, #8] 8006a8e: 4b19 ldr r3, [pc, #100] @ (8006af4 ) 8006a90: 4013 ands r3, r2 8006a92: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8006a94: 68fb ldr r3, [r7, #12] 8006a96: 2b06 cmp r3, #6 8006a98: d015 beq.n 8006ac6 8006a9a: 68fb ldr r3, [r7, #12] 8006a9c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8006aa0: d011 beq.n 8006ac6 { __HAL_TIM_ENABLE(htim); 8006aa2: 687b ldr r3, [r7, #4] 8006aa4: 681b ldr r3, [r3, #0] 8006aa6: 681a ldr r2, [r3, #0] 8006aa8: 687b ldr r3, [r7, #4] 8006aaa: 681b ldr r3, [r3, #0] 8006aac: f042 0201 orr.w r2, r2, #1 8006ab0: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8006ab2: e008 b.n 8006ac6 } } else { __HAL_TIM_ENABLE(htim); 8006ab4: 687b ldr r3, [r7, #4] 8006ab6: 681b ldr r3, [r3, #0] 8006ab8: 681a ldr r2, [r3, #0] 8006aba: 687b ldr r3, [r7, #4] 8006abc: 681b ldr r3, [r3, #0] 8006abe: f042 0201 orr.w r2, r2, #1 8006ac2: 601a str r2, [r3, #0] 8006ac4: e000 b.n 8006ac8 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8006ac6: bf00 nop } /* Return function status */ return HAL_OK; 8006ac8: 2300 movs r3, #0 } 8006aca: 4618 mov r0, r3 8006acc: 3714 adds r7, #20 8006ace: 46bd mov sp, r7 8006ad0: f85d 7b04 ldr.w r7, [sp], #4 8006ad4: 4770 bx lr 8006ad6: bf00 nop 8006ad8: 40012c00 .word 0x40012c00 8006adc: 40000400 .word 0x40000400 8006ae0: 40000800 .word 0x40000800 8006ae4: 40000c00 .word 0x40000c00 8006ae8: 40013400 .word 0x40013400 8006aec: 40014000 .word 0x40014000 8006af0: 40015000 .word 0x40015000 8006af4: 00010007 .word 0x00010007 08006af8 : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 8006af8: b580 push {r7, lr} 8006afa: b084 sub sp, #16 8006afc: af00 add r7, sp, #0 8006afe: 6078 str r0, [r7, #4] uint32_t itsource = htim->Instance->DIER; 8006b00: 687b ldr r3, [r7, #4] 8006b02: 681b ldr r3, [r3, #0] 8006b04: 68db ldr r3, [r3, #12] 8006b06: 60fb str r3, [r7, #12] uint32_t itflag = htim->Instance->SR; 8006b08: 687b ldr r3, [r7, #4] 8006b0a: 681b ldr r3, [r3, #0] 8006b0c: 691b ldr r3, [r3, #16] 8006b0e: 60bb str r3, [r7, #8] /* Capture compare 1 event */ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) 8006b10: 68bb ldr r3, [r7, #8] 8006b12: f003 0302 and.w r3, r3, #2 8006b16: 2b00 cmp r3, #0 8006b18: d020 beq.n 8006b5c { if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) 8006b1a: 68fb ldr r3, [r7, #12] 8006b1c: f003 0302 and.w r3, r3, #2 8006b20: 2b00 cmp r3, #0 8006b22: d01b beq.n 8006b5c { { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); 8006b24: 687b ldr r3, [r7, #4] 8006b26: 681b ldr r3, [r3, #0] 8006b28: f06f 0202 mvn.w r2, #2 8006b2c: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 8006b2e: 687b ldr r3, [r7, #4] 8006b30: 2201 movs r2, #1 8006b32: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 8006b34: 687b ldr r3, [r7, #4] 8006b36: 681b ldr r3, [r3, #0] 8006b38: 699b ldr r3, [r3, #24] 8006b3a: f003 0303 and.w r3, r3, #3 8006b3e: 2b00 cmp r3, #0 8006b40: d003 beq.n 8006b4a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8006b42: 6878 ldr r0, [r7, #4] 8006b44: f000 fa48 bl 8006fd8 8006b48: e005 b.n 8006b56 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8006b4a: 6878 ldr r0, [r7, #4] 8006b4c: f000 fa3a bl 8006fc4 HAL_TIM_PWM_PulseFinishedCallback(htim); 8006b50: 6878 ldr r0, [r7, #4] 8006b52: f000 fa4b bl 8006fec #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8006b56: 687b ldr r3, [r7, #4] 8006b58: 2200 movs r2, #0 8006b5a: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) 8006b5c: 68bb ldr r3, [r7, #8] 8006b5e: f003 0304 and.w r3, r3, #4 8006b62: 2b00 cmp r3, #0 8006b64: d020 beq.n 8006ba8 { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) 8006b66: 68fb ldr r3, [r7, #12] 8006b68: f003 0304 and.w r3, r3, #4 8006b6c: 2b00 cmp r3, #0 8006b6e: d01b beq.n 8006ba8 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); 8006b70: 687b ldr r3, [r7, #4] 8006b72: 681b ldr r3, [r3, #0] 8006b74: f06f 0204 mvn.w r2, #4 8006b78: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 8006b7a: 687b ldr r3, [r7, #4] 8006b7c: 2202 movs r2, #2 8006b7e: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 8006b80: 687b ldr r3, [r7, #4] 8006b82: 681b ldr r3, [r3, #0] 8006b84: 699b ldr r3, [r3, #24] 8006b86: f403 7340 and.w r3, r3, #768 @ 0x300 8006b8a: 2b00 cmp r3, #0 8006b8c: d003 beq.n 8006b96 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8006b8e: 6878 ldr r0, [r7, #4] 8006b90: f000 fa22 bl 8006fd8 8006b94: e005 b.n 8006ba2 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8006b96: 6878 ldr r0, [r7, #4] 8006b98: f000 fa14 bl 8006fc4 HAL_TIM_PWM_PulseFinishedCallback(htim); 8006b9c: 6878 ldr r0, [r7, #4] 8006b9e: f000 fa25 bl 8006fec #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8006ba2: 687b ldr r3, [r7, #4] 8006ba4: 2200 movs r2, #0 8006ba6: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) 8006ba8: 68bb ldr r3, [r7, #8] 8006baa: f003 0308 and.w r3, r3, #8 8006bae: 2b00 cmp r3, #0 8006bb0: d020 beq.n 8006bf4 { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) 8006bb2: 68fb ldr r3, [r7, #12] 8006bb4: f003 0308 and.w r3, r3, #8 8006bb8: 2b00 cmp r3, #0 8006bba: d01b beq.n 8006bf4 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); 8006bbc: 687b ldr r3, [r7, #4] 8006bbe: 681b ldr r3, [r3, #0] 8006bc0: f06f 0208 mvn.w r2, #8 8006bc4: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 8006bc6: 687b ldr r3, [r7, #4] 8006bc8: 2204 movs r2, #4 8006bca: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 8006bcc: 687b ldr r3, [r7, #4] 8006bce: 681b ldr r3, [r3, #0] 8006bd0: 69db ldr r3, [r3, #28] 8006bd2: f003 0303 and.w r3, r3, #3 8006bd6: 2b00 cmp r3, #0 8006bd8: d003 beq.n 8006be2 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8006bda: 6878 ldr r0, [r7, #4] 8006bdc: f000 f9fc bl 8006fd8 8006be0: e005 b.n 8006bee { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8006be2: 6878 ldr r0, [r7, #4] 8006be4: f000 f9ee bl 8006fc4 HAL_TIM_PWM_PulseFinishedCallback(htim); 8006be8: 6878 ldr r0, [r7, #4] 8006bea: f000 f9ff bl 8006fec #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8006bee: 687b ldr r3, [r7, #4] 8006bf0: 2200 movs r2, #0 8006bf2: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) 8006bf4: 68bb ldr r3, [r7, #8] 8006bf6: f003 0310 and.w r3, r3, #16 8006bfa: 2b00 cmp r3, #0 8006bfc: d020 beq.n 8006c40 { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) 8006bfe: 68fb ldr r3, [r7, #12] 8006c00: f003 0310 and.w r3, r3, #16 8006c04: 2b00 cmp r3, #0 8006c06: d01b beq.n 8006c40 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); 8006c08: 687b ldr r3, [r7, #4] 8006c0a: 681b ldr r3, [r3, #0] 8006c0c: f06f 0210 mvn.w r2, #16 8006c10: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 8006c12: 687b ldr r3, [r7, #4] 8006c14: 2208 movs r2, #8 8006c16: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 8006c18: 687b ldr r3, [r7, #4] 8006c1a: 681b ldr r3, [r3, #0] 8006c1c: 69db ldr r3, [r3, #28] 8006c1e: f403 7340 and.w r3, r3, #768 @ 0x300 8006c22: 2b00 cmp r3, #0 8006c24: d003 beq.n 8006c2e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8006c26: 6878 ldr r0, [r7, #4] 8006c28: f000 f9d6 bl 8006fd8 8006c2c: e005 b.n 8006c3a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8006c2e: 6878 ldr r0, [r7, #4] 8006c30: f000 f9c8 bl 8006fc4 HAL_TIM_PWM_PulseFinishedCallback(htim); 8006c34: 6878 ldr r0, [r7, #4] 8006c36: f000 f9d9 bl 8006fec #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8006c3a: 687b ldr r3, [r7, #4] 8006c3c: 2200 movs r2, #0 8006c3e: 771a strb r2, [r3, #28] } } /* TIM Update event */ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) 8006c40: 68bb ldr r3, [r7, #8] 8006c42: f003 0301 and.w r3, r3, #1 8006c46: 2b00 cmp r3, #0 8006c48: d00c beq.n 8006c64 { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) 8006c4a: 68fb ldr r3, [r7, #12] 8006c4c: f003 0301 and.w r3, r3, #1 8006c50: 2b00 cmp r3, #0 8006c52: d007 beq.n 8006c64 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); 8006c54: 687b ldr r3, [r7, #4] 8006c56: 681b ldr r3, [r3, #0] 8006c58: f06f 0201 mvn.w r2, #1 8006c5c: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 8006c5e: 6878 ldr r0, [r7, #4] 8006c60: f7fa f9a0 bl 8000fa4 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ 8006c64: 68bb ldr r3, [r7, #8] 8006c66: f003 0380 and.w r3, r3, #128 @ 0x80 8006c6a: 2b00 cmp r3, #0 8006c6c: d104 bne.n 8006c78 ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK))) 8006c6e: 68bb ldr r3, [r7, #8] 8006c70: f403 5300 and.w r3, r3, #8192 @ 0x2000 if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ 8006c74: 2b00 cmp r3, #0 8006c76: d00c beq.n 8006c92 { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 8006c78: 68fb ldr r3, [r7, #12] 8006c7a: f003 0380 and.w r3, r3, #128 @ 0x80 8006c7e: 2b00 cmp r3, #0 8006c80: d007 beq.n 8006c92 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK); 8006c82: 687b ldr r3, [r7, #4] 8006c84: 681b ldr r3, [r3, #0] 8006c86: f46f 5202 mvn.w r2, #8320 @ 0x2080 8006c8a: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 8006c8c: 6878 ldr r0, [r7, #4] 8006c8e: f000 fbb1 bl 80073f4 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break2 input event */ if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) 8006c92: 68bb ldr r3, [r7, #8] 8006c94: f403 7380 and.w r3, r3, #256 @ 0x100 8006c98: 2b00 cmp r3, #0 8006c9a: d00c beq.n 8006cb6 { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 8006c9c: 68fb ldr r3, [r7, #12] 8006c9e: f003 0380 and.w r3, r3, #128 @ 0x80 8006ca2: 2b00 cmp r3, #0 8006ca4: d007 beq.n 8006cb6 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); 8006ca6: 687b ldr r3, [r7, #4] 8006ca8: 681b ldr r3, [r3, #0] 8006caa: f46f 7280 mvn.w r2, #256 @ 0x100 8006cae: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->Break2Callback(htim); #else HAL_TIMEx_Break2Callback(htim); 8006cb0: 6878 ldr r0, [r7, #4] 8006cb2: f000 fba9 bl 8007408 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) 8006cb6: 68bb ldr r3, [r7, #8] 8006cb8: f003 0340 and.w r3, r3, #64 @ 0x40 8006cbc: 2b00 cmp r3, #0 8006cbe: d00c beq.n 8006cda { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) 8006cc0: 68fb ldr r3, [r7, #12] 8006cc2: f003 0340 and.w r3, r3, #64 @ 0x40 8006cc6: 2b00 cmp r3, #0 8006cc8: d007 beq.n 8006cda { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); 8006cca: 687b ldr r3, [r7, #4] 8006ccc: 681b ldr r3, [r3, #0] 8006cce: f06f 0240 mvn.w r2, #64 @ 0x40 8006cd2: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 8006cd4: 6878 ldr r0, [r7, #4] 8006cd6: f000 f993 bl 8007000 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) 8006cda: 68bb ldr r3, [r7, #8] 8006cdc: f003 0320 and.w r3, r3, #32 8006ce0: 2b00 cmp r3, #0 8006ce2: d00c beq.n 8006cfe { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) 8006ce4: 68fb ldr r3, [r7, #12] 8006ce6: f003 0320 and.w r3, r3, #32 8006cea: 2b00 cmp r3, #0 8006cec: d007 beq.n 8006cfe { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); 8006cee: 687b ldr r3, [r7, #4] 8006cf0: 681b ldr r3, [r3, #0] 8006cf2: f06f 0220 mvn.w r2, #32 8006cf6: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 8006cf8: 6878 ldr r0, [r7, #4] 8006cfa: f000 fb71 bl 80073e0 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Encoder index event */ if ((itflag & (TIM_FLAG_IDX)) == (TIM_FLAG_IDX)) 8006cfe: 68bb ldr r3, [r7, #8] 8006d00: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8006d04: 2b00 cmp r3, #0 8006d06: d00c beq.n 8006d22 { if ((itsource & (TIM_IT_IDX)) == (TIM_IT_IDX)) 8006d08: 68fb ldr r3, [r7, #12] 8006d0a: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8006d0e: 2b00 cmp r3, #0 8006d10: d007 beq.n 8006d22 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IDX); 8006d12: 687b ldr r3, [r7, #4] 8006d14: 681b ldr r3, [r3, #0] 8006d16: f46f 1280 mvn.w r2, #1048576 @ 0x100000 8006d1a: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->EncoderIndexCallback(htim); #else HAL_TIMEx_EncoderIndexCallback(htim); 8006d1c: 6878 ldr r0, [r7, #4] 8006d1e: f000 fb7d bl 800741c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Direction change event */ if ((itflag & (TIM_FLAG_DIR)) == (TIM_FLAG_DIR)) 8006d22: 68bb ldr r3, [r7, #8] 8006d24: f403 1300 and.w r3, r3, #2097152 @ 0x200000 8006d28: 2b00 cmp r3, #0 8006d2a: d00c beq.n 8006d46 { if ((itsource & (TIM_IT_DIR)) == (TIM_IT_DIR)) 8006d2c: 68fb ldr r3, [r7, #12] 8006d2e: f403 1300 and.w r3, r3, #2097152 @ 0x200000 8006d32: 2b00 cmp r3, #0 8006d34: d007 beq.n 8006d46 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_DIR); 8006d36: 687b ldr r3, [r7, #4] 8006d38: 681b ldr r3, [r3, #0] 8006d3a: f46f 1200 mvn.w r2, #2097152 @ 0x200000 8006d3e: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->DirectionChangeCallback(htim); #else HAL_TIMEx_DirectionChangeCallback(htim); 8006d40: 6878 ldr r0, [r7, #4] 8006d42: f000 fb75 bl 8007430 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Index error event */ if ((itflag & (TIM_FLAG_IERR)) == (TIM_FLAG_IERR)) 8006d46: 68bb ldr r3, [r7, #8] 8006d48: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8006d4c: 2b00 cmp r3, #0 8006d4e: d00c beq.n 8006d6a { if ((itsource & (TIM_IT_IERR)) == (TIM_IT_IERR)) 8006d50: 68fb ldr r3, [r7, #12] 8006d52: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8006d56: 2b00 cmp r3, #0 8006d58: d007 beq.n 8006d6a { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IERR); 8006d5a: 687b ldr r3, [r7, #4] 8006d5c: 681b ldr r3, [r3, #0] 8006d5e: f46f 0280 mvn.w r2, #4194304 @ 0x400000 8006d62: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IndexErrorCallback(htim); #else HAL_TIMEx_IndexErrorCallback(htim); 8006d64: 6878 ldr r0, [r7, #4] 8006d66: f000 fb6d bl 8007444 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Transition error event */ if ((itflag & (TIM_FLAG_TERR)) == (TIM_FLAG_TERR)) 8006d6a: 68bb ldr r3, [r7, #8] 8006d6c: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8006d70: 2b00 cmp r3, #0 8006d72: d00c beq.n 8006d8e { if ((itsource & (TIM_IT_TERR)) == (TIM_IT_TERR)) 8006d74: 68fb ldr r3, [r7, #12] 8006d76: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8006d7a: 2b00 cmp r3, #0 8006d7c: d007 beq.n 8006d8e { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TERR); 8006d7e: 687b ldr r3, [r7, #4] 8006d80: 681b ldr r3, [r3, #0] 8006d82: f46f 0200 mvn.w r2, #8388608 @ 0x800000 8006d86: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TransitionErrorCallback(htim); #else HAL_TIMEx_TransitionErrorCallback(htim); 8006d88: 6878 ldr r0, [r7, #4] 8006d8a: f000 fb65 bl 8007458 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 8006d8e: bf00 nop 8006d90: 3710 adds r7, #16 8006d92: 46bd mov sp, r7 8006d94: bd80 pop {r7, pc} ... 08006d98 : * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) { 8006d98: b580 push {r7, lr} 8006d9a: b084 sub sp, #16 8006d9c: af00 add r7, sp, #0 8006d9e: 6078 str r0, [r7, #4] 8006da0: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8006da2: 2300 movs r3, #0 8006da4: 73fb strb r3, [r7, #15] uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); 8006da6: 687b ldr r3, [r7, #4] 8006da8: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8006dac: 2b01 cmp r3, #1 8006dae: d101 bne.n 8006db4 8006db0: 2302 movs r3, #2 8006db2: e0f6 b.n 8006fa2 8006db4: 687b ldr r3, [r7, #4] 8006db6: 2201 movs r2, #1 8006db8: f883 203c strb.w r2, [r3, #60] @ 0x3c htim->State = HAL_TIM_STATE_BUSY; 8006dbc: 687b ldr r3, [r7, #4] 8006dbe: 2202 movs r2, #2 8006dc0: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; 8006dc4: 687b ldr r3, [r7, #4] 8006dc6: 681b ldr r3, [r3, #0] 8006dc8: 689b ldr r3, [r3, #8] 8006dca: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); 8006dcc: 68bb ldr r3, [r7, #8] 8006dce: f423 1344 bic.w r3, r3, #3211264 @ 0x310000 8006dd2: f023 0377 bic.w r3, r3, #119 @ 0x77 8006dd6: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8006dd8: 68bb ldr r3, [r7, #8] 8006dda: f423 437f bic.w r3, r3, #65280 @ 0xff00 8006dde: 60bb str r3, [r7, #8] htim->Instance->SMCR = tmpsmcr; 8006de0: 687b ldr r3, [r7, #4] 8006de2: 681b ldr r3, [r3, #0] 8006de4: 68ba ldr r2, [r7, #8] 8006de6: 609a str r2, [r3, #8] switch (sClockSourceConfig->ClockSource) 8006de8: 683b ldr r3, [r7, #0] 8006dea: 681b ldr r3, [r3, #0] 8006dec: 4a6f ldr r2, [pc, #444] @ (8006fac ) 8006dee: 4293 cmp r3, r2 8006df0: f000 80c1 beq.w 8006f76 8006df4: 4a6d ldr r2, [pc, #436] @ (8006fac ) 8006df6: 4293 cmp r3, r2 8006df8: f200 80c6 bhi.w 8006f88 8006dfc: 4a6c ldr r2, [pc, #432] @ (8006fb0 ) 8006dfe: 4293 cmp r3, r2 8006e00: f000 80b9 beq.w 8006f76 8006e04: 4a6a ldr r2, [pc, #424] @ (8006fb0 ) 8006e06: 4293 cmp r3, r2 8006e08: f200 80be bhi.w 8006f88 8006e0c: 4a69 ldr r2, [pc, #420] @ (8006fb4 ) 8006e0e: 4293 cmp r3, r2 8006e10: f000 80b1 beq.w 8006f76 8006e14: 4a67 ldr r2, [pc, #412] @ (8006fb4 ) 8006e16: 4293 cmp r3, r2 8006e18: f200 80b6 bhi.w 8006f88 8006e1c: 4a66 ldr r2, [pc, #408] @ (8006fb8 ) 8006e1e: 4293 cmp r3, r2 8006e20: f000 80a9 beq.w 8006f76 8006e24: 4a64 ldr r2, [pc, #400] @ (8006fb8 ) 8006e26: 4293 cmp r3, r2 8006e28: f200 80ae bhi.w 8006f88 8006e2c: 4a63 ldr r2, [pc, #396] @ (8006fbc ) 8006e2e: 4293 cmp r3, r2 8006e30: f000 80a1 beq.w 8006f76 8006e34: 4a61 ldr r2, [pc, #388] @ (8006fbc ) 8006e36: 4293 cmp r3, r2 8006e38: f200 80a6 bhi.w 8006f88 8006e3c: 4a60 ldr r2, [pc, #384] @ (8006fc0 ) 8006e3e: 4293 cmp r3, r2 8006e40: f000 8099 beq.w 8006f76 8006e44: 4a5e ldr r2, [pc, #376] @ (8006fc0 ) 8006e46: 4293 cmp r3, r2 8006e48: f200 809e bhi.w 8006f88 8006e4c: f1b3 1f10 cmp.w r3, #1048592 @ 0x100010 8006e50: f000 8091 beq.w 8006f76 8006e54: f1b3 1f10 cmp.w r3, #1048592 @ 0x100010 8006e58: f200 8096 bhi.w 8006f88 8006e5c: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8006e60: f000 8089 beq.w 8006f76 8006e64: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8006e68: f200 808e bhi.w 8006f88 8006e6c: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8006e70: d03e beq.n 8006ef0 8006e72: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8006e76: f200 8087 bhi.w 8006f88 8006e7a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8006e7e: f000 8086 beq.w 8006f8e 8006e82: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8006e86: d87f bhi.n 8006f88 8006e88: 2b70 cmp r3, #112 @ 0x70 8006e8a: d01a beq.n 8006ec2 8006e8c: 2b70 cmp r3, #112 @ 0x70 8006e8e: d87b bhi.n 8006f88 8006e90: 2b60 cmp r3, #96 @ 0x60 8006e92: d050 beq.n 8006f36 8006e94: 2b60 cmp r3, #96 @ 0x60 8006e96: d877 bhi.n 8006f88 8006e98: 2b50 cmp r3, #80 @ 0x50 8006e9a: d03c beq.n 8006f16 8006e9c: 2b50 cmp r3, #80 @ 0x50 8006e9e: d873 bhi.n 8006f88 8006ea0: 2b40 cmp r3, #64 @ 0x40 8006ea2: d058 beq.n 8006f56 8006ea4: 2b40 cmp r3, #64 @ 0x40 8006ea6: d86f bhi.n 8006f88 8006ea8: 2b30 cmp r3, #48 @ 0x30 8006eaa: d064 beq.n 8006f76 8006eac: 2b30 cmp r3, #48 @ 0x30 8006eae: d86b bhi.n 8006f88 8006eb0: 2b20 cmp r3, #32 8006eb2: d060 beq.n 8006f76 8006eb4: 2b20 cmp r3, #32 8006eb6: d867 bhi.n 8006f88 8006eb8: 2b00 cmp r3, #0 8006eba: d05c beq.n 8006f76 8006ebc: 2b10 cmp r3, #16 8006ebe: d05a beq.n 8006f76 8006ec0: e062 b.n 8006f88 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 8006ec2: 687b ldr r3, [r7, #4] 8006ec4: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 8006ec6: 683b ldr r3, [r7, #0] 8006ec8: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 8006eca: 683b ldr r3, [r7, #0] 8006ecc: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 8006ece: 683b ldr r3, [r7, #0] 8006ed0: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 8006ed2: f000 f9cf bl 8007274 /* Select the External clock mode1 and the ETRF trigger */ tmpsmcr = htim->Instance->SMCR; 8006ed6: 687b ldr r3, [r7, #4] 8006ed8: 681b ldr r3, [r3, #0] 8006eda: 689b ldr r3, [r3, #8] 8006edc: 60bb str r3, [r7, #8] tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); 8006ede: 68bb ldr r3, [r7, #8] 8006ee0: f043 0377 orr.w r3, r3, #119 @ 0x77 8006ee4: 60bb str r3, [r7, #8] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8006ee6: 687b ldr r3, [r7, #4] 8006ee8: 681b ldr r3, [r3, #0] 8006eea: 68ba ldr r2, [r7, #8] 8006eec: 609a str r2, [r3, #8] break; 8006eee: e04f b.n 8006f90 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 8006ef0: 687b ldr r3, [r7, #4] 8006ef2: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 8006ef4: 683b ldr r3, [r7, #0] 8006ef6: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 8006ef8: 683b ldr r3, [r7, #0] 8006efa: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 8006efc: 683b ldr r3, [r7, #0] 8006efe: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 8006f00: f000 f9b8 bl 8007274 /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; 8006f04: 687b ldr r3, [r7, #4] 8006f06: 681b ldr r3, [r3, #0] 8006f08: 689a ldr r2, [r3, #8] 8006f0a: 687b ldr r3, [r7, #4] 8006f0c: 681b ldr r3, [r3, #0] 8006f0e: f442 4280 orr.w r2, r2, #16384 @ 0x4000 8006f12: 609a str r2, [r3, #8] break; 8006f14: e03c b.n 8006f90 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 8006f16: 687b ldr r3, [r7, #4] 8006f18: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 8006f1a: 683b ldr r3, [r7, #0] 8006f1c: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 8006f1e: 683b ldr r3, [r7, #0] 8006f20: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 8006f22: 461a mov r2, r3 8006f24: f000 f92a bl 800717c TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); 8006f28: 687b ldr r3, [r7, #4] 8006f2a: 681b ldr r3, [r3, #0] 8006f2c: 2150 movs r1, #80 @ 0x50 8006f2e: 4618 mov r0, r3 8006f30: f000 f983 bl 800723a break; 8006f34: e02c b.n 8006f90 /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI2_ConfigInputStage(htim->Instance, 8006f36: 687b ldr r3, [r7, #4] 8006f38: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 8006f3a: 683b ldr r3, [r7, #0] 8006f3c: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 8006f3e: 683b ldr r3, [r7, #0] 8006f40: 68db ldr r3, [r3, #12] TIM_TI2_ConfigInputStage(htim->Instance, 8006f42: 461a mov r2, r3 8006f44: f000 f949 bl 80071da TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); 8006f48: 687b ldr r3, [r7, #4] 8006f4a: 681b ldr r3, [r3, #0] 8006f4c: 2160 movs r1, #96 @ 0x60 8006f4e: 4618 mov r0, r3 8006f50: f000 f973 bl 800723a break; 8006f54: e01c b.n 8006f90 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 8006f56: 687b ldr r3, [r7, #4] 8006f58: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 8006f5a: 683b ldr r3, [r7, #0] 8006f5c: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 8006f5e: 683b ldr r3, [r7, #0] 8006f60: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 8006f62: 461a mov r2, r3 8006f64: f000 f90a bl 800717c TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); 8006f68: 687b ldr r3, [r7, #4] 8006f6a: 681b ldr r3, [r3, #0] 8006f6c: 2140 movs r1, #64 @ 0x40 8006f6e: 4618 mov r0, r3 8006f70: f000 f963 bl 800723a break; 8006f74: e00c b.n 8006f90 case TIM_CLOCKSOURCE_ITR11: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_INSTANCE((htim->Instance), sClockSourceConfig->ClockSource)); TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); 8006f76: 687b ldr r3, [r7, #4] 8006f78: 681a ldr r2, [r3, #0] 8006f7a: 683b ldr r3, [r7, #0] 8006f7c: 681b ldr r3, [r3, #0] 8006f7e: 4619 mov r1, r3 8006f80: 4610 mov r0, r2 8006f82: f000 f95a bl 800723a break; 8006f86: e003 b.n 8006f90 } default: status = HAL_ERROR; 8006f88: 2301 movs r3, #1 8006f8a: 73fb strb r3, [r7, #15] break; 8006f8c: e000 b.n 8006f90 break; 8006f8e: bf00 nop } htim->State = HAL_TIM_STATE_READY; 8006f90: 687b ldr r3, [r7, #4] 8006f92: 2201 movs r2, #1 8006f94: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 8006f98: 687b ldr r3, [r7, #4] 8006f9a: 2200 movs r2, #0 8006f9c: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 8006fa0: 7bfb ldrb r3, [r7, #15] } 8006fa2: 4618 mov r0, r3 8006fa4: 3710 adds r7, #16 8006fa6: 46bd mov sp, r7 8006fa8: bd80 pop {r7, pc} 8006faa: bf00 nop 8006fac: 00100070 .word 0x00100070 8006fb0: 00100060 .word 0x00100060 8006fb4: 00100050 .word 0x00100050 8006fb8: 00100040 .word 0x00100040 8006fbc: 00100030 .word 0x00100030 8006fc0: 00100020 .word 0x00100020 08006fc4 : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 8006fc4: b480 push {r7} 8006fc6: b083 sub sp, #12 8006fc8: af00 add r7, sp, #0 8006fca: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } 8006fcc: bf00 nop 8006fce: 370c adds r7, #12 8006fd0: 46bd mov sp, r7 8006fd2: f85d 7b04 ldr.w r7, [sp], #4 8006fd6: 4770 bx lr 08006fd8 : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 8006fd8: b480 push {r7} 8006fda: b083 sub sp, #12 8006fdc: af00 add r7, sp, #0 8006fde: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } 8006fe0: bf00 nop 8006fe2: 370c adds r7, #12 8006fe4: 46bd mov sp, r7 8006fe6: f85d 7b04 ldr.w r7, [sp], #4 8006fea: 4770 bx lr 08006fec : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 8006fec: b480 push {r7} 8006fee: b083 sub sp, #12 8006ff0: af00 add r7, sp, #0 8006ff2: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 8006ff4: bf00 nop 8006ff6: 370c adds r7, #12 8006ff8: 46bd mov sp, r7 8006ffa: f85d 7b04 ldr.w r7, [sp], #4 8006ffe: 4770 bx lr 08007000 : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 8007000: b480 push {r7} 8007002: b083 sub sp, #12 8007004: af00 add r7, sp, #0 8007006: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 8007008: bf00 nop 800700a: 370c adds r7, #12 800700c: 46bd mov sp, r7 800700e: f85d 7b04 ldr.w r7, [sp], #4 8007012: 4770 bx lr 08007014 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 8007014: b480 push {r7} 8007016: b085 sub sp, #20 8007018: af00 add r7, sp, #0 800701a: 6078 str r0, [r7, #4] 800701c: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 800701e: 687b ldr r3, [r7, #4] 8007020: 681b ldr r3, [r3, #0] 8007022: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8007024: 687b ldr r3, [r7, #4] 8007026: 4a4c ldr r2, [pc, #304] @ (8007158 ) 8007028: 4293 cmp r3, r2 800702a: d017 beq.n 800705c 800702c: 687b ldr r3, [r7, #4] 800702e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8007032: d013 beq.n 800705c 8007034: 687b ldr r3, [r7, #4] 8007036: 4a49 ldr r2, [pc, #292] @ (800715c ) 8007038: 4293 cmp r3, r2 800703a: d00f beq.n 800705c 800703c: 687b ldr r3, [r7, #4] 800703e: 4a48 ldr r2, [pc, #288] @ (8007160 ) 8007040: 4293 cmp r3, r2 8007042: d00b beq.n 800705c 8007044: 687b ldr r3, [r7, #4] 8007046: 4a47 ldr r2, [pc, #284] @ (8007164 ) 8007048: 4293 cmp r3, r2 800704a: d007 beq.n 800705c 800704c: 687b ldr r3, [r7, #4] 800704e: 4a46 ldr r2, [pc, #280] @ (8007168 ) 8007050: 4293 cmp r3, r2 8007052: d003 beq.n 800705c 8007054: 687b ldr r3, [r7, #4] 8007056: 4a45 ldr r2, [pc, #276] @ (800716c ) 8007058: 4293 cmp r3, r2 800705a: d108 bne.n 800706e { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 800705c: 68fb ldr r3, [r7, #12] 800705e: f023 0370 bic.w r3, r3, #112 @ 0x70 8007062: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 8007064: 683b ldr r3, [r7, #0] 8007066: 685b ldr r3, [r3, #4] 8007068: 68fa ldr r2, [r7, #12] 800706a: 4313 orrs r3, r2 800706c: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 800706e: 687b ldr r3, [r7, #4] 8007070: 4a39 ldr r2, [pc, #228] @ (8007158 ) 8007072: 4293 cmp r3, r2 8007074: d023 beq.n 80070be 8007076: 687b ldr r3, [r7, #4] 8007078: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800707c: d01f beq.n 80070be 800707e: 687b ldr r3, [r7, #4] 8007080: 4a36 ldr r2, [pc, #216] @ (800715c ) 8007082: 4293 cmp r3, r2 8007084: d01b beq.n 80070be 8007086: 687b ldr r3, [r7, #4] 8007088: 4a35 ldr r2, [pc, #212] @ (8007160 ) 800708a: 4293 cmp r3, r2 800708c: d017 beq.n 80070be 800708e: 687b ldr r3, [r7, #4] 8007090: 4a34 ldr r2, [pc, #208] @ (8007164 ) 8007092: 4293 cmp r3, r2 8007094: d013 beq.n 80070be 8007096: 687b ldr r3, [r7, #4] 8007098: 4a33 ldr r2, [pc, #204] @ (8007168 ) 800709a: 4293 cmp r3, r2 800709c: d00f beq.n 80070be 800709e: 687b ldr r3, [r7, #4] 80070a0: 4a33 ldr r2, [pc, #204] @ (8007170 ) 80070a2: 4293 cmp r3, r2 80070a4: d00b beq.n 80070be 80070a6: 687b ldr r3, [r7, #4] 80070a8: 4a32 ldr r2, [pc, #200] @ (8007174 ) 80070aa: 4293 cmp r3, r2 80070ac: d007 beq.n 80070be 80070ae: 687b ldr r3, [r7, #4] 80070b0: 4a31 ldr r2, [pc, #196] @ (8007178 ) 80070b2: 4293 cmp r3, r2 80070b4: d003 beq.n 80070be 80070b6: 687b ldr r3, [r7, #4] 80070b8: 4a2c ldr r2, [pc, #176] @ (800716c ) 80070ba: 4293 cmp r3, r2 80070bc: d108 bne.n 80070d0 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 80070be: 68fb ldr r3, [r7, #12] 80070c0: f423 7340 bic.w r3, r3, #768 @ 0x300 80070c4: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 80070c6: 683b ldr r3, [r7, #0] 80070c8: 68db ldr r3, [r3, #12] 80070ca: 68fa ldr r2, [r7, #12] 80070cc: 4313 orrs r3, r2 80070ce: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 80070d0: 68fb ldr r3, [r7, #12] 80070d2: f023 0280 bic.w r2, r3, #128 @ 0x80 80070d6: 683b ldr r3, [r7, #0] 80070d8: 695b ldr r3, [r3, #20] 80070da: 4313 orrs r3, r2 80070dc: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 80070de: 687b ldr r3, [r7, #4] 80070e0: 68fa ldr r2, [r7, #12] 80070e2: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 80070e4: 683b ldr r3, [r7, #0] 80070e6: 689a ldr r2, [r3, #8] 80070e8: 687b ldr r3, [r7, #4] 80070ea: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 80070ec: 683b ldr r3, [r7, #0] 80070ee: 681a ldr r2, [r3, #0] 80070f0: 687b ldr r3, [r7, #4] 80070f2: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 80070f4: 687b ldr r3, [r7, #4] 80070f6: 4a18 ldr r2, [pc, #96] @ (8007158 ) 80070f8: 4293 cmp r3, r2 80070fa: d013 beq.n 8007124 80070fc: 687b ldr r3, [r7, #4] 80070fe: 4a1a ldr r2, [pc, #104] @ (8007168 ) 8007100: 4293 cmp r3, r2 8007102: d00f beq.n 8007124 8007104: 687b ldr r3, [r7, #4] 8007106: 4a1a ldr r2, [pc, #104] @ (8007170 ) 8007108: 4293 cmp r3, r2 800710a: d00b beq.n 8007124 800710c: 687b ldr r3, [r7, #4] 800710e: 4a19 ldr r2, [pc, #100] @ (8007174 ) 8007110: 4293 cmp r3, r2 8007112: d007 beq.n 8007124 8007114: 687b ldr r3, [r7, #4] 8007116: 4a18 ldr r2, [pc, #96] @ (8007178 ) 8007118: 4293 cmp r3, r2 800711a: d003 beq.n 8007124 800711c: 687b ldr r3, [r7, #4] 800711e: 4a13 ldr r2, [pc, #76] @ (800716c ) 8007120: 4293 cmp r3, r2 8007122: d103 bne.n 800712c { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 8007124: 683b ldr r3, [r7, #0] 8007126: 691a ldr r2, [r3, #16] 8007128: 687b ldr r3, [r7, #4] 800712a: 631a str r2, [r3, #48] @ 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 800712c: 687b ldr r3, [r7, #4] 800712e: 2201 movs r2, #1 8007130: 615a str r2, [r3, #20] /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) 8007132: 687b ldr r3, [r7, #4] 8007134: 691b ldr r3, [r3, #16] 8007136: f003 0301 and.w r3, r3, #1 800713a: 2b01 cmp r3, #1 800713c: d105 bne.n 800714a { /* Clear the update flag */ CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); 800713e: 687b ldr r3, [r7, #4] 8007140: 691b ldr r3, [r3, #16] 8007142: f023 0201 bic.w r2, r3, #1 8007146: 687b ldr r3, [r7, #4] 8007148: 611a str r2, [r3, #16] } } 800714a: bf00 nop 800714c: 3714 adds r7, #20 800714e: 46bd mov sp, r7 8007150: f85d 7b04 ldr.w r7, [sp], #4 8007154: 4770 bx lr 8007156: bf00 nop 8007158: 40012c00 .word 0x40012c00 800715c: 40000400 .word 0x40000400 8007160: 40000800 .word 0x40000800 8007164: 40000c00 .word 0x40000c00 8007168: 40013400 .word 0x40013400 800716c: 40015000 .word 0x40015000 8007170: 40014000 .word 0x40014000 8007174: 40014400 .word 0x40014400 8007178: 40014800 .word 0x40014800 0800717c : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 800717c: b480 push {r7} 800717e: b087 sub sp, #28 8007180: af00 add r7, sp, #0 8007182: 60f8 str r0, [r7, #12] 8007184: 60b9 str r1, [r7, #8] 8007186: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; 8007188: 68fb ldr r3, [r7, #12] 800718a: 6a1b ldr r3, [r3, #32] 800718c: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC1E; 800718e: 68fb ldr r3, [r7, #12] 8007190: 6a1b ldr r3, [r3, #32] 8007192: f023 0201 bic.w r2, r3, #1 8007196: 68fb ldr r3, [r7, #12] 8007198: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 800719a: 68fb ldr r3, [r7, #12] 800719c: 699b ldr r3, [r3, #24] 800719e: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; 80071a0: 693b ldr r3, [r7, #16] 80071a2: f023 03f0 bic.w r3, r3, #240 @ 0xf0 80071a6: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 4U); 80071a8: 687b ldr r3, [r7, #4] 80071aa: 011b lsls r3, r3, #4 80071ac: 693a ldr r2, [r7, #16] 80071ae: 4313 orrs r3, r2 80071b0: 613b str r3, [r7, #16] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 80071b2: 697b ldr r3, [r7, #20] 80071b4: f023 030a bic.w r3, r3, #10 80071b8: 617b str r3, [r7, #20] tmpccer |= TIM_ICPolarity; 80071ba: 697a ldr r2, [r7, #20] 80071bc: 68bb ldr r3, [r7, #8] 80071be: 4313 orrs r3, r2 80071c0: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 80071c2: 68fb ldr r3, [r7, #12] 80071c4: 693a ldr r2, [r7, #16] 80071c6: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 80071c8: 68fb ldr r3, [r7, #12] 80071ca: 697a ldr r2, [r7, #20] 80071cc: 621a str r2, [r3, #32] } 80071ce: bf00 nop 80071d0: 371c adds r7, #28 80071d2: 46bd mov sp, r7 80071d4: f85d 7b04 ldr.w r7, [sp], #4 80071d8: 4770 bx lr 080071da : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 80071da: b480 push {r7} 80071dc: b087 sub sp, #28 80071de: af00 add r7, sp, #0 80071e0: 60f8 str r0, [r7, #12] 80071e2: 60b9 str r1, [r7, #8] 80071e4: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ tmpccer = TIMx->CCER; 80071e6: 68fb ldr r3, [r7, #12] 80071e8: 6a1b ldr r3, [r3, #32] 80071ea: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC2E; 80071ec: 68fb ldr r3, [r7, #12] 80071ee: 6a1b ldr r3, [r3, #32] 80071f0: f023 0210 bic.w r2, r3, #16 80071f4: 68fb ldr r3, [r7, #12] 80071f6: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 80071f8: 68fb ldr r3, [r7, #12] 80071fa: 699b ldr r3, [r3, #24] 80071fc: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 80071fe: 693b ldr r3, [r7, #16] 8007200: f423 4370 bic.w r3, r3, #61440 @ 0xf000 8007204: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 12U); 8007206: 687b ldr r3, [r7, #4] 8007208: 031b lsls r3, r3, #12 800720a: 693a ldr r2, [r7, #16] 800720c: 4313 orrs r3, r2 800720e: 613b str r3, [r7, #16] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 8007210: 697b ldr r3, [r7, #20] 8007212: f023 03a0 bic.w r3, r3, #160 @ 0xa0 8007216: 617b str r3, [r7, #20] tmpccer |= (TIM_ICPolarity << 4U); 8007218: 68bb ldr r3, [r7, #8] 800721a: 011b lsls r3, r3, #4 800721c: 697a ldr r2, [r7, #20] 800721e: 4313 orrs r3, r2 8007220: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 8007222: 68fb ldr r3, [r7, #12] 8007224: 693a ldr r2, [r7, #16] 8007226: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8007228: 68fb ldr r3, [r7, #12] 800722a: 697a ldr r2, [r7, #20] 800722c: 621a str r2, [r3, #32] } 800722e: bf00 nop 8007230: 371c adds r7, #28 8007232: 46bd mov sp, r7 8007234: f85d 7b04 ldr.w r7, [sp], #4 8007238: 4770 bx lr 0800723a : * (*) Value not defined in all devices. * * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { 800723a: b480 push {r7} 800723c: b085 sub sp, #20 800723e: af00 add r7, sp, #0 8007240: 6078 str r0, [r7, #4] 8007242: 6039 str r1, [r7, #0] uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; 8007244: 687b ldr r3, [r7, #4] 8007246: 689b ldr r3, [r3, #8] 8007248: 60fb str r3, [r7, #12] /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; 800724a: 68fb ldr r3, [r7, #12] 800724c: f423 1340 bic.w r3, r3, #3145728 @ 0x300000 8007250: f023 0370 bic.w r3, r3, #112 @ 0x70 8007254: 60fb str r3, [r7, #12] /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 8007256: 683a ldr r2, [r7, #0] 8007258: 68fb ldr r3, [r7, #12] 800725a: 4313 orrs r3, r2 800725c: f043 0307 orr.w r3, r3, #7 8007260: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8007262: 687b ldr r3, [r7, #4] 8007264: 68fa ldr r2, [r7, #12] 8007266: 609a str r2, [r3, #8] } 8007268: bf00 nop 800726a: 3714 adds r7, #20 800726c: 46bd mov sp, r7 800726e: f85d 7b04 ldr.w r7, [sp], #4 8007272: 4770 bx lr 08007274 : * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { 8007274: b480 push {r7} 8007276: b087 sub sp, #28 8007278: af00 add r7, sp, #0 800727a: 60f8 str r0, [r7, #12] 800727c: 60b9 str r1, [r7, #8] 800727e: 607a str r2, [r7, #4] 8007280: 603b str r3, [r7, #0] uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; 8007282: 68fb ldr r3, [r7, #12] 8007284: 689b ldr r3, [r3, #8] 8007286: 617b str r3, [r7, #20] /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8007288: 697b ldr r3, [r7, #20] 800728a: f423 437f bic.w r3, r3, #65280 @ 0xff00 800728e: 617b str r3, [r7, #20] /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 8007290: 683b ldr r3, [r7, #0] 8007292: 021a lsls r2, r3, #8 8007294: 687b ldr r3, [r7, #4] 8007296: 431a orrs r2, r3 8007298: 68bb ldr r3, [r7, #8] 800729a: 4313 orrs r3, r2 800729c: 697a ldr r2, [r7, #20] 800729e: 4313 orrs r3, r2 80072a0: 617b str r3, [r7, #20] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 80072a2: 68fb ldr r3, [r7, #12] 80072a4: 697a ldr r2, [r7, #20] 80072a6: 609a str r2, [r3, #8] } 80072a8: bf00 nop 80072aa: 371c adds r7, #28 80072ac: 46bd mov sp, r7 80072ae: f85d 7b04 ldr.w r7, [sp], #4 80072b2: 4770 bx lr 080072b4 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 80072b4: b480 push {r7} 80072b6: b085 sub sp, #20 80072b8: af00 add r7, sp, #0 80072ba: 6078 str r0, [r7, #4] 80072bc: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 80072be: 687b ldr r3, [r7, #4] 80072c0: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 80072c4: 2b01 cmp r3, #1 80072c6: d101 bne.n 80072cc 80072c8: 2302 movs r3, #2 80072ca: e074 b.n 80073b6 80072cc: 687b ldr r3, [r7, #4] 80072ce: 2201 movs r2, #1 80072d0: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 80072d4: 687b ldr r3, [r7, #4] 80072d6: 2202 movs r2, #2 80072d8: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 80072dc: 687b ldr r3, [r7, #4] 80072de: 681b ldr r3, [r3, #0] 80072e0: 685b ldr r3, [r3, #4] 80072e2: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 80072e4: 687b ldr r3, [r7, #4] 80072e6: 681b ldr r3, [r3, #0] 80072e8: 689b ldr r3, [r3, #8] 80072ea: 60bb str r3, [r7, #8] /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) 80072ec: 687b ldr r3, [r7, #4] 80072ee: 681b ldr r3, [r3, #0] 80072f0: 4a34 ldr r2, [pc, #208] @ (80073c4 ) 80072f2: 4293 cmp r3, r2 80072f4: d009 beq.n 800730a 80072f6: 687b ldr r3, [r7, #4] 80072f8: 681b ldr r3, [r3, #0] 80072fa: 4a33 ldr r2, [pc, #204] @ (80073c8 ) 80072fc: 4293 cmp r3, r2 80072fe: d004 beq.n 800730a 8007300: 687b ldr r3, [r7, #4] 8007302: 681b ldr r3, [r3, #0] 8007304: 4a31 ldr r2, [pc, #196] @ (80073cc ) 8007306: 4293 cmp r3, r2 8007308: d108 bne.n 800731c { /* Check the parameters */ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); /* Clear the MMS2 bits */ tmpcr2 &= ~TIM_CR2_MMS2; 800730a: 68fb ldr r3, [r7, #12] 800730c: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000 8007310: 60fb str r3, [r7, #12] /* Select the TRGO2 source*/ tmpcr2 |= sMasterConfig->MasterOutputTrigger2; 8007312: 683b ldr r3, [r7, #0] 8007314: 685b ldr r3, [r3, #4] 8007316: 68fa ldr r2, [r7, #12] 8007318: 4313 orrs r3, r2 800731a: 60fb str r3, [r7, #12] } /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 800731c: 68fb ldr r3, [r7, #12] 800731e: f023 7300 bic.w r3, r3, #33554432 @ 0x2000000 8007322: f023 0370 bic.w r3, r3, #112 @ 0x70 8007326: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 8007328: 683b ldr r3, [r7, #0] 800732a: 681b ldr r3, [r3, #0] 800732c: 68fa ldr r2, [r7, #12] 800732e: 4313 orrs r3, r2 8007330: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 8007332: 687b ldr r3, [r7, #4] 8007334: 681b ldr r3, [r3, #0] 8007336: 68fa ldr r2, [r7, #12] 8007338: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800733a: 687b ldr r3, [r7, #4] 800733c: 681b ldr r3, [r3, #0] 800733e: 4a21 ldr r2, [pc, #132] @ (80073c4 ) 8007340: 4293 cmp r3, r2 8007342: d022 beq.n 800738a 8007344: 687b ldr r3, [r7, #4] 8007346: 681b ldr r3, [r3, #0] 8007348: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800734c: d01d beq.n 800738a 800734e: 687b ldr r3, [r7, #4] 8007350: 681b ldr r3, [r3, #0] 8007352: 4a1f ldr r2, [pc, #124] @ (80073d0 ) 8007354: 4293 cmp r3, r2 8007356: d018 beq.n 800738a 8007358: 687b ldr r3, [r7, #4] 800735a: 681b ldr r3, [r3, #0] 800735c: 4a1d ldr r2, [pc, #116] @ (80073d4 ) 800735e: 4293 cmp r3, r2 8007360: d013 beq.n 800738a 8007362: 687b ldr r3, [r7, #4] 8007364: 681b ldr r3, [r3, #0] 8007366: 4a1c ldr r2, [pc, #112] @ (80073d8 ) 8007368: 4293 cmp r3, r2 800736a: d00e beq.n 800738a 800736c: 687b ldr r3, [r7, #4] 800736e: 681b ldr r3, [r3, #0] 8007370: 4a15 ldr r2, [pc, #84] @ (80073c8 ) 8007372: 4293 cmp r3, r2 8007374: d009 beq.n 800738a 8007376: 687b ldr r3, [r7, #4] 8007378: 681b ldr r3, [r3, #0] 800737a: 4a18 ldr r2, [pc, #96] @ (80073dc ) 800737c: 4293 cmp r3, r2 800737e: d004 beq.n 800738a 8007380: 687b ldr r3, [r7, #4] 8007382: 681b ldr r3, [r3, #0] 8007384: 4a11 ldr r2, [pc, #68] @ (80073cc ) 8007386: 4293 cmp r3, r2 8007388: d10c bne.n 80073a4 { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 800738a: 68bb ldr r3, [r7, #8] 800738c: f023 0380 bic.w r3, r3, #128 @ 0x80 8007390: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 8007392: 683b ldr r3, [r7, #0] 8007394: 689b ldr r3, [r3, #8] 8007396: 68ba ldr r2, [r7, #8] 8007398: 4313 orrs r3, r2 800739a: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 800739c: 687b ldr r3, [r7, #4] 800739e: 681b ldr r3, [r3, #0] 80073a0: 68ba ldr r2, [r7, #8] 80073a2: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 80073a4: 687b ldr r3, [r7, #4] 80073a6: 2201 movs r2, #1 80073a8: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 80073ac: 687b ldr r3, [r7, #4] 80073ae: 2200 movs r2, #0 80073b0: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 80073b4: 2300 movs r3, #0 } 80073b6: 4618 mov r0, r3 80073b8: 3714 adds r7, #20 80073ba: 46bd mov sp, r7 80073bc: f85d 7b04 ldr.w r7, [sp], #4 80073c0: 4770 bx lr 80073c2: bf00 nop 80073c4: 40012c00 .word 0x40012c00 80073c8: 40013400 .word 0x40013400 80073cc: 40015000 .word 0x40015000 80073d0: 40000400 .word 0x40000400 80073d4: 40000800 .word 0x40000800 80073d8: 40000c00 .word 0x40000c00 80073dc: 40014000 .word 0x40014000 080073e0 : * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 80073e0: b480 push {r7} 80073e2: b083 sub sp, #12 80073e4: af00 add r7, sp, #0 80073e6: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 80073e8: bf00 nop 80073ea: 370c adds r7, #12 80073ec: 46bd mov sp, r7 80073ee: f85d 7b04 ldr.w r7, [sp], #4 80073f2: 4770 bx lr 080073f4 : * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 80073f4: b480 push {r7} 80073f6: b083 sub sp, #12 80073f8: af00 add r7, sp, #0 80073fa: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 80073fc: bf00 nop 80073fe: 370c adds r7, #12 8007400: 46bd mov sp, r7 8007402: f85d 7b04 ldr.w r7, [sp], #4 8007406: 4770 bx lr 08007408 : * @brief Break2 detection callback in non blocking mode * @param htim: TIM handle * @retval None */ __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) { 8007408: b480 push {r7} 800740a: b083 sub sp, #12 800740c: af00 add r7, sp, #0 800740e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIMEx_Break2Callback could be implemented in the user file */ } 8007410: bf00 nop 8007412: 370c adds r7, #12 8007414: 46bd mov sp, r7 8007416: f85d 7b04 ldr.w r7, [sp], #4 800741a: 4770 bx lr 0800741c : * @brief Encoder index callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim) { 800741c: b480 push {r7} 800741e: b083 sub sp, #12 8007420: af00 add r7, sp, #0 8007422: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_EncoderIndexCallback could be implemented in the user file */ } 8007424: bf00 nop 8007426: 370c adds r7, #12 8007428: 46bd mov sp, r7 800742a: f85d 7b04 ldr.w r7, [sp], #4 800742e: 4770 bx lr 08007430 : * @brief Direction change callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim) { 8007430: b480 push {r7} 8007432: b083 sub sp, #12 8007434: af00 add r7, sp, #0 8007436: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_DirectionChangeCallback could be implemented in the user file */ } 8007438: bf00 nop 800743a: 370c adds r7, #12 800743c: 46bd mov sp, r7 800743e: f85d 7b04 ldr.w r7, [sp], #4 8007442: 4770 bx lr 08007444 : * @brief Index error callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim) { 8007444: b480 push {r7} 8007446: b083 sub sp, #12 8007448: af00 add r7, sp, #0 800744a: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_IndexErrorCallback could be implemented in the user file */ } 800744c: bf00 nop 800744e: 370c adds r7, #12 8007450: 46bd mov sp, r7 8007452: f85d 7b04 ldr.w r7, [sp], #4 8007456: 4770 bx lr 08007458 : * @brief Transition error callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim) { 8007458: b480 push {r7} 800745a: b083 sub sp, #12 800745c: af00 add r7, sp, #0 800745e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_TransitionErrorCallback could be implemented in the user file */ } 8007460: bf00 nop 8007462: 370c adds r7, #12 8007464: 46bd mov sp, r7 8007466: f85d 7b04 ldr.w r7, [sp], #4 800746a: 4770 bx lr 0800746c : * parameters in the UART_InitTypeDef and initialize the associated handle. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 800746c: b580 push {r7, lr} 800746e: b082 sub sp, #8 8007470: af00 add r7, sp, #0 8007472: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8007474: 687b ldr r3, [r7, #4] 8007476: 2b00 cmp r3, #0 8007478: d101 bne.n 800747e { return HAL_ERROR; 800747a: 2301 movs r3, #1 800747c: e042 b.n 8007504 { /* Check the parameters */ assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); } if (huart->gState == HAL_UART_STATE_RESET) 800747e: 687b ldr r3, [r7, #4] 8007480: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8007484: 2b00 cmp r3, #0 8007486: d106 bne.n 8007496 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 8007488: 687b ldr r3, [r7, #4] 800748a: 2200 movs r2, #0 800748c: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8007490: 6878 ldr r0, [r7, #4] 8007492: f7fa f8a7 bl 80015e4 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 8007496: 687b ldr r3, [r7, #4] 8007498: 2224 movs r2, #36 @ 0x24 800749a: f8c3 2088 str.w r2, [r3, #136] @ 0x88 __HAL_UART_DISABLE(huart); 800749e: 687b ldr r3, [r7, #4] 80074a0: 681b ldr r3, [r3, #0] 80074a2: 681a ldr r2, [r3, #0] 80074a4: 687b ldr r3, [r7, #4] 80074a6: 681b ldr r3, [r3, #0] 80074a8: f022 0201 bic.w r2, r2, #1 80074ac: 601a str r2, [r3, #0] /* Perform advanced settings configuration */ /* For some items, configuration requires to be done prior TE and RE bits are set */ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) 80074ae: 687b ldr r3, [r7, #4] 80074b0: 6a9b ldr r3, [r3, #40] @ 0x28 80074b2: 2b00 cmp r3, #0 80074b4: d002 beq.n 80074bc { UART_AdvFeatureConfig(huart); 80074b6: 6878 ldr r0, [r7, #4] 80074b8: f000 fbb2 bl 8007c20 } /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) 80074bc: 6878 ldr r0, [r7, #4] 80074be: f000 f8b3 bl 8007628 80074c2: 4603 mov r3, r0 80074c4: 2b01 cmp r3, #1 80074c6: d101 bne.n 80074cc { return HAL_ERROR; 80074c8: 2301 movs r3, #1 80074ca: e01b b.n 8007504 } /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 80074cc: 687b ldr r3, [r7, #4] 80074ce: 681b ldr r3, [r3, #0] 80074d0: 685a ldr r2, [r3, #4] 80074d2: 687b ldr r3, [r7, #4] 80074d4: 681b ldr r3, [r3, #0] 80074d6: f422 4290 bic.w r2, r2, #18432 @ 0x4800 80074da: 605a str r2, [r3, #4] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 80074dc: 687b ldr r3, [r7, #4] 80074de: 681b ldr r3, [r3, #0] 80074e0: 689a ldr r2, [r3, #8] 80074e2: 687b ldr r3, [r7, #4] 80074e4: 681b ldr r3, [r3, #0] 80074e6: f022 022a bic.w r2, r2, #42 @ 0x2a 80074ea: 609a str r2, [r3, #8] __HAL_UART_ENABLE(huart); 80074ec: 687b ldr r3, [r7, #4] 80074ee: 681b ldr r3, [r3, #0] 80074f0: 681a ldr r2, [r3, #0] 80074f2: 687b ldr r3, [r7, #4] 80074f4: 681b ldr r3, [r3, #0] 80074f6: f042 0201 orr.w r2, r2, #1 80074fa: 601a str r2, [r3, #0] /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); 80074fc: 6878 ldr r0, [r7, #4] 80074fe: f000 fc31 bl 8007d64 8007502: 4603 mov r3, r0 } 8007504: 4618 mov r0, r3 8007506: 3708 adds r7, #8 8007508: 46bd mov sp, r7 800750a: bd80 pop {r7, pc} 0800750c : * @param Size Amount of data elements (u8 or u16) to be sent. * @param Timeout Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { 800750c: b580 push {r7, lr} 800750e: b08a sub sp, #40 @ 0x28 8007510: af02 add r7, sp, #8 8007512: 60f8 str r0, [r7, #12] 8007514: 60b9 str r1, [r7, #8] 8007516: 603b str r3, [r7, #0] 8007518: 4613 mov r3, r2 800751a: 80fb strh r3, [r7, #6] const uint8_t *pdata8bits; const uint16_t *pdata16bits; uint32_t tickstart; /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 800751c: 68fb ldr r3, [r7, #12] 800751e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8007522: 2b20 cmp r3, #32 8007524: d17b bne.n 800761e { if ((pData == NULL) || (Size == 0U)) 8007526: 68bb ldr r3, [r7, #8] 8007528: 2b00 cmp r3, #0 800752a: d002 beq.n 8007532 800752c: 88fb ldrh r3, [r7, #6] 800752e: 2b00 cmp r3, #0 8007530: d101 bne.n 8007536 { return HAL_ERROR; 8007532: 2301 movs r3, #1 8007534: e074 b.n 8007620 } huart->ErrorCode = HAL_UART_ERROR_NONE; 8007536: 68fb ldr r3, [r7, #12] 8007538: 2200 movs r2, #0 800753a: f8c3 2090 str.w r2, [r3, #144] @ 0x90 huart->gState = HAL_UART_STATE_BUSY_TX; 800753e: 68fb ldr r3, [r7, #12] 8007540: 2221 movs r2, #33 @ 0x21 8007542: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 8007546: f7fa f9b1 bl 80018ac 800754a: 6178 str r0, [r7, #20] huart->TxXferSize = Size; 800754c: 68fb ldr r3, [r7, #12] 800754e: 88fa ldrh r2, [r7, #6] 8007550: f8a3 2054 strh.w r2, [r3, #84] @ 0x54 huart->TxXferCount = Size; 8007554: 68fb ldr r3, [r7, #12] 8007556: 88fa ldrh r2, [r7, #6] 8007558: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 800755c: 68fb ldr r3, [r7, #12] 800755e: 689b ldr r3, [r3, #8] 8007560: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8007564: d108 bne.n 8007578 8007566: 68fb ldr r3, [r7, #12] 8007568: 691b ldr r3, [r3, #16] 800756a: 2b00 cmp r3, #0 800756c: d104 bne.n 8007578 { pdata8bits = NULL; 800756e: 2300 movs r3, #0 8007570: 61fb str r3, [r7, #28] pdata16bits = (const uint16_t *) pData; 8007572: 68bb ldr r3, [r7, #8] 8007574: 61bb str r3, [r7, #24] 8007576: e003 b.n 8007580 } else { pdata8bits = pData; 8007578: 68bb ldr r3, [r7, #8] 800757a: 61fb str r3, [r7, #28] pdata16bits = NULL; 800757c: 2300 movs r3, #0 800757e: 61bb str r3, [r7, #24] } while (huart->TxXferCount > 0U) 8007580: e030 b.n 80075e4 { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) 8007582: 683b ldr r3, [r7, #0] 8007584: 9300 str r3, [sp, #0] 8007586: 697b ldr r3, [r7, #20] 8007588: 2200 movs r2, #0 800758a: 2180 movs r1, #128 @ 0x80 800758c: 68f8 ldr r0, [r7, #12] 800758e: f000 fc93 bl 8007eb8 8007592: 4603 mov r3, r0 8007594: 2b00 cmp r3, #0 8007596: d005 beq.n 80075a4 { huart->gState = HAL_UART_STATE_READY; 8007598: 68fb ldr r3, [r7, #12] 800759a: 2220 movs r2, #32 800759c: f8c3 2088 str.w r2, [r3, #136] @ 0x88 return HAL_TIMEOUT; 80075a0: 2303 movs r3, #3 80075a2: e03d b.n 8007620 } if (pdata8bits == NULL) 80075a4: 69fb ldr r3, [r7, #28] 80075a6: 2b00 cmp r3, #0 80075a8: d10b bne.n 80075c2 { huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU); 80075aa: 69bb ldr r3, [r7, #24] 80075ac: 881b ldrh r3, [r3, #0] 80075ae: 461a mov r2, r3 80075b0: 68fb ldr r3, [r7, #12] 80075b2: 681b ldr r3, [r3, #0] 80075b4: f3c2 0208 ubfx r2, r2, #0, #9 80075b8: 629a str r2, [r3, #40] @ 0x28 pdata16bits++; 80075ba: 69bb ldr r3, [r7, #24] 80075bc: 3302 adds r3, #2 80075be: 61bb str r3, [r7, #24] 80075c0: e007 b.n 80075d2 } else { huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); 80075c2: 69fb ldr r3, [r7, #28] 80075c4: 781a ldrb r2, [r3, #0] 80075c6: 68fb ldr r3, [r7, #12] 80075c8: 681b ldr r3, [r3, #0] 80075ca: 629a str r2, [r3, #40] @ 0x28 pdata8bits++; 80075cc: 69fb ldr r3, [r7, #28] 80075ce: 3301 adds r3, #1 80075d0: 61fb str r3, [r7, #28] } huart->TxXferCount--; 80075d2: 68fb ldr r3, [r7, #12] 80075d4: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 80075d8: b29b uxth r3, r3 80075da: 3b01 subs r3, #1 80075dc: b29a uxth r2, r3 80075de: 68fb ldr r3, [r7, #12] 80075e0: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 while (huart->TxXferCount > 0U) 80075e4: 68fb ldr r3, [r7, #12] 80075e6: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 80075ea: b29b uxth r3, r3 80075ec: 2b00 cmp r3, #0 80075ee: d1c8 bne.n 8007582 } if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) 80075f0: 683b ldr r3, [r7, #0] 80075f2: 9300 str r3, [sp, #0] 80075f4: 697b ldr r3, [r7, #20] 80075f6: 2200 movs r2, #0 80075f8: 2140 movs r1, #64 @ 0x40 80075fa: 68f8 ldr r0, [r7, #12] 80075fc: f000 fc5c bl 8007eb8 8007600: 4603 mov r3, r0 8007602: 2b00 cmp r3, #0 8007604: d005 beq.n 8007612 { huart->gState = HAL_UART_STATE_READY; 8007606: 68fb ldr r3, [r7, #12] 8007608: 2220 movs r2, #32 800760a: f8c3 2088 str.w r2, [r3, #136] @ 0x88 return HAL_TIMEOUT; 800760e: 2303 movs r3, #3 8007610: e006 b.n 8007620 } /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8007612: 68fb ldr r3, [r7, #12] 8007614: 2220 movs r2, #32 8007616: f8c3 2088 str.w r2, [r3, #136] @ 0x88 return HAL_OK; 800761a: 2300 movs r3, #0 800761c: e000 b.n 8007620 } else { return HAL_BUSY; 800761e: 2302 movs r3, #2 } } 8007620: 4618 mov r0, r3 8007622: 3720 adds r7, #32 8007624: 46bd mov sp, r7 8007626: bd80 pop {r7, pc} 08007628 : * @brief Configure the UART peripheral. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { 8007628: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 800762c: b08c sub sp, #48 @ 0x30 800762e: af00 add r7, sp, #0 8007630: 6178 str r0, [r7, #20] uint32_t tmpreg; uint16_t brrtemp; UART_ClockSourceTypeDef clocksource; uint32_t usartdiv; HAL_StatusTypeDef ret = HAL_OK; 8007632: 2300 movs r3, #0 8007634: f887 302a strb.w r3, [r7, #42] @ 0x2a * the UART Word Length, Parity, Mode and oversampling: * set the M bits according to huart->Init.WordLength value * set PCE and PS bits according to huart->Init.Parity value * set TE and RE bits according to huart->Init.Mode value * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; 8007638: 697b ldr r3, [r7, #20] 800763a: 689a ldr r2, [r3, #8] 800763c: 697b ldr r3, [r7, #20] 800763e: 691b ldr r3, [r3, #16] 8007640: 431a orrs r2, r3 8007642: 697b ldr r3, [r7, #20] 8007644: 695b ldr r3, [r3, #20] 8007646: 431a orrs r2, r3 8007648: 697b ldr r3, [r7, #20] 800764a: 69db ldr r3, [r3, #28] 800764c: 4313 orrs r3, r2 800764e: 62fb str r3, [r7, #44] @ 0x2c MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); 8007650: 697b ldr r3, [r7, #20] 8007652: 681b ldr r3, [r3, #0] 8007654: 681a ldr r2, [r3, #0] 8007656: 4baa ldr r3, [pc, #680] @ (8007900 ) 8007658: 4013 ands r3, r2 800765a: 697a ldr r2, [r7, #20] 800765c: 6812 ldr r2, [r2, #0] 800765e: 6af9 ldr r1, [r7, #44] @ 0x2c 8007660: 430b orrs r3, r1 8007662: 6013 str r3, [r2, #0] /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8007664: 697b ldr r3, [r7, #20] 8007666: 681b ldr r3, [r3, #0] 8007668: 685b ldr r3, [r3, #4] 800766a: f423 5140 bic.w r1, r3, #12288 @ 0x3000 800766e: 697b ldr r3, [r7, #20] 8007670: 68da ldr r2, [r3, #12] 8007672: 697b ldr r3, [r7, #20] 8007674: 681b ldr r3, [r3, #0] 8007676: 430a orrs r2, r1 8007678: 605a str r2, [r3, #4] /* Configure * - UART HardWare Flow Control: set CTSE and RTSE bits according * to huart->Init.HwFlowCtl value * - one-bit sampling method versus three samples' majority rule according * to huart->Init.OneBitSampling (not applicable to LPUART) */ tmpreg = (uint32_t)huart->Init.HwFlowCtl; 800767a: 697b ldr r3, [r7, #20] 800767c: 699b ldr r3, [r3, #24] 800767e: 62fb str r3, [r7, #44] @ 0x2c if (!(UART_INSTANCE_LOWPOWER(huart))) 8007680: 697b ldr r3, [r7, #20] 8007682: 681b ldr r3, [r3, #0] 8007684: 4a9f ldr r2, [pc, #636] @ (8007904 ) 8007686: 4293 cmp r3, r2 8007688: d004 beq.n 8007694 { tmpreg |= huart->Init.OneBitSampling; 800768a: 697b ldr r3, [r7, #20] 800768c: 6a1b ldr r3, [r3, #32] 800768e: 6afa ldr r2, [r7, #44] @ 0x2c 8007690: 4313 orrs r3, r2 8007692: 62fb str r3, [r7, #44] @ 0x2c } MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); 8007694: 697b ldr r3, [r7, #20] 8007696: 681b ldr r3, [r3, #0] 8007698: 689b ldr r3, [r3, #8] 800769a: f023 436e bic.w r3, r3, #3992977408 @ 0xee000000 800769e: f423 6330 bic.w r3, r3, #2816 @ 0xb00 80076a2: 697a ldr r2, [r7, #20] 80076a4: 6812 ldr r2, [r2, #0] 80076a6: 6af9 ldr r1, [r7, #44] @ 0x2c 80076a8: 430b orrs r3, r1 80076aa: 6093 str r3, [r2, #8] /*-------------------------- USART PRESC Configuration -----------------------*/ /* Configure * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); 80076ac: 697b ldr r3, [r7, #20] 80076ae: 681b ldr r3, [r3, #0] 80076b0: 6adb ldr r3, [r3, #44] @ 0x2c 80076b2: f023 010f bic.w r1, r3, #15 80076b6: 697b ldr r3, [r7, #20] 80076b8: 6a5a ldr r2, [r3, #36] @ 0x24 80076ba: 697b ldr r3, [r7, #20] 80076bc: 681b ldr r3, [r3, #0] 80076be: 430a orrs r2, r1 80076c0: 62da str r2, [r3, #44] @ 0x2c /*-------------------------- USART BRR Configuration -----------------------*/ UART_GETCLOCKSOURCE(huart, clocksource); 80076c2: 697b ldr r3, [r7, #20] 80076c4: 681b ldr r3, [r3, #0] 80076c6: 4a90 ldr r2, [pc, #576] @ (8007908 ) 80076c8: 4293 cmp r3, r2 80076ca: d125 bne.n 8007718 80076cc: 4b8f ldr r3, [pc, #572] @ (800790c ) 80076ce: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80076d2: f003 0303 and.w r3, r3, #3 80076d6: 2b03 cmp r3, #3 80076d8: d81a bhi.n 8007710 80076da: a201 add r2, pc, #4 @ (adr r2, 80076e0 ) 80076dc: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80076e0: 080076f1 .word 0x080076f1 80076e4: 08007701 .word 0x08007701 80076e8: 080076f9 .word 0x080076f9 80076ec: 08007709 .word 0x08007709 80076f0: 2301 movs r3, #1 80076f2: f887 302b strb.w r3, [r7, #43] @ 0x2b 80076f6: e116 b.n 8007926 80076f8: 2302 movs r3, #2 80076fa: f887 302b strb.w r3, [r7, #43] @ 0x2b 80076fe: e112 b.n 8007926 8007700: 2304 movs r3, #4 8007702: f887 302b strb.w r3, [r7, #43] @ 0x2b 8007706: e10e b.n 8007926 8007708: 2308 movs r3, #8 800770a: f887 302b strb.w r3, [r7, #43] @ 0x2b 800770e: e10a b.n 8007926 8007710: 2310 movs r3, #16 8007712: f887 302b strb.w r3, [r7, #43] @ 0x2b 8007716: e106 b.n 8007926 8007718: 697b ldr r3, [r7, #20] 800771a: 681b ldr r3, [r3, #0] 800771c: 4a7c ldr r2, [pc, #496] @ (8007910 ) 800771e: 4293 cmp r3, r2 8007720: d138 bne.n 8007794 8007722: 4b7a ldr r3, [pc, #488] @ (800790c ) 8007724: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8007728: f003 030c and.w r3, r3, #12 800772c: 2b0c cmp r3, #12 800772e: d82d bhi.n 800778c 8007730: a201 add r2, pc, #4 @ (adr r2, 8007738 ) 8007732: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8007736: bf00 nop 8007738: 0800776d .word 0x0800776d 800773c: 0800778d .word 0x0800778d 8007740: 0800778d .word 0x0800778d 8007744: 0800778d .word 0x0800778d 8007748: 0800777d .word 0x0800777d 800774c: 0800778d .word 0x0800778d 8007750: 0800778d .word 0x0800778d 8007754: 0800778d .word 0x0800778d 8007758: 08007775 .word 0x08007775 800775c: 0800778d .word 0x0800778d 8007760: 0800778d .word 0x0800778d 8007764: 0800778d .word 0x0800778d 8007768: 08007785 .word 0x08007785 800776c: 2300 movs r3, #0 800776e: f887 302b strb.w r3, [r7, #43] @ 0x2b 8007772: e0d8 b.n 8007926 8007774: 2302 movs r3, #2 8007776: f887 302b strb.w r3, [r7, #43] @ 0x2b 800777a: e0d4 b.n 8007926 800777c: 2304 movs r3, #4 800777e: f887 302b strb.w r3, [r7, #43] @ 0x2b 8007782: e0d0 b.n 8007926 8007784: 2308 movs r3, #8 8007786: f887 302b strb.w r3, [r7, #43] @ 0x2b 800778a: e0cc b.n 8007926 800778c: 2310 movs r3, #16 800778e: f887 302b strb.w r3, [r7, #43] @ 0x2b 8007792: e0c8 b.n 8007926 8007794: 697b ldr r3, [r7, #20] 8007796: 681b ldr r3, [r3, #0] 8007798: 4a5e ldr r2, [pc, #376] @ (8007914 ) 800779a: 4293 cmp r3, r2 800779c: d125 bne.n 80077ea 800779e: 4b5b ldr r3, [pc, #364] @ (800790c ) 80077a0: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80077a4: f003 0330 and.w r3, r3, #48 @ 0x30 80077a8: 2b30 cmp r3, #48 @ 0x30 80077aa: d016 beq.n 80077da 80077ac: 2b30 cmp r3, #48 @ 0x30 80077ae: d818 bhi.n 80077e2 80077b0: 2b20 cmp r3, #32 80077b2: d00a beq.n 80077ca 80077b4: 2b20 cmp r3, #32 80077b6: d814 bhi.n 80077e2 80077b8: 2b00 cmp r3, #0 80077ba: d002 beq.n 80077c2 80077bc: 2b10 cmp r3, #16 80077be: d008 beq.n 80077d2 80077c0: e00f b.n 80077e2 80077c2: 2300 movs r3, #0 80077c4: f887 302b strb.w r3, [r7, #43] @ 0x2b 80077c8: e0ad b.n 8007926 80077ca: 2302 movs r3, #2 80077cc: f887 302b strb.w r3, [r7, #43] @ 0x2b 80077d0: e0a9 b.n 8007926 80077d2: 2304 movs r3, #4 80077d4: f887 302b strb.w r3, [r7, #43] @ 0x2b 80077d8: e0a5 b.n 8007926 80077da: 2308 movs r3, #8 80077dc: f887 302b strb.w r3, [r7, #43] @ 0x2b 80077e0: e0a1 b.n 8007926 80077e2: 2310 movs r3, #16 80077e4: f887 302b strb.w r3, [r7, #43] @ 0x2b 80077e8: e09d b.n 8007926 80077ea: 697b ldr r3, [r7, #20] 80077ec: 681b ldr r3, [r3, #0] 80077ee: 4a4a ldr r2, [pc, #296] @ (8007918 ) 80077f0: 4293 cmp r3, r2 80077f2: d125 bne.n 8007840 80077f4: 4b45 ldr r3, [pc, #276] @ (800790c ) 80077f6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80077fa: f003 03c0 and.w r3, r3, #192 @ 0xc0 80077fe: 2bc0 cmp r3, #192 @ 0xc0 8007800: d016 beq.n 8007830 8007802: 2bc0 cmp r3, #192 @ 0xc0 8007804: d818 bhi.n 8007838 8007806: 2b80 cmp r3, #128 @ 0x80 8007808: d00a beq.n 8007820 800780a: 2b80 cmp r3, #128 @ 0x80 800780c: d814 bhi.n 8007838 800780e: 2b00 cmp r3, #0 8007810: d002 beq.n 8007818 8007812: 2b40 cmp r3, #64 @ 0x40 8007814: d008 beq.n 8007828 8007816: e00f b.n 8007838 8007818: 2300 movs r3, #0 800781a: f887 302b strb.w r3, [r7, #43] @ 0x2b 800781e: e082 b.n 8007926 8007820: 2302 movs r3, #2 8007822: f887 302b strb.w r3, [r7, #43] @ 0x2b 8007826: e07e b.n 8007926 8007828: 2304 movs r3, #4 800782a: f887 302b strb.w r3, [r7, #43] @ 0x2b 800782e: e07a b.n 8007926 8007830: 2308 movs r3, #8 8007832: f887 302b strb.w r3, [r7, #43] @ 0x2b 8007836: e076 b.n 8007926 8007838: 2310 movs r3, #16 800783a: f887 302b strb.w r3, [r7, #43] @ 0x2b 800783e: e072 b.n 8007926 8007840: 697b ldr r3, [r7, #20] 8007842: 681b ldr r3, [r3, #0] 8007844: 4a35 ldr r2, [pc, #212] @ (800791c ) 8007846: 4293 cmp r3, r2 8007848: d12a bne.n 80078a0 800784a: 4b30 ldr r3, [pc, #192] @ (800790c ) 800784c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8007850: f403 7340 and.w r3, r3, #768 @ 0x300 8007854: f5b3 7f40 cmp.w r3, #768 @ 0x300 8007858: d01a beq.n 8007890 800785a: f5b3 7f40 cmp.w r3, #768 @ 0x300 800785e: d81b bhi.n 8007898 8007860: f5b3 7f00 cmp.w r3, #512 @ 0x200 8007864: d00c beq.n 8007880 8007866: f5b3 7f00 cmp.w r3, #512 @ 0x200 800786a: d815 bhi.n 8007898 800786c: 2b00 cmp r3, #0 800786e: d003 beq.n 8007878 8007870: f5b3 7f80 cmp.w r3, #256 @ 0x100 8007874: d008 beq.n 8007888 8007876: e00f b.n 8007898 8007878: 2300 movs r3, #0 800787a: f887 302b strb.w r3, [r7, #43] @ 0x2b 800787e: e052 b.n 8007926 8007880: 2302 movs r3, #2 8007882: f887 302b strb.w r3, [r7, #43] @ 0x2b 8007886: e04e b.n 8007926 8007888: 2304 movs r3, #4 800788a: f887 302b strb.w r3, [r7, #43] @ 0x2b 800788e: e04a b.n 8007926 8007890: 2308 movs r3, #8 8007892: f887 302b strb.w r3, [r7, #43] @ 0x2b 8007896: e046 b.n 8007926 8007898: 2310 movs r3, #16 800789a: f887 302b strb.w r3, [r7, #43] @ 0x2b 800789e: e042 b.n 8007926 80078a0: 697b ldr r3, [r7, #20] 80078a2: 681b ldr r3, [r3, #0] 80078a4: 4a17 ldr r2, [pc, #92] @ (8007904 ) 80078a6: 4293 cmp r3, r2 80078a8: d13a bne.n 8007920 80078aa: 4b18 ldr r3, [pc, #96] @ (800790c ) 80078ac: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80078b0: f403 6340 and.w r3, r3, #3072 @ 0xc00 80078b4: f5b3 6f40 cmp.w r3, #3072 @ 0xc00 80078b8: d01a beq.n 80078f0 80078ba: f5b3 6f40 cmp.w r3, #3072 @ 0xc00 80078be: d81b bhi.n 80078f8 80078c0: f5b3 6f00 cmp.w r3, #2048 @ 0x800 80078c4: d00c beq.n 80078e0 80078c6: f5b3 6f00 cmp.w r3, #2048 @ 0x800 80078ca: d815 bhi.n 80078f8 80078cc: 2b00 cmp r3, #0 80078ce: d003 beq.n 80078d8 80078d0: f5b3 6f80 cmp.w r3, #1024 @ 0x400 80078d4: d008 beq.n 80078e8 80078d6: e00f b.n 80078f8 80078d8: 2300 movs r3, #0 80078da: f887 302b strb.w r3, [r7, #43] @ 0x2b 80078de: e022 b.n 8007926 80078e0: 2302 movs r3, #2 80078e2: f887 302b strb.w r3, [r7, #43] @ 0x2b 80078e6: e01e b.n 8007926 80078e8: 2304 movs r3, #4 80078ea: f887 302b strb.w r3, [r7, #43] @ 0x2b 80078ee: e01a b.n 8007926 80078f0: 2308 movs r3, #8 80078f2: f887 302b strb.w r3, [r7, #43] @ 0x2b 80078f6: e016 b.n 8007926 80078f8: 2310 movs r3, #16 80078fa: f887 302b strb.w r3, [r7, #43] @ 0x2b 80078fe: e012 b.n 8007926 8007900: cfff69f3 .word 0xcfff69f3 8007904: 40008000 .word 0x40008000 8007908: 40013800 .word 0x40013800 800790c: 40021000 .word 0x40021000 8007910: 40004400 .word 0x40004400 8007914: 40004800 .word 0x40004800 8007918: 40004c00 .word 0x40004c00 800791c: 40005000 .word 0x40005000 8007920: 2310 movs r3, #16 8007922: f887 302b strb.w r3, [r7, #43] @ 0x2b /* Check LPUART instance */ if (UART_INSTANCE_LOWPOWER(huart)) 8007926: 697b ldr r3, [r7, #20] 8007928: 681b ldr r3, [r3, #0] 800792a: 4aae ldr r2, [pc, #696] @ (8007be4 ) 800792c: 4293 cmp r3, r2 800792e: f040 8097 bne.w 8007a60 { /* Retrieve frequency clock */ switch (clocksource) 8007932: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 8007936: 2b08 cmp r3, #8 8007938: d823 bhi.n 8007982 800793a: a201 add r2, pc, #4 @ (adr r2, 8007940 ) 800793c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8007940: 08007965 .word 0x08007965 8007944: 08007983 .word 0x08007983 8007948: 0800796d .word 0x0800796d 800794c: 08007983 .word 0x08007983 8007950: 08007973 .word 0x08007973 8007954: 08007983 .word 0x08007983 8007958: 08007983 .word 0x08007983 800795c: 08007983 .word 0x08007983 8007960: 0800797b .word 0x0800797b { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 8007964: f7fe fd38 bl 80063d8 8007968: 6278 str r0, [r7, #36] @ 0x24 break; 800796a: e010 b.n 800798e case UART_CLOCKSOURCE_HSI: pclk = (uint32_t) HSI_VALUE; 800796c: 4b9e ldr r3, [pc, #632] @ (8007be8 ) 800796e: 627b str r3, [r7, #36] @ 0x24 break; 8007970: e00d b.n 800798e case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); 8007972: f7fe fcc3 bl 80062fc 8007976: 6278 str r0, [r7, #36] @ 0x24 break; 8007978: e009 b.n 800798e case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 800797a: f44f 4300 mov.w r3, #32768 @ 0x8000 800797e: 627b str r3, [r7, #36] @ 0x24 break; 8007980: e005 b.n 800798e default: pclk = 0U; 8007982: 2300 movs r3, #0 8007984: 627b str r3, [r7, #36] @ 0x24 ret = HAL_ERROR; 8007986: 2301 movs r3, #1 8007988: f887 302a strb.w r3, [r7, #42] @ 0x2a break; 800798c: bf00 nop } /* If proper clock source reported */ if (pclk != 0U) 800798e: 6a7b ldr r3, [r7, #36] @ 0x24 8007990: 2b00 cmp r3, #0 8007992: f000 8130 beq.w 8007bf6 { /* Compute clock after Prescaler */ lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]); 8007996: 697b ldr r3, [r7, #20] 8007998: 6a5b ldr r3, [r3, #36] @ 0x24 800799a: 4a94 ldr r2, [pc, #592] @ (8007bec ) 800799c: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 80079a0: 461a mov r2, r3 80079a2: 6a7b ldr r3, [r7, #36] @ 0x24 80079a4: fbb3 f3f2 udiv r3, r3, r2 80079a8: 61bb str r3, [r7, #24] /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || 80079aa: 697b ldr r3, [r7, #20] 80079ac: 685a ldr r2, [r3, #4] 80079ae: 4613 mov r3, r2 80079b0: 005b lsls r3, r3, #1 80079b2: 4413 add r3, r2 80079b4: 69ba ldr r2, [r7, #24] 80079b6: 429a cmp r2, r3 80079b8: d305 bcc.n 80079c6 (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) 80079ba: 697b ldr r3, [r7, #20] 80079bc: 685b ldr r3, [r3, #4] 80079be: 031b lsls r3, r3, #12 if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || 80079c0: 69ba ldr r2, [r7, #24] 80079c2: 429a cmp r2, r3 80079c4: d903 bls.n 80079ce { ret = HAL_ERROR; 80079c6: 2301 movs r3, #1 80079c8: f887 302a strb.w r3, [r7, #42] @ 0x2a 80079cc: e113 b.n 8007bf6 } else { /* Check computed UsartDiv value is in allocated range (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */ usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 80079ce: 6a7b ldr r3, [r7, #36] @ 0x24 80079d0: 2200 movs r2, #0 80079d2: 60bb str r3, [r7, #8] 80079d4: 60fa str r2, [r7, #12] 80079d6: 697b ldr r3, [r7, #20] 80079d8: 6a5b ldr r3, [r3, #36] @ 0x24 80079da: 4a84 ldr r2, [pc, #528] @ (8007bec ) 80079dc: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 80079e0: b29b uxth r3, r3 80079e2: 2200 movs r2, #0 80079e4: 603b str r3, [r7, #0] 80079e6: 607a str r2, [r7, #4] 80079e8: e9d7 2300 ldrd r2, r3, [r7] 80079ec: e9d7 0102 ldrd r0, r1, [r7, #8] 80079f0: f7f8 fc1a bl 8000228 <__aeabi_uldivmod> 80079f4: 4602 mov r2, r0 80079f6: 460b mov r3, r1 80079f8: 4610 mov r0, r2 80079fa: 4619 mov r1, r3 80079fc: f04f 0200 mov.w r2, #0 8007a00: f04f 0300 mov.w r3, #0 8007a04: 020b lsls r3, r1, #8 8007a06: ea43 6310 orr.w r3, r3, r0, lsr #24 8007a0a: 0202 lsls r2, r0, #8 8007a0c: 6979 ldr r1, [r7, #20] 8007a0e: 6849 ldr r1, [r1, #4] 8007a10: 0849 lsrs r1, r1, #1 8007a12: 2000 movs r0, #0 8007a14: 460c mov r4, r1 8007a16: 4605 mov r5, r0 8007a18: eb12 0804 adds.w r8, r2, r4 8007a1c: eb43 0905 adc.w r9, r3, r5 8007a20: 697b ldr r3, [r7, #20] 8007a22: 685b ldr r3, [r3, #4] 8007a24: 2200 movs r2, #0 8007a26: 469a mov sl, r3 8007a28: 4693 mov fp, r2 8007a2a: 4652 mov r2, sl 8007a2c: 465b mov r3, fp 8007a2e: 4640 mov r0, r8 8007a30: 4649 mov r1, r9 8007a32: f7f8 fbf9 bl 8000228 <__aeabi_uldivmod> 8007a36: 4602 mov r2, r0 8007a38: 460b mov r3, r1 8007a3a: 4613 mov r3, r2 8007a3c: 623b str r3, [r7, #32] if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) 8007a3e: 6a3b ldr r3, [r7, #32] 8007a40: f5b3 7f40 cmp.w r3, #768 @ 0x300 8007a44: d308 bcc.n 8007a58 8007a46: 6a3b ldr r3, [r7, #32] 8007a48: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8007a4c: d204 bcs.n 8007a58 { huart->Instance->BRR = usartdiv; 8007a4e: 697b ldr r3, [r7, #20] 8007a50: 681b ldr r3, [r3, #0] 8007a52: 6a3a ldr r2, [r7, #32] 8007a54: 60da str r2, [r3, #12] 8007a56: e0ce b.n 8007bf6 } else { ret = HAL_ERROR; 8007a58: 2301 movs r3, #1 8007a5a: f887 302a strb.w r3, [r7, #42] @ 0x2a 8007a5e: e0ca b.n 8007bf6 } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ } /* if (pclk != 0) */ } /* Check UART Over Sampling to set Baud Rate Register */ else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 8007a60: 697b ldr r3, [r7, #20] 8007a62: 69db ldr r3, [r3, #28] 8007a64: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 8007a68: d166 bne.n 8007b38 { switch (clocksource) 8007a6a: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 8007a6e: 2b08 cmp r3, #8 8007a70: d827 bhi.n 8007ac2 8007a72: a201 add r2, pc, #4 @ (adr r2, 8007a78 ) 8007a74: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8007a78: 08007a9d .word 0x08007a9d 8007a7c: 08007aa5 .word 0x08007aa5 8007a80: 08007aad .word 0x08007aad 8007a84: 08007ac3 .word 0x08007ac3 8007a88: 08007ab3 .word 0x08007ab3 8007a8c: 08007ac3 .word 0x08007ac3 8007a90: 08007ac3 .word 0x08007ac3 8007a94: 08007ac3 .word 0x08007ac3 8007a98: 08007abb .word 0x08007abb { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 8007a9c: f7fe fc9c bl 80063d8 8007aa0: 6278 str r0, [r7, #36] @ 0x24 break; 8007aa2: e014 b.n 8007ace case UART_CLOCKSOURCE_PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); 8007aa4: f7fe fcae bl 8006404 8007aa8: 6278 str r0, [r7, #36] @ 0x24 break; 8007aaa: e010 b.n 8007ace case UART_CLOCKSOURCE_HSI: pclk = (uint32_t) HSI_VALUE; 8007aac: 4b4e ldr r3, [pc, #312] @ (8007be8 ) 8007aae: 627b str r3, [r7, #36] @ 0x24 break; 8007ab0: e00d b.n 8007ace case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); 8007ab2: f7fe fc23 bl 80062fc 8007ab6: 6278 str r0, [r7, #36] @ 0x24 break; 8007ab8: e009 b.n 8007ace case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 8007aba: f44f 4300 mov.w r3, #32768 @ 0x8000 8007abe: 627b str r3, [r7, #36] @ 0x24 break; 8007ac0: e005 b.n 8007ace default: pclk = 0U; 8007ac2: 2300 movs r3, #0 8007ac4: 627b str r3, [r7, #36] @ 0x24 ret = HAL_ERROR; 8007ac6: 2301 movs r3, #1 8007ac8: f887 302a strb.w r3, [r7, #42] @ 0x2a break; 8007acc: bf00 nop } /* USARTDIV must be greater than or equal to 0d16 */ if (pclk != 0U) 8007ace: 6a7b ldr r3, [r7, #36] @ 0x24 8007ad0: 2b00 cmp r3, #0 8007ad2: f000 8090 beq.w 8007bf6 { usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 8007ad6: 697b ldr r3, [r7, #20] 8007ad8: 6a5b ldr r3, [r3, #36] @ 0x24 8007ada: 4a44 ldr r2, [pc, #272] @ (8007bec ) 8007adc: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8007ae0: 461a mov r2, r3 8007ae2: 6a7b ldr r3, [r7, #36] @ 0x24 8007ae4: fbb3 f3f2 udiv r3, r3, r2 8007ae8: 005a lsls r2, r3, #1 8007aea: 697b ldr r3, [r7, #20] 8007aec: 685b ldr r3, [r3, #4] 8007aee: 085b lsrs r3, r3, #1 8007af0: 441a add r2, r3 8007af2: 697b ldr r3, [r7, #20] 8007af4: 685b ldr r3, [r3, #4] 8007af6: fbb2 f3f3 udiv r3, r2, r3 8007afa: 623b str r3, [r7, #32] if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 8007afc: 6a3b ldr r3, [r7, #32] 8007afe: 2b0f cmp r3, #15 8007b00: d916 bls.n 8007b30 8007b02: 6a3b ldr r3, [r7, #32] 8007b04: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8007b08: d212 bcs.n 8007b30 { brrtemp = (uint16_t)(usartdiv & 0xFFF0U); 8007b0a: 6a3b ldr r3, [r7, #32] 8007b0c: b29b uxth r3, r3 8007b0e: f023 030f bic.w r3, r3, #15 8007b12: 83fb strh r3, [r7, #30] brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); 8007b14: 6a3b ldr r3, [r7, #32] 8007b16: 085b lsrs r3, r3, #1 8007b18: b29b uxth r3, r3 8007b1a: f003 0307 and.w r3, r3, #7 8007b1e: b29a uxth r2, r3 8007b20: 8bfb ldrh r3, [r7, #30] 8007b22: 4313 orrs r3, r2 8007b24: 83fb strh r3, [r7, #30] huart->Instance->BRR = brrtemp; 8007b26: 697b ldr r3, [r7, #20] 8007b28: 681b ldr r3, [r3, #0] 8007b2a: 8bfa ldrh r2, [r7, #30] 8007b2c: 60da str r2, [r3, #12] 8007b2e: e062 b.n 8007bf6 } else { ret = HAL_ERROR; 8007b30: 2301 movs r3, #1 8007b32: f887 302a strb.w r3, [r7, #42] @ 0x2a 8007b36: e05e b.n 8007bf6 } } } else { switch (clocksource) 8007b38: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 8007b3c: 2b08 cmp r3, #8 8007b3e: d828 bhi.n 8007b92 8007b40: a201 add r2, pc, #4 @ (adr r2, 8007b48 ) 8007b42: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8007b46: bf00 nop 8007b48: 08007b6d .word 0x08007b6d 8007b4c: 08007b75 .word 0x08007b75 8007b50: 08007b7d .word 0x08007b7d 8007b54: 08007b93 .word 0x08007b93 8007b58: 08007b83 .word 0x08007b83 8007b5c: 08007b93 .word 0x08007b93 8007b60: 08007b93 .word 0x08007b93 8007b64: 08007b93 .word 0x08007b93 8007b68: 08007b8b .word 0x08007b8b { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 8007b6c: f7fe fc34 bl 80063d8 8007b70: 6278 str r0, [r7, #36] @ 0x24 break; 8007b72: e014 b.n 8007b9e case UART_CLOCKSOURCE_PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); 8007b74: f7fe fc46 bl 8006404 8007b78: 6278 str r0, [r7, #36] @ 0x24 break; 8007b7a: e010 b.n 8007b9e case UART_CLOCKSOURCE_HSI: pclk = (uint32_t) HSI_VALUE; 8007b7c: 4b1a ldr r3, [pc, #104] @ (8007be8 ) 8007b7e: 627b str r3, [r7, #36] @ 0x24 break; 8007b80: e00d b.n 8007b9e case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); 8007b82: f7fe fbbb bl 80062fc 8007b86: 6278 str r0, [r7, #36] @ 0x24 break; 8007b88: e009 b.n 8007b9e case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 8007b8a: f44f 4300 mov.w r3, #32768 @ 0x8000 8007b8e: 627b str r3, [r7, #36] @ 0x24 break; 8007b90: e005 b.n 8007b9e default: pclk = 0U; 8007b92: 2300 movs r3, #0 8007b94: 627b str r3, [r7, #36] @ 0x24 ret = HAL_ERROR; 8007b96: 2301 movs r3, #1 8007b98: f887 302a strb.w r3, [r7, #42] @ 0x2a break; 8007b9c: bf00 nop } if (pclk != 0U) 8007b9e: 6a7b ldr r3, [r7, #36] @ 0x24 8007ba0: 2b00 cmp r3, #0 8007ba2: d028 beq.n 8007bf6 { /* USARTDIV must be greater than or equal to 0d16 */ usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 8007ba4: 697b ldr r3, [r7, #20] 8007ba6: 6a5b ldr r3, [r3, #36] @ 0x24 8007ba8: 4a10 ldr r2, [pc, #64] @ (8007bec ) 8007baa: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8007bae: 461a mov r2, r3 8007bb0: 6a7b ldr r3, [r7, #36] @ 0x24 8007bb2: fbb3 f2f2 udiv r2, r3, r2 8007bb6: 697b ldr r3, [r7, #20] 8007bb8: 685b ldr r3, [r3, #4] 8007bba: 085b lsrs r3, r3, #1 8007bbc: 441a add r2, r3 8007bbe: 697b ldr r3, [r7, #20] 8007bc0: 685b ldr r3, [r3, #4] 8007bc2: fbb2 f3f3 udiv r3, r2, r3 8007bc6: 623b str r3, [r7, #32] if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 8007bc8: 6a3b ldr r3, [r7, #32] 8007bca: 2b0f cmp r3, #15 8007bcc: d910 bls.n 8007bf0 8007bce: 6a3b ldr r3, [r7, #32] 8007bd0: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8007bd4: d20c bcs.n 8007bf0 { huart->Instance->BRR = (uint16_t)usartdiv; 8007bd6: 6a3b ldr r3, [r7, #32] 8007bd8: b29a uxth r2, r3 8007bda: 697b ldr r3, [r7, #20] 8007bdc: 681b ldr r3, [r3, #0] 8007bde: 60da str r2, [r3, #12] 8007be0: e009 b.n 8007bf6 8007be2: bf00 nop 8007be4: 40008000 .word 0x40008000 8007be8: 00f42400 .word 0x00f42400 8007bec: 080086fc .word 0x080086fc } else { ret = HAL_ERROR; 8007bf0: 2301 movs r3, #1 8007bf2: f887 302a strb.w r3, [r7, #42] @ 0x2a } } } /* Initialize the number of data to process during RX/TX ISR execution */ huart->NbTxDataToProcess = 1; 8007bf6: 697b ldr r3, [r7, #20] 8007bf8: 2201 movs r2, #1 8007bfa: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = 1; 8007bfe: 697b ldr r3, [r7, #20] 8007c00: 2201 movs r2, #1 8007c02: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 /* Clear ISR function pointers */ huart->RxISR = NULL; 8007c06: 697b ldr r3, [r7, #20] 8007c08: 2200 movs r2, #0 8007c0a: 675a str r2, [r3, #116] @ 0x74 huart->TxISR = NULL; 8007c0c: 697b ldr r3, [r7, #20] 8007c0e: 2200 movs r2, #0 8007c10: 679a str r2, [r3, #120] @ 0x78 return ret; 8007c12: f897 302a ldrb.w r3, [r7, #42] @ 0x2a } 8007c16: 4618 mov r0, r3 8007c18: 3730 adds r7, #48 @ 0x30 8007c1a: 46bd mov sp, r7 8007c1c: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 08007c20 : * @brief Configure the UART peripheral advanced features. * @param huart UART handle. * @retval None */ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) { 8007c20: b480 push {r7} 8007c22: b083 sub sp, #12 8007c24: af00 add r7, sp, #0 8007c26: 6078 str r0, [r7, #4] /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); /* if required, configure RX/TX pins swap */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) 8007c28: 687b ldr r3, [r7, #4] 8007c2a: 6a9b ldr r3, [r3, #40] @ 0x28 8007c2c: f003 0308 and.w r3, r3, #8 8007c30: 2b00 cmp r3, #0 8007c32: d00a beq.n 8007c4a { assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); 8007c34: 687b ldr r3, [r7, #4] 8007c36: 681b ldr r3, [r3, #0] 8007c38: 685b ldr r3, [r3, #4] 8007c3a: f423 4100 bic.w r1, r3, #32768 @ 0x8000 8007c3e: 687b ldr r3, [r7, #4] 8007c40: 6b9a ldr r2, [r3, #56] @ 0x38 8007c42: 687b ldr r3, [r7, #4] 8007c44: 681b ldr r3, [r3, #0] 8007c46: 430a orrs r2, r1 8007c48: 605a str r2, [r3, #4] } /* if required, configure TX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) 8007c4a: 687b ldr r3, [r7, #4] 8007c4c: 6a9b ldr r3, [r3, #40] @ 0x28 8007c4e: f003 0301 and.w r3, r3, #1 8007c52: 2b00 cmp r3, #0 8007c54: d00a beq.n 8007c6c { assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); 8007c56: 687b ldr r3, [r7, #4] 8007c58: 681b ldr r3, [r3, #0] 8007c5a: 685b ldr r3, [r3, #4] 8007c5c: f423 3100 bic.w r1, r3, #131072 @ 0x20000 8007c60: 687b ldr r3, [r7, #4] 8007c62: 6ada ldr r2, [r3, #44] @ 0x2c 8007c64: 687b ldr r3, [r7, #4] 8007c66: 681b ldr r3, [r3, #0] 8007c68: 430a orrs r2, r1 8007c6a: 605a str r2, [r3, #4] } /* if required, configure RX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) 8007c6c: 687b ldr r3, [r7, #4] 8007c6e: 6a9b ldr r3, [r3, #40] @ 0x28 8007c70: f003 0302 and.w r3, r3, #2 8007c74: 2b00 cmp r3, #0 8007c76: d00a beq.n 8007c8e { assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); 8007c78: 687b ldr r3, [r7, #4] 8007c7a: 681b ldr r3, [r3, #0] 8007c7c: 685b ldr r3, [r3, #4] 8007c7e: f423 3180 bic.w r1, r3, #65536 @ 0x10000 8007c82: 687b ldr r3, [r7, #4] 8007c84: 6b1a ldr r2, [r3, #48] @ 0x30 8007c86: 687b ldr r3, [r7, #4] 8007c88: 681b ldr r3, [r3, #0] 8007c8a: 430a orrs r2, r1 8007c8c: 605a str r2, [r3, #4] } /* if required, configure data inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) 8007c8e: 687b ldr r3, [r7, #4] 8007c90: 6a9b ldr r3, [r3, #40] @ 0x28 8007c92: f003 0304 and.w r3, r3, #4 8007c96: 2b00 cmp r3, #0 8007c98: d00a beq.n 8007cb0 { assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); 8007c9a: 687b ldr r3, [r7, #4] 8007c9c: 681b ldr r3, [r3, #0] 8007c9e: 685b ldr r3, [r3, #4] 8007ca0: f423 2180 bic.w r1, r3, #262144 @ 0x40000 8007ca4: 687b ldr r3, [r7, #4] 8007ca6: 6b5a ldr r2, [r3, #52] @ 0x34 8007ca8: 687b ldr r3, [r7, #4] 8007caa: 681b ldr r3, [r3, #0] 8007cac: 430a orrs r2, r1 8007cae: 605a str r2, [r3, #4] } /* if required, configure RX overrun detection disabling */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) 8007cb0: 687b ldr r3, [r7, #4] 8007cb2: 6a9b ldr r3, [r3, #40] @ 0x28 8007cb4: f003 0310 and.w r3, r3, #16 8007cb8: 2b00 cmp r3, #0 8007cba: d00a beq.n 8007cd2 { assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); 8007cbc: 687b ldr r3, [r7, #4] 8007cbe: 681b ldr r3, [r3, #0] 8007cc0: 689b ldr r3, [r3, #8] 8007cc2: f423 5180 bic.w r1, r3, #4096 @ 0x1000 8007cc6: 687b ldr r3, [r7, #4] 8007cc8: 6bda ldr r2, [r3, #60] @ 0x3c 8007cca: 687b ldr r3, [r7, #4] 8007ccc: 681b ldr r3, [r3, #0] 8007cce: 430a orrs r2, r1 8007cd0: 609a str r2, [r3, #8] } /* if required, configure DMA disabling on reception error */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) 8007cd2: 687b ldr r3, [r7, #4] 8007cd4: 6a9b ldr r3, [r3, #40] @ 0x28 8007cd6: f003 0320 and.w r3, r3, #32 8007cda: 2b00 cmp r3, #0 8007cdc: d00a beq.n 8007cf4 { assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); 8007cde: 687b ldr r3, [r7, #4] 8007ce0: 681b ldr r3, [r3, #0] 8007ce2: 689b ldr r3, [r3, #8] 8007ce4: f423 5100 bic.w r1, r3, #8192 @ 0x2000 8007ce8: 687b ldr r3, [r7, #4] 8007cea: 6c1a ldr r2, [r3, #64] @ 0x40 8007cec: 687b ldr r3, [r7, #4] 8007cee: 681b ldr r3, [r3, #0] 8007cf0: 430a orrs r2, r1 8007cf2: 609a str r2, [r3, #8] } /* if required, configure auto Baud rate detection scheme */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) 8007cf4: 687b ldr r3, [r7, #4] 8007cf6: 6a9b ldr r3, [r3, #40] @ 0x28 8007cf8: f003 0340 and.w r3, r3, #64 @ 0x40 8007cfc: 2b00 cmp r3, #0 8007cfe: d01a beq.n 8007d36 { assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); 8007d00: 687b ldr r3, [r7, #4] 8007d02: 681b ldr r3, [r3, #0] 8007d04: 685b ldr r3, [r3, #4] 8007d06: f423 1180 bic.w r1, r3, #1048576 @ 0x100000 8007d0a: 687b ldr r3, [r7, #4] 8007d0c: 6c5a ldr r2, [r3, #68] @ 0x44 8007d0e: 687b ldr r3, [r7, #4] 8007d10: 681b ldr r3, [r3, #0] 8007d12: 430a orrs r2, r1 8007d14: 605a str r2, [r3, #4] /* set auto Baudrate detection parameters if detection is enabled */ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) 8007d16: 687b ldr r3, [r7, #4] 8007d18: 6c5b ldr r3, [r3, #68] @ 0x44 8007d1a: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8007d1e: d10a bne.n 8007d36 { assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); 8007d20: 687b ldr r3, [r7, #4] 8007d22: 681b ldr r3, [r3, #0] 8007d24: 685b ldr r3, [r3, #4] 8007d26: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000 8007d2a: 687b ldr r3, [r7, #4] 8007d2c: 6c9a ldr r2, [r3, #72] @ 0x48 8007d2e: 687b ldr r3, [r7, #4] 8007d30: 681b ldr r3, [r3, #0] 8007d32: 430a orrs r2, r1 8007d34: 605a str r2, [r3, #4] } } /* if required, configure MSB first on communication line */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) 8007d36: 687b ldr r3, [r7, #4] 8007d38: 6a9b ldr r3, [r3, #40] @ 0x28 8007d3a: f003 0380 and.w r3, r3, #128 @ 0x80 8007d3e: 2b00 cmp r3, #0 8007d40: d00a beq.n 8007d58 { assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); 8007d42: 687b ldr r3, [r7, #4] 8007d44: 681b ldr r3, [r3, #0] 8007d46: 685b ldr r3, [r3, #4] 8007d48: f423 2100 bic.w r1, r3, #524288 @ 0x80000 8007d4c: 687b ldr r3, [r7, #4] 8007d4e: 6cda ldr r2, [r3, #76] @ 0x4c 8007d50: 687b ldr r3, [r7, #4] 8007d52: 681b ldr r3, [r3, #0] 8007d54: 430a orrs r2, r1 8007d56: 605a str r2, [r3, #4] } } 8007d58: bf00 nop 8007d5a: 370c adds r7, #12 8007d5c: 46bd mov sp, r7 8007d5e: f85d 7b04 ldr.w r7, [sp], #4 8007d62: 4770 bx lr 08007d64 : * @brief Check the UART Idle State. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { 8007d64: b580 push {r7, lr} 8007d66: b098 sub sp, #96 @ 0x60 8007d68: af02 add r7, sp, #8 8007d6a: 6078 str r0, [r7, #4] uint32_t tickstart; /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8007d6c: 687b ldr r3, [r7, #4] 8007d6e: 2200 movs r2, #0 8007d70: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 8007d74: f7f9 fd9a bl 80018ac 8007d78: 6578 str r0, [r7, #84] @ 0x54 /* Check if the Transmitter is enabled */ if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) 8007d7a: 687b ldr r3, [r7, #4] 8007d7c: 681b ldr r3, [r3, #0] 8007d7e: 681b ldr r3, [r3, #0] 8007d80: f003 0308 and.w r3, r3, #8 8007d84: 2b08 cmp r3, #8 8007d86: d12f bne.n 8007de8 { /* Wait until TEACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 8007d88: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 8007d8c: 9300 str r3, [sp, #0] 8007d8e: 6d7b ldr r3, [r7, #84] @ 0x54 8007d90: 2200 movs r2, #0 8007d92: f44f 1100 mov.w r1, #2097152 @ 0x200000 8007d96: 6878 ldr r0, [r7, #4] 8007d98: f000 f88e bl 8007eb8 8007d9c: 4603 mov r3, r0 8007d9e: 2b00 cmp r3, #0 8007da0: d022 beq.n 8007de8 { /* Disable TXE interrupt for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); 8007da2: 687b ldr r3, [r7, #4] 8007da4: 681b ldr r3, [r3, #0] 8007da6: 63bb str r3, [r7, #56] @ 0x38 */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8007da8: 6bbb ldr r3, [r7, #56] @ 0x38 8007daa: e853 3f00 ldrex r3, [r3] 8007dae: 637b str r3, [r7, #52] @ 0x34 return(result); 8007db0: 6b7b ldr r3, [r7, #52] @ 0x34 8007db2: f023 0380 bic.w r3, r3, #128 @ 0x80 8007db6: 653b str r3, [r7, #80] @ 0x50 8007db8: 687b ldr r3, [r7, #4] 8007dba: 681b ldr r3, [r3, #0] 8007dbc: 461a mov r2, r3 8007dbe: 6d3b ldr r3, [r7, #80] @ 0x50 8007dc0: 647b str r3, [r7, #68] @ 0x44 8007dc2: 643a str r2, [r7, #64] @ 0x40 */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8007dc4: 6c39 ldr r1, [r7, #64] @ 0x40 8007dc6: 6c7a ldr r2, [r7, #68] @ 0x44 8007dc8: e841 2300 strex r3, r2, [r1] 8007dcc: 63fb str r3, [r7, #60] @ 0x3c return(result); 8007dce: 6bfb ldr r3, [r7, #60] @ 0x3c 8007dd0: 2b00 cmp r3, #0 8007dd2: d1e6 bne.n 8007da2 huart->gState = HAL_UART_STATE_READY; 8007dd4: 687b ldr r3, [r7, #4] 8007dd6: 2220 movs r2, #32 8007dd8: f8c3 2088 str.w r2, [r3, #136] @ 0x88 __HAL_UNLOCK(huart); 8007ddc: 687b ldr r3, [r7, #4] 8007dde: 2200 movs r2, #0 8007de0: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Timeout occurred */ return HAL_TIMEOUT; 8007de4: 2303 movs r3, #3 8007de6: e063 b.n 8007eb0 } } /* Check if the Receiver is enabled */ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) 8007de8: 687b ldr r3, [r7, #4] 8007dea: 681b ldr r3, [r3, #0] 8007dec: 681b ldr r3, [r3, #0] 8007dee: f003 0304 and.w r3, r3, #4 8007df2: 2b04 cmp r3, #4 8007df4: d149 bne.n 8007e8a { /* Wait until REACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 8007df6: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 8007dfa: 9300 str r3, [sp, #0] 8007dfc: 6d7b ldr r3, [r7, #84] @ 0x54 8007dfe: 2200 movs r2, #0 8007e00: f44f 0180 mov.w r1, #4194304 @ 0x400000 8007e04: 6878 ldr r0, [r7, #4] 8007e06: f000 f857 bl 8007eb8 8007e0a: 4603 mov r3, r0 8007e0c: 2b00 cmp r3, #0 8007e0e: d03c beq.n 8007e8a { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8007e10: 687b ldr r3, [r7, #4] 8007e12: 681b ldr r3, [r3, #0] 8007e14: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8007e16: 6a7b ldr r3, [r7, #36] @ 0x24 8007e18: e853 3f00 ldrex r3, [r3] 8007e1c: 623b str r3, [r7, #32] return(result); 8007e1e: 6a3b ldr r3, [r7, #32] 8007e20: f423 7390 bic.w r3, r3, #288 @ 0x120 8007e24: 64fb str r3, [r7, #76] @ 0x4c 8007e26: 687b ldr r3, [r7, #4] 8007e28: 681b ldr r3, [r3, #0] 8007e2a: 461a mov r2, r3 8007e2c: 6cfb ldr r3, [r7, #76] @ 0x4c 8007e2e: 633b str r3, [r7, #48] @ 0x30 8007e30: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8007e32: 6af9 ldr r1, [r7, #44] @ 0x2c 8007e34: 6b3a ldr r2, [r7, #48] @ 0x30 8007e36: e841 2300 strex r3, r2, [r1] 8007e3a: 62bb str r3, [r7, #40] @ 0x28 return(result); 8007e3c: 6abb ldr r3, [r7, #40] @ 0x28 8007e3e: 2b00 cmp r3, #0 8007e40: d1e6 bne.n 8007e10 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8007e42: 687b ldr r3, [r7, #4] 8007e44: 681b ldr r3, [r3, #0] 8007e46: 3308 adds r3, #8 8007e48: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8007e4a: 693b ldr r3, [r7, #16] 8007e4c: e853 3f00 ldrex r3, [r3] 8007e50: 60fb str r3, [r7, #12] return(result); 8007e52: 68fb ldr r3, [r7, #12] 8007e54: f023 0301 bic.w r3, r3, #1 8007e58: 64bb str r3, [r7, #72] @ 0x48 8007e5a: 687b ldr r3, [r7, #4] 8007e5c: 681b ldr r3, [r3, #0] 8007e5e: 3308 adds r3, #8 8007e60: 6cba ldr r2, [r7, #72] @ 0x48 8007e62: 61fa str r2, [r7, #28] 8007e64: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8007e66: 69b9 ldr r1, [r7, #24] 8007e68: 69fa ldr r2, [r7, #28] 8007e6a: e841 2300 strex r3, r2, [r1] 8007e6e: 617b str r3, [r7, #20] return(result); 8007e70: 697b ldr r3, [r7, #20] 8007e72: 2b00 cmp r3, #0 8007e74: d1e5 bne.n 8007e42 huart->RxState = HAL_UART_STATE_READY; 8007e76: 687b ldr r3, [r7, #4] 8007e78: 2220 movs r2, #32 8007e7a: f8c3 208c str.w r2, [r3, #140] @ 0x8c __HAL_UNLOCK(huart); 8007e7e: 687b ldr r3, [r7, #4] 8007e80: 2200 movs r2, #0 8007e82: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Timeout occurred */ return HAL_TIMEOUT; 8007e86: 2303 movs r3, #3 8007e88: e012 b.n 8007eb0 } } /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; 8007e8a: 687b ldr r3, [r7, #4] 8007e8c: 2220 movs r2, #32 8007e8e: f8c3 2088 str.w r2, [r3, #136] @ 0x88 huart->RxState = HAL_UART_STATE_READY; 8007e92: 687b ldr r3, [r7, #4] 8007e94: 2220 movs r2, #32 8007e96: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8007e9a: 687b ldr r3, [r7, #4] 8007e9c: 2200 movs r2, #0 8007e9e: 66da str r2, [r3, #108] @ 0x6c huart->RxEventType = HAL_UART_RXEVENT_TC; 8007ea0: 687b ldr r3, [r7, #4] 8007ea2: 2200 movs r2, #0 8007ea4: 671a str r2, [r3, #112] @ 0x70 __HAL_UNLOCK(huart); 8007ea6: 687b ldr r3, [r7, #4] 8007ea8: 2200 movs r2, #0 8007eaa: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 8007eae: 2300 movs r3, #0 } 8007eb0: 4618 mov r0, r3 8007eb2: 3758 adds r7, #88 @ 0x58 8007eb4: 46bd mov sp, r7 8007eb6: bd80 pop {r7, pc} 08007eb8 : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 8007eb8: b580 push {r7, lr} 8007eba: b084 sub sp, #16 8007ebc: af00 add r7, sp, #0 8007ebe: 60f8 str r0, [r7, #12] 8007ec0: 60b9 str r1, [r7, #8] 8007ec2: 603b str r3, [r7, #0] 8007ec4: 4613 mov r3, r2 8007ec6: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8007ec8: e04f b.n 8007f6a { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 8007eca: 69bb ldr r3, [r7, #24] 8007ecc: f1b3 3fff cmp.w r3, #4294967295 8007ed0: d04b beq.n 8007f6a { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 8007ed2: f7f9 fceb bl 80018ac 8007ed6: 4602 mov r2, r0 8007ed8: 683b ldr r3, [r7, #0] 8007eda: 1ad3 subs r3, r2, r3 8007edc: 69ba ldr r2, [r7, #24] 8007ede: 429a cmp r2, r3 8007ee0: d302 bcc.n 8007ee8 8007ee2: 69bb ldr r3, [r7, #24] 8007ee4: 2b00 cmp r3, #0 8007ee6: d101 bne.n 8007eec { return HAL_TIMEOUT; 8007ee8: 2303 movs r3, #3 8007eea: e04e b.n 8007f8a } if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) 8007eec: 68fb ldr r3, [r7, #12] 8007eee: 681b ldr r3, [r3, #0] 8007ef0: 681b ldr r3, [r3, #0] 8007ef2: f003 0304 and.w r3, r3, #4 8007ef6: 2b00 cmp r3, #0 8007ef8: d037 beq.n 8007f6a 8007efa: 68bb ldr r3, [r7, #8] 8007efc: 2b80 cmp r3, #128 @ 0x80 8007efe: d034 beq.n 8007f6a 8007f00: 68bb ldr r3, [r7, #8] 8007f02: 2b40 cmp r3, #64 @ 0x40 8007f04: d031 beq.n 8007f6a { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) 8007f06: 68fb ldr r3, [r7, #12] 8007f08: 681b ldr r3, [r3, #0] 8007f0a: 69db ldr r3, [r3, #28] 8007f0c: f003 0308 and.w r3, r3, #8 8007f10: 2b08 cmp r3, #8 8007f12: d110 bne.n 8007f36 { /* Clear Overrun Error flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); 8007f14: 68fb ldr r3, [r7, #12] 8007f16: 681b ldr r3, [r3, #0] 8007f18: 2208 movs r2, #8 8007f1a: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 8007f1c: 68f8 ldr r0, [r7, #12] 8007f1e: f000 f838 bl 8007f92 huart->ErrorCode = HAL_UART_ERROR_ORE; 8007f22: 68fb ldr r3, [r7, #12] 8007f24: 2208 movs r2, #8 8007f26: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Process Unlocked */ __HAL_UNLOCK(huart); 8007f2a: 68fb ldr r3, [r7, #12] 8007f2c: 2200 movs r2, #0 8007f2e: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_ERROR; 8007f32: 2301 movs r3, #1 8007f34: e029 b.n 8007f8a } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) 8007f36: 68fb ldr r3, [r7, #12] 8007f38: 681b ldr r3, [r3, #0] 8007f3a: 69db ldr r3, [r3, #28] 8007f3c: f403 6300 and.w r3, r3, #2048 @ 0x800 8007f40: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8007f44: d111 bne.n 8007f6a { /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); 8007f46: 68fb ldr r3, [r7, #12] 8007f48: 681b ldr r3, [r3, #0] 8007f4a: f44f 6200 mov.w r2, #2048 @ 0x800 8007f4e: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 8007f50: 68f8 ldr r0, [r7, #12] 8007f52: f000 f81e bl 8007f92 huart->ErrorCode = HAL_UART_ERROR_RTO; 8007f56: 68fb ldr r3, [r7, #12] 8007f58: 2220 movs r2, #32 8007f5a: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Process Unlocked */ __HAL_UNLOCK(huart); 8007f5e: 68fb ldr r3, [r7, #12] 8007f60: 2200 movs r2, #0 8007f62: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_TIMEOUT; 8007f66: 2303 movs r3, #3 8007f68: e00f b.n 8007f8a while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8007f6a: 68fb ldr r3, [r7, #12] 8007f6c: 681b ldr r3, [r3, #0] 8007f6e: 69da ldr r2, [r3, #28] 8007f70: 68bb ldr r3, [r7, #8] 8007f72: 4013 ands r3, r2 8007f74: 68ba ldr r2, [r7, #8] 8007f76: 429a cmp r2, r3 8007f78: bf0c ite eq 8007f7a: 2301 moveq r3, #1 8007f7c: 2300 movne r3, #0 8007f7e: b2db uxtb r3, r3 8007f80: 461a mov r2, r3 8007f82: 79fb ldrb r3, [r7, #7] 8007f84: 429a cmp r2, r3 8007f86: d0a0 beq.n 8007eca } } } } return HAL_OK; 8007f88: 2300 movs r3, #0 } 8007f8a: 4618 mov r0, r3 8007f8c: 3710 adds r7, #16 8007f8e: 46bd mov sp, r7 8007f90: bd80 pop {r7, pc} 08007f92 : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 8007f92: b480 push {r7} 8007f94: b095 sub sp, #84 @ 0x54 8007f96: af00 add r7, sp, #0 8007f98: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8007f9a: 687b ldr r3, [r7, #4] 8007f9c: 681b ldr r3, [r3, #0] 8007f9e: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8007fa0: 6b7b ldr r3, [r7, #52] @ 0x34 8007fa2: e853 3f00 ldrex r3, [r3] 8007fa6: 633b str r3, [r7, #48] @ 0x30 return(result); 8007fa8: 6b3b ldr r3, [r7, #48] @ 0x30 8007faa: f423 7390 bic.w r3, r3, #288 @ 0x120 8007fae: 64fb str r3, [r7, #76] @ 0x4c 8007fb0: 687b ldr r3, [r7, #4] 8007fb2: 681b ldr r3, [r3, #0] 8007fb4: 461a mov r2, r3 8007fb6: 6cfb ldr r3, [r7, #76] @ 0x4c 8007fb8: 643b str r3, [r7, #64] @ 0x40 8007fba: 63fa str r2, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8007fbc: 6bf9 ldr r1, [r7, #60] @ 0x3c 8007fbe: 6c3a ldr r2, [r7, #64] @ 0x40 8007fc0: e841 2300 strex r3, r2, [r1] 8007fc4: 63bb str r3, [r7, #56] @ 0x38 return(result); 8007fc6: 6bbb ldr r3, [r7, #56] @ 0x38 8007fc8: 2b00 cmp r3, #0 8007fca: d1e6 bne.n 8007f9a ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 8007fcc: 687b ldr r3, [r7, #4] 8007fce: 681b ldr r3, [r3, #0] 8007fd0: 3308 adds r3, #8 8007fd2: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8007fd4: 6a3b ldr r3, [r7, #32] 8007fd6: e853 3f00 ldrex r3, [r3] 8007fda: 61fb str r3, [r7, #28] return(result); 8007fdc: 69fb ldr r3, [r7, #28] 8007fde: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8007fe2: f023 0301 bic.w r3, r3, #1 8007fe6: 64bb str r3, [r7, #72] @ 0x48 8007fe8: 687b ldr r3, [r7, #4] 8007fea: 681b ldr r3, [r3, #0] 8007fec: 3308 adds r3, #8 8007fee: 6cba ldr r2, [r7, #72] @ 0x48 8007ff0: 62fa str r2, [r7, #44] @ 0x2c 8007ff2: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8007ff4: 6ab9 ldr r1, [r7, #40] @ 0x28 8007ff6: 6afa ldr r2, [r7, #44] @ 0x2c 8007ff8: e841 2300 strex r3, r2, [r1] 8007ffc: 627b str r3, [r7, #36] @ 0x24 return(result); 8007ffe: 6a7b ldr r3, [r7, #36] @ 0x24 8008000: 2b00 cmp r3, #0 8008002: d1e3 bne.n 8007fcc /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8008004: 687b ldr r3, [r7, #4] 8008006: 6edb ldr r3, [r3, #108] @ 0x6c 8008008: 2b01 cmp r3, #1 800800a: d118 bne.n 800803e { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800800c: 687b ldr r3, [r7, #4] 800800e: 681b ldr r3, [r3, #0] 8008010: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8008012: 68fb ldr r3, [r7, #12] 8008014: e853 3f00 ldrex r3, [r3] 8008018: 60bb str r3, [r7, #8] return(result); 800801a: 68bb ldr r3, [r7, #8] 800801c: f023 0310 bic.w r3, r3, #16 8008020: 647b str r3, [r7, #68] @ 0x44 8008022: 687b ldr r3, [r7, #4] 8008024: 681b ldr r3, [r3, #0] 8008026: 461a mov r2, r3 8008028: 6c7b ldr r3, [r7, #68] @ 0x44 800802a: 61bb str r3, [r7, #24] 800802c: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800802e: 6979 ldr r1, [r7, #20] 8008030: 69ba ldr r2, [r7, #24] 8008032: e841 2300 strex r3, r2, [r1] 8008036: 613b str r3, [r7, #16] return(result); 8008038: 693b ldr r3, [r7, #16] 800803a: 2b00 cmp r3, #0 800803c: d1e6 bne.n 800800c } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 800803e: 687b ldr r3, [r7, #4] 8008040: 2220 movs r2, #32 8008042: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8008046: 687b ldr r3, [r7, #4] 8008048: 2200 movs r2, #0 800804a: 66da str r2, [r3, #108] @ 0x6c /* Reset RxIsr function pointer */ huart->RxISR = NULL; 800804c: 687b ldr r3, [r7, #4] 800804e: 2200 movs r2, #0 8008050: 675a str r2, [r3, #116] @ 0x74 } 8008052: bf00 nop 8008054: 3754 adds r7, #84 @ 0x54 8008056: 46bd mov sp, r7 8008058: f85d 7b04 ldr.w r7, [sp], #4 800805c: 4770 bx lr 0800805e : * @brief Disable the FIFO mode. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) { 800805e: b480 push {r7} 8008060: b085 sub sp, #20 8008062: af00 add r7, sp, #0 8008064: 6078 str r0, [r7, #4] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); /* Process Locked */ __HAL_LOCK(huart); 8008066: 687b ldr r3, [r7, #4] 8008068: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 800806c: 2b01 cmp r3, #1 800806e: d101 bne.n 8008074 8008070: 2302 movs r3, #2 8008072: e027 b.n 80080c4 8008074: 687b ldr r3, [r7, #4] 8008076: 2201 movs r2, #1 8008078: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 800807c: 687b ldr r3, [r7, #4] 800807e: 2224 movs r2, #36 @ 0x24 8008080: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 8008084: 687b ldr r3, [r7, #4] 8008086: 681b ldr r3, [r3, #0] 8008088: 681b ldr r3, [r3, #0] 800808a: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 800808c: 687b ldr r3, [r7, #4] 800808e: 681b ldr r3, [r3, #0] 8008090: 681a ldr r2, [r3, #0] 8008092: 687b ldr r3, [r7, #4] 8008094: 681b ldr r3, [r3, #0] 8008096: f022 0201 bic.w r2, r2, #1 800809a: 601a str r2, [r3, #0] /* Disable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); 800809c: 68fb ldr r3, [r7, #12] 800809e: f023 5300 bic.w r3, r3, #536870912 @ 0x20000000 80080a2: 60fb str r3, [r7, #12] huart->FifoMode = UART_FIFOMODE_DISABLE; 80080a4: 687b ldr r3, [r7, #4] 80080a6: 2200 movs r2, #0 80080a8: 665a str r2, [r3, #100] @ 0x64 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 80080aa: 687b ldr r3, [r7, #4] 80080ac: 681b ldr r3, [r3, #0] 80080ae: 68fa ldr r2, [r7, #12] 80080b0: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 80080b2: 687b ldr r3, [r7, #4] 80080b4: 2220 movs r2, #32 80080b6: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 80080ba: 687b ldr r3, [r7, #4] 80080bc: 2200 movs r2, #0 80080be: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 80080c2: 2300 movs r3, #0 } 80080c4: 4618 mov r0, r3 80080c6: 3714 adds r7, #20 80080c8: 46bd mov sp, r7 80080ca: f85d 7b04 ldr.w r7, [sp], #4 80080ce: 4770 bx lr 080080d0 : * @arg @ref UART_TXFIFO_THRESHOLD_7_8 * @arg @ref UART_TXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { 80080d0: b580 push {r7, lr} 80080d2: b084 sub sp, #16 80080d4: af00 add r7, sp, #0 80080d6: 6078 str r0, [r7, #4] 80080d8: 6039 str r1, [r7, #0] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 80080da: 687b ldr r3, [r7, #4] 80080dc: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 80080e0: 2b01 cmp r3, #1 80080e2: d101 bne.n 80080e8 80080e4: 2302 movs r3, #2 80080e6: e02d b.n 8008144 80080e8: 687b ldr r3, [r7, #4] 80080ea: 2201 movs r2, #1 80080ec: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 80080f0: 687b ldr r3, [r7, #4] 80080f2: 2224 movs r2, #36 @ 0x24 80080f4: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 80080f8: 687b ldr r3, [r7, #4] 80080fa: 681b ldr r3, [r3, #0] 80080fc: 681b ldr r3, [r3, #0] 80080fe: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 8008100: 687b ldr r3, [r7, #4] 8008102: 681b ldr r3, [r3, #0] 8008104: 681a ldr r2, [r3, #0] 8008106: 687b ldr r3, [r7, #4] 8008108: 681b ldr r3, [r3, #0] 800810a: f022 0201 bic.w r2, r2, #1 800810e: 601a str r2, [r3, #0] /* Update TX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); 8008110: 687b ldr r3, [r7, #4] 8008112: 681b ldr r3, [r3, #0] 8008114: 689b ldr r3, [r3, #8] 8008116: f023 4160 bic.w r1, r3, #3758096384 @ 0xe0000000 800811a: 687b ldr r3, [r7, #4] 800811c: 681b ldr r3, [r3, #0] 800811e: 683a ldr r2, [r7, #0] 8008120: 430a orrs r2, r1 8008122: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 8008124: 6878 ldr r0, [r7, #4] 8008126: f000 f84f bl 80081c8 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 800812a: 687b ldr r3, [r7, #4] 800812c: 681b ldr r3, [r3, #0] 800812e: 68fa ldr r2, [r7, #12] 8008130: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 8008132: 687b ldr r3, [r7, #4] 8008134: 2220 movs r2, #32 8008136: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 800813a: 687b ldr r3, [r7, #4] 800813c: 2200 movs r2, #0 800813e: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 8008142: 2300 movs r3, #0 } 8008144: 4618 mov r0, r3 8008146: 3710 adds r7, #16 8008148: 46bd mov sp, r7 800814a: bd80 pop {r7, pc} 0800814c : * @arg @ref UART_RXFIFO_THRESHOLD_7_8 * @arg @ref UART_RXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { 800814c: b580 push {r7, lr} 800814e: b084 sub sp, #16 8008150: af00 add r7, sp, #0 8008152: 6078 str r0, [r7, #4] 8008154: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 8008156: 687b ldr r3, [r7, #4] 8008158: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 800815c: 2b01 cmp r3, #1 800815e: d101 bne.n 8008164 8008160: 2302 movs r3, #2 8008162: e02d b.n 80081c0 8008164: 687b ldr r3, [r7, #4] 8008166: 2201 movs r2, #1 8008168: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 800816c: 687b ldr r3, [r7, #4] 800816e: 2224 movs r2, #36 @ 0x24 8008170: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 8008174: 687b ldr r3, [r7, #4] 8008176: 681b ldr r3, [r3, #0] 8008178: 681b ldr r3, [r3, #0] 800817a: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 800817c: 687b ldr r3, [r7, #4] 800817e: 681b ldr r3, [r3, #0] 8008180: 681a ldr r2, [r3, #0] 8008182: 687b ldr r3, [r7, #4] 8008184: 681b ldr r3, [r3, #0] 8008186: f022 0201 bic.w r2, r2, #1 800818a: 601a str r2, [r3, #0] /* Update RX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); 800818c: 687b ldr r3, [r7, #4] 800818e: 681b ldr r3, [r3, #0] 8008190: 689b ldr r3, [r3, #8] 8008192: f023 6160 bic.w r1, r3, #234881024 @ 0xe000000 8008196: 687b ldr r3, [r7, #4] 8008198: 681b ldr r3, [r3, #0] 800819a: 683a ldr r2, [r7, #0] 800819c: 430a orrs r2, r1 800819e: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 80081a0: 6878 ldr r0, [r7, #4] 80081a2: f000 f811 bl 80081c8 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 80081a6: 687b ldr r3, [r7, #4] 80081a8: 681b ldr r3, [r3, #0] 80081aa: 68fa ldr r2, [r7, #12] 80081ac: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 80081ae: 687b ldr r3, [r7, #4] 80081b0: 2220 movs r2, #32 80081b2: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 80081b6: 687b ldr r3, [r7, #4] 80081b8: 2200 movs r2, #0 80081ba: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 80081be: 2300 movs r3, #0 } 80081c0: 4618 mov r0, r3 80081c2: 3710 adds r7, #16 80081c4: 46bd mov sp, r7 80081c6: bd80 pop {r7, pc} 080081c8 : * the UART configuration registers. * @param huart UART handle. * @retval None */ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) { 80081c8: b480 push {r7} 80081ca: b085 sub sp, #20 80081cc: af00 add r7, sp, #0 80081ce: 6078 str r0, [r7, #4] uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (huart->FifoMode == UART_FIFOMODE_DISABLE) 80081d0: 687b ldr r3, [r7, #4] 80081d2: 6e5b ldr r3, [r3, #100] @ 0x64 80081d4: 2b00 cmp r3, #0 80081d6: d108 bne.n 80081ea { huart->NbTxDataToProcess = 1U; 80081d8: 687b ldr r3, [r7, #4] 80081da: 2201 movs r2, #1 80081dc: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = 1U; 80081e0: 687b ldr r3, [r7, #4] 80081e2: 2201 movs r2, #1 80081e4: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; } } 80081e8: e031 b.n 800824e rx_fifo_depth = RX_FIFO_DEPTH; 80081ea: 2308 movs r3, #8 80081ec: 73fb strb r3, [r7, #15] tx_fifo_depth = TX_FIFO_DEPTH; 80081ee: 2308 movs r3, #8 80081f0: 73bb strb r3, [r7, #14] rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); 80081f2: 687b ldr r3, [r7, #4] 80081f4: 681b ldr r3, [r3, #0] 80081f6: 689b ldr r3, [r3, #8] 80081f8: 0e5b lsrs r3, r3, #25 80081fa: b2db uxtb r3, r3 80081fc: f003 0307 and.w r3, r3, #7 8008200: 737b strb r3, [r7, #13] tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); 8008202: 687b ldr r3, [r7, #4] 8008204: 681b ldr r3, [r3, #0] 8008206: 689b ldr r3, [r3, #8] 8008208: 0f5b lsrs r3, r3, #29 800820a: b2db uxtb r3, r3 800820c: f003 0307 and.w r3, r3, #7 8008210: 733b strb r3, [r7, #12] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 8008212: 7bbb ldrb r3, [r7, #14] 8008214: 7b3a ldrb r2, [r7, #12] 8008216: 4911 ldr r1, [pc, #68] @ (800825c ) 8008218: 5c8a ldrb r2, [r1, r2] 800821a: fb02 f303 mul.w r3, r2, r3 (uint16_t)denominator[tx_fifo_threshold]; 800821e: 7b3a ldrb r2, [r7, #12] 8008220: 490f ldr r1, [pc, #60] @ (8008260 ) 8008222: 5c8a ldrb r2, [r1, r2] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 8008224: fb93 f3f2 sdiv r3, r3, r2 8008228: b29a uxth r2, r3 800822a: 687b ldr r3, [r7, #4] 800822c: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 8008230: 7bfb ldrb r3, [r7, #15] 8008232: 7b7a ldrb r2, [r7, #13] 8008234: 4909 ldr r1, [pc, #36] @ (800825c ) 8008236: 5c8a ldrb r2, [r1, r2] 8008238: fb02 f303 mul.w r3, r2, r3 (uint16_t)denominator[rx_fifo_threshold]; 800823c: 7b7a ldrb r2, [r7, #13] 800823e: 4908 ldr r1, [pc, #32] @ (8008260 ) 8008240: 5c8a ldrb r2, [r1, r2] huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 8008242: fb93 f3f2 sdiv r3, r3, r2 8008246: b29a uxth r2, r3 8008248: 687b ldr r3, [r7, #4] 800824a: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 } 800824e: bf00 nop 8008250: 3714 adds r7, #20 8008252: 46bd mov sp, r7 8008254: f85d 7b04 ldr.w r7, [sp], #4 8008258: 4770 bx lr 800825a: bf00 nop 800825c: 08008714 .word 0x08008714 8008260: 0800871c .word 0x0800871c 08008264 : 8008264: 4402 add r2, r0 8008266: 4603 mov r3, r0 8008268: 4293 cmp r3, r2 800826a: d100 bne.n 800826e 800826c: 4770 bx lr 800826e: f803 1b01 strb.w r1, [r3], #1 8008272: e7f9 b.n 8008268 08008274 <__libc_init_array>: 8008274: b570 push {r4, r5, r6, lr} 8008276: 4d0d ldr r5, [pc, #52] @ (80082ac <__libc_init_array+0x38>) 8008278: 4c0d ldr r4, [pc, #52] @ (80082b0 <__libc_init_array+0x3c>) 800827a: 1b64 subs r4, r4, r5 800827c: 10a4 asrs r4, r4, #2 800827e: 2600 movs r6, #0 8008280: 42a6 cmp r6, r4 8008282: d109 bne.n 8008298 <__libc_init_array+0x24> 8008284: 4d0b ldr r5, [pc, #44] @ (80082b4 <__libc_init_array+0x40>) 8008286: 4c0c ldr r4, [pc, #48] @ (80082b8 <__libc_init_array+0x44>) 8008288: f000 f818 bl 80082bc <_init> 800828c: 1b64 subs r4, r4, r5 800828e: 10a4 asrs r4, r4, #2 8008290: 2600 movs r6, #0 8008292: 42a6 cmp r6, r4 8008294: d105 bne.n 80082a2 <__libc_init_array+0x2e> 8008296: bd70 pop {r4, r5, r6, pc} 8008298: f855 3b04 ldr.w r3, [r5], #4 800829c: 4798 blx r3 800829e: 3601 adds r6, #1 80082a0: e7ee b.n 8008280 <__libc_init_array+0xc> 80082a2: f855 3b04 ldr.w r3, [r5], #4 80082a6: 4798 blx r3 80082a8: 3601 adds r6, #1 80082aa: e7f2 b.n 8008292 <__libc_init_array+0x1e> 80082ac: 0800872c .word 0x0800872c 80082b0: 0800872c .word 0x0800872c 80082b4: 0800872c .word 0x0800872c 80082b8: 08008730 .word 0x08008730 080082bc <_init>: 80082bc: b5f8 push {r3, r4, r5, r6, r7, lr} 80082be: bf00 nop 80082c0: bcf8 pop {r3, r4, r5, r6, r7} 80082c2: bc08 pop {r3} 80082c4: 469e mov lr, r3 80082c6: 4770 bx lr 080082c8 <_fini>: 80082c8: b5f8 push {r3, r4, r5, r6, r7, lr} 80082ca: bf00 nop 80082cc: bcf8 pop {r3, r4, r5, r6, r7} 80082ce: bc08 pop {r3} 80082d0: 469e mov lr, r3 80082d2: 4770 bx lr